Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a display area and a non-display area, the non-display area comprises at least one binding sub-area, the binding sub-area is used for being electrically connected with a circuit board, the array substrate further comprises a driving module arranged in the non-display area, and the circuit board provides a driving control signal for the driving module through the binding sub-area; the at least one binding sub-region comprises at least three signal providing regions; the binding sub-area comprises a plurality of bonding pad terminals arranged in the at least three signal providing areas, and the bonding pad terminals provide driving control signals for the driving module through signal wires. According to the invention, the temperature of the signal wires is reduced by increasing the signal access points.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In the related borderless screen display products, the driving module includes a plurality of cascaded driving circuits, and the plurality of cascaded driving circuits are arranged along a first direction. In the related art, the non-display area includes at least one binding sub-area, and the at least one binding sub-area can be arranged along a first direction; the at least one binding sub-area includes two signal supply areas, the first signal supply area can be set at the left end of the leftmost binding sub-area, and the second signal supply area can be set at the right end of the rightmost binding sub-area. Therefore, the length of the signal line for receiving the driving control signal of the driving circuit located in the middle is longer, so the temperature of the signal line is high, which can cause abnormality of the driving circuit, or generate high-temperature gravity yellow spots in the display screen, affecting the display effect. Summary of the invention

[0003] In one aspect, at least one embodiment of the present invention provides an array substrate, comprising a display area and a non-display area, wherein the non-display area comprises at least one binding sub-area, wherein the binding sub-area is used to be electrically connected to a circuit board, and the array substrate further comprises a driving module disposed in the non-display area, wherein the circuit board provides a driving control signal to the driving module through the binding sub-area;

[0004] The at least one binding sub-region includes at least three signal providing regions;

[0005] The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal routings.

[0006] Optionally, the non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction;

[0007] The binding sub-region includes a first signal providing region and a second signal providing region;

[0008] The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals;

[0009] The first pad terminal corresponds to the first signal providing area, and the second pad terminal corresponds to the second signal providing area;

[0010] The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

[0011] Optionally, the array substrate described in at least one embodiment of the present invention further includes a data line at least partially disposed in the display area;

[0012] The plurality of pad terminals further include a plurality of third pad terminals;

[0013] The third pad terminal is arranged between the first pad terminal and the second pad terminal;

[0014] The third pad terminal is electrically connected to the data line and is used to provide a data voltage for the data line.

[0015] Optionally, the drive control signal includes at least one of a clock signal, a common electrode voltage signal, a DC voltage signal, and a frame start signal.

[0016] Optionally, the signal wiring is used to provide a clock signal for the driving module; the non-display area includes a first binding sub-area and a second binding sub-area;

[0017] The array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region;

[0018] The clock signal line includes a first end and a second end that are arranged opposite to each other;

[0019] The first signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is arranged at a second end of the first binding sub-region;

[0020] The first signal providing region of the second binding sub-region is arranged at a first end of the second binding sub-region, and the second signal providing region of the second binding sub-region is arranged at a second end of the first binding sub-region;

[0021] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the second binding sub-region is close to the second end of the clock signal line.

[0022] Optionally, the clock signal line is arranged in a first metal layer; the first binding sub-region is electrically connected to the clock signal line via a signal routing line formed in a second metal layer and arranged in a second signal providing region thereof;

[0023] The second binding sub-region is electrically connected to the clock signal line through a signal trace formed on the second metal layer and arranged in the first signal providing region thereof;

[0024] The first metal layer and the second metal layer are different metal layers.

[0025] Optionally, the first binding sub-region is electrically connected to the clock signal line through a signal trace formed on the first metal layer and arranged in the first signal providing region thereof;

[0026] The second binding sub-region is electrically connected to the clock signal line through a signal routing line formed on the first metal layer and arranged in the second signal providing region thereof.

[0027] Optionally, the non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; and the plurality of pad terminals are arranged along the first direction;

[0028] The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

[0029] Optionally, the signal wiring is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0030] The clock signal line includes a first end and a second end;

[0031] The signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is arranged at a second end of the Mth binding sub-region;

[0032] The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M;

[0033] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

[0034] Optionally, the non-display area includes a binding sub-area; the plurality of pad terminals are arranged along a first direction;

[0035] The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3

[0036] Two of the N signal providing areas are disposed at opposite sides of the binding sub-area, and signal providing areas other than the two signal providing areas of the N signal providing areas are disposed in the middle of the binding sub-area.

[0037] Optionally, the signal wiring is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0038] The clock signal line includes a first end and a second end;

[0039] The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

[0040] Optionally, the non-display area includes a first non-display region arranged on a first side of the display area;

[0041] The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

[0042] Optionally, the signal routing includes at least two electrically connected signal line portions;

[0043] The at least two signal line portions are respectively formed in different metal layers.

[0044] Optionally, the array substrate includes a first metal layer and a second metal layer;

[0045] The signal routing line includes a first signal line portion and a second signal line portion;

[0046] The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

[0047] Optionally, the array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer;

[0048] The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer;

[0049] The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

[0050] Optionally, the array substrate further includes a base;

[0051] An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

[0052] Optionally, the plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage;

[0053] The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad;

[0054] The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer;

[0055] The second sub-pad includes a third sub-pad portion formed on the first metal layer;

[0056] The third sub pad includes a fourth sub pad portion formed in the first metal layer.

[0057] Optionally, the driving module includes a multi-stage driving circuit;

[0058] The driving circuit includes an output transistor;

[0059] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0060] The channel width-to-length ratio of the output transistor is less than a first width-to-length ratio threshold.

[0061] Optionally, the driving circuit further includes an output reset transistor;

[0062] The gate of the output reset transistor is electrically connected to the reset terminal, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal;

[0063] The channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

[0064] Optionally, the signal trace is used to transmit a clock signal;

[0065] The rising edge of the clock signal includes at least two steps.

[0066] In a second aspect, an embodiment of the present invention provides a display device, comprising a circuit board and the above-mentioned array substrate;

[0067] The circuit board is electrically connected to the binding sub-region in the array substrate, and is used to provide a driving control signal to the driving module in the array substrate through the binding sub-region. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1A is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0069] Figure 1Bis a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0070] Figure 1C yes Figure 1A An enlarged schematic diagram of the first binding sub-region Q1 in FIG.

[0071] Figure 1D yes Figure 1A An enlarged schematic diagram of the second binding sub-region Q2 in FIG.

[0072] Figure 2A yes Figure 1A A waveform diagram of a current I0 on a clock signal line when at least one embodiment of the array substrate shown is in operation;

[0073] Figure 2B is a waveform diagram of the current I1 on the clock signal line when the relevant array substrate is working;

[0074] Figure 3A is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0075] Figure 3B is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0076] Figure 3C yes Figure 3A An enlarged schematic diagram of the first binding sub-region Q1 and the second binding sub-region Q2;

[0077] Figure 3D yes Figure 3A An enlarged schematic diagram of the third binding sub-region Q3 and the fourth binding sub-region Q4;

[0078] Figure 4A is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0079] Figure 4B is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0080] Figure 4C yes Figure 4A An enlarged schematic diagram of the first binding sub-region Q1 in FIG.

[0081] Figure 5 is a layout diagram of six signal lines in an array substrate according to at least one embodiment of the present invention;

[0082] Figure 6 yes Figure 5 A layout diagram of the gate metal layer in FIG.

[0083] Figure 7 yes Figure 5 Layout diagram of source and drain metal layers in FIG.

[0084] Figure 8 yes Figure 5 A layout diagram of the conductive layer in FIG.

[0085] Fig. 9 yes Figure 5 A-A' cross-section diagram;

[0086] Fig.10 It is a schematic diagram of the connection relationship between the actual pad terminal and the signal trace;

[0087] Fig.11 yes Fig.10 A layout diagram of the gate metal layer in FIG.

[0088] Fig.12 yes Fig.10 Layout diagram of source and drain metal layers in FIG.

[0089] Fig.13 yes Fig.10 Layout of the conductive layer in

[0090] Fig.14 It is a schematic diagram of the connection relationship between the actual signal routing and the GOA module;

[0091] Fig.15 is a circuit diagram of at least one embodiment of the driving circuit;

[0092] Fig.16 It is a waveform diagram of the current on the clock signal line before and after the channel width-to-length ratio of the output transistor M3 decreases;

[0093] Fig.17 It is a comparison diagram of the channel width W of M3 and the current I on the clock signal line;

[0094] Fig.18 is a comparison chart of the channel width of M3 and the falling time Tf of the driving signal;

[0095] Fig.19 is a waveform diagram of a clock signal CLK in at least one embodiment of the present invention;

[0096] Fig. 20 It is the waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes two steps;

[0097] Fig.21 It is a waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes only one step in the related art. DETAILED DESCRIPTION

[0098] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0099] The array substrate of the embodiment of the present invention comprises a display area and a non-display area, the non-display area comprises at least one binding sub-area, the binding sub-area is used to be electrically connected to a circuit board, the array substrate further comprises a driving module arranged in the non-display area, the circuit board provides a driving control signal to the driving module through the binding sub-area;

[0100] The at least one binding sub-region includes at least three signal providing regions;

[0101] The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal routings.

[0102] In the related borderless screen display product, the driving module includes a plurality of cascaded driving circuits, and the plurality of cascaded driving circuits are arranged along the first direction. In the related art, the non-display area includes at least one binding sub-area, and the at least one binding sub-area can be arranged along the first direction; the at least one binding sub-area includes two signal supply areas, the first signal supply area can be set at the left end of the leftmost binding sub-area, and the second signal supply area can be set at the right end of the rightmost binding sub-area. Therefore, the length of the signal routing line for receiving the driving control signal of the driving circuit located in the middle is longer, so the temperature of the signal routing line is high, which can cause the driving circuit to be abnormal, or generate a high-temperature gravity yellow spot in the display screen, affecting the display effect. Based on this, in the array substrate described in the embodiment of the present invention, the non-display area includes at least one binding sub-area, and the circuit board provides the driving module with a driving control signal through the binding sub-area, and the at least one binding sub-area is set to include at least three signal supply areas, and the pad terminals set in the at least three signal supply areas provide the driving module with a driving control signal through the signal routing, so as to reduce the temperature of the signal routing line by increasing the signal access point.

[0103] In at least one embodiment of the present invention, the first direction may be a row direction, that is, a horizontal direction, but is not limited thereto.

[0104] In the borderless screen display product, gate lines extending along the row direction and gate lines extending along the column direction are provided, and the gate lines in the row direction and the gate lines in the column direction are electrically connected. Referring to FIG. 1 , the gate lines GLH extending along the row direction and the gate lines GLV extending along the column direction are electrically connected through a connection point D, as well as data lines extending along the column direction. The gate lines extending along the column direction are electrically connected to a driving module for receiving a driving signal generated by the driving module. The driving module includes a plurality of cascaded driving circuits (the driving circuits may be gate driving circuits).

[0105] Optionally, the drive control signal includes at least one of a clock signal, a common electrode voltage signal, a direct current voltage signal, and a frame start signal.

[0106] In at least one embodiment of the present invention, the drive control signal includes but is not limited to a ground signal, a power supply voltage signal, a common electrode voltage signal, a common electrode feedback voltage signal, a clock signal, a high voltage signal, a first low voltage signal, a second low voltage signal, a frame start signal, an ADD test signal, etc. The principle of the above signals generating heat for the signal routing is the same, except that the clock signal is a high-frequency square wave signal relative to other signals, and the heat generated by the signal routing for transmitting the clock signal has the greatest impact on the temperature of the signal routing. In at least one embodiment of the present invention, the drive control signal is taken as a clock signal for example for description.

[0107] In related high-resolution, high-refresh rate display products, due to limitations such as the border and charging rate, the current of the signal routing that transmits the drive control signal is relatively large, resulting in high signal routing temperature, which is prone to defects such as multiple outputs of the drive circuit and high-temperature black spots on the display.

[0108] In at least one embodiment of the present invention, the non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction;

[0109] The binding sub-region includes a first signal providing region and a second signal providing region;

[0110] The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals;

[0111] The first pad terminal corresponds to the first signal providing area, and the second pad terminal corresponds to the second signal providing area;

[0112] The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

[0113] In a specific implementation, the non-display area may include multiple binding sub-areas, each binding sub-area may include two signal supply areas, the multiple pad terminals include a first pad terminal arranged in the first signal supply area and a second pad terminal arranged in the second signal supply area, and the first pad terminal and the second pad terminal are arranged on opposite sides of the binding sub-area.

[0114] The array substrate described in at least one embodiment of the present invention further includes a data line at least partially disposed in the display area;

[0115] The plurality of pad terminals further include a plurality of third pad terminals;

[0116] The third pad terminal is arranged between the first pad terminal and the second pad terminal;

[0117] The third pad terminal is electrically connected to the data line and is used to provide a data voltage for the data line.

[0118] In a specific implementation, the array substrate may further include a data line extending along a vertical direction, and a third pad terminal disposed between the first pad terminal and the second pad terminal provides a data voltage for the data line.

[0119] In at least one embodiment of the present invention, the signal wiring is used to provide a clock signal for the driving module; the non-display area includes a first binding sub-area and a second binding sub-area;

[0120] The array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region;

[0121] The clock signal line includes a first end and a second end;

[0122] The first signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is arranged at a second end of the first binding sub-region;

[0123] The first signal providing region of the second binding sub-region is arranged at a first end of the second binding sub-region, and the second signal providing region of the second binding sub-region is arranged at a second end of the first binding sub-region;

[0124] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the second binding sub-region is close to the second end of the clock signal line.

[0125] In a specific implementation, the non-display area may include two binding sub-areas, at least one clock signal line extending along the first direction is arranged between the driving module and the binding sub-area, the first signal supply area of ​​the first binding sub-area is arranged at the first end of the first binding sub-area, and the second signal supply area of ​​the first binding sub-area is arranged at the second end of the first binding sub-area; the first signal supply area of ​​the second binding sub-area is arranged at the first end of the second binding sub-area, and the second signal supply area of ​​the second binding sub-area is arranged at the second end of the first binding sub-area; the first end of the first binding sub-area is close to the first end of the clock signal line, and the second end of the second binding sub-area is close to the second end of the clock signal line.

[0126] Optionally, when the first direction is a horizontal direction, the first end may be a left end, and the second end may be a right end, but is not limited thereto.

[0127] In at least one embodiment of the present invention, the clock signal line is arranged in the first metal layer; the first binding sub-region is electrically connected to the clock signal line through a signal routing line formed in the second metal layer and arranged in the second signal providing region thereof;

[0128] The second binding sub-region is electrically connected to the clock signal line through a signal trace formed on the second metal layer and arranged in the first signal providing region thereof;

[0129] The first metal layer and the second metal layer are different metal layers.

[0130] In a specific implementation, the first binding sub-region is electrically connected to the clock signal line via a signal routing located in a second signal providing region and located on a different layer from the clock signal line; the second binding sub-region is electrically connected to the clock signal line via a signal routing located in a first signal providing region and located on a different layer from the clock signal line, so as to avoid a short circuit between the signal routing and the clock signal line at the intersection.

[0131] In at least one embodiment of the present invention, the first binding sub-region is electrically connected to the clock signal line through a signal trace formed on the first metal layer and arranged in the first signal providing region thereof;

[0132] The second binding sub-region is electrically connected to the clock signal line through a signal routing line formed on the first metal layer and arranged in the second signal providing region thereof.

[0133] In a specific implementation, at the edge, the first binding sub-region is electrically connected to the clock signal line through a signal routing set on the same layer as the clock signal line in its first signal providing region, and the second binding sub-region is electrically connected to the clock signal line through a signal routing set on the same layer as the clock signal line in its second signal providing region, so as to facilitate electrical connection between the signal routing and the clock signal line.

[0134] Optionally, the first metal layer may be a gate metal layer, and the second metal layer may be a source / drain metal layer, but is not limited thereto.

[0135] like Figure 1A As shown, the array substrate described in at least one embodiment of the present invention includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0;

[0136] The array substrate described in at least one embodiment of the present invention includes a driving module, a first binding sub-region Q1 and a second binding sub-region Q2;

[0137] The driving module includes a plurality of driving circuits arranged along a first direction;

[0138] The first signal providing area included in the first binding sub-area Q1 is marked as S11, the second signal providing area included in the first binding sub-area Q1 is marked as S12, and the third signal providing area included in the first binding sub-area Q1 is marked as S13;

[0139] The first signal providing area included in the second binding sub-area Q2 is marked as S21, the second signal providing area included in the second binding sub-area Q2 is marked as S22, and the third signal providing area included in the second binding sub-area Q2 is marked as S23;

[0140] S11 is arranged at the left end of Q1, S12 is arranged at the right end of Q1, and S13 is arranged between S11 and S12, that is, S11 and S12 are arranged at opposite sides of S13;

[0141] S21 is arranged at the left end of Q2, S22 is arranged at the right end of Q2, and S23 is arranged between S21 and S22, that is, S21 and S22 are arranged at opposite sides of S23;

[0142] At least one embodiment of the array substrate includes a first first pad terminal H11, a second first pad terminal H21, a third first pad terminal H31, and a fourth first pad terminal H41 disposed at S11;

[0143] At least one embodiment of the array substrate further includes a fifth first pad terminal H51, a sixth first pad terminal H61, and a seventh first pad terminal H71 disposed at S21;

[0144] At least one embodiment of the array substrate further includes a first second pad terminal H12, a second second pad terminal H22 and a third second pad terminal H32 disposed at S12;

[0145] At least one embodiment of the array substrate further includes a fourth second pad terminal H42, a fifth second pad terminal H52, a sixth second pad terminal H62 and a seventh second pad terminal H72 disposed at S22;

[0146] At least one embodiment of the array substrate further includes a first third pad terminal H13, a second third pad terminal H23, a third third pad terminal H33, a fourth third pad terminal H43, a fifth third pad terminal H53 and a sixth third pad terminal H63 disposed at S13;

[0147] At least one embodiment of the array substrate further includes a seventh third pad terminal H73, an eighth third pad terminal H83, a ninth third pad terminal H93, a tenth third pad terminal H103, an eleventh third pad terminal H113 and a twelfth third pad terminal H123 disposed at S23;

[0148] exist Figure 1A In the embodiment, the first-stage driving circuit included in the driving module is labeled GA1, the second-stage driving circuit included in the driving module is labeled GA2, the third-stage driving circuit included in the driving module is labeled GA3, the p-th stage driving circuit included in the driving module is labeled GAp, the p+1-th stage driving circuit included in the driving module is labeled GAp+2, the p+2-th stage driving circuit included in the driving module is labeled GAp+3, the p+3-th stage driving circuit included in the driving module is labeled GAp+4, the p+4-th stage driving circuit included in the driving module is labeled GAp+5, the p+5-th stage driving circuit included in the driving module is labeled GAb-2, the b-2-th stage driving module included in the driving module is labeled GAb-1, and the b-1-th stage driving module included in the driving module is labeled GAb;

[0149] Wherein, p and b are positive integers.

[0150] exist Figure 1AIn at least one embodiment shown, the first clock signal line is labeled CK1, the second clock signal line is labeled CK2, and the third clock signal line is labeled CK3; each clock signal line is disposed in the gate metal layer;

[0151] CK1, CK2, and CK3 all extend in the horizontal direction;

[0152] Each pad terminal is arranged in a horizontal direction;

[0153] The first data line is labeled DL1, the second data line is labeled DL2, the third data line is labeled DL3, the fourth data line is labeled DL4, the fifth data line is labeled DL5, the sixth data line is labeled DL6, the seventh data line is labeled DL7, the eighth data line is labeled DL8, the ninth data line is labeled DL9, the tenth data line is labeled DL10, the eleventh data line is labeled DL11, and the twelfth data line is labeled DL12; each data line is set in the source and drain metal layer.

[0154] exist Figure 1A In at least one embodiment shown, H11 is directly electrically connected to GA1 through a first signal wiring L1 provided in the gate metal layer, or H11 is electrically connected to GA1 and GA2 at the same time through the first signal wiring provided in the gate metal layer, so as to provide an initial trigger signal (STV signal) of the driving circuit, H21 is electrically connected to the left end of CK1 through a second signal wiring L2 provided in the gate metal layer, H31 is electrically connected to the left end of CK2 through a third signal wiring L3 provided in the gate metal layer, and H41 is electrically connected to the left end of CK3 through a fourth signal wiring L4 provided in the gate metal layer, so as to provide a clock signal;

[0155] H12 is electrically connected to CK3 via a fifth signal wire L5 disposed on the source-drain metal layer, H22 is electrically connected to CK2 via a sixth signal wire L6 disposed on the source-drain metal layer, and H32 is electrically connected to CK1 via a seventh signal wire L7 disposed on the source-drain metal layer;

[0156] H51 is electrically connected to CK3 via an eighth signal wire L8 disposed on the source-drain metal layer, H61 is electrically connected to CK2 via a ninth signal wire L9 disposed on the source-drain metal layer, and H71 is electrically connected to CK1 via a tenth signal wire L10 disposed on the source-drain metal layer;

[0157] H42 is electrically connected to the right end of CK3 through the eleventh signal wiring L11 provided on the gate metal layer, H52 is electrically connected to the right end of CK2 through the twelfth signal wiring L12 provided on the gate metal layer, and H62 is electrically connected to the right end of CK1 through the thirteenth signal wiring L13 provided on the gate metal layer, so as to provide a clock signal; H72 is directly electrically connected to Gab through the fourteenth signal wiring L14 provided on the gate metal layer, or H72 is simultaneously connected to GAb-1 and Gab through the fourteenth signal wiring L14 provided on the gate metal layer, so as to provide an initial trigger signal. Optionally, in this case, the driving circuit included at both ends of the driving module can be electrically connected to the initial trigger signal, so that the driving module can realize a bidirectional scanning mode, or only the driving circuit included at one of the two ends of the driving module can be electrically connected to the initial trigger signal to realize unidirectional scanning, which is not limited here;

[0158] H13 is electrically connected to DL1, H23 is electrically connected to DL2, H33 is electrically connected to DL3, H43 is electrically connected to DL4, H53 is electrically connected to DL5, H63 is electrically connected to DL6, H73 is electrically connected to DL7, H83 is electrically connected to DL8, H93 is electrically connected to DL9, H103 is electrically connected to DL10, H113 is electrically connected to DL11, and H123 is electrically connected to DL12.

[0159] exist Figure 1A In at least one embodiment of the array substrate shown, the driving module, CK1, CK2, CK3, and each binding sub-region are all arranged in the first non-display region F1, so that a full-screen display effect can be achieved.

[0160] like Figure 1B As shown, in Figure 1A On the basis of, except for the first end and the second end of each clock signal line, the first end is the left end and the second end is the right end;

[0161] exist Figure 1B , D11 is the first end of CK1, D12 is the second end of CK1, D21 is the first end of CK2, D22 is the second end of CK2, D31 is the first end of CK3, and D32 is the second end of CK3.

[0162] Figure 1C yes Figure 1A An enlarged schematic diagram of the first binding sub-region Q1 in FIG. Figure 1D yes Figure 1A An enlarged schematic diagram of the second binding sub-region Q2 in FIG.

[0163] Figure 2A yes Figure 1AThe waveform diagram of the current I0 on the clock signal line when at least one embodiment of the array substrate shown in FIG. 1 is in operation, Figure 2B It is a waveform diagram of the current I1 on the clock signal line when the relevant array substrate is working.

[0164] After comparison, Figure 1A When at least one embodiment of the array substrate shown is in operation, the current value of the current I0 on the clock signal line is smaller than the current value of the current I1 on the clock signal line when the corresponding array substrate is in operation.

[0165] In at least one embodiment of the present invention, the non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; the array substrate includes a plurality of pad terminals disposed in the binding sub-areas, and the plurality of pad terminals are arranged along the first direction;

[0166] The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

[0167] In a specific implementation, the non-display area may include at least three binding sub-areas arranged along the first direction, and the signal providing area included in each binding sub-area may be arranged at the first end or the second end of the binding sub-area.

[0168] In at least one embodiment of the present invention, the signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0169] The clock signal line includes a first end and a second end that are arranged opposite to each other;

[0170] The signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is arranged at a second end of the Mth binding sub-region;

[0171] The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M;

[0172] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

[0173] Optionally, the first end may be a left end, and the second end may be a right end.

[0174] In a specific implementation, when the non-display area includes at least three binding sub-areas arranged along a first direction (the first direction can be a horizontal direction), the signal providing area of ​​the first binding sub-area located on the leftmost side can be set at the left end of the first binding sub-area, the signal providing area of ​​the Mth binding sub-area located on the rightmost side can be set at the right end of the Mth binding sub-area, the mth binding sub-area is set between the first binding sub-area and the Mth binding sub-area, the signal providing areas of the mth binding sub-area are set at the left end or the right end of the mth binding sub-area, the left end of the first binding sub-area is close to the left end of the clock signal line, and the right end of the Mth binding sub-area is close to the right end of the clock signal line.

[0175] like Figure 3A As shown, the array substrate described in at least one embodiment of the present invention includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0;

[0176] The array substrate described in at least one embodiment of the present invention includes a driving module, a first binding sub-region Q1, a second binding sub-region Q2, a third binding sub-region Q3 and a fourth binding sub-region Q4; each binding sub-region includes a signal providing region;

[0177] The driving module includes a plurality of driving circuits arranged along a first direction;

[0178] The signal providing area included in the first binding sub-area Q1 is marked as S1; the signal providing area included in the second binding sub-area Q2 is marked as S2; the signal providing area included in the third binding sub-area Q3 is marked as S3; the signal providing area included in the fourth binding sub-area Q4 is marked as S4;

[0179] S1 is set at the left end of Q1; S2 is set at the left end of Q2; S3 is set at the right end of Q3; S4 is set at the right end of Q4;

[0180] exist Figure 3AIn the embodiment, the first-stage driving circuit included in the driving module is labeled GA1, the second-stage driving circuit included in the driving module is labeled GA2, the third-stage driving circuit included in the driving module is labeled GA3, the p-th stage driving circuit included in the driving module is labeled GAp, the p+1-th stage driving circuit included in the driving module is labeled GAp+2, the p+2-th stage driving circuit included in the driving module is labeled GAp+3, the p+3-th stage driving circuit included in the driving module is labeled GAp+4, the p+4-th stage driving circuit included in the driving module is labeled GAp+5, the p+5-th stage driving circuit included in the driving module is labeled GAb-2, the b-2-th stage driving module included in the driving module is labeled GAb-1, and the b-1-th stage driving module included in the driving module is labeled GAb;

[0181] Wherein, p and b are positive integers.

[0182] exist Figure 3A In at least one embodiment shown, the first clock signal line is labeled CK1, the second clock signal line is labeled CK2, and the third clock signal line is labeled CK3; each clock signal line is disposed in the gate metal layer;

[0183] CK1, CK2, and CK3 all extend in the horizontal direction;

[0184] Each pad terminal is arranged in a horizontal direction;

[0185] exist Figure 3A , the first first pad terminal is labeled H11, the second first pad terminal is labeled H21; the third first pad terminal is labeled H31, the fourth first pad terminal is labeled H41; the fifth first pad terminal is labeled H51, the sixth first pad terminal is labeled H61; the seventh first pad terminal is labeled H71, the eighth first pad terminal is labeled H81; the ninth first pad terminal is labeled H91, the tenth first pad terminal is labeled H101; the eleventh first pad terminal is labeled H111, the twelfth first pad terminal is labeled H121; the thirteenth first pad terminal is labeled H131, the fourteenth first pad terminal is labeled H141;

[0186] H11, H21, H31 and H41 are arranged at S1, H51, H61 and H71 are arranged at S2, H81, H91 and H101 are arranged at S3, H111, H121, H131 and H141 are arranged at S4; H11 is directly electrically connected to GA1 and GA2 for providing a clock signal;

[0187] H21 is electrically connected to the left end of CK1, H31 is electrically connected to the left end of CK2, and H41 is electrically connected to the left end of CK3;

[0188] H51 is electrically connected to the middle of CK3, H61 is electrically connected to the middle of CK2, and H71 is electrically connected to the middle of CK3;

[0189] H81 is electrically connected to the middle of CK3, H91 is electrically connected to the middle of CK2, and H101 is electrically connected to the middle of CK3;

[0190] H111 is electrically connected to the right end of CK3, H121 is electrically connected to the right end of CK2, H131 is electrically connected to the right end of CK1, and H141 is directly electrically connected to GAb-1 and Gab for providing clock signals.

[0191] exist Figure 3A In at least one embodiment of the array substrate shown, the driving module, CK1, CK2, CK3, and each binding sub-region are all disposed in the first non-display region F1.

[0192] like Figure 3B As shown, in Figure 3A On the basis of, except for the first end and the second end of each clock signal line, the first end is the left end and the second end is the right end;

[0193] exist Figure 3B , D11 is the first end of CK1, D12 is the second end of CK1, D21 is the first end of CK2, D22 is the second end of CK2, D31 is the first end of CK3, and D32 is the second end of CK3.

[0194] Figure 3C yes Figure 3A An enlarged schematic diagram of the first binding sub-region Q1 and the second binding sub-region Q2, Figure 3D yes Figure 3A An enlarged schematic diagram of the third binding sub-region Q3 and the fourth binding sub-region Q4.

[0195] exist Figure 3AIn at least one embodiment shown, the number of binding sub-areas is an even number, the pad terminal for providing the clock signal of the binding sub-area located at the leftmost end is led out from the left end of the binding sub-area, and the pad terminal for providing the clock signal of the binding sub-area located at the rightmost end is led out from the right end of the binding sub-area, and the binding sub-area located in the middle can be divided into two groups, the pad terminal for providing the clock signal of the binding sub-area close to the left end is led out from the left end of the binding sub-area, and the pad terminal for providing the clock signal of the binding sub-area close to the right end is led out from the right end of the binding sub-area, that is, the overall design is symmetrical with the center line of the array substrate.

[0196] In at least one embodiment of the present invention, the number of the binding sub-regions may be an even number or an odd number;

[0197] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area, and the pad terminal for providing the clock signal of the middle binding sub-area can be partially led out from the left end of the binding sub-area and the other part from the right end of the binding sub-area; or, the pad terminal for providing the clock signal of the middle binding sub-area can be led out entirely from the left end or the right end.

[0198] In at least one embodiment of the present invention, the number of the binding sub-regions may be an even number or an odd number;

[0199] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area, and the pad terminal for providing the clock signal of the middle binding sub-area can be led out from both the left and right ends of the binding sub-area.

[0200] In at least one embodiment of the present invention, the number of the binding sub-regions may be an even number or an odd number;

[0201] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area, the pad terminals for providing the clock signal of the part of the binding sub-area located in the middle are led out from both the left and right ends of the binding sub-area, and the pad terminals for providing the clock signal of another part of the binding sub-area located in the middle are led out from the left or right end of the binding sub-area.

[0202] In at least one embodiment of the present invention, the non-display area includes a binding sub-area; the array substrate includes a plurality of pad terminals disposed in the binding sub-area, and the plurality of pad terminals are arranged along a first direction;

[0203] The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3

[0204] Two of the N signal providing areas are disposed at opposite sides of the binding sub-area, and signal providing areas other than the two signal providing areas of the N signal providing areas are disposed in the middle of the binding sub-area.

[0205] In a specific implementation, the non-display area may include a binding sub-area, the binding sub-area includes at least three signal supply areas, and the N signal supply areas are arranged along the first direction.

[0206] In at least one embodiment of the present invention, the signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0207] The clock signal line includes a first end and a second end;

[0208] The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

[0209] like Figure 4A As shown, the array substrate described in at least one embodiment of the present invention includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0;

[0210] The array substrate described in at least one embodiment of the present invention includes a driving module and a first binding sub-region Q1; the first binding sub-region includes four signal providing regions;

[0211] The driving module includes a plurality of driving circuits arranged along a first direction;

[0212] The first signal providing area included in the first binding sub-area Q1 is marked as S1; the second signal providing area included in the first binding sub-area Q1 is marked as S2; the third signal providing area included in the first binding sub-area Q1 is marked as S3; the fourth signal providing area included in the first binding sub-area Q1 is marked as S4;

[0213] S1 is arranged at the left end of Q1; S2 and S3 are arranged between S1 and S4; S4 is arranged at the right end of Q1;

[0214] exist Figure 4AIn the embodiment, the first-stage driving circuit included in the driving module is labeled GA1, the second-stage driving circuit included in the driving module is labeled GA2, the third-stage driving circuit included in the driving module is labeled GA3, the p-th stage driving circuit included in the driving module is labeled GAp, the p+1-th stage driving circuit included in the driving module is labeled GAp+2, the p+2-th stage driving circuit included in the driving module is labeled GAp+3, the p+3-th stage driving circuit included in the driving module is labeled GAp+4, the p+4-th stage driving circuit included in the driving module is labeled GAp+5, the p+5-th stage driving circuit included in the driving module is labeled GAb-2, the b-2-th stage driving module included in the driving module is labeled GAb-1, and the b-1-th stage driving module included in the driving module is labeled GAb;

[0215] Wherein, p and b are positive integers.

[0216] exist Figure 4A In at least one embodiment shown, the first clock signal line is labeled CK1, the second clock signal line is labeled CK2, and the third clock signal line is labeled CK3; each clock signal line is disposed in the gate metal layer;

[0217] CK1, CK2, and CK3 all extend in the horizontal direction;

[0218] Each pad terminal is arranged in a horizontal direction;

[0219] exist Figure 4A , the first first pad terminal is labeled H11, the second first pad terminal is labeled H21; the third first pad terminal is labeled H31, the fourth first pad terminal is labeled H41; the fifth first pad terminal is labeled H51, the sixth first pad terminal is labeled H61; the seventh first pad terminal is labeled H71, the eighth first pad terminal is labeled H81; the ninth first pad terminal is labeled H91, the tenth first pad terminal is labeled H101; the eleventh first pad terminal is labeled H111, the twelfth first pad terminal is labeled H121; the thirteenth first pad terminal is labeled H131, the fourteenth first pad terminal is labeled H141;

[0220] H11, H21, H31 and H41 are arranged at S1, H51, H61 and H71 are arranged at S2, H81, H91 and H101 are arranged at S3, H111, H121, H131 and H141 are arranged at S4; H11 is directly electrically connected to GA1 and GA2 for providing a clock signal;

[0221] H21 is electrically connected to the left end of CK1, H31 is electrically connected to the left end of CK2, and H41 is electrically connected to the left end of CK3;

[0222] H51 is electrically connected to the middle of CK3, H61 is electrically connected to the middle of CK2, and H71 is electrically connected to the middle of CK3;

[0223] H81 is electrically connected to the middle of CK3, H91 is electrically connected to the middle of CK2, and H101 is electrically connected to the middle of CK3;

[0224] H111 is electrically connected to the right end of CK3, H121 is electrically connected to the right end of CK2, H131 is electrically connected to the right end of CK1, and H141 is directly electrically connected to GAb-1 and Gab for providing clock signals.

[0225] exist Figure 4A In at least one embodiment of the array substrate shown, the driving module, CK1, CK2, CK3, and each binding sub-region are all disposed in the first non-display region F1.

[0226] like Figure 4B As shown, in Figure 4A On the basis of, except for the first end and the second end of each clock signal line, the first end is the left end and the second end is the right end;

[0227] exist Figure 4B , D11 is the first end of CK1, D12 is the second end of CK1, D21 is the first end of CK2, D22 is the second end of CK2, D31 is the first end of CK3, and D32 is the second end of CK3.

[0228] Figure 4C yes Figure 4A An enlarged schematic diagram of the first binding sub-region Q1 in FIG.

[0229] In at least one embodiment of the present invention, the non-display area includes a first non-display region disposed on a first side of the display area;

[0230] The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

[0231] In at least one embodiment of the present invention, the signal trace includes at least two electrically connected signal line portions;

[0232] The at least two signal line portions are respectively formed in different metal layers.

[0233] In a specific implementation, the heat source power of the signal routing mainly comes from the current flowing through the signal routing and the square resistance per unit length. In the related art, the signal routing adopts a single-layer routing, and in at least one embodiment of the present invention, the signal routing is configured to include at least two electrically connected signal line portions, and at least two signal line portions are respectively formed in different metal layers, thereby reducing the resistance of the signal routing, thereby achieving the purpose of reducing the heat source power and thus reducing the temperature of the signal routing.

[0234] Optionally, the array substrate includes a first metal layer and a second metal layer;

[0235] The signal routing line includes a first signal line portion and a second signal line portion;

[0236] The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

[0237] In at least one embodiment of the present invention, the array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer;

[0238] The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer;

[0239] The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

[0240] The array substrate described in at least one embodiment of the present invention further includes a base;

[0241] An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

[0242] Figure 5 It is a layout diagram of six signal lines (six signal lines are used as an example, and the number of signal lines is not specifically limited) in an array substrate according to at least one embodiment of the present invention.

[0243] exist Figure 5 , the first signal line is labeled L1, the second signal line is labeled L2, the third signal line is labeled L3, the fourth signal line is labeled L4, the fifth signal line is labeled L5, and the sixth signal line is labeled L6;

[0244] Figure 6 yes Figure 5 The layout diagram of the gate metal layer in Figure 7 yes Figure 5 Layout diagram of source and drain metal layers in Figure 8 yes Figure 5 Layout diagram of the conductive layer in .

[0245] exist Figure 6 , the first signal line portion labeled L11 is included in the first signal routing, the first signal line portion labeled L21 is included in the second signal routing, the first signal line portion labeled L31 is included in the third signal routing, the first signal line portion labeled L41 is included in the fourth signal routing, the first signal line portion labeled L51 is included in the fifth signal routing, and the first signal line portion labeled L61 is included in the sixth signal routing.

[0246] like Figure 7 As shown, L12 is the second signal line portion included in the first signal routing, L22 is the second signal routing portion included in the second signal routing, L32 is the second signal line portion included in the third signal routing, L42 is the second signal routing portion included in the fourth signal routing, L52 is the second signal line portion included in the fifth signal routing, and L62 is the second signal routing portion included in the sixth signal routing.

[0247] Fig. 9 yes Figure 5 A-A' cross-section diagram.

[0248] exist Fig. 9 In the figure, 90 is a substrate, 91 is a gate metal layer, 92 is a first insulating layer (the first insulating layer may be, for example, a gate insulating layer), 93 is a source-drain metal layer, 94 is a second insulating layer (the second insulating layer may be, for example, a PVX passivation layer), and 95 is a conductive layer (optionally, the conductive layer may be an ITO (indium tin oxide) layer on the same layer as the pixel electrode or the common electrode).

[0249] like Figure 5-Figure 9 As shown, the orthographic projection of L11 on the substrate at least partially overlaps with the orthographic projection of L12 on the substrate, the orthographic projection of L21 on the substrate at least partially overlaps with the orthographic projection of L22 on the substrate, the orthographic projection of L31 on the substrate at least partially overlaps with the orthographic projection of L32 on the substrate, the orthographic projection of L41 on the substrate at least partially overlaps with the orthographic projection of L42 on the substrate, the orthographic projection of L51 on the substrate at least partially overlaps with the orthographic projection of L52 on the substrate, and the orthographic projection of L61 on the substrate at least partially overlaps with the orthographic projection of L62 on the substrate, and optionally, they may also completely overlap.

[0250] In specific implementation, when each signal line adopts double-layer wiring, the resistance value of each signal line can be reduced from 0.85 ohms in single-layer wiring to 0.43 ohms. The double-layer wiring has no effect on the current of each signal line. The temperature of the signal line is reduced from 53.3 degrees Celsius to 42.2 degrees Celsius, and the temperature of the signal line is directly and effectively reduced.

[0251] Optionally, the plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage;

[0252] The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad;

[0253] The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer;

[0254] The second sub-pad includes a third sub-pad portion formed on the first metal layer;

[0255] The third sub pad includes a fourth sub pad portion formed in the first metal layer.

[0256] Fig.10 It is a schematic diagram of the actual connection relationship between the pad terminal and the signal trace.

[0257] Fig.11 yes Fig.10 The layout diagram of the gate metal layer in Fig.12 yes Fig.10 Layout diagram of source and drain metal layers in Fig.13 yes Fig.10 Layout diagram of the conductive layer in .

[0258] like Fig.10 As shown, the first pad terminal for transmitting the clock signal includes a first sub-pad H01 and a second sub-pad H02; the third sub-pad H03 labeled H03 is used for transmitting the data voltage;

[0259] like Fig.11 As shown, the first sub-pad H01 includes a first sub-pad portion HB1, the second sub-pad H02 includes a third sub-pad portion HB3, and the third sub-pad H03 includes a fourth sub-pad portion HB4;

[0260] like Fig.12 As shown, the first sub-pad H01 includes a second sub-pad portion HB2;

[0261] exist Fig.10 In the figure, the pad labeled HD is a dummy pad.

[0262] In a specific implementation, each pad terminal further includes a conductive layer (the conductive layer may be made of, for example, ITO (indium tin oxide)). Fig.11 and Fig.12 The first sub-pad portion HB1 is arranged on the gate metal layer, including two branch structures, and the second sub-pad portion HB2 is arranged on the source-drain metal layer, including two branches, wherein the two branches included in HB1 and the two branches included in HB2 are arranged opposite to each other (the two branches included in HB1 are designed on the right side, and the two branches included in HB2 are designed on the left side, and do not overlap in the direction perpendicular to the substrate), HB1 and HB2 are electrically connected through a conductive layer and a via, the conductive layer is exposed to be bound to an FPC (flexible printed circuit), and the conductive pattern located on the conductive layer is used to electrically connect the sub-pad portion formed on the gate metal layer and the sub-pad portion formed on the source-drain metal layer included in the same pad terminal.

[0263] Fig.14 This is a schematic diagram of the actual connection between the signal routing and the GOA module. Fig.14 Among them, the part labeled GA is the driving circuit included in the driving module.

[0264] In at least one embodiment of the present invention, the driving module includes a multi-stage driving circuit;

[0265] The driving circuit includes an output transistor;

[0266] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0267] The channel width-to-length ratio of the output transistor is less than a first width-to-length ratio threshold.

[0268] In a specific implementation, the driving circuit includes an output transistor, and the output transistor is used to control the connection or disconnection between the clock signal line and the driving signal output terminal under the control of the potential of the first node. In the related art, the channel width-to-length ratio of the output transistor is relatively large, which has a great impact on the load of the clock signal line, thereby increasing the temperature of the signal line. By reducing the channel width-to-length ratio of the output transistor, the current on the clock signal line is reduced to reduce the temperature on the signal line. At the same time, the reduction of the channel width-to-length ratio of the output transistor will increase the falling time Tf of the driving signal, which can be compensated by increasing the channel width-to-length ratio of the output reset transistor.

[0269] Optionally, the first width-to-length ratio threshold may be greater than or equal to 6000 / 4.3 and less than or equal to 20000 / 4.3. Optionally, the first width-to-length ratio threshold may be greater than or equal to 9000 / 4.3 and less than or equal to 12000 / 4.3. For example, the first width-to-length ratio threshold may be 11000 / 4.3, 10500 / 4.3, 12000 / 5.3, etc., but is not limited thereto.

[0270] In at least one embodiment of the present invention, the driving circuit further includes an output reset transistor;

[0271] The gate of the output reset transistor is electrically connected to the reset terminal, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal;

[0272] The channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

[0273] Optionally, the second width-to-length ratio threshold may be greater than or equal to 10000 / 4.3 and less than or equal to 25000 / 4.3. Optionally, the second width-to-length ratio threshold may be greater than or equal to 13000 / 4.3 and less than or equal to 19000 / 4.3. For example, the second width-to-length ratio threshold may be 14000 / 4.3, 15000 / 4.3, 16000 / 4.3, etc., but is not limited thereto.

[0274] Optionally, the channel width-to-length ratio of the output transistor of the driving circuit can be smaller than the channel width-to-length ratio of the output reset transistor. For example, the channel width-to-length ratio of the output transistor of the driving circuit / the channel width-to-length ratio of the output reset transistor is between 1.1 and 1.4, including the endpoint values. Such a design improves the temperature on the peripheral signal routing without affecting the normal operation of the driving circuit.

[0275] like Fig.15 As shown, at least one embodiment of the driving circuit may include a first transistor M1, a second transistor M2, an output transistor M3, an output reset transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a storage capacitor C0;

[0276] exist Fig.15Among them, labeled I1 is the input terminal, labeled R1 is the reset signal terminal, labeled STV0 is the frame reset terminal, labeled LVGL is the first low voltage terminal, labeled VGL is the second low voltage terminal, labeled PU is the first node, labeled PD1 is the first second node, labeled PD2 is the second first node, labeled OC is the carry output terminal, labeled GU is the drive signal output terminal, labeled RST is the reset terminal, labeled CLK is the clock signal terminal, labeled VDDO is the first control voltage terminal, and labeled VDDE is the second control voltage terminal.

[0277] Fig.15 What is shown is only one embodiment of the driving circuit, and the structure of the driving circuit is not limited.

[0278] Taking the channel length of the driving transistor in the driving circuit as 4.3μm as an example, in the relevant technology, the channel width-to-length ratio of M3 can be 17500 / 4.3, and the channel width-to-length ratio of M4 can be 16000 / 4.3. While ensuring the frame, the channel width of M3 is simulated and adjusted with a step value of 1000μm. When the channel width-to-length ratio of M3 is reduced to 10500 / 4.3, the RMS (root mean square) value of the current of the corresponding clock signal line decreases from 35.33mA to 30.16mA, and the fall time of the driving signal increases from 1.88μs to 2.06μs. The temperature of the clock signal line drops significantly, from 53.3 degrees Celsius directly to 47.7 degrees Celsius. At the same time, it has little impact on the fall time of the driving signal, and the image quality loss is small.

[0279] exist Fig.16 , B1 is a waveform diagram of the current I on the clock signal line before the channel width-to-length ratio of M3 decreases, and B2 is a waveform diagram of the current I on the clock signal line after the channel width-to-length ratio of M3 decreases.

[0280] exist Fig.16 In the figure, the vertical axis is the current I on the clock signal line, in A, and the horizontal axis is the time t, in μs.

[0281] Fig.17 This is a comparison chart of the channel width W of M3 and the current I on the clock signal line. Fig.18 It is a comparison chart of the channel width of M3 and the falling time Tf of the driving signal.

[0282] In at least one embodiment of the present invention, the signal trace is used to transmit a clock signal;

[0283] The rising edge of the clock signal includes at least two steps. Specifically, the rising edge of the clock signal can include at least two steps by adding a clock signal charge sharing (CLK Charge Sharing) circuit at the circuit driving end.

[0284] In a specific implementation, the rising edge of the clock signal is controlled to have multiple stages, that is, when the potential of the clock signal is controlled to change suddenly from a low voltage Vgl to a high voltage Vgh, the intermediate voltage GPM is increased to split the large single peak of the current on the rising edge of the clock signal into two smaller peaks, thereby achieving the purpose of reducing the current on the clock signal line.

[0285] In at least one embodiment of the present invention, the waveform of the clock signal CLK is as follows: Fig.19 shown.

[0286] exist Fig.19 In at least one embodiment shown, the voltage value of the intermediate voltage GPM is (Vgl+Vgh) / 2, the potential of the clock signal CLK is the duration of GPM is 0.5H, 1H is a line scanning time, and after simulation, the RMS value of the current on the clock signal line drops from 35.33mA to 30.82mA.

[0287] Fig. 20 It is the waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes two steps. Fig.21 It is a waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes only one step in the related art.

[0288] The display device described in the embodiment of the present invention comprises a circuit board and the above-mentioned array substrate;

[0289] The circuit board is electrically connected to the binding sub-region in the array substrate, and is used to provide a driving control signal to the driving module in the array substrate through the binding sub-region. The number of circuit boards can correspond to the binding sub-regions included in the array substrate. For example, if there are two binding sub-regions, two circuit boards can be provided.

[0290] In at least one embodiment of the present invention, a display device may include at least one circuit board, the circuit board includes a binding area, and at least one binding area included in at least one circuit board includes at least three signal providing areas; the binding area includes a plurality of gold finger structures for achieving electrical connection with a pad terminal of an array substrate (electrical connection may be achieved by welding or ACF (anisotropic conductive adhesive) etc.), transmitting data lines of the display area to provide data signals and control signals of a driving circuit.

[0291] The circuit board may be a flexible circuit board, and the circuit board may further include a data driving chip.

[0292] In at least one embodiment of the present invention, the display device may include two circuit boards, each circuit board is bound to a corresponding binding sub-area, and the circuit board includes a plurality of first gold fingers, a plurality of second gold fingers, and a plurality of third gold fingers;

[0293] The first gold finger and the second gold finger are arranged on opposite sides of the circuit board, and the third gold finger is arranged between the first gold finger and the second gold finger;

[0294] The first gold finger is electrically connected to the first pad terminal for transmitting a driving control signal; the second gold finger is electrically connected to the second pad terminal for transmitting a driving control signal; the third gold finger is electrically connected to the third pad terminal for transmitting a data voltage.

[0295] In at least one embodiment of the present invention, the display device may include at least three circuit boards, each circuit board is respectively bound to a corresponding binding sub-area, and the circuit board includes a plurality of first gold fingers; the first gold fingers are electrically connected to the first pad terminal for transmitting a driving control signal;

[0296] The first gold finger included in the circuit board located at the far left is arranged at the left end of the circuit board, and the first gold finger included in the circuit board located at the far right can be arranged at the right end of the circuit board;

[0297] The first gold finger included in the circuit board located in the middle can be arranged at the left end and / or the right end of the circuit board.

[0298] In at least one embodiment of the present invention, the display device may include a circuit board, the circuit board is bound to the corresponding binding sub-area, and the circuit board includes a plurality of first gold fingers; the first gold fingers are electrically connected to the first pad terminal for transmitting a driving control signal;

[0299] The first gold fingers can be arranged at the left end, the right end and the middle of the circuit board.

[0300] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area and a non-display area, wherein the non-display area comprises at least one binding sub-area, and the binding sub-area is used to be electrically connected to a circuit board. The array substrate further comprises a driving module arranged in the non-display area, and the circuit board provides a driving control signal to the driving module through the binding sub-area. The at least one binding sub-region includes at least three signal providing regions; The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal routings.

2. The array substrate according to claim 1, characterized in that: The non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction; The binding sub-region includes a first signal providing region and a second signal providing region; The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals; The first pad terminal corresponds to the first signal providing area, and the second pad terminal corresponds to the second signal providing area; The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

3. The array substrate according to claim 2, characterized in that: Also included is a data line at least partially disposed in the display area; The plurality of pad terminals further include a plurality of third pad terminals; The third pad terminal is arranged between the first pad terminal and the second pad terminal; The third pad terminal is electrically connected to the data line and is used to provide a data voltage for the data line.

4. The array substrate according to claim 1, wherein: The driving control signal includes at least one of a clock signal, a common electrode voltage signal, a direct current voltage signal, and a frame start signal.

5. The array substrate according to claim 2, characterized in that: The signal wiring is used to provide a clock signal for the driving module; the non-display area includes a first binding sub-area and a second binding sub-area; The array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end that are arranged opposite to each other; The first signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is arranged at a second end of the first binding sub-region; The first signal providing region of the second binding sub-region is arranged at a first end of the second binding sub-region, and the second signal providing region of the second binding sub-region is arranged at a second end of the first binding sub-region; The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the second binding sub-region is close to the second end of the clock signal line.

6. The array substrate according to claim 5, characterized in that: The clock signal line is arranged on the first metal layer; the first binding sub-region is electrically connected to the clock signal line via a signal routing line formed on the second metal layer and arranged in its second signal providing region; The second binding sub-region is electrically connected to the clock signal line through a signal trace formed on the second metal layer and arranged in the first signal providing region thereof; The first metal layer and the second metal layer are different metal layers.

7. The array substrate according to claim 6, characterized in that: The first binding sub-region is electrically connected to the clock signal line through a signal trace formed on the first metal layer and arranged in the first signal providing region thereof; The second binding sub-region is electrically connected to the clock signal line through a signal routing line formed on the first metal layer and arranged in the second signal providing region thereof.

8. The array substrate according to claim 1, wherein: The non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; the plurality of pad terminals are arranged along the first direction; The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

9. The array substrate according to claim 8, characterized in that: The signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end; The signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is arranged at a second end of the Mth binding sub-region; The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M; The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

10. The array substrate according to claim 1, wherein: The non-display area includes a binding sub-area; the plurality of pad terminals are arranged along a first direction; The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3 Two of the N signal providing areas are disposed at opposite sides of the binding sub-area, and signal providing areas other than the two signal providing areas of the N signal providing areas are disposed in the middle of the binding sub-area.

11. The array substrate according to claim 10, characterized in that: The signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end; The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

12. The array substrate according to claim 5, 6, 7, 9 or 11, characterized in that: The non-display area includes a first non-display region disposed on a first side of the display area; The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

13. The array substrate according to any one of claims 1 to 11, characterized in that: The signal routing includes at least two electrically connected signal line portions; The at least two signal line portions are respectively formed in different metal layers.

14. The array substrate according to claim 13, wherein: The array substrate comprises a first metal layer and a second metal layer; The signal routing line includes a first signal line portion and a second signal line portion; The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

15. The array substrate according to claim 14, characterized in that: The array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer; The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer; The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

16. The array substrate according to claim 14, characterized in that: The array substrate further comprises a base; An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

17. The array substrate according to claim 14, wherein: The plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage; The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad; The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer; The second sub-pad includes a third sub-pad portion formed on the first metal layer; The third sub pad includes a fourth sub pad portion formed in the first metal layer.

18. The array substrate according to any one of claims 1 to 11, characterized in that: The driving module includes a multi-stage driving circuit; The driving circuit includes an output transistor; The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal; The channel width-to-length ratio of the output transistor is less than a first width-to-length ratio threshold.

19. The array substrate according to claim 18, wherein: The driving circuit also includes an output reset transistor; The gate of the output reset transistor is electrically connected to the reset terminal, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal; The channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

20. The array substrate according to any one of claims 1 to 11, characterized in that: The signal trace is used to transmit the clock signal; The rising edge of the clock signal includes at least two steps.

21. A display device, characterized in that: A circuit board and an array substrate as claimed in any one of claims 1 to 20; The circuit board is electrically connected to the binding sub-region in the array substrate, and is used to provide a driving control signal to the driving module in the array substrate through the binding sub-region.

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