Display device

Abstract

A display device is provided. The display device includes: a circuit layer disposed on a substrate, the circuit layer including a plurality of light-emitting pixel driving portions electrically connected to a plurality of light-emitting elements, respectively, and a plurality of data wires transmitting data signals of the plurality of light-emitting pixel driving portions; a display driving circuit which generates data signals of the plurality of light-emitting pixel driving parts; and a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wires and including a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal. A first data wire among the data wires is electrically connected to the display driving circuit through the first demultiplexing transistor and a transfer path smaller than a first extension length. A second data wire among the data wires is electrically connected to the display driving circuit through the second demultiplexing transistor and the transmission path of the first extension length or more.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, and digital televisions.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, a light emitting display device, etc. Here, the light emitting display device may include an organic light emitting display device having an organic light emitting element, an inorganic light emitting display device having an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device having an ultra-small light emitting element.

[0004] An organic light emitting display device uses a plurality of light emitting elements each including a light emitting layer of an organic light emitting material to display an image. As described above, an organic light emitting display device uses self-luminous elements to realize image display, so that compared with other display devices, it can have relatively excellent performance in terms of power consumption, response speed, light emitting efficiency, brightness, and wide viewing angle.

[0005] One side of the display device may be a display surface including a display area for displaying an image and a non-display area as a periphery of the display area. In the display area, light emitting areas emitting light with various brightness and colors may be arranged.

[0006] As the display device becomes higher in resolution or larger in size, the number of data wirings increases, and the transmission paths between the data wirings and the display driving circuits are dispersed more widely. As a result, distorted or delayed data signals may be supplied to data wirings with longer transmission paths among the multiple data wirings.

[0007] Furthermore, as the display device becomes higher in resolution or larger in size, the number of channels of the display driving circuit or the number of display driving circuits may increase as the number of data wirings increases, which may be disadvantageous in reducing the thickness of the display device and the manufacturing cost. Summary of the invention

[0008] Therefore, an object of the present invention is to provide a display device that can reduce distortion of data signals without changing a display driving circuit, thereby contributing to higher resolution or larger size.

[0009] The subject of the present invention is not limited to the subject mentioned above, and those skilled in the art should be able to clearly understand other technical subjects not mentioned through the following description.

[0010] The display device according to the embodiment for solving the above-mentioned problem comprises: a substrate including a main area and a sub-area protruding from one side of the main area, wherein the main area includes a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer arranged on the substrate, including a plurality of light-emitting pixel driving units electrically connected to a plurality of light-emitting elements of the plurality of light-emitting areas and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; a display driving circuit generating data signals of the plurality of light-emitting pixel driving units; and a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings, including a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal. A first data wiring among the data wirings is electrically connected to the display driving circuit through the first demultiplexing transistor and a transmission path less than a first extension length. A second data wiring among the data wirings is electrically connected to the display driving circuit through the second demultiplexing transistor and a transmission path longer than the first extension length.

[0011] The first demultiplexing control signal may be supplied during a first period in each image frame period. The second demultiplexing control signal may be supplied during a second period after the first period in each image frame period.

[0012] It may be that the data signal of the second data wiring includes a compensation value corresponding to the first extension length.

[0013] A voltage level of a maximum grayscale of the data signal of the second data wiring may be higher than a voltage level of a maximum grayscale of the data signal of the first data wiring based on the compensation value.

[0014] The second period may be longer than the first period based on the compensation value.

[0015] It may be that the display driving circuit and the demultiplexing circuit are arranged in the sub-region of the substrate. It may be that, among the first data wiring and the second data wiring, the first data wiring is closer to the sub-region. It may be that the circuit layer further comprises: a plurality of data supply wirings extending from the sub-region toward the display region and electrically connected between the plurality of data wirings and the demultiplexing circuit. It may be that the transmission path of the first data wiring comprises a first data supply wiring among the data supply wirings that is electrically connected between the first demultiplexing transistor and the first data wiring. It may be that the transmission path of the second data wiring comprises a second data supply wiring among the data supply wirings that is electrically connected between the second demultiplexing transistor and the second data wiring.

[0016] The first data wiring may be directly electrically connected to the first data supply wiring. The transmission path of the second data wiring may include: a first detour auxiliary wiring, which is arranged in the display area, extends in the first direction, and is electrically connected to the second data wiring; and a second detour auxiliary wiring, which is arranged in the display area, extends in the second direction together with the data wiring, forms a pair with the first data wiring, and is electrically connected between the first detour auxiliary wiring and the second data supply wiring.

[0017] The demultiplexing circuit may further include: a third demultiplexing transistor, which is turned on according to a third demultiplexing control signal supplied in a third period after the second period in each image frame period. The second data wiring may be electrically connected to the display driving circuit via the second demultiplexing transistor and a transmission path having a length greater than the first extension length and less than the second extension length. The third data wiring among the data wirings may be electrically connected to the display driving circuit via the third demultiplexing transistor and a transmission path having a length greater than the second extension length.

[0018] The demultiplexing circuit may further include: a fourth demultiplexing transistor, which is turned on according to a fourth demultiplexing control signal supplied in a fourth period after the third period in each image frame period. The third data wiring may be electrically connected to the display driving circuit via the third demultiplexing transistor and a transmission path having a length greater than the second extension and less than the third extension. The fourth data wiring among the data wirings may be electrically connected to the display driving circuit via the fourth demultiplexing transistor and a transmission path having a length greater than the third extension.

[0019] The display device according to the embodiment for solving the above-mentioned problem includes: a substrate including a main area and a sub-area protruding from one side of the main area, the main area including a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer arranged on the substrate, including a plurality of light-emitting pixel driving units electrically connected to a plurality of light-emitting elements of the plurality of light-emitting areas and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; a display driving circuit generating data signals of the plurality of light-emitting pixel driving units; and a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings. The transmission path between a first data wiring among the data wirings and the demultiplexing circuit is less than a first extension length. The transmission path between a second data wiring among the data wirings and the demultiplexing circuit is greater than the first extension length. The demultiplexing circuit outputs the data signal of the first data wiring in a first period within each image frame period, and outputs the data signal of the second data wiring in a second period after the first period within each image frame period.

[0020] It may be that the data signal of the second data wiring includes a compensation value corresponding to the first extension length.

[0021] It may be that the display driving circuit and the demultiplexing circuit are arranged in the sub-region of the substrate. It may be that, among the first data wiring and the second data wiring, the first data wiring is closer to the sub-region. It may be that the circuit layer further includes: a plurality of data supply wirings extending from the sub-region toward the display region and electrically connected between the plurality of data wirings and the demultiplexing circuit. It may be that the transmission path between the first data wiring and the demultiplexing circuit includes a first data supply wiring among the data supply wirings that is electrically connected between the demultiplexing circuit and the first data wiring. It may be that the transmission path between the second data wiring and the demultiplexing circuit includes a second data supply wiring among the data supply wirings that is electrically connected between the demultiplexing circuit and the second data wiring.

[0022] The first data wiring may be directly electrically connected to the first data supply wiring. The transmission path between the second data wiring and the demultiplexing circuit may further include: a first detour auxiliary wiring, arranged in the display area, extending in the first direction, and electrically connected to the second data wiring; and a second detour auxiliary wiring, arranged in the display area, extending in the second direction together with the data wiring, forming a pair with the first data wiring, and electrically connected between the first detour auxiliary wiring and the second data supply wiring.

[0023] It may be that the demultiplexing circuit includes: a plurality of first demultiplexing transistors, which are turned on according to a first demultiplexing control signal during the first period of each image frame, and are respectively electrically connected between the display driving circuit and the first data supply wiring; and a plurality of second demultiplexing transistors, which are turned on according to a second demultiplexing control signal during the second period of each image frame, and are respectively electrically connected between the display driving circuit and the second data supply wiring.

[0024] It may be that the transmission path between the second data wiring and the demultiplexing circuit is greater than the first extension length and less than the second extension length, the transmission path between the third data wiring among the data wirings and the demultiplexing circuit is greater than the second extension length, and the demultiplexing circuit outputs the data signal of the third data wiring during a third period after the second period during each image frame period.

[0025] It may be that the transmission path between the third data wiring and the demultiplexing circuit is greater than the second extension length and less than the third extension length, the transmission path between the fourth data wiring among the data wirings and the demultiplexing circuit is greater than the third extension length, and the demultiplexing circuit outputs the data signal of the fourth data wiring during a fourth period after the third period during each image frame period.

[0026] The display device according to the embodiment for solving the above-mentioned problem comprises: a substrate including a main area and a sub-area protruding from one side of the main area, wherein the main area comprises a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer arranged on the substrate, comprising a plurality of light-emitting pixel driving units electrically connected to a plurality of light-emitting elements of the plurality of light-emitting areas and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; a display driving circuit generating data signals of the plurality of light-emitting pixel driving units; and a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings, comprising a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal. The data wiring comprises a first data wiring and a second data wiring. Of the first data wiring and the second data wiring, the second data wiring is closer to the non-display area in a direction intersecting with the data wiring. The circuit layer further includes: a first detour auxiliary wiring, arranged in the display area, extending in the first direction, and electrically connected to the second data wiring; and a second detour auxiliary wiring, arranged in the display area, extending in the second direction together with the data wiring, forming a pair with the first data wiring, and electrically connected between the first detour auxiliary wiring and the second data supply wiring. A first demultiplexing transistor is electrically connected between the first data wiring and the display driving circuit, and a second demultiplexing transistor is electrically connected between the second data wiring and the display driving circuit.

[0027] The first demultiplexing transistor may be turned on according to the first demultiplexing control signal supplied in a first period in each image frame period. The second demultiplexing transistor may be turned on according to the second demultiplexing control signal supplied in a second period after the first period in each image frame period.

[0028] The display driving circuit and the demultiplexing circuit may be arranged in the sub-region of the substrate. The circuit layer may further include: a plurality of data supply wirings extending from the sub-region toward the display region and electrically connected between the plurality of data wirings and the demultiplexing circuit. The first data wiring may be directly electrically connected to a first data supply wiring among the data supply wirings. The second data wiring among the data supply wirings may be electrically connected to the second data supply wiring through the first detour auxiliary wiring and the second detour auxiliary wiring.

[0029] The first data wiring may be electrically connected to the display driving circuit via the first demultiplexing transistor and a transmission path shorter than the first extension length. The second data wiring may be electrically connected to the display driving circuit via the second demultiplexing transistor and a transmission path longer than the first extension length. The data signal of the second data wiring may include a compensation value corresponding to the first extension length.

[0030] Details of other embodiments are included in the detailed description and drawings.

[0031] (Effects of the Invention)

[0032] The display device involved in the embodiment may include a circuit layer including multiple light-emitting pixel driving units and multiple data wirings, a display driving circuit generating data signals for the multiple light-emitting pixel driving units, and a demultiplexing circuit electrically connected between the display driving circuit and the multiple data wirings.

[0033] The demultiplexing circuit may include a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal.

[0034] A first data wiring among the data wirings may be electrically connected to the display driving circuit through a first demultiplexing transistor and a transfer path that is smaller than the first extension length.

[0035] A second data wiring among the data wirings may be electrically connected to the display driving circuit via a second demultiplexing transistor and a transmission path having a length longer than the first extension.

[0036] That is, the demultiplexing circuit can output the data signal of the first data wiring and the data signal of the second data wiring in different periods. Thus, the display driving circuit can output the data signal of the second data wiring to which the compensation value corresponding to the first extension length is applied based on the data control signal of the timing control unit.

[0037] Therefore, even without changing the display driving circuit, the distortion of the data signal of the second data wiring caused by the relatively long transmission path longer than the first extension length can be prevented. Therefore, it is possible to achieve higher resolution and larger size without affecting the thinning of the display device and the reduction of manufacturing cost.

[0038] The effects of the embodiments are not limited to the above-exemplified ones, and more effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a perspective view showing a display device according to the embodiment.

[0040] Figure 2 Yes means Figure 1 A plan view of a display device.

[0041] Figure 3 Yes means Figure 2 AA′ cross-sectional view.

[0042] Figure 4 Yes means Figure 2 Layout diagram of Part B.

[0043] Figure 5 Yes means Figure 3 Block diagram of the circuit layer.

[0044] Figure 6 Yes means Figure 4 and Figure 5 The equivalent circuit diagram of the light-emitting pixel driving unit is shown.

[0045] Figure 7 Yes means Figure 6 A cross-sectional view of the driving transistor, the sixth transistor and the light emitting element is shown.

[0046] Figure 8 It means that the embodiment involves Figure 2 A plan view of the substrate.

[0047] Fig. 9 It means that the embodiment involves Figure 8 Layout diagram of part C.

[0048] Fig.10 Yes means Fig. 9 The timing diagram of the first demultiplexing control signal and the second demultiplexing control signal is shown.

[0049] Fig.11 FIG. 1 is a diagram showing an example in which a gamma curve is applied to the compensation value according to the embodiment.

[0050] Fig.12 This is a diagram showing an example in which the compensation value according to the embodiment is applied to the first period and the second period.

[0051] Fig.13 It means that an embodiment involves Figure 8 Layout diagram of part C.

[0052] Fig.14 Yes means Fig.13 The timing diagram of the first demultiplexing control signal, the second demultiplexing control signal and the third demultiplexing control signal is shown.

[0053] Fig.15 It means that an embodiment involves Figure 8 Layout diagram of part C.

[0054] Fig.16 Yes means Fig.15 The timing diagram of the first demultiplexing control signal, the second demultiplexing control signal, the third demultiplexing control signal and the fourth demultiplexing control signal is shown.

[0055] Fig.17 It means that other embodiments involve Figure 2 A plan view of the substrate.

[0056] Fig.18 Yes means Fig.17 Layout diagram of Section D.

[0057] Fig.19 Yes means Fig.18 Cross-sectional view of EE′.

[0058] Explanation of symbols:

[0059] 100: display device; 200: display driving circuit; 300: circuit board; 400: touch driving circuit; 110: substrate; 120: circuit layer; 130: component layer; 140: sealing layer; 150: touch sensor layer; 160: polarization layer; DA: display area; NDA: non-display area; SBA: sub-area; EA: light-emitting area; EPD: light-emitting pixel driving unit; DL: data wiring; DMC: demultiplexing circuit; DL1: first data wiring; DL2: second data wiring; DL3: third data wiring; DL4: fourth data wiring; DS PL1: first data supply wiring; DSPL2: second data supply wiring; DSPL3: third data supply wiring; DSPL4: fourth data supply wiring; DXT1: first demultiplexing transistor; DXT2: second demultiplexing transistor; DXT3: third demultiplexing transistor; DXT4: fourth demultiplexing transistor; CLA: first demultiplexing control signal; CLB: second demultiplexing control signal; CLC: third demultiplexing control signal; CLD: fourth demultiplexing control signal; TASL1: first detour auxiliary wiring; TASL2: second detour auxiliary wiring. DETAILED DESCRIPTION

[0060] References and Attachments Figure 1 The advantages, features and methods of achieving the advantages and features of the present invention will become clear from the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in different forms. The embodiments are only provided to make the disclosure of the present invention complete and to fully inform the scope of the invention to those skilled in the art. The present invention should be defined only by the scope of the claims.

[0061] The case where an element or layer is located on other elements or layers includes not only the case where it is directly located on other elements, but also the case where there are other layers or other elements in between. Throughout the specification, the same symbol refers to the same constituent element. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings used to illustrate the embodiments are illustrative, and the present invention is not limited to the illustrated cases.

[0062] Although the terms "first" and "second" are used to describe each component, each component is certainly not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical concept of the present invention, the first component mentioned below can also be the second component.

[0063] The various features of the various embodiments of the present invention may be partially or wholly combined or combined with one another, various linkages and drives are technically possible, and the various embodiments may be implemented independently of one another or together in an associated relationship.

[0064] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 It is a perspective view showing a display device according to the embodiment. Figure 2 Yes means Figure 1 A plan view of a display device. Figure 3 Yes means Figure 2 AA′ cross-sectional view.

[0066] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying dynamic images or static images, and can be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic manuals, electronic books, PMPs (portable multimedia players), navigators, UMPCs (Ultra Mobile PCs), but also as a display screen for various products such as televisions, notebooks, monitors, billboards, and Internet of Things (IOT) devices.

[0067] The display device 100 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). The following description will focus on the case where the display device 100 is an organic light-emitting display device. However, the present invention is not limited to this, and can be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0068] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a certain curvature or a varying curvature. In addition, the display device 100 may be formed to be soft so as to be bendable, foldable, curved, foldable, or rollable.

[0069] like Figure 1 , Figure 2 and Figure 3 As shown, the display device 100 includes a substrate 110 .

[0070] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0071] like Figure 2 As shown, the main area MA may include a display area DA arranged in a large part of the center and a non-display area NDA arranged around the display area DA.

[0072] The display area DA may be formed as a rectangular plane having short sides in the first direction DR1 and long sides in the second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display area DA is not limited to a quadrilateral, and may be formed as a polygon other than a quadrilateral, a circle, or an ellipse.

[0073] The non-display area NDA may be disposed at an edge position of the main area MA so as to surround the display area DA.

[0074] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA toward one side of the second direction DR2 .

[0075] By deforming the sub-area SBA so that a part thereof is bent, another part of the sub-area SBA can be disposed on the back side of the display device 100. Figures 1 to 3 The display driving circuit 200 configured in another part of the sub-area SBA, the circuit board 300 partially overlapping with the other part of the sub-area SBA, and the touch driving circuit 400 configured on the circuit board 300 can be configured on the back side of the display device 100.

[0076] Figure 2 and Figure 3 The display device 100 is shown in a state where a portion of the sub-area SBA is bent. The display device 100 may have a certain thickness in a third direction DR3 crossing the first direction DR1 and the second direction DR2.

[0077] Reference Figure 3 The display device 100 according to the embodiment includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and a component layer 130 disposed on the circuit layer 120 .

[0078] The display device 100 according to the embodiment may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140 .

[0079] In addition, the display device 100 according to the embodiment may further include a polarization layer 160 disposed on the touch sensor layer 150 in order to reduce reflection of external light.

[0080] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that is bendable, foldable, or rollable.

[0081] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0082] The substrate 110 may include a main area MA and a sub area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0083] Figure 4 Yes means Figure 2 Layout diagram of Part B.

[0084] Reference Figure 4 The display area DA of the display device 100 according to the embodiment may include a plurality of light-emitting areas EA. In addition, the display area DA may also include a non-light-emitting area ( Figure 7 of NEA).

[0085] A plurality of light-emitting pixel driving parts EPD corresponding to each light-emitting area EA may be arranged in parallel with each other along the first direction DR1 and the second direction DR2 in the display area DA. Each light-emitting pixel driving part EPD may be connected to the light-emitting elements ( Figure 6 LEL) are electrically connected respectively.

[0086] The light emitting area EA may be in a rhombus-shaped or rectangular-shaped plane. However, this is only an example, and the plane shape of the light emitting area EA involved in one embodiment is not limited to Figure 4 That is, the light emitting area EA may have a polygonal shape such as a quadrilateral, a pentagon, a hexagon, or the like, or a circular or elliptical plane shape including a curved edge position.

[0087] The light emitting area EA may include a first light emitting area EA1 emitting a first color light based on a predetermined wavelength band, a second light emitting area EA2 emitting a second color light based on a wavelength band lower than the first color, and a third light emitting area EA3 emitting a third color light based on a wavelength band lower than the second color.

[0088] As an example, the first color may be red based on a wavelength range of 600 nm to 750 nm, the second color may be green based on a wavelength range of 480 nm to 560 nm, and the third color may be blue based on a wavelength range of 370 nm to 460 nm.

[0089] The first light emitting area EA1 and the third light emitting area EA3 may be alternately arranged in at least one direction among the first direction DR1 and the second direction DR2.

[0090] The second light emitting regions EA2 may be arranged parallel to each other in at least one direction among the first direction DR1 and the second direction DR2.

[0091] In addition, the second light emitting region EA2 may be adjacent to the first light emitting region EA1 and the third light emitting region EA3 in diagonal directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2.

[0092] Through the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other among the plurality of light emitting areas EA, pixels PX displaying various brightness and colors can be realized.

[0093] In other words, the pixel PX may be a basic unit for displaying various colors such as white at a predetermined brightness.

[0094] Each pixel PX may include at least one first light emitting area EA1, at least one second light emitting area EA2, and at least one third light emitting area EA3 adjacent to each other. Thus, each pixel PX may display various colors by mixing the light emitted from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other.

[0095] Figure 5 Yes means Figure 3 Block diagram of the circuit layer.

[0096] Reference Figure 5 The circuit layer 120 of the display device 100 according to the embodiment may include a light-emitting pixel driving unit EPD corresponding to each light-emitting area EA of the display area DA and a data wiring DL electrically connected to the light-emitting pixel driving unit EPD.

[0097] The display device 100 according to the embodiment may include a data line DL that transmits a data signal of a light-emitting pixel driving unit EPD. Figure 6 A display driving circuit 200 having a Vdata).

[0098] The display device 100 of the embodiment may further include a gate driving circuit 101 for supplying one or more gate signals to the light-emitting pixel driving unit EPD, and a light-emitting control signal ( Figure 6 The invention also includes a light emitting control circuit 102 for controlling a light emitting pixel driving unit EPD, a timing control unit 500 for controlling a driving timing, and a power supply unit 600 for providing various power supplies and voltages to the light emitting pixel driving unit EPD.

[0099] The timing control section 500 receives an image signal supplied from outside the display device 100 .

[0100] The timing control part 500 may output the image data DATA and the data control signal DCS to the display driving circuit 200 .

[0101] In addition, the timing control unit 500 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101 and a light emission control driving signal ECS for controlling the operation timing of the light emission control circuit 102 .

[0102] For example, the timing control unit 500 can generate a scanning control signal SCS and a light emission control driving signal ECS, output the scanning control signal SCS to the gate driving circuit 101 through the scanning control wiring, and output the light emission control driving signal ECS to the light emission control circuit 102 through the light emission control driving wiring.

[0103] The display driving circuit 200 may convert the image data DATA into an analog data voltage and output the analog data voltage to the data wiring DL.

[0104] The gate driving circuit 101 generates a gate signal according to the scanning control signal SCS, and sequentially outputs the gate signal to the gate wiring GL. The gate wiring GL may include a gate line that transmits a scanning write signal ( Figure 6 GW) scan write wiring ( Figure 6 GWL), transmit scan initialization signal ( Figure 6 GI) scan initialization wiring ( Figure 6 GIL) and pass gate control signals ( Figure 6 Gate control wiring of GC) Figure 6 of GCL).

[0105] The light emission control circuit 102 can sequentially output light emission control signals ( Figure 6 The light emission control signal EC of the light emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. On the other hand, the light emission control circuit 102 may be built into the gate driving circuit 101 instead of being separately provided from the gate driving circuit 101.

[0106] The power supply unit 600 can supply power to the light-emitting pixel driving unit EPD and the light-emitting element ( Figure 6 Various power supplies required to drive the LEL).

[0107] As an example, the power supply unit 600 may supply power for driving the light emitting element ( Figure 6 The first power supply (LEL) Figure 6 ELVDD) and the second power supply ( Figure 6 ELVSS) and an initialization power supply ( Figure 6 Vint).

[0108] Figure 6 Yes means Figure 4 and Figure 5 The equivalent circuit diagram of the light-emitting pixel driving unit is shown.

[0109] Reference Figure 6 In the display device 100 of the embodiment, one light emitting element LEL among the plurality of light emitting elements LEL of the element layer 130 may be electrically connected between one light emitting pixel driving unit EPD among the plurality of light emitting pixel driving units EPD of the circuit layer 120 and the second power source ELVSS.

[0110] That is, the anode of the light emitting element LEL ( Figure 7 131) can be electrically connected to the light-emitting pixel driving unit EPD to the cathode ( Figure 7134) can apply the second power source ELVSS having a voltage level lower than the first power source ELVDD.

[0111] The capacitor Cel connected in parallel with the light emitting element LEL represents a parasitic capacitance between the anode 131 and the cathode 134 .

[0112] The circuit layer 120 may include a first power wiring VDL transferring a first power source ELVDD and an initialization power wiring VIL transferring an initialization power source Vint.

[0113] The circuit layer 120 may further include a scan write wiring GWL transmitting a scan write signal GW, a scan initialization wiring GIL transmitting a scan initialization signal GI, a light emission control wiring ECL transmitting a light emission control signal EC, and a gate control wiring GCL transmitting a gate control signal GC.

[0114] One light emitting pixel driving part EPD in the circuit layer 120 may include a driving transistor DT generating a driving current for driving the light emitting element LEL, transistors ST1 ˜ ST6 electrically connected to the driving transistor DT, and at least one capacitor PC1 .

[0115] The driving transistor DT and the light emitting element LEL are connected in series between the first power source ELVDD and the second power source ELVSS.

[0116] That is, the first electrode (eg, source electrode) of the driving transistor DT may be electrically connected to the first power wiring VDL through the fifth transistor ST5. In addition, the second electrode (eg, drain electrode) of the driving transistor DT may be electrically connected to the anode 131 of the light emitting element LEL through the sixth transistor ST6.

[0117] The first electrode of the driving transistor DT may be electrically connected to the data line DL through the second transistor ST2 .

[0118] The gate electrode of the driving transistor DT may be electrically connected to the first power wiring VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the driving transistor DT and the first power wiring VDL.

[0119] Thereby, the potential of the gate electrode of the driving transistor DT can be maintained at the first power source ELVDD supplied from the first power source wiring VDL.

[0120] In addition, if the data signal Vdata of the data wiring DL is transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2, a voltage difference between the first power source ELVDD and a voltage corresponding to the data signal Vdata may be generated between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT.

[0121] At this time, if the voltage difference between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT (i.e., the gate-source voltage difference) becomes greater than the threshold voltage, the driving transistor DT is turned on, thereby generating a drain-source current of the driving transistor DT corresponding to the data signal Vdata.

[0122] Next, if the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving transistor DT can be connected in series with the light emitting element LEL between the first power wiring VDL and the second power wiring VSL. Thus, the drain-source current of the driving transistor DT corresponding to the data signal Vdata can be supplied as the driving current of the light emitting element LEL.

[0123] Thus, the light emitting element LEL can emit light with brightness corresponding to the data signal Vdata.

[0124] The first transistor ST1 may be electrically connected between a gate electrode of the driving transistor DT and a second electrode of the driving transistor DT. The first transistor ST1 may be turned on according to a scan write signal GW of the scan write wiring GWL. The first transistor ST1 may be composed of a 1-1 transistor ST11 and a 1-2 transistor ST12.

[0125] The second transistor ST2 may be electrically connected between the first electrode of the driving transistor DT and the data wiring DL. The second transistor ST2 may be turned on according to the scan write signal GW of the scan write wiring GWL.

[0126] The third transistor ST3 may be connected between the gate electrode of the driving transistor DT and the initialization power wiring VIL. The third transistor ST3 may be turned on according to the scanning initialization signal GI of the scanning initialization wiring GIL. The third transistor ST3 may be composed of a 3-1 transistor ST31 and a 3-2 transistor ST32.

[0127] The fourth transistor ST4 may be electrically connected between the anode 131 of the light emitting element LEL and the initialization power wiring VIL. The fourth transistor ST4 may be turned on according to the gate control signal GC of the gate control wiring GCL.

[0128] The fifth transistor ST5 may be electrically connected between the first electrode of the driving transistor DT and the first power wiring VDL.

[0129] The sixth transistor ST6 may be electrically connected between the second electrode of the driving transistor DT and the anode 131 of the light emitting element LEL.

[0130] The fifth transistor ST5 and the sixth transistor ST6 may be turned on according to the light emission control signal EC of the light emission control wiring ECL.

[0131] like Figure 6 As shown, the driving transistor DT and the first transistor ST1 to the sixth transistor T6 can be set as P-type MOSFET. However, this is only an example, and the driving transistor DT and a part of the first transistor ST1 to the sixth transistor T6 can also be set as N-type MOSFET. As an example, the first transistor ST1 and the third transistor ST3 can be set as N-type MOSFET.

[0132] Figure 7 Yes means Figure 6 A cross-sectional view of the driving transistor, the sixth transistor and the light emitting element is shown.

[0133] Reference Figure 7 The display device 100 involved in the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110, a component layer 130 on the circuit layer 120, a sealing layer 140 on the component layer 130, and a touch sensor layer 150 on the sealing layer 140.

[0134] In addition, the display device 100 according to the embodiment may further include a polarization layer 160 disposed on the touch sensor layer 150 .

[0135] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may include polyimide.

[0136] The circuit layer 120 may include a plurality of light emitting pixel driving parts EPD electrically connected to the plurality of light emitting elements LEL disposed in the light emitting area EA, respectively.

[0137] The light emitting pixel driving unit EPD may include a driving transistor DT and transistors ST1 ˜ ST6 electrically connected to the driving transistor DT.

[0138] According to an embodiment, the driving transistor DT and the transistors ST1 to ST6 may respectively include a channel region, a source region, a drain region formed of a semiconductor layer, and a gate electrode formed of a first gate conductive layer on a first gate insulating layer 122 covering the semiconductor layer.

[0139] The source region and the drain region may be connected to both sides of the channel region, respectively. The source region and the drain region may have higher conductivity than the channel region.

[0140] The gate electrode overlaps the channel region.

[0141] The first capacitor PC1 of the light emitting pixel driving part EPD may be provided as an overlap region between the gate electrode GEDT of the driving transistor DT and the capacitor electrode CAE. The capacitor electrode CAE may be formed of a second gate conductive layer on the second gate insulating layer 123 covering the first gate conductive layer.

[0142] The anode 131 of the element layer 130 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2 .

[0143] The first anode connection electrode ANDE1 may be formed of a first source-drain conductive layer (hereinafter, referred to as ANDE1) on the interlayer insulating layer 124 covering the second gate conductive layer. Such a first anode connection electrode ANDE1 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through a first anode contact hole ANCT1 penetrating the interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0144] The second anode connection electrode ANDE2 may be formed of a second source-drain conductive layer (hereinafter, referred to as ANDE2) on the first planarization layer 125 covering the first source-drain conductive layer. Such second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 penetrating the first planarization layer 125.

[0145] The anode 131 of the element layer 130 may be disposed on the second planarization layer 126 covering the second source-drain conductive layer. The anode 131 may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second planarization layer 126 .

[0146] In other words, the circuit layer 120 may include a buffer layer 121 configured on the substrate 110, a semiconductor layer CADT, SADT, DADT, CA6, SA6, DA6 configured on the buffer layer 121, a first gate insulating layer 122 covering the semiconductor layer CADT, SADT, DADT, CA6, SA6, DA6, a first gate conductive layer GEDT, GE6 configured on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer GEDT, GE6, a second gate conductive layer CAE configured on the second gate insulating layer 123, an interlayer insulating layer 124 covering the second gate conductive layer CAE, a first source-drain conductive layer ADNE1 configured on the interlayer insulating layer 124, a first planarizing layer 125 covering the first source-drain conductive layer ADNE1, a second source-drain conductive layer ANDE2 configured on the first planarizing layer 125, and a second planarizing layer 126 covering the second source-drain conductive layer ANDE2.

[0147] The buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 may be formed of at least one inorganic film. As an example, the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 may be formed of a multi-film in which one or more inorganic films of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0148] The first planarization layer 125 and the second planarization layer 126 may be formed of organic films such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0149] The semiconductor layers CADT, SADT, DADT, CA6, SA6, and DA6 may be formed of a semiconductor material selected from the group consisting of polysilicon (Poly Silicon), single crystal silicon, and oxide semiconductor.

[0150] The channel regions CADT, CA6 overlapping the gate electrodes GEDT, GE6 in the semiconductor layers CADT, SADT, DADT, CA6, SA6, DA6 can maintain semiconductor characteristics, and the remaining source regions SADT, SA6 and drain regions DADT, DA6 can be made conductive.

[0151] The first gate conductive layer GEDT, GE6, the second gate conductive layer CAE, the first source and drain conductive layer ADNE1 and the second source and drain conductive layer ADNE2 can be formed by multiple layers of more than two of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), respectively.

[0152] The element layer 130 may include a light emitting element LEL disposed in each light emitting area EA and a pixel definition film 132 .

[0153] Each light emitting element LEL may include an anode 131 and a cathode 134 facing each other and a light emitting layer 133 disposed therebetween. Alternatively, each light emitting element LEL may further include a first common layer 135 disposed between the anode 131 and the light emitting layer 133 and a second common layer 136 disposed between the light emitting layer 133 and the cathode 134.

[0154] The first common layer 135 may include a hole transport layer. Alternatively, the first common layer 135 may further include a hole injection layer between the anode 131 and the hole transport layer.

[0155] The light emitting layer 133 on the first common layer 135 may be disposed in each light emitting area EA. The light emitting layer 133 of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may include different materials or different contents of organic light emitting materials from each other.

[0156] As an example, the light emitting layer 133 may be formed of an organic light emitting material that converts electron-hole pairs into light. The organic light emitting material may include a host substance and a dopant. The dopant may include a phosphorescent substance or a fluorescent substance.

[0157] The second common layer 136 under the cathode 134 may be disposed in the entire display area DA including the emission area EA. The second common layer 136 may include an electron transport layer. Alternatively, the second common layer 136 may further include an electron injection layer between the cathode 134 and the electron transport layer.

[0158] The sealing layer 140 may be disposed on the circuit layer 120 and cover the device layer 130 .

[0159] The sealing layer 140 may include a first sealing layer 141 configured on the element layer 130 and formed of an inorganic insulating material, a second sealing layer 142 configured on the first sealing layer 141 and overlapping with the element layer 130 and formed of an organic insulating material, and a third sealing layer 143 configured on the first sealing layer 141 and covering the second sealing layer 142 and formed of an inorganic insulating material.

[0160] The second sealing layer 142 may be formed of an organic insulating material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0161] Figure 8 It means that the embodiment involves Figure 2 A plan view of the substrate.

[0162] Reference Figure 8 The substrate 110 of the display device 100 according to the embodiment includes a main area MA corresponding to a display surface and a sub-area SBA protruding from one side of the main area MA.

[0163] The main area MA includes a display area DA arranged in the central majority and a non-display area NDA arranged at an edge position and surrounding the display area DA.

[0164] The display area DA may include an adjacent area ADJA facing the sub-area SBA in the second direction DR2 and a separation area DSTA disposed between the adjacent area ADJA and the non-display area NDA in the first direction DR1 .

[0165] The display area DA may include a plurality of separation areas DSTA respectively connected to both sides of the adjacent area ADJA in the first direction DR1.

[0166] The non-display area NDA may include a gate driving circuit area GDRA where a gate driving circuit 101 and a light emitting control circuit 102 are configured.

[0167] The gate driving circuit area GDRA may be disposed in a portion adjacent to at least one side of the display area DA along the first direction DR1 in the non-display area NDA.

[0168] The sub-region SBA may include a bending region BA deformed into a curved shape, a first sub-region SB1 disposed between one side of the bending region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bending region BA.

[0169] If the bending area BA is deformed into a curved shape, the second sub-area SB2 is disposed below the substrate 110 and overlaps with the main area MA.

[0170] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0171] The signal pad SPD bonded to the circuit board 300 may be disposed at one side edge position of the second sub-region SB2 .

[0172] Fig. 9 It means that the embodiment involves Figure 8 Layout diagram of part C. Fig.10 Yes means Fig. 9 The timing diagram of the first demultiplexing control signal and the second demultiplexing control signal is shown.

[0173] Reference Fig. 9 The display driving circuit 200 of the display device 100 according to the embodiment may be configured in the sub-region SBA of the substrate 110 .

[0174] The display driving circuit 200 may be disposed in the second sub-region SB2 of the sub-region SBA. Thus, if the bending region BA of the sub-region SBA is deformed into a curved shape, the display driving circuit 200 may be disposed together with the second sub-region SB2 on the rear surface of the substrate 110 and overlap the main region MA of the substrate 110 .

[0175] The data wirings DL of the circuit layer 120 of the display device 100 according to the embodiment may include first data wirings DL1 arranged in the adjacent area ADJA and second data wirings DL2 arranged in the separated area DSTA.

[0176] Among the first data wiring DL1 and the second data wiring DL2 , the first data wiring DL1 may be disposed closer to the sub-region SBA.

[0177] As an example, the first data wiring DL1 may face the sub-area SBA in the second direction DR2 or be adjacent to the sub-area SBA within a critical distance. In addition, the second data wiring DL2 may be adjacent to the non-display area NDA in the first direction DR1.

[0178] As described above, the first data wiring DL1 may be disposed adjacent to the sub-area SBA, so that a path for transmitting a data signal to the first data wiring DL1 (hereinafter, referred to as a 'transmission path') may be shorter than the first extension length.

[0179] In contrast, the second data wiring DL2 may be farther away from the sub-area SBA than the first data wiring DL1 , so that a transfer path of a data signal of the second data wiring DL2 may be longer than the first extension length.

[0180] That is, the data signal of the second data wiring DL2 can be supplied via a relatively long transmission path longer than the first extension length compared to the data signal of the first data wiring DL1. Therefore, the data signal of the second data wiring DL2 is more easily distorted due to delay or voltage drop than the data signal of the first data wiring DL1.

[0181] As an example, the first extension length may be selected as one of a median value and an average value of the transmission paths of the plurality of data wirings DL. As another example, the first extension length may also be selected as a critical value at which the difference between the data signal at the time point at which it reaches the data wiring DL and the data signal at the time point at which it is output from the output buffer of the display driving circuit 200 affects the brightness.

[0182] The display device 100 according to the embodiment may include a demultiplexing circuit DMC for classifying the transmission paths between the display driving circuit 200 and the data lines DL according to the extension lengths in order to facilitate the compensation of the transmission paths having a length longer than the first extension length.

[0183] According to an embodiment, the demultiplexing circuit DMC may be configured in the sub-area SBA of the substrate 110 together with the display driving circuit 200 .

[0184] As an example, the demultiplexing circuit DMC may be disposed in the second sub-region SB2 in the sub-region SBA. That is, the demultiplexing circuit DMC may be disposed between the display driving circuit 200 and the bending area BA.

[0185] That is, the display device 100 according to the embodiment may further include a demultiplexing circuit DMC electrically connected between the display driving circuit 200 and the data wiring DL of the circuit layer 120 .

[0186] According to an embodiment, the demultiplexing circuit DMC may include a first demultiplexing control signal ( Fig.10 The first demultiplexing transistor DXT1 is turned on by the CLA) and the second demultiplexing control signal ( Fig.10 The second demultiplexing transistor DXT2 is turned on by CLB).

[0187] The first data wiring DL1 may be electrically connected to the display driving circuit 200 through the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC and a transfer path smaller than the first extension length.

[0188] The second data wiring DL2 may be electrically connected to the display driving circuit 200 via the second demultiplexing transistor DXT2 of the demultiplexing circuit DMC and a transmission path having a first extension length or more.

[0189] According to an embodiment, the circuit layer 120 may further include a data supply wiring DSPL extending from the sub-area SBA toward the display area DA and electrically connected between the data wiring DL and the demultiplexing circuit DMC.

[0190] The transfer path of the first data wiring DL1 may include the first data supply wiring DSPL1 electrically connected between the first demultiplexing transistor DXT1 and the first data wiring DL1 among the data supply wirings DSPL.

[0191] As an example, the first data supply wiring DSPL1 may include a first data output wiring DOPL1 extending from the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC toward the bending area BA, a first data bending wiring DBDL1 extending from the first data output wiring DOPL1 toward the first sub-area SB1, and a first data extension wiring DEXL1 extending from the first data bending wiring DBDL1 toward the first data wiring DL1. That is, the first data output wiring DOPL1 may be arranged in the second sub-area SB2, the first data bending wiring DBDL1 may be arranged in the bending area BA, and the first data extension wiring DEXL1 may be arranged in the first sub-area SB1 and the non-display area NDA.

[0192] As an example, the first data bending wiring DBDL1 may be disposed in the second source-drain conductive layer ANDE2 on the first planarization layer 125 or in the third source-drain conductive layer (not shown) on the second planarization layer 126 .

[0193] In addition, the first data output wiring DOPL1 and the first data extension wiring DEXL1 may be disposed in the first gate conductive layer GEDT, GE6 or the second gate conductive layer CAE covered by the interlayer insulating layer 124 .

[0194] The transfer path of the second data wiring DL2 may include the second data supply wiring DSPL2 electrically connected between the second demultiplexing transistor DXT2 and the second data wiring DL2 among the data supply wiring DSPL.

[0195] As an example, the second data supply wiring DSPL2 may include a second data output wiring DOPL2 extending from the second demultiplexing transistor DXT2 of the demultiplexing circuit DMC toward the bending area BA, a second data bending wiring DBDL2 extending from the second data output wiring DOPL2 toward the first sub-area SB1, and a second data extension wiring DEXL2 extending from the second data bending wiring DBDL2 toward the second data wiring DL2. That is, the second data output wiring DOPL2 may be configured in the second sub-area SB2, the second data bending wiring DBDL2 may be configured in the bending area BA, and the second data extension wiring DEXL2 may be configured in the first sub-area SB1 and the non-display area NDA.

[0196] As an example, the second data bending wiring DBDL2 may be disposed in the second source-drain conductive layer ANDE2 on the first planarization layer 125 or the third source-drain conductive layer on the second planarization layer 126 .

[0197] In addition, the second data output wiring DOPL2 and the second data extension wiring DEXL2 may be disposed in the first gate conductive layer GEDT, GE6 or the second gate conductive layer CAE covered by the interlayer insulating layer 124 .

[0198] According to an embodiment, the circuit layer 120 may further include a first power supply wiring VDSPL disposed in the non-display area NDA and transmitting the first power source ELVDD and a second power supply wiring VSSPL transmitting the second power source ELVSS.

[0199] The first power supply wiring VDSPL and the second power supply wiring VSSPL may extend from the respective signal pads SPD of the second sub-area SB2 toward the non-display area NDA, respectively.

[0200] The display driving circuit 200 may supply the first demultiplexing control signal CLA to the first demultiplexing control wiring CLAL, and supply the second demultiplexing control signal CLB to the second demultiplexing control wiring CLBL.

[0201] Reference Fig.10 The output buffer OPBF of the display driving circuit 200 can output the data signal of the light-emitting pixel driving unit EPD during each image frame period (n)-th_H, (n+1)-th_H (here, n is a natural number greater than 1).

[0202] The first demultiplexing control signal CLA may be supplied in a first period AT in each image frame period (n)-th_H, (n+1)-th_H. The second demultiplexing control signal CLB may be supplied in a second period BT after the first period AT in each image frame period (n)-th_H, (n+1)-th_H.

[0203] That is, the data signal of the first data wiring DL1 can be transmitted to the first data supply wiring DSPL1 in the first period AT in each image frame period (n)-th_H, (n+1)-th_H through the first demultiplexing transistor DXT1 turned on according to the first demultiplexing control signal CLA.

[0204] In addition, the data signal of the second data wiring DL2 can be transmitted to the second data supply wiring DSPL2 in the second period BT after the first period AT in each image frame period (n)-th_H, (n+1)-th_H through the second demultiplexing transistor DXT2 turned on according to the second demultiplexing control signal CLB.

[0205] Thus, the display driving circuit 200 can output the data signal of the first data wiring DL1 in the first period AT, and output the data signal of the second data wiring DL2 transmitted to the transmission path having the first extension length or longer in the second period BT after the first period AT.

[0206] That is, according to the embodiment, the display driving circuit 200 outputs the data signal of the first data wiring DL1 and the data signal of the second data wiring DL2 at different periods from each other.

[0207] Therefore, the display driving circuit 200 can output the data signal of the second data wiring DL2 to which the compensation value corresponding to the first extension length is applied in the second period BT based on the data control signal DCS of the timing control unit 500 .

[0208] That is, the data signal of the second data wiring DL2 may be different from the data signal of the first data wiring DL1 and may include a compensation value corresponding to the first extension length.

[0209] According to an embodiment, the compensation value may be applied by increasing the voltage level of the data control signal DCS of the timing control unit 500 according to the grayscale of the data signal or by extending the output period of the data signal.

[0210] As described above, even if the display driving circuit 200 does not include a compensation circuit associated with a relatively long transmission path, a compensation value corresponding to the first extension length can be applied to the data signal of the second data wiring DL2 transmitted to the transmission path longer than the first extension length.

[0211] Thus, even without changing the display driving circuit 200, it is possible to prevent the display quality from being degraded due to distortion of the data signal caused by the relatively long transmission path, thereby facilitating higher resolution and larger size without affecting the thinning of the display device 100 and the reduction of manufacturing costs.

[0212] on the other hand, Fig.10 The second period BT is arranged directly after the first period AT and a short blank period BK is included after the first period AT and the second period BT, but this is only an example. As an example, a waiting period may be further arranged between the first period AT and the second period BT.

[0213] Fig.11 FIG. 1 is a diagram showing an example in which a gamma curve is applied to the compensation value according to the embodiment.

[0214] Reference Fig.11 The display driving circuit 200 of the embodiment can generate the data signal of the first data wiring DL1 based on the general gamma curve GC. On the contrary, when generating the data signal of the second data wiring DL2, the display driving circuit 200 can be based on the compensation gamma curve CC having a higher slope and a voltage level of the highest grayscale than the general gamma curve GC.

[0215] The voltage level CC_max of the highest grayscale of the compensation gamma curve CC is higher than the voltage level GC_max of the highest grayscale of the general gamma curve GC.

[0216] That is, the highest grayscale voltage level CC_max of the data signal of the second data wiring DL2 may be higher than the highest grayscale voltage level GC_max of the data signal of the first data wiring DL1 according to the compensation value corresponding to the first extension length.

[0217] Thus, distortion of the data signal of the second data wiring DL2 based on the transmission path having the first extension length or longer can be compensated in advance, thereby preventing degradation of image quality caused by the transmission path having the first extension length or longer.

[0218] Fig.12 This is a diagram showing an example in which the compensation value according to the embodiment is applied to the first period and the second period.

[0219] Reference Fig.12 The display driving circuit 200 involved in the embodiment can adjust the length of the second period BT′ of the data signal output to the second data wiring DL2 of the transmission path longer than the first extension length to be longer than the length of the first period AT′ of the data signal output to the first data wiring DL1 according to the data control signal DCS of the timing control unit 500.

[0220] Therefore, even if the data signal of the second data wiring DL2 is delayed compared with the data signal of the first data wiring DL1 due to the transmission path longer than the first extension length, the data signal of the second data wiring DL2 can be less distorted because the data signal is supplied during the relatively long second period BT′.

[0221] on the other hand, Fig. 9 The demultiplexing circuit DMC is shown as including two demultiplexing transistors DXT1 and DXT2 , but this is merely an example, and the demultiplexing circuit DMC may include three or more demultiplexing transistors.

[0222] Fig.13 It means that an embodiment involves Figure 8 Layout diagram of part C. Fig.14 Yes means Fig.13 The timing diagram of the first demultiplexing control signal, the second demultiplexing control signal and the third demultiplexing control signal is shown.

[0223] Reference Fig.13 The display device 100 according to one embodiment is similar to the display device 100 in that the demultiplexing circuit DMC further includes a third demultiplexing transistor DXT3 and the data wiring DL of the circuit layer 120 further includes a third data wiring DL3. Figures 1 to 12 The display device 100 of the illustrated embodiment is substantially the same, and thus repeated descriptions are omitted below.

[0224] According to one embodiment, the display area DA of the substrate 110 may include an adjacent area ADJA facing at least a portion of the sub-area SBA in the second direction DR2 and first and second separation areas DSTA1 and DSTA2 arranged between the adjacent area ADJA and the non-display area NDA in the first direction DR1.

[0225] The adjacent area ADJA may face a central portion of the sub-area SBA in the first direction DR1.

[0226] The first separated area DSTA1 may be disposed between the adjacent area ADJA and the second separated area DSTA2. The first separated area DSTA1 may face one side portion of the sub-area SBA in the first direction DR1.

[0227] The second separation area DSTA2 may be disposed between the first separation area DSTA1 and the non-display area NDA. The second separation area DSTA2 may be disposed adjacent to a bent corner of the substrate 110 .

[0228] According to an embodiment, the data wirings DL of the circuit layer 120 may include a first data wiring DL1 arranged in the adjacent area ADJA, a second data wiring DL2 arranged in the first separated area DSTA1, and a third data wiring DL3 arranged in the second separated area DSTA2.

[0229] Among the first data wiring DL1, the second data wiring DL2 and the third data wiring DL3, the first data wiring DL1 can be configured to be closest to the central portion of the sub-area SBA in the first direction DR1, and the third data wiring DL3 can be configured to be farthest from the sub-area SBA and closest to the non-display area NDA in the first direction DR1.

[0230] Thus, the transmission path of the first data wiring DL1 may be shorter than the first extension length, the transmission path of the second data wiring DL2 may be longer than the first extension length and shorter than the second extension length, and the transmission path of the third data wiring DL3 may be longer than the second extension length.

[0231] According to an embodiment, in order to implement compensation for a transfer path shorter than the second extension length and compensation for a transfer path longer than the second extension length in different ways, the demultiplexing circuit DMC includes not only the first demultiplexing transistor DXT1 and the second demultiplexing transistor DXT2, but also a third demultiplexing control signal ( Fig.14 The third demultiplexing transistor DXT3 is turned on by CLC).

[0232] According to an embodiment, the first data wiring DL1 may be electrically connected to the display driving circuit 200 through the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC and a transfer path smaller than the first extension length.

[0233] The second data wiring DL2 may be electrically connected to the display driving circuit 200 through the second demultiplexing transistor DXT2 of the demultiplexing circuit DMC and a transmission path longer than the first extension length and shorter than the second extension length.

[0234] The third data wiring DL3 may be electrically connected to the display driving circuit 200 via the third demultiplexing transistor DXT3 of the demultiplexing circuit DMC and a transmission path having a second extension length or more.

[0235] The transfer path of the third data wiring DL3 may include a third data supply wiring DSPL3 electrically connected between the third demultiplexing transistor DXT3 and the third data wiring DL3 among the data supply wiring DSPL.

[0236] As an example, the third data supply wiring DSPL3 may include a third data output wiring DOPL3 extending from the third demultiplexing transistor DXT3 of the demultiplexing circuit DMC toward the bending area BA, a third data bending wiring DBDL3 extending from the third data output wiring DOPL3 toward the first sub-area SB1, and a third data extension wiring DEXL3 extending from the third data bending wiring DBDL3 toward the third data wiring DL3. That is, the third data output wiring DOPL3 may be configured in the second sub-area SB2, the third data bending wiring DBDL3 may be configured in the bending area BA, and the third data extension wiring DEXL3 may be configured in the first sub-area SB1 and the non-display area NDA.

[0237] As an example, the third data bending wiring DBDL3 may be disposed in the second source-drain conductive layer ANDE2 on the first planarization layer 125 or the third source-drain conductive layer on the second planarization layer 126 .

[0238] In addition, the third data output wiring DOPL3 and the third data extension wiring DEXL3 may be disposed in the first gate conductive layer GEDT, GE6 or the second gate conductive layer CAE covered by the interlayer insulating layer 124 .

[0239] Reference Fig.14 The third demultiplexing control signal CLC may be supplied in a third period CT after the second period BT in each of the image frame periods (n)-th_H and (n+1)-th_H.

[0240] Thus, the data signal of the third data wiring DL3 can be supplied to the third data supply wiring DSPL3 in the third period CT after the second period BT in each image frame period (n)-th_H, (n+1)-th_H through the third demultiplexing transistor DXT3 turned on according to the third demultiplexing control signal CLC.

[0241] Therefore, the display driving circuit 200 can output the data signal of the third data wiring DL3 to which the compensation value corresponding to the second extension length is applied in the third period CT based on the data control signal DCS of the timing control unit 500 .

[0242] The compensation value may be applied by increasing the voltage level of the data control signal DCS of the timing control unit 500 in accordance with the grayscale of the data signal or by extending the output period of the data signal.

[0243] Fig.15 It means that an embodiment involves Figure 8 Layout diagram of part C. Fig.16 Yes means Fig.15 The timing diagram of the first demultiplexing control signal, the second demultiplexing control signal, the third demultiplexing control signal and the fourth demultiplexing control signal is shown.

[0244] Reference Fig.15 The display device 100 according to the embodiment is similar to the display device 100 according to the embodiment except that the demultiplexing circuit DMC further includes a fourth demultiplexing transistor DXT4 and the data wiring DL of the circuit layer 120 further includes a fourth data wiring DL4. Fig.13 and Fig.14 The display device 100 of the embodiment shown is substantially the same, and thus repeated descriptions are omitted below.

[0245] According to an embodiment, the display area DA of the substrate 110 may further include a third separation area DSTA3 disposed between the second separation area DSTA2 and the non-display area NDA.

[0246] The second isolated area DSTA2 may be disposed between the first isolated area DSTA1 and the third isolated area DSTA3 .

[0247] The third spaced apart area DSTA3 may be disposed closer to the bent corner of the substrate 110 than the second spaced apart area DSTA2 .

[0248] According to an embodiment, the data wiring DL of the circuit layer 120 may further include a fourth data wiring DL4 disposed in the third isolated area DSTA3 .

[0249] Among the first, second, third, and fourth data wirings DL1, DL2, DL3, and DL4, the fourth data wiring DL4 may be disposed farthest from the sub-area SBA and closest to the non-display area NDA in the first direction DR1.

[0250] Thus, the transmission path of the third data wiring DL3 may be longer than the second extension length and shorter than the third extension length. In addition, the transmission path of the fourth data wiring DL4 may be longer than the third extension length.

[0251] According to an embodiment, in order to implement compensation for a transfer path shorter than the third extension length and compensation for a transfer path longer than the third extension length in different ways, the demultiplexing circuit DMC may further include a fourth demultiplexing control signal ( Fig.16 The fourth demultiplexing transistor DXT4 is turned on by CLD).

[0252] The third data wiring DL3 may be electrically connected to the display driving circuit 200 through the third demultiplexing transistor DXT3 of the demultiplexing circuit DMC and a transmission path that is greater than the second extension length and less than the third extension length.

[0253] The fourth data wiring DL4 may be electrically connected to the display driving circuit 200 via the fourth demultiplexing transistor DXT4 of the demultiplexing circuit DMC and a transmission path having a third extension length or more.

[0254] The transfer path of the fourth data wiring DL4 may include a fourth data supply wiring DSPL4 electrically connected between the fourth demultiplexing transistor DXT4 and the fourth data wiring DL4 among the data supply wiring DSPL.

[0255] As an example, the fourth data supply wiring DSPL4 may include a fourth data output wiring DOPL4 extending from the fourth demultiplexing transistor DXT4 of the demultiplexing circuit DMC toward the bending area BA, a fourth data bending wiring DBDL4 extending from the fourth data output wiring DOPL4 toward the first sub-area SB1, and a fourth data extension wiring DEXL4 extending from the fourth data bending wiring DBDL4 toward the fourth data wiring DL4. That is, the fourth data output wiring DOPL4 may be configured in the second sub-area SB2, the fourth data bending wiring DBDL4 may be configured in the bending area BA, and the fourth data extension wiring DEXL4 may be configured in the first sub-area SB1 and the non-display area NDA.

[0256] As an example, the fourth data bending wiring DBDL4 may be disposed in the second source-drain conductive layer ANDE2 on the first planarization layer 125 or the third source-drain conductive layer on the second planarization layer 126 .

[0257] In addition, the fourth data output wiring DOPL4 and the fourth data extension wiring DEXL4 may be disposed in the first gate conductive layer GEDT, GE6 or the second gate conductive layer CAE covered by the interlayer insulating layer 124 .

[0258] Reference Fig.16 The fourth demultiplexing control signal CLD may be supplied in a fourth period DT after the third period CT in each of the image frame periods (n)-th_H and (n+1)-th_H.

[0259] Thus, the data signal of the fourth data wiring DL4 can be transmitted to the fourth data supply wiring DSPL4 in the fourth period DT after the third period CT in each image frame period (n)-th_H, (n+1)-th_H through the fourth demultiplexing transistor DXT4 turned on according to the fourth demultiplexing control signal CLD.

[0260] Therefore, the display driving circuit 200 can output the data signal of the fourth data wiring DL4 to which the compensation value corresponding to the third extension length is applied in the fourth period DT based on the data control signal DCS of the timing control unit 500 .

[0261] The compensation value may be applied by increasing the voltage level of the data control signal DCS of the timing control unit 500 in accordance with the grayscale of the data signal or by extending the output period of the data signal.

[0262] On the other hand, as the number of data lines DL increases with higher resolution or larger size, the number of data supply lines DSPL arranged in the non-display area NDA also increases, so that the reduction in the width of the non-display area NDA may be limited.

[0263] The following other embodiments provide a display device 100 that can reduce the width of the non-display area NDA.

[0264] Fig.17 It means that other embodiments involve Figure 2 A plan view of the substrate. Fig.18 Yes means Fig.17 Layout diagram of Section D. Fig.19 Yes means Fig.18 Cross-sectional view of EE′.

[0265] Reference Fig.17 The display area DA of the substrate 110 of the display device 100 according to other embodiments includes a detour area DEA disposed on one side adjacent to the sub-area SBA and a general area GA disposed in the remaining area except the detour area DEA. Figure 8 The embodiments shown are substantially the same, and therefore repeated descriptions are omitted below.

[0266] According to other embodiments, the detour area DEA arranged on one side of the second direction DR2 adjacent to the sub-area SBA in the display area DA may include a central detour middle area MDDA arranged in the first direction DR1, and a first detour side area SDA1 and a second detour side area SDA2 arranged between the detour middle area MDDA and the non-display area NDA in the first direction DR1.

[0267] The first detour lateral area SDA1 may be connected to one side of the detour middle area MDDA, and may be arranged between the detour middle area MDDA and the second detour lateral area SDA2.

[0268] The second detour lateral area SDA2 may be connected to the non-display area NDA, and may be disposed between the first detour lateral area SDA1 and the non-display area NDA.

[0269] The second roundabout lateral area SDA2 may be disposed closer to the bent corner of the substrate 110 than the roundabout middle area MDDA and the first roundabout lateral area SDA1 .

[0270] The first and second detour lateral areas SDA1 and SDA2 may be disposed between each of both sides of the detour middle area MDDA in the first direction DR1 and the non-display area NDA.

[0271] In the display area DA, the general area GA arranged between the detour area DEA and the non-display area NDA in the second direction DR2 may include a general middle area GMA connected to the detour middle area MDDA of the detour area DEA in the second direction DR2, a first general side area GSA1 connected to the first detour side area SDA1 of the detour area DEA in the second direction DR2, and a second general side area GSA2 connected to the second detour side area SDA2 of the detour area DEA in the second direction DR2.

[0272] Reference Fig.18 In the display device 100 according to other embodiments, except that the second data wiring DL2 is electrically connected to the second data supply wiring DSPL2 through the first auxiliary detour wiring TASL1 and the second auxiliary detour wiring TASL2 arranged in the display area DA, Figures 1 to 12 The embodiments shown are substantially the same, and therefore repeated descriptions are omitted below.

[0273] According to other embodiments, the data wiring DL may include a first data wiring DL1 arranged in the first detour lateral area SDA1 and a second data wiring DL2 arranged in the second detour lateral area SDA2.

[0274] That is, among the first data wiring DL1 and the second data wiring DL2 , the first data wiring DL1 may be arranged closer to the sub-area SBA, and the second data wiring DL2 may be arranged closer to the non-display area NDA in the first direction DR1 .

[0275] According to other embodiments, the data supply wiring DSPL may extend toward the detour middle area MDDA and the first detour side area SDA1 adjacent to the sub-area SBA.

[0276] That is, among the data supply wirings DSPL, the first data supply wiring DSPL1 transmitting the data signal of the first data wiring DL1 arranged in the first detour lateral area SDA1 may extend toward the first detour lateral area SDA1 and be directly electrically connected to the first data wiring DL1 .

[0277] On the contrary, among the data supply wiring DSPL, the second data supply wiring DSPL2 that transmits the data signal of the second data wiring DL2 arranged in the second detour side area SDA2 may extend toward the first detour side area SDA1 instead of extending toward the second detour side area SDA2. In addition, the second data supply wiring DSPL2 may be electrically connected to the second data wiring DL2 through the first detour auxiliary wiring TASL1 and the second detour auxiliary wiring TASL2 arranged in the detour area DEA of the display area DA.

[0278] The first auxiliary bypass wiring TASL1 may be disposed in the bypass area DEA of the display area DA, extend in the first direction DR1 intersecting the data wiring DL, and be electrically connected to the second data wiring DL2.

[0279] The second auxiliary bypass wiring TASL2 may extend in the second direction DR2 in parallel with the data wiring DL, form a pair with the first data wiring DL1, and be electrically connected between the first auxiliary bypass wiring TASL1 and the second data supply wiring DSPL2.

[0280] Since the second auxiliary bypass wiring TASL2 is paired with the first data wiring DL1, it can be arranged in the first lateral bypass area SDA1 together with the first data wiring DL1. Thus, the second data supply wiring DSPL2 can extend toward the first lateral bypass area SDA1 and be electrically connected to the second auxiliary bypass wiring TASL2.

[0281] As described above, the second data supply wiring DSPL2 is not directly electrically connected to the second data wiring DL2, and therefore may not extend toward the second detour lateral area SDA2 adjacent to the bent corner of the substrate 110. Thus, the extension length of the second data supply wiring DSPL2 may be reduced, and thus the width of the non-display area NDA may be reduced.

[0282] Furthermore, the first data wiring DL1 may be electrically connected to the demultiplexing circuit DMC and the display driving circuit 200 through the first data supply wiring DSPL1. Thus, the transmission path of the data signal of the first data wiring DL1 may be shorter than the first extension length.

[0283] In other words, the first data wiring DL1 may be electrically connected to the display driving circuit 200 through the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC and a transmission path smaller than the first extension length.

[0284] Different from this, the second data wiring DL2 can be electrically connected to the demultiplexing circuit DMC and the display driving circuit 200 through the first auxiliary detour wiring TASL1, the second auxiliary detour wiring TASL2 and the second data supply wiring DSPL2. Therefore, the transmission path of the data signal of the second data wiring DL2 can be longer than the first extension length.

[0285] That is, the second data wiring DL2 may be electrically connected to the display driving circuit 200 via the second demultiplexing transistor DXT2 of the demultiplexing circuit DMC and a transmission path having a first extension length or more.

[0286] The data wiring DL may further include a third data wiring DL3 disposed in the meandering middle area MDDA.

[0287] Among the data supply wirings DSPL, the third data supply wiring DSPL3 transmitting the data signal of the third data wiring DL3 may extend toward the detour middle area MDDA and be directly electrically connected to the third data wiring DL3.

[0288] like Fig.18 As shown, the third data supply wiring DSPL3 may be not connected to the demultiplexing circuit DMC but may be directly electrically connected to the display driving circuit 200. However, this is merely an example, and the third data supply wiring DSPL3 may also be electrically connected to the demultiplexing circuit DMC.

[0289] As an example, the third data wiring DL3 can be directly electrically connected to the third data supply wiring DSPL3, so it can be predicted that the transmission path of the data signal of the third data wiring DL3 is shorter than the first extension length. Therefore, the third data supply wiring DSPL3 can also be electrically connected to the display driving circuit 200 through the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC like the first data supply wiring DSPL1.

[0290] On the other hand, according to other embodiments, the first detour auxiliary wiring TASL1 can be configured between the second data wiring DL2 and the second detour auxiliary wiring TASL2, and the second detour auxiliary wiring TASL2 can be configured between the first detour auxiliary wiring TASL1 and the second data supply wiring DSPL2 while being paired with the first data wiring DL1.

[0291] As described above, as the first and second auxiliary detour wirings TASL1 and TASL2 are limitedly arranged in the detour area DEA, the ends of the first and second auxiliary detour wirings TASL1 and TASL2 are arranged in a predetermined rule. Thus, the first and second auxiliary detour wirings TASL1 and TASL2 may be more recognizable.

[0292] In order to prevent the above situation, according to other embodiments, the circuit layer 120 may also include a plurality of second power auxiliary horizontal wirings VSAHL arranged in the general area GA and extending in the first direction DR1, and a plurality of second power auxiliary vertical wirings VSAVL respectively paired with the second data wiring DL2 and the third data wiring DL3 and extending in the second direction DR2, like the first bypass auxiliary wiring TASL1.

[0293] The second power supply assist horizontal wiring VSAHL and the second power supply assist vertical wiring VSAVL may be electrically connected to each other and to the second power supply wiring VSSPL.

[0294] Among the plurality of second power auxiliary horizontal wirings VSAHL, two second power auxiliary horizontal wirings VSAHL may extend from both ends of the first bypass auxiliary wiring TASL1 toward the non-display area NDA.

[0295] Among the plurality of second power auxiliary vertical wirings VSAVL, one second power auxiliary vertical wiring VSAVL may extend from one end of the second bypass auxiliary wiring TASL2 toward the non-display area NDA in a direction away from the sub-area SBA.

[0296] Reference Fig.19 , the data wiring DL and the second bypass auxiliary wiring TASL2 may be disposed on at least one insulating layer covering the first bypass auxiliary wiring TASL1.

[0297] As an example, the data wiring DL, the second detour auxiliary wiring TASL2, and the second power auxiliary vertical wiring VSAVL can be arranged in the third source-drain conductive layer on the first planarization layer 125 and covered by the second planarization layer 126. In addition, the first detour auxiliary wiring TASL1 and the second power auxiliary horizontal wiring VSAHL can be arranged in the first source-drain conductive layer ANDE1 on the interlayer insulating layer 124 covered by the first planarization layer 125.

[0298] The first detour auxiliary wiring TASL1 may be electrically connected to the second data wiring DL2 through the first detour connection hole TCH1 and to the second detour auxiliary wiring TASL2 through the second detour connection hole TCH2. The first detour connection hole TCH1 and the second detour connection hole TCH2 may respectively penetrate the first planarization layer 125.

[0299] As described above, according to other embodiments, the second data wiring DL2 can be electrically connected to the second data supply wiring DSPL2 through the first detour auxiliary wiring TASL1 and the second detour auxiliary wiring TASL2. Thus, the second data supply wiring DSPL2 extends toward the first detour lateral area SDA1, thereby reducing the extension length of the second data supply wiring DSPL2, and thus reducing the width of the non-display area NDA.

[0300] In addition, according to other embodiments, the first data supply wiring DSPL1 directly electrically connected to the first data wiring DL1 can be electrically connected to the first demultiplexing transistor DXT1 of the demultiplexing circuit DMC. Different from this, the second data supply wiring DSPL2 electrically connected to the second data wiring DL2 through the first detour auxiliary wiring TASL1 and the second detour auxiliary wiring TASL2 can be electrically connected to the second demultiplexing transistor DXT2 of the demultiplexing circuit DMC.

[0301] The first demultiplexing transistor DXT1 may be turned on according to the first demultiplexing control signal CLA supplied in the first period AT in each image frame period (n)-th_H, (n+1)-th_H. The second demultiplexing transistor DXT2 may be turned on according to the second demultiplexing control signal CLB supplied in the second period BT after the first period AT in each image frame period (n)-th_H, (n+1)-th_H.

[0302] Thus, the display driving circuit 200 can output the data signal of the first data wiring DL1 in the first period AT, and output the data signal of the second data wiring DL2 to which the compensation value corresponding to the first extension length is applied based on the data control signal DCS of the timing control unit 500 in the second period BT.

[0303] That is, even if the display driving circuit 200 does not include a compensation circuit associated with a relatively long extension path, the compensation value corresponding to the first extension length can be applied to the data signal of the second data wiring DL2 transmitted to the transmission path having a transmission length longer than the first extension length.

[0304] Thus, even without changing the display driving circuit 200, it is possible to prevent the display quality from being degraded due to distortion of data signals caused by a relatively long transmission path, thereby facilitating higher resolution and larger size without affecting the thinning of the display device and the reduction of manufacturing costs.

[0305] The embodiments of the present invention are described above with reference to the accompanying drawings, but those skilled in the art should be able to understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and are not restrictive.

Claims

1. A display device, comprising: A substrate, comprising a main area and a sub-area protruding from one side of the main area, wherein the main area comprises a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate, comprising a plurality of light-emitting pixel driving units electrically connected to the plurality of light-emitting elements of the plurality of light-emitting regions, respectively, and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; A display driving circuit generates data signals for the plurality of light-emitting pixel driving units; as well as a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings, comprising a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal, A first data wiring among the data wirings is electrically connected to the display driving circuit through the first demultiplexing transistor and a transmission path shorter than a first extension length, A second data wiring among the data wirings is electrically connected to the display driving circuit via the second demultiplexing transistor and a transmission path having a length longer than the first extension.

2. The display device according to claim 1, wherein: In a first period within each image frame period, the first demultiplexing control signal is supplied, The second demultiplexing control signal is supplied in a second period after the first period in each image frame period.

3. The display device according to claim 2, wherein: The data signal of the second data wiring includes a compensation value corresponding to the first extension length.

4. The display device according to claim 3, wherein: A voltage level of a highest grayscale of a data signal of the second data wiring is higher than a voltage level of a highest grayscale of a data signal of the first data wiring based on the compensation value.

5. The display device according to claim 3, wherein: The second period is longer than the first period based on the compensation value.

6. The display device according to claim 2, wherein: The display driving circuit and the demultiplexing circuit are arranged in the sub-region of the substrate, Of the first data wiring and the second data wiring, the first data wiring is closer to the sub-region, The circuit layer further includes: a plurality of data supply wirings extending from the sub-area toward the display area and electrically connected between the plurality of data wirings and the demultiplexing circuit, The transmission path of the first data wiring includes a first data supply wiring electrically connected between the first demultiplexing transistor and the first data wiring among the data supply wirings. The transmission path of the second data wiring includes a second data supply wiring among the data supply wirings electrically connected between the second demultiplexing transistor and the second data wiring.

7. The display device according to claim 6, wherein: The first data wiring is directly electrically connected to the first data supply wiring, The transmission path of the second data wiring includes: a first bypass auxiliary wiring, arranged in the display area, extending in a first direction, and electrically connected to the second data wiring; and The second auxiliary bypass wiring is arranged in the display area, extends in the second direction together with the data wiring, forms a pair with the first data wiring, and is electrically connected between the first auxiliary bypass wiring and the second data supply wiring.

8. The display device according to claim 2, wherein: The demultiplexing circuit further includes: a third demultiplexing transistor, which is turned on according to a third demultiplexing control signal supplied in a third period after the second period in each image frame period; The second data wiring is electrically connected to the display driving circuit through the second demultiplexing transistor and a transmission path having a length greater than the first extension length and less than a second extension length. A third data wiring among the data wirings is electrically connected to the display driving circuit via the third demultiplexing transistor and a transmission path having a length longer than the second extension.

9. The display device according to claim 8, wherein: The demultiplexing circuit further includes: a fourth demultiplexing transistor, which is turned on according to a fourth demultiplexing control signal supplied in a fourth period after the third period in each image frame period, The third data wiring is electrically connected to the display driving circuit through the third demultiplexing transistor and a transmission path having a length greater than the second extension length and less than the third extension length. A fourth data wiring among the data wirings is electrically connected to the display driving circuit via the fourth demultiplexing transistor and a transmission path having a length longer than the third length.

10. A display device, comprising: A substrate, comprising a main area and a sub-area protruding from one side of the main area, wherein the main area comprises a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate, comprising a plurality of light-emitting pixel driving units electrically connected to the plurality of light-emitting elements of the plurality of light-emitting regions, respectively, and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; A display driving circuit generates data signals for the plurality of light-emitting pixel driving units; as well as a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings, A transmission path between a first data wiring among the data wirings and the demultiplexing circuit is smaller than a first extension length, A transmission path between a second data wiring among the data wirings and the demultiplexing circuit is longer than the first extension length, The demultiplexing circuit outputs the data signal of the first data wiring in a first period in each image frame period, and outputs the data signal of the second data wiring in a second period after the first period in each image frame period.

11. The display device according to claim 10, wherein: The data signal of the second data wiring includes a compensation value corresponding to the first extension length.

12. The display device according to claim 11, wherein: The display driving circuit and the demultiplexing circuit are arranged in the sub-region of the substrate, Of the first data wiring and the second data wiring, the first data wiring is closer to the sub-region, The circuit layer further includes: a plurality of data supply wirings extending from the sub-area toward the display area and electrically connected between the plurality of data wirings and the demultiplexing circuit, The transmission path between the first data wiring and the demultiplexing circuit includes a first data supply wiring among the data supply wirings electrically connected between the demultiplexing circuit and the first data wiring. The transmission path between the second data wiring and the demultiplexing circuit includes a second data supply wiring among the data supply wirings electrically connected between the demultiplexing circuit and the second data wiring.

13. The display device according to claim 12, wherein: The first data wiring is directly electrically connected to the first data supply wiring, The transmission path between the second data wiring and the demultiplexing circuit also includes: a first bypass auxiliary wiring, arranged in the display area, extending in a first direction, and electrically connected to the second data wiring; and The second auxiliary bypass wiring is arranged in the display area, extends in the second direction together with the data wiring, forms a pair with the first data wiring, and is electrically connected between the first auxiliary bypass wiring and the second data supply wiring.

14. The display device according to claim 12, wherein: The demultiplexing circuit comprises: a plurality of first demultiplexing transistors, which are turned on according to a first demultiplexing control signal during the first period of each image frame period and are electrically connected between the display driving circuit and the first data supply wiring respectively; and A plurality of second demultiplexing transistors are turned on according to a second demultiplexing control signal during the second period of each image frame period, and are electrically connected between the display driving circuit and the second data supply wiring, respectively.

15. The display device according to claim 12, wherein: The transmission path between the second data wiring and the demultiplexing circuit is longer than the first extension length and shorter than the second extension length, A transmission path between a third data wiring among the data wirings and the demultiplexing circuit is longer than the second extension length, The demultiplexing circuit outputs the data signal of the third data wiring in a third period after the second period in each image frame period.

16. The display device according to claim 15, wherein: The transmission path between the third data wiring and the demultiplexing circuit is longer than the second extension length and shorter than the third extension length. A transmission path between a fourth data wiring among the data wirings and the demultiplexing circuit is longer than the third extension length, The demultiplexing circuit outputs the data signal of the fourth data wiring in a fourth period after the third period in each image frame period.

17. A display device, comprising: A substrate, comprising a main area and a sub-area protruding from one side of the main area, wherein the main area comprises a display area in which a plurality of light-emitting areas are arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate, comprising a plurality of light-emitting pixel driving units electrically connected to the plurality of light-emitting elements of the plurality of light-emitting regions, and a plurality of data wirings for transmitting data signals of the plurality of light-emitting pixel driving units; A display driving circuit generates data signals for the plurality of light-emitting pixel driving units; as well as a demultiplexing circuit electrically connected between the display driving circuit and the plurality of data wirings, comprising a plurality of first demultiplexing transistors turned on according to a first demultiplexing control signal and a plurality of second demultiplexing transistors turned on according to a second demultiplexing control signal, The data wiring includes a first data wiring and a second data wiring, Of the first data wiring and the second data wiring, the second data wiring is closer to the non-display area in a direction crossing the data wiring, The circuit layer also includes: A first bypass auxiliary wiring is arranged in the display area, extends in a first direction, and is electrically connected to the second data wiring; as well as a second bypass auxiliary wiring, arranged in the display area, extending in the second direction together with the data wiring, forming a pair with the first data wiring, and electrically connecting the first bypass auxiliary wiring and the second data supply wiring; The first demultiplexing transistor is electrically connected between the first data wiring and the display driving circuit. The second demultiplexing transistor is electrically connected between the second data wiring and the display driving circuit.

18. The display device according to claim 17, wherein: The first demultiplexing transistor is turned on according to the first demultiplexing control signal supplied during a first period in each image frame period, The second demultiplexing transistor is turned on according to the second demultiplexing control signal supplied in a second period after the first period in each image frame period.

19. The display device according to claim 18, wherein: The display driving circuit and the demultiplexing circuit are arranged in the sub-region of the substrate, The circuit layer further includes: a plurality of data supply wirings extending from the sub-area toward the display area and electrically connected between the plurality of data wirings and the demultiplexing circuit, The first data wiring is directly electrically connected to a first data supply wiring among the data supply wirings, The second data wiring is electrically connected to the second data supply wiring among the data supply wirings through the first auxiliary bypass wiring and the second auxiliary bypass wiring.

20. The display device according to claim 19, wherein: The first data wiring is electrically connected to the display driving circuit through the first demultiplexing transistor and a transmission path shorter than a first extension length, The second data wiring is electrically connected to the display driving circuit via the second demultiplexing transistor and a transmission path having a length longer than the first extension. The data signal of the second data wiring includes a compensation value corresponding to the first extension length.

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