Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a substrate, a circuit layer, and an element layer. The circuit layer includes a data pad line disposed in the second sub-region and electrically connected between the data line and the display driving circuit; a data dummy line disposed in the second sub-region, extending from the bending region, and spaced apart from the display driving circuit; and a readout pad line disposed in the second sub-region and electrically connected between the readout line and the scan driving circuit. The second sub-region includes a first line group region in which the data pad line is arranged, a second line group region in which the data dummy line is arranged, and a third line group region in which the readout pad line is arranged. At least a portion of the third line group region overlaps the second line group region.

Description

Technical Field

[0001] The present disclosure relates to a display device and an electronic device including the display device. Background Art

[0002] As an information-oriented society develops, increasing demands are placed on display devices regarding the manner in which images can be displayed. For example, display devices are used in various form factors for different electronic devices including smartphones, digital cameras, notebook computers, navigation devices, and smart televisions.

[0003] In addition, in addition to the function of displaying an image, the display device may also include one or more input functions. For example, the display device may include a touch sensing function that senses the position of a touch on the screen based on a change in capacitance. In another example, the display device may include a scanning function for detecting the curvature of an object in contact with the screen based on a difference in the amount of light reflected from the screen. Summary of the invention

[0004] According to an embodiment, a display device may include light-emitting elements respectively corresponding to emission areas arranged in a display area that can realize an image display function, light-emitting pixel drivers respectively electrically connected to the light-emitting elements, and a display driving circuit that sends data signals to the light-emitting pixel drivers through data lines.

[0005] In addition, the display device may further include a scan driving circuit receiving a light sensing signal of the light sensing element that senses the amount of light, wherein the scan driving circuit may receive the light sensing signal through a readout line.

[0006] The substrate of the display device may include a main area including a display area and a sub-area protruding from one side of the main area. The sub-area may include a bendable bending area, a first sub-area between the main area and the bending area, and a second sub-area overlapping the main area through the bending area having a curved shape.

[0007] A display driving circuit and a scan driving circuit may be arranged in the second sub-area.

[0008] The second sub-area may have a limited width, so the pad line connected to the scan drive circuit may overlap the pad line connected to the display drive circuit. Accordingly, parasitic capacitance and signal coupling defects may occur, which may cause signal distortion in the pad line connected to the scan drive circuit. As a result, it is difficult to improve the accuracy of the scan function.

[0009] In view of the foregoing, aspects of the present disclosure provide a display device that can improve the accuracy of a scanning function by reducing signal distortion in a pad line.

[0010] According to one aspect of the present disclosure, a display device may include a substrate including a display area and a non-display area arranged at the periphery of the display area, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer and including a plurality of light-emitting elements and a plurality of light-sensing elements. The substrate may also include a sub-area protruding from the non-display area and in which a display drive circuit and a scan drive circuit are installed. The circuit layer may include a plurality of light-emitting pixel drivers electrically connected to the plurality of light-emitting elements, a plurality of light-sensing pixel drivers electrically connected to the plurality of light-sensing elements, a plurality of data lines arranged in the display area and electrically connected to the plurality of light-emitting pixel drivers, a plurality of readout lines arranged in the display area and electrically connected to the plurality of light-sensing pixel drivers, a plurality of data pad lines arranged in the sub-area and electrically connected between the plurality of data lines and the display drive circuit, and a plurality of readout pad lines arranged in the sub-area and electrically connected between the plurality of readout lines and the scan drive circuit. The sub-area may include a first line group area in which a plurality of data pad lines are arranged; a second line group area arranged in the sub-area and separated from the display driving circuit, wherein the second line group area is a dummy area; and a third line group area in which a plurality of readout pad lines are arranged, wherein at least a portion of the third line group area overlaps with the second line group area.

[0011] A plurality of data dummy lines may be arranged in a second line group area and located at the same layer of a circuit layer as a plurality of data pad lines, wherein the second line group area may be surrounded by the first line group area in a sub-area, wherein at least a portion of a third line group area overlaps with the first line group area, and wherein a plurality of readout pad lines of the third line group area overlapping with the second line group area are relatively sparsely concentrated, and a plurality of readout pad lines of the third line group area overlapping with the first line group area are relatively densely concentrated.

[0012] The circuit layer may also include a plurality of DC power supply lines extending from the non-display area to the sub-area and sending DC power of different voltage levels, and a plurality of DC power pad lines arranged in the sub-area and electrically connected to the DC power supply lines, respectively, wherein, in a portion of the third line group area overlapping with the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

[0013] The display device may further include a plurality of holes arranged in the third line group region and penetrating the plurality of direct current power supply pad lines.

[0014] According to one aspect of the present disclosure, a display device is provided, the display device including a substrate including a main area and a sub-area protruding from one side of the main area, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer. The main area may include a display area arranged at a central portion and a non-display area arranged at the periphery of the display area. The sub-area includes a bending area, a first sub-area arranged between a first side of the bending area and the main area, and a second sub-area connected to a second side of the bending area and in which a display drive circuit and a scan drive circuit are installed. The display area includes a plurality of emission areas spaced apart from each other, a non-emission area as a space between the plurality of emission areas, and a plurality of light sensing areas arranged in the non-emission area. The element layer may include a plurality of light emitting elements respectively arranged in the plurality of emission areas and a plurality of light sensing elements respectively arranged in the plurality of light sensing areas. The circuit layer includes a plurality of light-emitting pixel drivers electrically connected to a plurality of light-emitting elements, a plurality of light-sensing pixel drivers electrically connected to a plurality of light-sensing elements, a plurality of data lines arranged in a display area and electrically connected to the light-emitting pixel drivers, a plurality of readout lines arranged in a display area and electrically connected to the plurality of light-sensing pixel drivers, a plurality of data pad lines arranged in a second sub-area and electrically connected between the plurality of data lines and a display driving circuit, and a plurality of readout pad lines arranged in a second sub-area and electrically connected between the plurality of readout lines and a scan driving circuit. The second sub-area includes a first line group area in which a plurality of data pad lines are arranged; a plurality of second line group areas arranged in the second sub-area, extending from the bending area and spaced apart from the display driving circuit, wherein the second line group areas are dummy areas; and a third line group area in which a plurality of readout pad lines are arranged. At least a portion of the third line group area overlaps with the plurality of second line group areas.

[0015] A plurality of data dummy lines may be arranged in the plurality of second line group areas and extend from the bending area, wherein the plurality of data dummy lines may be located at the same layer of the circuit layer as the data pad line. Each of the second line group areas is surrounded by the bending area and the first line group area.

[0016] The circuit layer may further include a plurality of DC power supply lines extending from the non-display area to the first sub-area and transmitting DC power of different voltage levels, and a plurality of DC power pad lines arranged in the second sub-area and electrically connected to the DC power supply lines, respectively. In a portion of the third line group area overlapping the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

[0017] A plurality of DC power pad lines may be arranged on an interlayer insulating layer covering a plurality of data pad lines and a plurality of data dummy lines. A plurality of readout pad lines may be arranged on a first dam layer covering a plurality of DC power pad lines. In a portion of the third line group area overlapping the first line group area, a plurality of DC power pad lines may be interposed between the plurality of readout pad lines and the plurality of data pad lines.

[0018] The display device may further include an encapsulation layer arranged on the element layer and a touch sensor layer arranged on the encapsulation layer. The circuit layer may further include a plurality of touch sensor pad lines arranged in the second sub-area and electrically connected to the plurality of touch sensor lines of the touch sensor layer, respectively. The second sub-area may further include a fourth line group area in which a plurality of touch sensor pad lines are arranged. At least one DC power pad line among the DC power pad lines includes a first line layer and a second line layer overlapping each other. The first line layer may be arranged on an interlayer insulating layer covering a plurality of data pad lines and a plurality of data dummy lines. A plurality of readout pad lines may be arranged on a first dam layer covering the first line layer. The second line layer may be arranged on a second dam layer covering the readout pad lines. In a portion of the third line group area overlapping with the fourth line group area, a plurality of readout pad lines may overlap with a plurality of touch sensor pad lines and a second line layer in the fourth line group area.

[0019] A plurality of touch sensor pad lines may be arranged on the buffer planarization layer covering the second line layer and overlap the second line layer. In a portion of the third line group area overlapping the fourth line group area, the second line layer may be interposed between the plurality of readout pad lines and the plurality of touch sensor pad lines.

[0020] The display device may further include a plurality of holes arranged in the third line group region, spaced apart from each other, and penetrating the second line layer.

[0021] The touch sensor pad lines may be spaced apart from the plurality of holes.

[0022] A portion of the second wire layer spaced apart from the third wire group region may contact the first wire layer through a connection groove penetrating the first dam layer and the second dam layer.

[0023] The DC power source may include a first power source and a second power source for driving a plurality of light emitting pixels, a first initialization power source for initializing a plurality of light emitting pixel drivers, and a second initialization power source for initializing a plurality of light emitting pixel drivers.

[0024] According to one aspect of the present disclosure, an electronic device may include a bracket, a display device arranged on the bracket and emitting light for image display, and a cover window arranged on the display device. The display device may include a substrate including a main area and a sub-area protruding from one side of the main area, a circuit layer arranged on the substrate, a component layer arranged on the circuit layer, an encapsulation layer arranged on the component layer, and a touch sensor layer arranged on the encapsulation layer. The main area may include a display area arranged at a central portion and a non-display area arranged at the periphery of the display area. The sub-area may include a curved area having a curved form, a first sub-area arranged between a first side of the curved area and the main area, and a second sub-area connected to a second side of the curved area and in which a display drive circuit and a scan drive circuit are installed. The display area may include a plurality of emission areas spaced apart from each other, a non-emission area as a space between the plurality of emission areas, and a plurality of light sensing areas arranged in the non-emission area. The component layer may include a plurality of light emitting elements respectively arranged in the emission area and a plurality of light sensing elements respectively arranged in the plurality of light sensing areas. The circuit layer may include a plurality of light-emitting pixel drivers electrically connected to the light-emitting element; a plurality of light-sensing pixel drivers electrically connected to the light-sensing element; a plurality of data lines arranged in the display area and electrically connected to the plurality of light-emitting pixel drivers; a plurality of readout lines arranged in the display area and electrically connected to the plurality of light-sensing pixel drivers; a plurality of data pad lines arranged in the second sub-area and electrically connected between the plurality of data lines and the display driving circuit; a plurality of data dummy lines arranged in the second sub-area, extending from the bending area and spaced apart from the display driving circuit; and a plurality of readout pad lines arranged in the second sub-area and electrically connected between the plurality of readout lines and the scan driving circuit. The second sub-area may include a first line group area in which a plurality of data pad lines are arranged, a second line group area in which a plurality of data dummy lines are arranged and spaced apart from each other, and a third line group area in which a plurality of readout pad lines are arranged. At least a portion of the third line group area overlaps with the plurality of second line group areas.

[0025] The data dummy line may be located at the same layer of the circuit layer as the data pad line. Each of the second line group regions may be surrounded by the bending region and the first line group region.

[0026] The circuit layer may further include a plurality of DC power supply lines extending from the non-display area to the first sub-area and transmitting DC power of different voltage levels, and a plurality of DC power pad lines arranged in the second sub-area and electrically connected to the DC power supply lines, respectively. In a portion of the third line group area overlapping the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

[0027] A plurality of DC power pad lines may be arranged on an interlayer insulating layer covering a plurality of data pad lines and a plurality of data dummy lines. A plurality of readout pad lines may be arranged on a first dam layer covering a plurality of DC power pad lines. In a portion of the third line group area overlapping the first line group area, a plurality of DC power pad lines may be interposed between the plurality of readout pad lines and the plurality of data pad lines.

[0028] The circuit layer may further include a plurality of touch sensor pad lines arranged in the second sub-area and electrically connected to the plurality of touch sensor lines of the touch sensor layer, respectively. The second sub-area may further include a fourth line group area in which the plurality of touch sensor pad lines are arranged. At least one DC power pad line among the DC power pad lines may include a first line layer and a second line layer overlapping each other. The first line layer may be arranged on an interlayer insulating layer covering a plurality of data pad lines and a plurality of data dummy lines. A plurality of readout pad lines may be arranged on a first dam layer covering the first line layer. A plurality of second line layers may be arranged on a second dam layer covering a plurality of readout pad lines. In a portion of the third line group area overlapping with the fourth line group area, a plurality of readout pad lines overlap with the touch sensor pad lines and a plurality of second line layers of the fourth line group area.

[0029] A plurality of touch sensor pad lines may be arranged on the buffer planarization layer covering the second line layer and overlap the second line layer. In a portion of the third line group area overlapping the fourth line group area, the second line layer may be interposed between the plurality of readout pad lines and the plurality of touch sensor pad lines.

[0030] The display device may further include a plurality of holes arranged in the third line group region, spaced apart from each other, and penetrating the second line layer.

[0031] The touch sensor pad lines may be spaced apart from the plurality of holes.

[0032] A portion of the second wire layer spaced apart from the third wire group region may contact the first wire layer through a connection groove penetrating the first dam layer and the second dam layer.

[0033] The DC power source may include a first power source and a second power source for driving a plurality of light emitting pixels, a first initialization power source for initializing a plurality of light emitting pixel drivers, and a second initialization power source for initializing a plurality of light emitting pixel drivers.

[0034] The display device according to the embodiment may include a substrate, a circuit layer, and an element layer. The substrate includes a main region and a sub region protruding from one side of the main region.

[0035] The sub-area may include a bending area having a curved shape, a first sub-area arranged between a first side of the bending area and the main area, and a second sub-area connected to a second side of the bending area and in which a display driving circuit and a scan driving circuit are installed. The element layer may include light emitting elements respectively arranged in emission areas of the display area and light sensing elements respectively arranged in light sensing areas of the display area.

[0036] The circuit layer may include a light-emitting pixel driver electrically connected to each of the light-emitting elements; a light-sensing pixel driver electrically connected to each of the light-sensing elements; a data line electrically connected to the light-emitting pixel driver; a readout line electrically connected to the light-sensing pixel driver; a data pad line arranged in the second sub-area and electrically connected between the data line and the display driving circuit; a data dummy line arranged in the second sub-area, extending from the bending area and spaced apart from the display driving circuit; and a readout pad line arranged in the second sub-area and electrically connecting the readout line to the scanning driving circuit.

[0037] The second sub-region may include a first line group region in which the data pad lines may be arranged, a second line group region in which the data dummy lines may be arranged and spaced apart from each other, and a third line group region in which the readout pad lines may be arranged. At least a portion of the third line group region may overlap the second line group region.

[0038] In this case, a portion of the readout pad line arranged in the third line group area overlapping the data pad line in the first line group area may be relatively small, and thus a defect in which a light sensing signal of the readout pad line is distorted by a data signal of the data pad line can be reduced.

[0039] In addition, according to an embodiment, the circuit layer may further include a DC power supply line arranged in the non-display area and transmitting a DC power supply of different voltage levels, and a DC power pad line arranged in the second sub-area and electrically connected to the DC power supply line, respectively. Some other areas of the third line group area may overlap with the first line group area and the DC power pad line.

[0040] That is, some other areas of the third line group area that overlap with the first line group area but not with the second line group area may also overlap with the DC power supply pad line. In this way, the light sensing signal of the readout pad line can be kept relatively stable by the DC power supply of the DC power supply pad line, and thus the distortion of the light sensing signal can be further reduced.

[0041] However, the effects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0043] Figure 1 is a perspective view showing an electronic device according to an embodiment;

[0044] Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in ;

[0045] Figure 3 It is shown Figure 2 A plan view of a display device;

[0046] Figure 4 is along Figure 3 A cross-sectional view taken along line A-A';

[0047] Figure 5 It is shown Figure 2 A plan view of the main area and sub-areas of the display device shown in ;

[0048] Figure 6 It is shown Figure 5 a layout diagram of part B;

[0049] Figure 7 It is shown Figure 6 A diagram of the scanning function of the light sensing area shown in FIG.

[0050] Figure 8 It is shown Figure 4 The block diagram of the circuit layer;

[0051] Fig. 9 yes Figure 8 The equivalent circuit diagram of the light-emitting pixel driver shown in;

[0052] Fig.10 yes Figure 8 An equivalent circuit diagram of a light sensing pixel driver shown in ;

[0053] Fig.11 It is shown Figure 4 A plan view of a touch sensor layer;

[0054] Fig.12 It is shown Fig.11 an enlarged view of a portion D of;

[0055] Fig.13 is along Fig.12 A cross-sectional view taken along line E-E';

[0056] Fig.14 is a diagram showing a method according to an embodiment of the present invention. Figure 5 a plan view of section C;

[0057] Fig.15 It is shown Fig.14 an enlarged view of part F;

[0058] Fig.16 is along Fig.15 A cross-sectional view taken along the line G-G';

[0059] Fig.17 is along Fig.15 A cross-sectional view taken along the line H-H';

[0060] Fig.18 is a diagram showing a method according to an embodiment of the present invention. Figure 5 a plan view of section C;

[0061] Fig.19 It is shown Fig.18 a plan view of Section I;

[0062] Fig. 20 yes Fig.19 an enlarged view of portion J of ; and

[0063] Fig.21 is along Fig. 20 A cross-sectional view taken along line K-K'. DETAILED DESCRIPTION

[0064] Now, the embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the embodiments can be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same parts. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0065] In order to clearly describe the embodiments of the present disclosure, some of parts that are not associated with the description may not be mentioned.

[0066] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0067] In addition, the phrase "in a plan view" means when observing the object portion from above, and the phrase "in a schematic cross-sectional view" means when observing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object may be located above or below the second object or on the side of the second object, and / or vice versa. Additionally, the term "overlap" may include stacking, stacking, facing or facing, extending on ..., covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "set aside ... "or "offset from ... "and any other suitable corresponding words that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0068] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It should be understood that in addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is turned over, a device located "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, spatially relative terms may be interpreted differently depending on the orientation.

[0069] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element via one or more intervening elements. It should also be understood that when the terms “comprise,” “comprising,” “has,” “have,” “having,” “include,” and / or “including,” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0070] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another element, or to facilitate its description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0071] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account errors associated with the measurements and with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0072] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0073] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly rigid meaning unless explicitly defined in the specification.

[0074] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0075] Figure 1 is a perspective view showing an electronic device 10 according to the embodiment. Figure 2 yes Figure 1 1 is an exploded perspective view of the electronic device 10 shown in FIG.

[0076] Reference Figure 1, the electronic device 10 according to the embodiment may include a display area. The electronic device 10 may display an image in the display area. The electronic device 10 may provide portability. For example, the electronic device 10 may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra mobile PC (UMPC). However, the electronic device 10 according to the embodiment is not limited to a portable electronic device, and may be a large device such as a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device.

[0077] The electronic device 10 according to the embodiment may include a display device 100 (see Figure 2 )'s shell has a cover window 11 and a lower cover 12.

[0078] Reference Figure 2 The electronic device 10 may further include a display device 100 , a bracket 13 , and a main circuit board 14 . The display device 100 , the bracket 13 , and the main circuit board 14 may be accommodated between the cover window 11 and the lower cover 12 .

[0079] The display device 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA displaying an image and a non-display area NDA around the display area DA. The sub-area SBA may protrude from one side of the main area MA.

[0080] The display device 100 may also include a display driving circuit 200 arranged in the sub-area SBA, a display circuit board 300 bonded to one side of the sub-area SBA, a touch driving circuit 400 and a scan driving circuit 500 mounted on the display circuit board 300, and a cable 600 extending from one side of the display circuit board 300.

[0081] In the present specification, the first direction DR1 may be a direction parallel to the short side of the electronic device 10 in a plan view, that is, a horizontal direction of the electronic device 10. The second direction DR2 may be a direction parallel to the long side of the electronic device 10 in a plan view, that is, a vertical direction of the electronic device 10. The third direction DR3 may be a thickness direction of the electronic device 10 perpendicular to a plane formed by the first direction DR1 and the second direction DR2.

[0082] The electronic device 10 may have a rectangular shape in a plan view. For example, the electronic device 10 may have a short side in the first direction DR1 and a long side in the second direction DR2. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the electronic device 10 is not limited to a rectangular shape, and may be formed in another shape, such as a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape.

[0083] The cover window 11 may be arranged on the display device 100 to cover the top surface of the display device 100. The cover window 11 may be used to protect the top surface of the display device 100. The cover window 11 may include a transparent light-transmitting portion and an opaque light-blocking portion. The light-transmitting portion may overlap with the display area DA of the display device 100 in the third direction DR3, and the light-blocking portion may overlap with the non-display area NDA of the display device 100 in the third direction DR3.

[0084] The cover window 11 may include a top surface portion forming a top surface of the electronic device 10, a left surface portion forming a left side surface of the electronic device 10, and a right surface portion forming a right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and the right surface portion thereof may extend from the right side of the top surface portion. Each of the top surface portion, the left surface portion, and the right surface portion of the cover window 11 may include a light-transmitting portion and a light-blocking portion.

[0085] The light-transmitting portion of the cover window 11 may be arranged on most of each of the top, left, and right surface portions of the cover window 11. The light-blocking portion of the cover window 11 may be arranged at the upper and lower edges of the top surface portion of the cover window 11, the upper, left, and lower edges of the left surface portion of the cover window 11, and the upper, right, and lower edges of the right surface portion of the cover window 11.

[0086] The display device 100 may be disposed under the cover window 11. That is, the cover window 11 may be disposed on the display device 100. The display device 100 may include a main area MA and a sub area SBA protruding from one side of the main area MA.

[0087] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may be arranged in most of the main area MA. The display area DA may be arranged at the center of the main area MA. The non-display area NDA may be arranged outside the display area DA. The non-display area NDA may be an edge area of ​​the main area MA.

[0088] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. The length of the sub-area SBA in the first direction DR1 may be less than or equal to the length of the main area MA in the first direction DR1. The length of the sub-area SBA in the second direction DR2 may be less than the length of the main area MA in the second direction DR2, but is not limited thereto. Since a portion of the sub-area SBA may be deformed to be bent, another portion of the sub-area SBA may overlap with the main area MA in the third direction DR3.

[0089] The display driving circuit 200 may be disposed in the sub-area SBA.

[0090] The display device 100 may include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from the left side of the top surface portion, and the right surface portion of the display device 100 may extend from the right side of the top surface portion. Each of the top surface portion, the left surface portion, and the right surface portion of the display device 100 may include a display area DA and a non-display area NDA.

[0091] The display area DA may be disposed in most of each of the top surface portion, the left surface portion, and the right surface portion of the display device 100 .

[0092] The non-display area NDA may be arranged at the upper and lower edges of the top surface portion of the display device 100 , the upper, left and lower edges of the left surface portion of the display device 100 , and the upper, right and lower edges of the right surface portion of the display device 100 .

[0093] The display driving circuit 200 may be mounted in the sub-area SBA of the display device 100 , and the display circuit board 300 may be attached to the sub-area SBA.

[0094] One end of the display circuit board 300 may be attached to a pad disposed at a lower edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film. The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having a portion formed of a rigid printed circuit board and a portion formed of a flexible printed circuit board.

[0095] Based on the control signal and the power supply voltage supplied from the display circuit board 300, the display driving circuit 200 can output the data signal Vdata to the data lines DL (see Fig. 9 The data signal Vdata may be provided by the light emitting pixel driver EPD of the display area DA (see Figure 8 ) output.

[0096] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted in the sub-area SBA of the display device 100. The display driving circuit 200 may be mounted in the sub-area SBA by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, this is only an example, and the embodiment is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0097] According to an embodiment, the touch driving circuit 400 and the scan driving circuit 500 may also be installed in the sub-area SBA of the display device 100. According to an embodiment, as shown in FIG. Figure 2 As shown in FIG. 1 , the touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300. The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 (see FIG. 1 ) of the display device 100. Figure 4 ).

[0098] The touch driving circuit 400 may apply a touch driving signal to the first driving line TL1 (see FIG. Fig.11 ) and the second driving line TL2 (see Fig.11 ), and based on the sensing line RL (see Fig.11 ) to detect the change of the charge of the capacitor and determine whether there is a touch or approach of the user. The touch of the user means that an object such as a finger of the user or a pen is in direct contact with the top surface of the cover window 11 arranged on the touch sensor layer. The approach of the user means that an object such as a pen or a finger of the user hovers above the top surface of the cover window 11. The touch drive circuit 400 may output touch data including touch coordinates corresponding to the touch or approach of the user to the main processor 15.

[0099] The scan driving circuit 500 may be electrically connected to a light sensing pixel driver DPD (see FIG. Figure 8 The scanning driving circuit 500 can periodically collect the light sensing area ODA arranged in the main area MA through the light sensing pixel driver DPD (see Figure 6 ) in the light sensing element PD (see Fig.10 In addition, based on the collected light sensing signals, the scan driving circuit 500 may output scan data about the shape of the object in contact with the screen to the main processor 15 by detecting the difference in the amount of light reflected by the object in contact with the screen.

[0100] The bracket 13 may be disposed under the display device 100. The bracket 13 may include plastic, metal, or both plastic and metal. The bracket 13 may include a first camera hole CMH1 into which the camera 16 may be inserted, a battery hole BH into which the battery 18 may be disposed, and a cable hole CAH through which a cable 600 connected to the display circuit board 300 may pass.

[0101] The main circuit board 14 and the battery 18 may be arranged under the bracket 13. The main circuit board 14 may be a printed circuit board, for example, a flexible printed circuit board. The main circuit board 14 may include a main processor 15, a camera 16, and a main connector 17. The main processor 15 may be formed as an integrated circuit.

[0102] The cameras 16 may be arranged on the top and bottom surfaces of the main circuit board 14. The main processor 15 may be arranged on the top surface of the main circuit board 14. The main connector 17 may be arranged on the bottom surface of the main circuit board 14.

[0103] The main processor 15 may control all functions of the electronic device 10. For example, the main processor 15 may output digital video data to the display driving circuit 200 through the display circuit board 300 so that the display device 100 displays an image. In addition, the main processor 15 may receive touch data including touch coordinates from the touch driving circuit 400, determine whether the user has touched or approached the touch sensor layer 150, and perform an operation corresponding to the touch input or the approach input. For example, the main processor 15 may perform an operation indicated by an icon touched by the user or run an application indicated by an icon touched by the user.

[0104] In addition, the main processor 15 may receive scan data from the scan driving circuit 500. The main processor 15 may execute or run an application based on whether the scan data is valid. The main processor 15 may be an application processor, a central processing unit, or a system chip formed of an integrated circuit.

[0105] The camera 16 may process image frames of still images or videos obtained by an image sensor in a camera mode and output them to the main processor 15 .

[0106] The cable 600 passing through the cable hole CAH of the bracket 13 may be connected to the main connector 17. Thus, the main circuit board 14 may be electrically connected to the display circuit board 300.

[0107] The battery 18 may be offset from the main circuit board 14. For example, the battery 18 may be arranged so as not to overlap with the main circuit board 14 in the third direction DR3. The battery 18 may overlap with the battery hole BH of the bracket 13 in the third direction DR3.

[0108] In addition, the main circuit board 14 may be equipped with a mobile communication module capable of transmitting and receiving radio signals in a mobile communication network with at least one of a base station, an external terminal, and a server. The radio signal may include various types of data according to transmission and reception of a voice signal, a video call signal, or a text / multimedia message.

[0109] The lower cover 12 may be disposed below the main circuit board 14 and the battery 18. The lower cover 12 may be fixed to the bracket 13. For example, the lower cover 12 may be fastened to the bracket 13. The lower cover 12 may form an upper side surface, a lower side surface, and a bottom surface of the electronic device 10. The lower cover 12 may include, for example, plastic, metal, or both plastic and metal.

[0110] The lower cover 12 may include a second camera hole CMH2 through which the bottom surface of the camera 16 may be exposed. The position of the camera 16 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera 16 are not limited to Figure 2 The embodiment shown in .

[0111] Figure 3 It is shown Figure 2 FIG. 1 is a plan view of a display device 100 . Figure 4 is along Figure 3 A cross-sectional view taken along line AA'. Figure 5 It is shown Figure 2 1 is a plan view of a main area and a sub-area of ​​a display device 100 shown in FIG. Figure 6 It is shown Figure 5 Layout diagram of part B.

[0112] Figure 3 and Figure 4 The display device 100 is shown in which a portion of the sub-area SBA is in a bent state.

[0113] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro light-emitting display using a micro or nano light-emitting diode (LED). In the following description, it may be assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto.

[0114] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include a bent portion formed at the left end and / or the right end, and the bent portion may have a constant curvature or a varying curvature. In addition, the display device 100 may be formed of a flexible material that may be bent, curved, folded, or curled.

[0115] Reference Figure 3 At least one surface of the display device 100 includes a main area MA from which light for displaying an image is emitted. The main area MA includes an emission area EA (see Figure 6 ) and a non-display area NDA arranged around the display area DA.

[0116] The display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1 in a plan view. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined curvature or may be angled (e.g., right angles). The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in other shapes, such as a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape.

[0117] The display area DA may occupy a portion of the main area MA. The display area DA may be disposed at a central portion of the main area MA.

[0118] Reference Figure 4 , the display device 100 may further include a sub-area SBA that may protrude from one side of the main area MA. The sub-area SBA may be an area that protrudes from the non-display area NDA of the main area MA to one side in the second direction DR2. In an embodiment in which a portion of the sub-area SBA is curved, another portion of the sub-area SBA may be arranged on the rear surface of the display device 100. For example, the sub-area SBA may include a curved portion and a flat portion.

[0119] The display device 100 according to the embodiment may include a substrate 110 including a main area MA and a sub-area SBA, a circuit layer 120 arranged on the substrate 110, an element layer 130 arranged on the circuit layer 120, an encapsulation layer 140 arranged on the element layer 130, and a touch sensor layer 150 arranged on the encapsulation layer 140.

[0120] The display device 100 may further include a polarizing layer 160 disposed on the touch sensor layer 150. The polarizing layer 160 may reduce reflection of external light.

[0121] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled. According to an embodiment, the substrate 110 may be formed of an insulating material such as glass.

[0122] Reference Figure 5 , the substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA that may be arranged at a central portion and a non-display area NDA that may be arranged at a periphery of the display area DA. The sub-area SBA may protrude from one side of the main area MA in the second direction DR2.

[0123] The sub-area SBA may include a bending area BA which may have a curved shape, a first sub-area SB1 disposed between one side of the bending area BA and the main area MA, and a second sub-area SB2 connected to the other side of the bending area BA. In the second direction DR2, one side of the second sub-area SB2 may be connected to the bending area BA, and a signal pad SPD connected to the display circuit board 300 may be arranged on the other side of the second sub-area SB2.

[0124] According to an embodiment, one or more of the display driving circuit 200, the touch driving circuit 400, and the scan driving circuit 500 may be arranged in the second sub-region SB2 of the substrate 110. However, this is only an example, and the display device 100 of the embodiment is not limited to Figure 5 That is, one or more of the display driving circuit 200 , the touch driving circuit 400 , and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0125] When the display driving circuit 200 is arranged on the display circuit board 300, the display driving circuit 200 is arranged in the second sub-area SB2 and is electrically connected to the data line DL (see Figure 8 ) between the data pad lines DPDL (see Fig.15 ) may extend from the bending area BA to the signal pads SPD arranged on the other side of the second sub-area SB2.

[0126] When the scan driving circuit 500 is arranged on the display circuit board 300, the second sub-area SB2 is arranged and electrically connected between the scan driving circuit 500 and the readout line ROL (see Figure 8 ) between the readout pad line ROPDL (see Fig.15 ) may extend from the bending area BA to the signal pads SPD arranged on the other side of the second sub-area SB2.

[0127] Reference Figure 6 , the display area DA may include emission areas EA, non-emission areas NEA as separation areas between the emission areas EA, and light sensing areas ODA arranged in parts of the non-emission areas NEA. Each of the emission areas EA may be a unit that emits light in a wavelength band corresponding to a specific color at a brightness corresponding to an image signal. Different emission areas EA may emit light in different wavelength bands corresponding to different colors.

[0128] Each of the emission areas EA may have a rhombus planar shape or a rectangular planar shape. However, this is only an example, and the planar shapes of the plurality of emission areas EA according to the embodiment are not limited to Figure 6 That is, the plurality of emission areas EA may have a polygonal shape such as a diamond shape or a hexagonal shape, a circular shape, or an elliptical shape other than a rectangular shape in a plan view.

[0129] The emission area EA may include a first emission area EA1 that emits light of a first color having a predetermined wavelength band, a second emission area EA2 that emits light of a second color having a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color having a wavelength band lower than the wavelength band of the second color. For example, the first color may be red having a wavelength band of about 600nm to about 750nm, the second color may be green having a wavelength band of about 480nm to about 560nm, and the third color may be blue having a wavelength band of about 370nm to about 460nm. However, this is only an example, and the wavelength bands of the first color, the second color, and the third color according to the embodiment of the present specification are not limited thereto.

[0130] Since the emission area EA includes a first emission area EA1, a second emission area EA2 and a third emission area EA3, each of the unit pixels UPX can be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2 and one or more third emission areas EA3 adjacent to each other in the emission area EA.

[0131] Each of the unit pixels UPX may be a unit for displaying various colors of light including white. That is, various colors of light displayed by the unit pixel UPX may be realized as a mixture of light emitted from two or more emission areas EA included in each unit pixel UPX.

[0132] In the case where the first color of the first emission area EA1, the second color of the second emission area EA2, and the third color of the third emission area EA3 are red, green, and blue, respectively, the third emission area EA3 may have a width greater than that of the first emission area EA1, and the second emission area EA2 may have a width less than that of the first emission area EA1. However, this is only an example, and the width of each of the emission areas EA is not limited to Figure 6 Width shown in .

[0133] Furthermore, the first emission region EA1 and the third emission region EA3 may be alternately arranged in the first direction DR1 or the second direction DR2. In addition, the second emission region EA2 may be arranged side by side in the first direction DR1 or the second direction DR2 and may be disposed between the first emission region EA1 and the third emission region EA3 in the first direction DR1.

[0134] In this case, each of the unit pixels UPX may include a first emission area EA1, a third emission area EA3, and two second emission areas EA2 that may be adjacent to each other. However, this is only an example, and the arrangement pattern of the emission areas EA and components of the unit pixels UPX according to the embodiment is not limited to Figure 6 The arrangement pattern shown in .

[0135] According to an embodiment, the display area DA may include a light sensing area ODA arranged in a portion of the non-emission area NEA. For example, the light sensing area ODA may be arranged between the second emission areas EA2 having a relatively small width in the second direction DR2. One or more emission areas EA may be arranged between the light sensing areas ODA in each of the first direction DR1 and the second direction DR2.

[0136] Refer again Figure 4 The circuit layer 120 on the substrate 110 may include a light-emitting pixel driver EPD (see Figure 8 ), light sensing pixel driver DPD (see Figure 8 ), data line DL (see Figure 8 ) and the readout line ROL (see Figure 8 ). The light-emitting pixel drivers EPD may correspond to the emission areas EA respectively (see Figure 6 ). Light sensing pixel driver DPD (see Figure 8 ) may correspond to the light sensing areas ODA (see Figure 6 ). Data line DL (see Figure 8 ) can be electrically connected to the light-emitting pixel driver EPD. The readout line ROL (see Figure 8 ) can be electrically connected to the light sensing pixel driver DPD.

[0137] The element layer 130 may include a light emitting element LE (see Fig. 9 ) and the light sensing element PD (see Fig.10 ). Light emitting element LE (see Fig. 9 ) may correspond to the emission areas EA respectively. The light sensing element PD (see Fig.10 ) may correspond to the light sensing areas ODA respectively.

[0138] The encapsulation layer 140 may cover the element layer 130. The encapsulation layer 140 may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0139] The touch sensor layer 150 may be disposed on the encapsulation layer 140 and may correspond to the main area MA. The touch sensor layer 150 may include a touch electrode for sensing a touch of a user or an object.

[0140] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 and their interfaces, and this is to prevent degradation of visibility of an image due to external light reflection.

[0141] The cover window 11 of the electronic device 10 (see Figure 2 ) may be disposed on the polarizing layer 160. The cover window 11 may be attached to the polarizing layer 160 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window 11 may be made of an inorganic material such as glass or an organic material such as a plastic or polymer material.

[0142] By covering the window 11 , the circuit layer 120 , the touch sensor layer 150 , the encapsulation layer 140 , and the element layer 130 may be protected from electrical and physical impacts on the display surface.

[0143] The display device 100 according to the embodiment may include the light sensing element PD disposed in the light sensing area ODA, and may provide a scanning function to detect the shape of an object in contact with the screen.

[0144] Figure 7 It is shown Figure 6 The scanning function of the light sensing area is shown in the diagram.

[0145] Reference Figure 7 , the fingerprint of the user's finger FG in contact with the cover window 11 includes ridges RID and valleys VAL between the ridges RID. The ridges RID in the fingerprint may be in contact with the cover window 11. The valleys VAL in the fingerprint may be spaced apart from the cover window 11. That is, the top surface of the cover window 11 facing the valleys VAL may be in contact with the air.

[0146] The light emitted from the emission area EA may be reflected by the user's finger FG in contact with the cover window 11 and emitted by the light sensing element PD of the light sensing area ODA (see Fig.10 Since the refractive index of the finger FG is different from that of the air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0147] Accordingly, based on the difference in the amount of light incident on the light sensing element PD, the ridges RID and the valleys VAL in the fingerprint can be derived, and thus the fingerprint pattern of the finger FG can be detected.

[0148] Figure 8 It is shown Figure 4 Block diagram of the circuit layer.

[0149] Reference Figure 8 , circuit layer 120 (see Figure 4) may include a light emitting pixel driver EPD, a light sensing pixel driver DPD, a data line DL, and a readout line ROL. The light emitting pixel driver EPD may correspond to the emission areas EA of the display area DA (see Figure 6 The light sensing pixel drivers DPD may correspond to the light sensing areas ODA of the display area DA (see Figure 6 ). The data lines DL may be arranged in the display area DA and electrically connected to the light emitting pixel driver EPD. The readout lines ROL may be arranged in the display area DA and electrically connected to the light sensing pixel driver DPD.

[0150] The display device 100 (see FIG. Figure 2 ) may include outputting a data signal Vdata to each of the light-emitting pixel drivers EPD (see Fig. 9 ), a display driving circuit 200 for collecting light sensing signals of a light sensing pixel driver DPD, a scanning driving circuit 500 for supplying one or more gate signals to a light emitting pixel driver EPD and a light sensing pixel driver DPD, a gate driving circuit 101 for transmitting an emission control signal EC (see Fig. 9 ) is supplied to the emission control circuit 102 of the light-emitting pixel driver EPD, a power supply unit 700 that supplies various DC power supply voltages to the light-emitting pixel driver EPD and the light-sensing pixel driver DPD, and a timing controller 800 that controls the driving timing.

[0151] The timing controller 800 may receive an image signal supplied from the outside of the display device 100. The timing controller 800 may output the image data DATA and the data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101 and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate the scan control signal SCS and the emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through the scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through the emission control driving line.

[0152] The display driving circuit 200 may convert the image data DATA into analog data voltages and output them to the data lines DL.

[0153] The gate driving circuit 101 may generate a gate signal in response to a scan control signal SCS and sequentially output the gate signal to the gate lines GL1 to GLn, where n may be a natural number greater than 0.

[0154] The power supply unit 700 may supply various types of DC power to drive the light emitting pixel driver EPD and the light sensing pixel driver DPD. For example, the DC power provided by the power supply unit 700 may include a DC power source for driving the light emitting element LE (see Fig. 9 ) of the first power supply ELVDD (see Fig. 9 ) and the second power supply ELVSS (see Fig. 9 ) and a first initialization power source VINT (see Fig. 9 ).

[0155] In addition, the DC power provided by the power supply unit 700 may also include a reset voltage Vrst for resetting (see Fig.10 ) and a second initialization power VAINT (see Fig.10 ).

[0156] The emission control circuit 102 may respond to the emission control driving signal ECS by converting the emission control signal EC (see Fig. 9 ) are sequentially output to the emission control line ECL. The emission control signal EC of the emission control circuit 102 may have a pulse of a first voltage level or a second voltage level. The emission control circuit 102 may not be provided separately from the gate driving circuit 101, and may be built in the gate driving circuit 101.

[0157] The scanning driving circuit 500 can be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD (see Fig.10 ).

[0158] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD, and the scan driving circuit 500 may detect the shape of the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0159] The scanning driving circuit 500 may generate scanning data according to the magnitude of the photocurrent detected by the photo sensing element PD and send it to the main processor 15 (see Figure 2 ), and the main processor 15 can compare the scan data with the reference data and run the application based on whether the scan data matches the user's fingerprint.

[0160] Fig. 9 yes Figure 8 The equivalent circuit diagram of the light-emitting pixel driver EPD is shown in FIG.

[0161] Reference Fig. 9 , circuit layer 120 (see Figure 4 ) may include respective emission areas EA (see Figure 6) corresponding to the light-emitting pixel driver EPD and the data line DL configured to send the data signal Vdata to the light-emitting pixel driver EPD. The light-emitting pixel driver EPD of the circuit layer 120 can be electrically connected to the element layer 130 (see Figure 4 )'s light emitting element LE.

[0162] The circuit layer 120 may further include a first power line VDL for transmitting a first power source ELVDD to the light-emitting pixel driver EPD and an initialization voltage line VIL for transmitting a first initialization power source VINT to the light-emitting pixel driver EPD. The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW to the light-emitting pixel driver EPD, a scan initialization line GIL for transmitting a scan initialization signal GI to the light-emitting pixel driver EPD, an emission control line ECL for transmitting an emission control signal EC to the light-emitting pixel driver EPD, and a gate control line GCL for transmitting a gate control signal GC to the light-emitting pixel driver EPD.

[0163] Reference Fig. 9 One of the light-emitting pixel drivers EPD of the circuit layer 120 may include a driving transistor DT that generates a driving current to drive the light-emitting element LE electrically connected to the one light-emitting pixel driver EPD. In addition, the light-emitting pixel driver EPD may further include two or more transistors ST1 to ST6 electrically connected to the driving transistor DT and at least one capacitor PC1.

[0164] The anode 131 of the light emitting element LE (see Fig.13 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode 134 of the light emitting element LE (see Fig.13 ) may be electrically connected to a second power line VSL transmitting a second power source ELVSS having a voltage level lower than that of the first power source ELVDD.

[0165] The light emitting element LE may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. In an embodiment, the light emitting element LE may be an inorganic light emitting element including a light emitting layer made of an inorganic semiconductor. In an embodiment, the light emitting element LE may be a quantum dot light emitting element having a quantum dot light emitting layer. In an embodiment, the light emitting element LE may be a micro light emitting diode.

[0166] The capacitor Cel connected in parallel with the light emitting element LE indicates a parasitic capacitance between the anode 131 and the cathode 134 .

[0167] The driving transistor DT may be connected in series to the light emitting element LE between the first power line VDL and the second power line VSL. That is, the first electrode (e.g., source electrode) of the driving transistor DT may be electrically connected to the first power line VDL through the fifth transistor ST5. In addition, the second electrode (e.g., drain electrode) of the driving transistor DT may be electrically connected to the anode 131 of the light emitting element LE through the sixth transistor ST6.

[0168] The first electrode of the driving transistor DT may be electrically connected to the data line DL through the second transistor ST2 .

[0169] The gate electrode of the driving transistor DT may be electrically connected to the first power line VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the driving transistor DT and the first power line VDL. The potential of the gate electrode of the driving transistor DT may be maintained by the first power source ELVDD of the first power line VDL.

[0170] When the data signal Vdata of the data line DL is transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2, a voltage difference corresponding to the data signal Vdata and the first power source ELVDD may be generated between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT. In this case, when the voltage difference (i.e., gate-source voltage difference) between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT is greater than or equal to the threshold voltage, the driving transistor DT may be turned on.

[0171] When the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving transistor DT may be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Accordingly, a drain-source current corresponding to the data signal Vdata may be generated by the turned-on driving transistor DT and may be supplied as a driving current of the light emitting element LE. Accordingly, the light emitting element LE may emit light having a brightness corresponding to the data signal Vdata.

[0172] The second transistor ST2 may be connected between the first electrode of the driving transistor DT and the data line DL. The first transistor ST1 may be connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT. The first transistor ST1 may include a plurality of sub-transistors connected in series. For example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

[0173] A first electrode of the first sub-transistor ST11 may be connected to the gate electrode of the driving transistor DT, a second electrode of the first sub-transistor ST11 may be connected to a first electrode of the second sub-transistor ST12, and a second electrode of the second sub-transistor ST12 may be connected to a second electrode of the driving transistor DT.

[0174] In this way, it is possible to prevent the potential of the gate electrode of the driving transistor DT from being changed due to the leakage current caused by the non-conducting first transistor ST1 .

[0175] The gate electrode of each of the second transistor ST2, the first sub-transistor ST11, and the second sub-transistor ST12 may be connected to the scan write line GWL. When the scan write signal GW is transmitted through the scan write line GWL, the second transistor ST2, the first sub-transistor ST11, and the second sub-transistor ST12 may be turned on. In this case, the data signal Vdata may be transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2.

[0176] In addition, through the turned-on first sub-transistor ST11 and the turned-on second sub-transistor ST12, the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT may have the same potential. Accordingly, the driving transistor DT may be turned on.

[0177] The third transistor ST3 may be connected between the gate electrode of the driving transistor DT and the initialization voltage line VIL.

[0178] The third transistor ST3 may include a plurality of sub-transistors connected in series. For example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

[0179] The first electrode of the third sub-transistor ST31 may be connected to the gate electrode of the driving transistor DT, the second electrode of the third sub-transistor ST31 may be connected to the first electrode of the fourth sub-transistor ST32, and the second electrode of the fourth sub-transistor ST32 may be connected to the initialization voltage line VIL. In this way, the potential of the gate electrode of the driving transistor DT may be prevented from changing due to the leakage current caused by the non-conducting third transistor ST3.

[0180] A gate electrode of each of the third and fourth sub-transistors ST31 and ST32 may be connected to the scan initialization line GIL.

[0181] When the scan initialization signal GI is transmitted through the scan initialization line GIL, the third and fourth sub-transistors ST31 and ST32 may be turned on, and thus, the potential of the gate electrode of the driving transistor DT may be initialized to the first initialization power source VINT of the initialization voltage line VIL.

[0182] The fourth transistor ST4 may be connected between the anode of the light emitting element LE and the initialization voltage line VIL. The gate electrode of the fourth transistor ST4 may be connected to the gate control line GCL. Accordingly, when the gate control signal GC is transmitted through the gate control line GCL, the fourth transistor ST4 may be turned on.

[0183] In this case, the potential of the anode of the light emitting element LE can be initialized to the first initialization power source VINT of the initialization voltage line VIL through the turned-on fourth transistor ST4. Accordingly, the light emitting element LE can be prevented from being driven by the current remaining in the anode.

[0184] The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL. The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode of the light emitting element LE. The gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line ECL.

[0185] Accordingly, when the emission control signal EC is transmitted through the emission control line ECL, the fifth transistor ST5 and the sixth transistor ST6 are turned on, and thus, the drain-source current of the driving transistor DT may be supplied as a driving current of the light emitting element LE.

[0186] Although Fig. 9 The driving transistor DT and the first transistor ST1 to the sixth transistor ST6 included in the light-emitting pixel driver EPD are all P-type metal oxide semiconductor field effect transistors (MOSFETs), but it should be noted that the light-emitting pixel driver EPD of the embodiment is not limited to Fig. 9 That is, at least one of the driving transistor DT and the first to sixth transistors ST1 to ST6 included in the light emitting pixel driver EPD according to the embodiment may be an N-type MOSFET.

[0187] Fig.10 yes Figure 8 The equivalent circuit diagram of the light sensing pixel driver DPD is shown in FIG.

[0188] Reference Fig.10 , circuit layer 120 (see Figure 4 ) may also include a reset control line RSTL electrically connected to the light sensing pixel driver DPD. Each of the light sensing pixel drivers DPD may include two or more sensing transistors LT1, LT2, and LT3, and may be electrically connected between each light sensing element PD and the scan driving circuit 500 (see Figure 8 For example, each of the light-sensing pixel drivers DPD may include a first sensing transistor LT1, a second sensing transistor LT2, and a third sensing transistor LT3.

[0189] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a light sensing signal.

[0190] The light sensing element PD may be a photodiode including a sensing anode, a sensing cathode, and a photoelectric conversion layer disposed between the sensing anode and the sensing cathode.

[0191] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a PN type or PIN type inorganic material. According to an embodiment, the photoelectric conversion element PD may also be an organic photodiode including an electron donor material generating donor ions and an electron acceptor material generating acceptor ions.

[0192] As photocharges generated in the photoelectric conversion layer in response to incident light move, a photocurrent may be generated between the sensing anode and the sensing cathode.

[0193] As an example, photocharges generated in the photoelectric conversion layer by light incident on the photo sensing element PD may be accumulated in the sensing anode. In this case, the voltage of the first node N1 electrically connected to the sensing anode may increase. When the photo sensing element PD and the readout line ROL are connected to the first node N1 by turning on the first sensing transistor LT1 and the third sensing transistor LT3, a sensing voltage may be accumulated at the third node N3 between the readout line ROL and the third sensing transistor LT3 in proportion to the voltage at the first node N1 where the charge is accumulated.

[0194] The first sensing transistor LT1 may be turned on by the voltage of the first node N1 to connect the second initialization power line VIL2 to the second electrode of the third sensing transistor LT3. The first sensing transistor LT1 may be a source follower amplifier that generates a source-drain current in proportion to the amount of charge of the first node N1 input to its gate electrode. The first electrode of the first sensing transistor LT1 is shown as being connected to the second initialization power line VIL2, but is not limited thereto, and may be connected to the first power line VDL or the initialization voltage line VIL (see Fig. 9 ).

[0195] The second sensing transistor LT2 may be turned on by the reset control signal RST of the reset control line RSTL to connect the first node N1 to the reset voltage line VRL. Accordingly, the potential of the first node N1 may be reset.

[0196] The third sensing transistor LT3 may be turned on by the scanning write signal GW of the scanning write line GWL to connect the second electrode of the first sensing transistor LT1 with the readout line ROL.

[0197] The active layer of each of the first sensing transistor LT1, the second sensing transistor LT2, and the third sensing transistor LT3 may include any one of polysilicon, amorphous silicon, and an oxide semiconductor. For example, the active layer of each of the first sensing transistor LT1 and the third sensing transistor LT3 may be made of polysilicon, and the active layer of the second sensing transistor LT2 may be made of an oxide semiconductor. In this case, the first sensing transistor LT1 and the third sensing transistor LT3 may be formed of a P-type MOSFET, and the second sensing transistor LT2 may be formed of an N-type MOSFET.

[0198] Fig.11 It is shown Figure 4 1. A plan view of touch sensor layer 150. Fig.12 It is shown Fig.11 An enlarged view of portion D of FIG. Fig.13 is along Fig.12 A cross-sectional view taken along line EE'.

[0199] Fig.11 A capacitive touch sensor layer 150 is shown. In this case, the touch drive circuit 400 (see Figure 2 ) can sense touch based on whether capacitance fluctuates. Fig.11 is only an example, and the touch sensor layer 150 according to the embodiment is not limited to Fig.11 For example, to simplify the description, Fig.11 Only some of the components of touch sensor layer 150 may be shown.

[0200] Reference Fig.11 The touch sensor layer 150 may be arranged in the main area MA (see Figure 4 The touch sensor layer 150 may include a touch sensing area TSA for sensing a user's touch and a touch peripheral area TPA around the touch sensing area TSA.

[0201] The touch sensing area TSA may have a larger area than the display area DA (see Figure 5 ) may be larger than the width of the display area DA. Accordingly, the touch peripheral area TPA as the periphery of the touch sensing area TSA may be larger than the width of the non-display area NDA (see FIG. 1 ) as the periphery of the display area DA. Figure 5 ). For example, the touch sensing area TSA may overlap with edges of the display area DA and the non-display area NDA that are in contact with the display area DA. In this case, the touch peripheral area TPA may overlap with the remaining portion of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0202] The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE that are arranged in a matrix form in the touch sensing area TSA and generate mutual capacitance, and touch sensor lines TSL disposed in the touch peripheral area TPA.

[0203] The sensor electrodes SE may include a driving electrode TE (touch driving electrode) to which a driving signal is applied and a sensing electrode RE (receiving electrode) for sensing a voltage charged in a mutual capacitance with the driving electrode TE.

[0204] The touch sensor line TSL may include a first drive line TL1, a second drive line TL2, and a sensing line RL. Each of the first drive line TL1 and the second drive line TL2 may be electrically connected to two or more drive electrodes TE extending in the second direction DR2 among the drive electrodes TE. The first drive line TL1 may be connected to the sub-area SBA (see FIG. 1 ) from one side of the touch peripheral area TPA located in the second direction DR2 of the touch sensing area TSA. Figure 5 ) extends to the sub-area SBA.

[0205] The second driving line TL2 may extend from a portion of the touch peripheral area TPA contacting the other side of the touch sensing area TSA in the second direction DR2 to the subarea SBA through a portion of the touch peripheral area TPA contacting one side of the touch sensing area TSA in the first direction DR1 .

[0206] The sensing line RL may be electrically connected to two or more sensing electrodes RE extending in the first direction DR1 among the sensing electrodes RE.

[0207] The sensing electrodes RE may be arranged in parallel in the first direction DR1. The sensing electrodes RE adjacent to each other in the first direction DR1 may be electrically connected to each other through the protrusions in the first direction DR1.

[0208] The driving electrodes TE may be arranged in parallel in the second direction DR2. The driving electrodes TE adjacent to each other in the second direction DR2 may be connected to each other via the bridge electrodes BE (see FIG. Fig.12 ) are electrically connected to each other.

[0209] Each of the driving electrode TE and the sensing electrode RE may have a shape surrounding the dummy electrode DE disposed at the center thereof.

[0210] Each of the dummy electrodes DE may be spaced apart from the driving electrode TE or the sensing electrode RE surrounding it. The dummy electrode DE may be maintained in a floating state.

[0211] Although Fig.11 It is shown that each of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE has a rhombus planar shape, but the embodiment is not limited to Fig.11For example, the planar shapes of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE may be a quadrilateral shape other than a rhombus shape, a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0212] The display device 100 (see FIG. Figure 2 ) may include a sub-area SB2 (see Figure 5 ) and connected to the display circuit board 300 (see Figure 2 )'s signal pad (not shown).

[0213] Reference Fig.12 The driving electrodes TE and the sensing electrodes RE may be formed of the same conductive layer and may be spaced apart from each other. The bridge electrode BE may be provided as a conductive layer different from the driving electrodes TE and the sensing electrodes RE.

[0214] Although Fig.12 The bridging electrode BE having a shape including at least one bend is shown, but the shape of the bridging electrode BE according to the embodiment is not limited to Fig.12 The shapes shown in .

[0215] The driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected to each other through two or more bridge electrodes BE. In this way, the reliability of the electrical connection between the driving electrodes TE may be improved.

[0216] Although Fig.12 It is shown that two bridging electrodes BE parallel to each other are arranged between driving electrodes TE adjacent to each other in the second direction DR2, but the embodiment is not limited to Fig.12 The embodiment shown in .

[0217] The bridge electrode BE may be electrically connected to the driving electrode TE through the touch contact hole TCNT1.

[0218] The driving electrode TE, the sensing electrode RE, and the bridging electrode BE may have a grid or mesh structure in a plan view. The dummy electrode DE may also have a grid or mesh structure in a plan view. In this way, since the emission area EA (see Figure 6 ) in which the overlapping width of the driving electrode TE, the sensing electrode RE, the dummy electrode DE and the bridge electrode BE can be reduced, thereby reducing the reduction in light emission efficiency caused by the driving electrode TE, the sensing electrode RE, the dummy electrode DE and the bridge electrode BE.

[0219] Although Fig.12 It is shown that each of the emission areas EA has a rhombus or rectangular planar shape, but the planar shape of the emission area EA according to the embodiment is not limited to Fig.12The planar shape shown in . That is, each of the emission areas EA may have a planar shape such as a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape. Different emission areas in the emission area EA may have different shapes and / or sizes. For example, the first emission area EA1 and the second emission area EA2 may have a square shape, and the third emission area EA3 may have a rectangular shape. In another example, the first emission area EA1 may have a relatively small square shape, and the second emission area EA2 may have a relatively large square shape. The description of the emission area EA is only an example, and the shape and / or size of the emission area EA according to the embodiment is not limited to the above description.

[0220] Reference Fig.13 According to the display device 100 of the embodiment (see Figure 4 ) may include a substrate 110, a circuit layer 120 on the substrate 110, a component layer 130 on the circuit layer 120, a packaging layer 140 on the component layer 130, and a touch sensor layer 150 on the packaging layer 140.

[0221] The circuit layer 120 may include the emission areas EA (see Figure 6 ) corresponding to the light-emitting pixel driver EPD (see Figure 8 ) and respectively with the optical sensing area ODA (see Figure 6 ) corresponding to the light sensing pixel driver DPD (see Figure 8 Each of the light emitting pixel drivers EPD may include a driving transistor DT and two or more transistors ST1 to ST6 electrically connected to the driving transistor DT (see Fig. 9 Each of the light sensing pixel drivers DPD may include two or more sensing transistors LT1, LT2, and LT3 (see Fig.10 ).

[0222] According to embodiments, the driving transistor DT, the two or more transistors ST1 to ST6 , and the two or more sensing transistors LT1 , LT2 , and LT3 may each include a semiconductor layer having a channel region, a source region, and a drain region, and a gate electrode overlapping the channel region of the semiconductor layer.

[0223] The circuit layer 120 may include a buffer layer 121, a first gate insulating layer 122, a second gate insulating layer 123, a first interlayer insulating layer 124, a third gate insulating layer 125, a second interlayer insulating layer 126, a first planarizing layer 127, a second planarizing layer 128, and a third planarizing layer 129 disposed on the substrate 110. The buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, the first interlayer insulating layer 124, the third gate insulating layer 125, the second interlayer insulating layer 126, the first planarizing layer 127, the second planarizing layer 128, and the third planarizing layer 129 may be sequentially stacked.

[0224] A channel region CADT, a source region SADT, a drain region DADT, a source region SA6, a channel region CA6, and a drain region DA6 may be formed on the buffer layer 121. Hereinafter, the channel region CADT, the source region SADT, the drain region DADT, the source region SA6, the channel region CA6, and the drain region DA6 may be referred to as a first semiconductor layer. A first gate insulating layer 122 may be formed on the buffer layer 121, the channel region CADT, the source region SADT, the drain region DADT, the source region SA6, the channel region CA6, and the drain region DA6. The gate electrode GEDT and the gate electrode GE6 may be formed by a first gate conductive layer on the first gate insulating layer 122. The second gate insulating layer 123 may be formed on the first gate insulating layer 122. The capacitor electrode CAE may be formed by a second gate conductive layer on the second gate insulating layer 123. The first interlayer insulating layer 124 may be formed on the capacitor electrode CAE and the second gate insulating layer 123. The source area SA3, the channel area CA3, and the drain area DA3 may be formed on the first interlayer insulating layer 124. Hereinafter, the source area SA3, the channel area CA3, and the drain area DA3 may be referred to as a second semiconductor layer. The third gate insulating layer 125 may be formed on the source area SA3, the channel area CA3, the drain area DA3, and the first interlayer insulating layer 124. The gate electrode GE3 may be formed of a third gate conductive layer on the third gate insulating layer 125. The second interlayer insulating layer 126 may be formed on the gate electrode GE3 and the third gate insulating layer 125. The first anode connection electrode ANDE1 may be formed on the second interlayer insulating layer 126. The first planarizing layer 127 may be formed on the first anode connection electrode ANDE1 and the second interlayer insulating layer 126. The second anode connection electrode ANDE2 may be formed on the first planarizing layer 127. The second planarizing layer 128 may be formed on the second anode connection electrode ANDE2 and the first planarizing layer 127. The third anode connection electrode ANDE3 may be formed on the second planarization layer 128. The third planarization layer 129 may be formed on the third anode connection electrode ANDE3 and the second planarization layer 128.

[0225] In one example, some of the driving transistor DT, two or more transistors ST1 to ST6, and two or more sensing transistors LT1, LT2, and LT3 (e.g., the driving transistor DT) may each include a channel region CADT, a source region SADT, and a drain region DADT formed by a first semiconductor layer on a buffer layer 121, and a gate electrode GEDT on a first gate insulating layer 122.

[0226] In addition, some other transistors (for example, the third transistor ST3) among the driving transistor DT, two or more transistors ST1 to ST6, and two or more sensing transistors LT1, LT2, and LT3 may each be provided as an N-type MOSFET including a channel region CA3 formed by a second semiconductor layer on the first interlayer insulating layer 124, a source region SA3, and a drain region DA3, and a gate electrode GE3 on a third gate insulating layer 125.

[0227] For example, among the driving transistor DT, two or more transistors ST1 to ST6 and two or more sensing transistors LT1, LT2 and LT3, the first transistor ST1 and the third transistor ST3 of the light-emitting pixel driver EPD and the second sensing transistor LT2 of the light-sensing pixel driver DPD can each be provided as a P-type MOSFET including a second semiconductor layer.

[0228] The buffer layer 121 may be used to block oxygen or moisture that has passed through the substrate 110, and may include an inorganic insulating material. Additionally, the buffer layer 121 may cover a light-blocking layer (not shown) disposed on the substrate 110, and the light-blocking layer may reduce leakage current of the first semiconductor layer caused by light. The buffer layer 121 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0229] Each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the first interlayer insulating layer 124 may be formed of at least one inorganic layer. For example, each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the first interlayer insulating layer 124 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0230] Each of the first planarization layer 127 and the second planarization layer 128 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0231] Each of the first semiconductor layer and the second semiconductor layer may include one of semiconductor materials of polycrystalline silicon, amorphous silicon, and oxide semiconductor. For example, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0232] In each of the driving transistor DT, the two or more transistors ST1 to ST6, and the two or more sensing transistors LT1, LT2, and LT3, source and drain regions may be connected to both sides of the channel region, respectively. The source and drain regions may have higher conductivity than the channel region.

[0233] In each of the driving transistor DT, the two or more transistors ST1 to ST6 , and the two or more sensing transistors LT1 , LT2 , and LT3 , a gate electrode may overlap a channel region.

[0234] The first capacitor PC1 of the light-emitting pixel driver EPD (see Fig. 9 ) may be provided as an overlap region between the gate electrode GEDT of the driving transistor DT and the capacitor electrode CAE. The capacitor electrode CAE may be formed of a second gate conductive layer on the second gate insulating layer 123 covering the first gate conductive layer.

[0235] The anode 131 of the element layer 130 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through the first anode connection electrode ANDE1 , the second anode connection electrode ANDE2 , and the third anode connection electrode ANDE3 .

[0236] The first anode connection electrode ANDE1 may be formed of a first source / drain conductive layer on the second interlayer insulating layer 126. The first anode connection electrode ANDE1 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through a first anode contact hole ANCT1 penetrating the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0237] The second anode connection electrode ANDE2 may be formed of a second source / drain conductive layer on the first planarization layer 127. The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 penetrating the first planarization layer 127.

[0238] The third anode connection electrode ANDE3 may be formed of a third source / drain conductive layer on the second planarization layer 128 . The third anode connection electrode ANDE3 may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second planarization layer 128 .

[0239] The anode 131 of the light emitting element LE may be disposed on the third planarization layer 129 covering the third anode connection electrode ANDE3. The anode 131 may be electrically connected to the third anode connection electrode ANDE3 through a fourth anode contact hole ANCT4 penetrating the third planarization layer 129.

[0240] The second source / drain conductive layer on the first planarization layer 127 may further include a data line DL (see FIG. 1 ) for transmitting a data signal Vdata to the light-emitting pixel driver EPD. Figure 8 ).

[0241] The third source / drain conductive layer on the second planarization layer 128 may further include a readout line ROL (see FIG. 1 ) for outputting a light sensing signal of the light sensing pixel driver DPD. Figure 8 ).

[0242] Each of the first gate conductive layer, the second gate conductive layer, the third gate conductive layer, the first source / drain conductive layer, the second source / drain conductive layer, and the third source / drain conductive layer may be formed as a multilayer including two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, each of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer may be formed as a single layer including molybdenum (Mo), aluminum (Al), copper (Cu), etc. In addition, each of the first source / drain conductive layer, the second source / drain conductive layer, and the third source / drain conductive layer may be formed as a triple layer of Ti / Al / Ti.

[0243] The element layer 130 may include light emitting elements LE corresponding to the emission areas EA, respectively (see Fig. 9 ) and the light sensing elements PD corresponding to the light sensing areas ODA (see Fig.10 ).

[0244] Each of the light emitting element LE and the light sensing element PD may have a structure in which a photoelectric conversion material is interposed between an anode and a cathode facing each other. For example, each of the light emitting elements LE may include an anode 131 and a cathode 134 facing each other and a light emitting layer 133 disposed therebetween.

[0245] According to an embodiment, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode 131 and the light emitting layer 133 and a second common layer 136 disposed between the light emitting layer 133 and the cathode 134. That is, the element layer 130 may include the anode 131 corresponding to the emission area EA, the non-emission area NEA (see Figure 6) corresponds to and covers the edge of the anode 131, a pixel defining layer 132 corresponding to the anode 131, a first common layer 135 respectively arranged on the anode 131, a light-emitting layer 133 respectively arranged on the first common layer 135, a second common layer 136 corresponding to the emission area EA and arranged on the light-emitting layer 133 and the pixel defining layer 132, and a cathode 134 arranged on the second common layer 136.

[0246] The anode 131 may be disposed in each of the emission areas EA, and may be electrically connected to one light emitting pixel driver EPD of the circuit layer 120. The anode 131 may be referred to as a pixel electrode.

[0247] The anode 131 may be formed of a metal material having high reflectivity such as a stack structure (Ti / Al / Ti) of aluminum (Al) and titanium (Ti), a stack structure (ITO / Al / ITO) of Al and indium tin oxide (ITO), an APC alloy, a stack structure (ITO / APC / ITO) of an APC alloy and ITO, etc. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0248] The first common layer 135 on the anode 131 may be disposed in each of the emission areas EA. The first common layer 135 may include a hole transport layer. Alternatively, the first common layer 135 may further include a hole injection layer between the anode 131 and the hole transport layer.

[0249] The light-emitting layer 133 on the first common layer 135 may be arranged in each of the emission areas EA. The light-emitting layer 133 of the first emission area EA1, the light-emitting layer 133 of the second emission area EA2, and the light-emitting layer 133 of the third emission area EA3 may include organic light-emitting materials having different materials or contents. For example, the light-emitting layer 133 may be formed of an organic light-emitting material that converts electron-hole pairs into light. The organic light-emitting material may include a host material and a dopant. The dopant may include a phosphorescent material or a fluorescent material.

[0250] The light emitting layer 133 of the first emission area EA1 emitting light of the first color may include a host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP).

[0251] In addition, the dopant of the light emitting layer 133 of the first emission region EA1 may include any one or more phosphorescent materials selected from bis(1-phenylisoquinoline)iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinoline)iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinoline)iridium (PQIr) and platinum octaethylporphyrin (PtOEP), or a phosphorescent material including PBD:Eu(DBM) 3 (Benzene) or perylene fluorescent materials.

[0252] The light emitting layer 133 of the second emission region EA2 emitting light of a second color having a wavelength band lower than that of the first color may include a host material including CBP or mCP. In addition, the light emitting layer 133 including fac tris(2-phenylpyridine)iridium (Ir(ppy) 3 ) or phosphorescent materials containing tris(8-hydroxyquinoline)aluminum (Alq 3 ) may be selected as a dopant for the light emitting layer 133 of the second emission area EA2.

[0253] The light emitting layer 133 of the third emission area EA3 emitting light of a third color having a wavelength band lower than that of the second color may include a host material including CBP or mCP. 2 The phosphorescent material of Irpic or L2BD111 may be selected as the dopant of the light emitting layer 133 of the third emission area EA3.

[0254] The description of the organic light emitting material of the light emitting layer 133 is only an example, and the material of the light emitting layer 133 according to the embodiment is not limited to the above description.

[0255] The second common layer 136 located under the cathode 134 may be disposed in the display area DA including the emission area EA (see Figure 6 ). The second common layer 136 located below the cathode 134 may be entirely arranged in the display area DA including the emission area EA. The second common layer 136 may include an electron transport layer. In an embodiment, the second common layer 136 may further include an electron injection layer between the cathode 134 and the electron transport layer.

[0256] The cathode electrode 134 may be entirely disposed in the display area DA including the emission area EA, and may be electrically connected to the second power line VSL (see FIG. 1 ). Fig. 9 ). The cathode 134 may be referred to as a common electrode.

[0257] The cathode 134 may include a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the cathode 138 is made of a semi-transmissive conductive material, an improvement in light output efficiency due to a microcavity effect can be expected.

[0258] Meanwhile, although not separately shown, the light sensing element PD of the element layer 130 has a substantially similar structure to that of the light emitting element LE except that the light emitting element LE includes a photoelectric conversion layer instead of the light emitting layer 133 , and thus redundant description may be omitted below.

[0259] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0260] The encapsulation layer 140 may include a first encapsulation layer 141 disposed on the element layer 130, a second encapsulation layer 142 disposed on the first encapsulation layer 141 and overlapping the element layer 130, and a third encapsulation layer 143 disposed on the first encapsulation layer 141 and covering the second encapsulation layer 142. The first encapsulation layer 141 may be made of an inorganic insulating material. The second encapsulation layer 142 may be made of an organic insulating material. The third encapsulation layer 143 may be made of an inorganic insulating material.

[0261] The second encapsulation layer 142 may be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0262] The second encapsulation layer 142 may be prepared by a process in which a liquid organic material is dropped on the first encapsulation layer 141 , widely spread to cover the display area DA, and then cured.

[0263] Accordingly, the display device 100 according to the embodiment may further include a dam (not shown) to limit the diffusion range of the organic material of the second encapsulation layer 142 .

[0264] One or more dams may be arranged in the non-display area NDA in the form of surrounding the periphery of the display area DA.

[0265] Since the second encapsulation layer 142 diffuses to the dam, the third encapsulation layer 143 may contact the first encapsulation layer 141 between the dam and the edge of the substrate 110 in the non-display area NDA. Accordingly, an encapsulation structure formed by adhesion of inorganic materials may be provided.

[0266] Each of the first encapsulation layer 141 and the third encapsulation layer 143 may have a structure in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked.

[0267] The touch sensor layer 150 may include a buffer planarization layer 151 arranged on the encapsulation layer 140, a bridging electrode BE arranged on the buffer planarization layer 151, a sensor insulation layer 152 covering the bridging electrode BE, a driving electrode TE and a sensing electrode RE arranged on the sensor insulation layer 152, and an overlying layer 153 covering the driving electrode TE and the sensing electrode RE.

[0268] Each of the buffer planarization layer 151 and the sensor insulating layer 152 may have a structure in which one or more inorganic layers of a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked.

[0269] The upper cladding layer 153 may be made of an organic material that can be disposed in a low temperature process. For example, the upper cladding layer 153 may be made of a negative photoresist material.

[0270] Each of the bridge electrode BE, the driving electrode TE, and the sensing electrode RE may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0271] Each of the dummy electrode DE disposed inside each of the driving electrode TE and the sensing electrode RE, the first and second driving lines TL1 and TL2 connected to the driving electrode TE, and the sensing line RL connected to the sensing electrode RE may be disposed at the same layer as the driving electrode TE and the sensing electrode RE.

[0272] The driving electrode TE may be electrically connected to the bridge electrode BE through the touch contact hole TCNT1 penetrating the sensor insulating layer 152 .

[0273] The driving electrode TE, the sensing electrode RE, the dummy electrode DE, the first and second driving lines TL1 and TL2, and the sensing line RL may have a structure including a low-reflection layer. In this way, the amount of light incident from the outside, reflected in the display device 100 and emitted (i.e., reflection of external light) can be reduced.

[0274] The second sub-area SB2 (see FIG. 1 ) of the sub-area SBA according to some embodiments will be described. Figure 5 ).

[0275] Fig.14 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Floor plan of Section C. Fig.15 It is shown Fig.14 An enlarged view of part F. Fig.16 is along Fig.15 A cross-sectional view taken along line G-G'. Fig.17 is along Fig.15 A cross-sectional view taken along line H-H'.

[0276] As mentioned above, the display device 100 according to the embodiment includes the substrate 110, the circuit layer 120, the element layer 130, the encapsulation layer 140, and the touch sensor layer 150 (see Figure 4 ).

[0277] The substrate 110 includes a main area MA and a sub-area SBA protruding from one side thereof (see Figure 5 The main area MA includes a display area DA arranged in most of the main area MA and a non-display area NDA arranged around the display area DA (see Figure 5The display area DA includes emission areas EA arranged with each other, non-emission areas NEA as separation areas between the emission areas EA, and light sensing areas ODA arranged in parts of the non-emission areas NEA (see Figure 6 ).

[0278] The element layer 130 includes light emitting elements LE respectively arranged in the emission areas EA (see Fig. 9 ) and light sensing elements PD respectively arranged in the light sensing area ODA (see Fig.10 ).

[0279] The circuit layer 120 of the display device 100 according to the embodiment includes light emitting pixel drivers EPD electrically connected to the light emitting elements LE of the element layer 130, light sensing pixel drivers DPD electrically connected to the light sensing elements PD of the element layer 130, data lines DL arranged in the display area DA and electrically connected to the light emitting pixel drivers EPD, and readout lines ROL arranged in the display area DA and electrically connected to the light sensing pixel drivers DPD (see Figure 8 ).

[0280] Reference Fig.14 The sub-area SBA includes a bending area BA deformed into a curved shape, a first sub-area SB1 arranged between the main area MA and one side of the bending area BA, and a second sub-area SB2 connected to the other side of the bending area BA.

[0281] The display driving circuit 200 and the scan driving circuit 500 may be disposed in the second sub-region SB2.

[0282] The second sub-area SB2 may include a first line group area LGA1, a second line group area LGA2, and a third line group area LGA3. The first line group area LGA1 may extend from the bending area BA to the display driving circuit 200. The second line group area LGA2 may be surrounded by the bending area BA and the first line group area LGA1 and spaced apart from each other. The second line group area LGA2 may be arranged in the second sub-area SB2 and spaced apart from the display driving circuit 200, wherein the second line group area LGA2 is a dummy area. The third line group area LGA3 may extend from the bending area BA to the touch driving circuit 400 (see Figure 5 ).

[0283] According to an embodiment, at least a portion of the third line group area LGA3 may overlap with the second line group area LGA2 .

[0284] Reference Fig.15According to the embodiment, the circuit layer 120 includes a data pad line DPDL arranged in the second sub-area SB2 of the sub-area SBA and electrically connecting the data line DL with the display driving circuit 200; a data dummy line DDML arranged in the second sub-area SB2, extending from the bending area BA and spaced apart from the display driving circuit 200; and a readout pad line ROPDL arranged in the second sub-area SB2 and electrically connected between the readout line ROL and the touch driving circuit 400.

[0285] The data pad lines DPDL may be densely concentrated in the first line group area LGA1 of the second sub-area SB2. The data dummy lines DDML may be densely concentrated in the second line group area LGA2 of the second sub-area SB2. Fig.17 As shown in , the data dummy line DDML may be located at the same layer as the data pad line DPDL. Fig.14 As shown in FIG. 4 , the second line group area LGA2 may not overlap with the first line group area LGA1 .

[0286] like Fig.15 As shown in , the data dummy line DDML may extend from the bending area BA in a direction substantially parallel to the adjacent data pad line DPDL, but may be spaced apart from the display driving circuit 200. Accordingly, as shown in FIG. Fig.14 As shown in FIG. 1 , each of the second line group areas LGA2 may be surrounded by the bending area BA and the first line group area LGA1 .

[0287] like Fig.15 As shown in FIG. 1 , the readout pad lines ROPDL may be densely concentrated in the third line group area LGA3 of the second sub-area SB2 .

[0288] According to an embodiment, at least a portion of the third line group area LGA3 may overlap with the second line group area LGA2. That is, in at least some areas of the third line group area LGA3, the readout pad line ROPDL may not overlap with the data pad line DPDL electrically connected to the display driving circuit 200. In addition, in at least some areas of the third line group area LGA3, the readout pad line ROPDL may overlap with the data dummy line DDML that is not connected to the display driving circuit 200 and is in a floating state.

[0289] According to the embodiments and Fig.15As shown in , the readout pad lines ROPDL of the third line group area LGA3 overlapping with the second line group area LGA2 may be relatively sparsely concentrated, and the readout pad lines ROPDL of the third line group area LGA3 overlapping with the first line group area LGA1 may be relatively densely concentrated. For example, the readout pad lines ROPDL may fan out in the portion of the third line group area LGA3 overlapping with the second line group area LGA2. The densely concentrated readout pad lines ROPDL of the third line group area LGA3 overlapping with the first line group area LGA1 may reduce the overlapping area and reduce the defect in which the light sensing signal of the readout pad line ROPDL may be distorted. For example, it is possible to reduce the distortion of the light sensing signal of the readout pad line ROPDL caused by the data signal of the data pad line DPDL.

[0290] like Fig.14 and Fig.15 As shown in FIG. 1 , the circuit layer 120 of the display device 100 according to the embodiment may further include a DC power supply line DCSPL ( Fig.14 VDSPL (not shown), Fig.15 VSSPL, VISPL, VAISPL) and DC power pad line DCPDL ( Fig.14 VDPDL, Fig.15 The DC power supply line DCSPL may extend from the non-display area NDA to the first sub-area SB1 and transmit DC power of different voltage levels ( Fig. 9 ELVDD, ELVSS, VINT and Fig.10 The DC power pad lines DCPDL may be arranged in the second sub-area SB2 and electrically connected to the DC power supply lines DCSPL (VDSPL, VSSPL, VISPL, VAISPL), respectively. For example, the DC power source may include a first power source ELVDD and a second power source ELVSS for driving the light emitting element LE, a first initialization power source VINT for initializing the light emitting pixel driver EPD, and a second initialization power source VAINT for initializing the light sensing pixel driver DPD.

[0291] According to an embodiment, the third line group area LGA3 may include another partial area overlapping with the first line group area LGA1. Some other areas of the third line group area LGA3 overlapping with the first line group area LGA1 may also overlap with the DC power supply pad line DCPDL. That is, another partial area of ​​the third line group area LGA3 may overlap with the first line group area LGA1 and the DC power supply pad line DCPDL.

[0292] In some other areas of the third line group area LGA3 overlapping with the first line group area LGA1, the readout pad line ROPDL may overlap with the data pad line DPDL and the DC power pad line DCPDL of the first line group area LGA1. Accordingly, in some other areas of the third line group area LGA3 overlapping with the first line group area LGA1, the light sensing signal of the readout pad line ROPDL can be kept relatively stable and have relatively small interference from the data signal of the data pad line DPDL by the DC power ELVDD, ELVSS, VINT and VAINT of the DC power pad line DCPDL. Accordingly, the distortion of the light sensing signal of the readout pad line ROPDL can be reduced.

[0293] According to an embodiment, the circuit layer 120 may further include data supply lines DSPL extending from the non-display area NDA to the first sub-area SB1 and electrically connected to the data lines DL of the display area DA, respectively, and DC power supply lines (DCSPL: VDSPL, VSSPL, VISPL, VAISPL) arranged in the non-display area NDA and the first sub-area SB1 and respectively transmitting DC power of different voltage levels.

[0294] The DC power supply line DCSPL may include a first power supply line VDSPL transmitting a first power ELVDD, a second power supply line VSSPL transmitting a second power ELVSS, a first initialization power supply line VISPL transmitting a first initialization power VINT, and a second initialization power supply line VAISPL transmitting a second initialization power VAINT.

[0295] In addition, although not shown separately, the DC power supply line DCSPL may also include a DC power supply line supplied to the gate drive circuit 101 and the emission control circuit 102 (see Figure 8 )'s gate level supply.

[0296] Also, according to an embodiment, the circuit layer 120 may further include bending lines BDL disposed in the bending area BA and electrically connecting the lines of the first sub-area SB1 and the lines of the second sub-area SB2 , respectively.

[0297] The bending line BDL may include a data bending line DBDL, at least one first power bending line VDBDL, at least one second power bending line VSBDL, at least one first initialization power bending line VIBDL, and at least one second initialization power bending line VAIBDL. The data bending lines DBDL may be electrically connected between the data supply line DSPL and the data pad line DPDL, respectively. At least one first power bending line VDBDL may be electrically connected between the first power supply line VDSPL and the first power pad line VDPDL. At least one second power bending line VSBDL may be electrically connected between the second power supply line VSSPL and the second power pad line VSPDL. At least one first initialization power bending line VIBDL may be electrically connected between the first initialization power supply line VISPL and the first initialization power pad line VIPDL. At least one second initialization power bending line VAIBDL may be electrically connected between the second initialization power supply line VAISPL and the second initialization power pad line VAIPDL.

[0298] According to an embodiment, the readout pad line ROPDL may extend to the bending area BA, the first sub-area SB1, and the non-display area NDA and may be respectively connected to the readout line ROL of the display area DA. However, this is only an example, and the display device 100 of the embodiment is not limited thereto. That is, according to an embodiment, the readout line ROL may be electrically connected to the readout pad line ROPDL through a readout connection line (not shown) arranged in the non-display area NDA and the first sub-area SB1 and a readout bending line (not shown) of the bending area BA, respectively.

[0299] Reference Fig.16 The display device 100 according to the embodiment may further include a bending hole BDH corresponding to the bending area BA and a dam BNK covering the bending hole BDH. The bending hole BDH may penetrate the inorganic layer including the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, the first interlayer insulating layer 124, the third gate insulating layer 125, and the second interlayer insulating layer 126 in the circuit layer 120.

[0300] The bending hole BDH is used to remove an inorganic layer relatively susceptible to bending stress from the bending area BA.

[0301] The dam BNK protects the bending hole BDH and the bending line in the bending area BA. In addition, the dam BNK may be a spacer supporting a fine pattern mask for arranging the light emitting layer 133 of the light emitting element LE and the photoelectric conversion layer (not shown) of the light sensing element PD among the element layer 130.

[0302] The dam BNK may extend to the first sub-region SB1 or the second sub-region SB2. The dam BNK may include dam layers each formed of an organic layer. For example, the dam BNK may include a dam layer formed of a first planarization layer 127 (see Fig.13 ) and a first dam layer BNL1 made of the same layer as the second planarization layer 128 (see Fig.13 ) is made of the same layer as the third planarization layer 129. In an embodiment, the dam BNK may further include a second dam layer BNL2 arranged on the second dam layer BNL2 and made of the same layer as the third planarization layer 129 (see Fig.13 ) is made of the same layer as the pixel defining layer 132. In an embodiment, the dam BNK may further include a third dam layer BNL3 disposed on the third dam layer BNL3 and made of the same layer as the pixel defining layer 132 (see Fig.13 )A fourth dam layer (not shown) is made of the same layer.

[0303] Each of the data supply line DSPL of the first sub-region SB1 and the data pad line DPDL of the second sub-region SB2 may include a gate electrode located at the first gate insulating layer 122 (see Fig.13 ) on the first gate conductive layer and on the second gate insulating layer 123 (see Fig.13 ) in one of the second gate conductive layers on top.

[0304] Similar to the data pad line DPDL, each of the data dummy lines DDML may be included in one of a first gate conductive layer located on the first gate insulating layer 122 and a second gate conductive layer located on the second gate insulating layer 123 .

[0305] The bending line BDL of the bending area BA (see Fig.15 The bending lines BDL (DBDL, VSBDL, VDBDL, VIBDL, and VAIBDL) of the bending area BA may be disposed on the first dam layer BNL1. That is, the bending lines BDL (DBDL, VSBDL, VDBDL, VIBDL, and VAIBDL) of the bending area BA may be included in the first planarization layer 127 (see Fig.13 ) in the second source / drain conductive layer on top.

[0306] The data bending line DBDL may be electrically connected to the data supply line DSPL through the first data connection hole DCH1 , and may be electrically connected to the data pad line DPDL through the second data connection hole DCH2 .

[0307] Each of the first and second data connection holes DCH1 and DCH2 may penetrate the first dam layer BNL1 , the second interlayer insulating layer 126 , the third gate insulating layer 125 , and the first interlayer insulating layer 124 , or may further penetrate the second gate insulating layer 123 .

[0308] Each of the DC power pad line DCPDL and the DC power supply lines VDSPL, VSSPL, VISPL, and VAISPL may be disposed on the second interlayer insulating layer 126 covering the data pad line DPDL and the data dummy line DDML. That is, each of the DC power pad line DCPDL and the DC power supply lines VDSPL, VSSPL, VISPL, and VAISPL may include a first line layer included in a first source / drain conductive layer located on the second interlayer insulating layer 126. For example, among the DC power pad lines DCPDL, a second power pad line VSPDL transmitting a second power source ELVSS may be disposed on the second interlayer insulating layer 126.

[0309] The second power bending line VSBDL may be disposed on the first dam layer BNL1 , may be electrically connected to the second power supply line VSSPL through the first power connection hole VCH1 , and may be connected to the second power pad line VSPDL through the second power connection hole VCH2 .

[0310] When the second power supply line VSSPL and the second power pad line VSPDL are disposed on the second interlayer insulating layer 126 , each of the first power connection hole VCH1 and the second power connection hole VCH2 may penetrate the first dam layer BNL1 .

[0311] Reference Fig.17 The readout pad line ROPDL may be disposed on the first dam layer BNL1 covering the DC power pad lines DCPDL (VDPDL, VSPDL, VIPDL, and VAIPDL). That is, the readout pad line ROPDL may be included in the second source / drain conductive layer located on the first planarization layer 127 .

[0312] At least some areas of the third line group area LGA3 where the readout pad lines ROPDL are densely concentrated may overlap with the second line group area LGA2, and other remaining areas may overlap with the first line group area LGA1. In some areas of the third line group area LGA3 overlapping with the second line group area LGA2, the readout pad lines ROPDL may overlap with the dummy data lines DDML. Additionally, in some areas of the third line group area LGA3 overlapping with the second line group area LGA2, the readout pad lines ROPDL may directly overlap with the dummy data lines DDML.

[0313] In other words, the dummy data line DDML may be in a floating state and may not be electrically connected to the display driving circuit 200. Accordingly, even in a region where the readout pad line ROPDL directly overlaps the dummy data line DDML, a light sensing signal of the readout pad line ROPDL may not be significantly distorted.

[0314] In some areas of the third line group area LGA3 overlapping with the first line group area LGA1, the readout pad line ROPDL may overlap with the data pad line DPDL of the first line group area LGA1, and also overlap with the DC power pad line DCPDL. That is, in some areas of the third line group area LGA3 overlapping with the first line group area LGA1, the DC power pad line DCPDL may be between the readout pad line ROPDL and the data pad line DPDL in the third direction DR3.

[0315] In this way, the effect of the data signal of the data pad line DPDL on the optical sensing signal of the readout pad line ROPDL can be shielded by the DC power pad line DCPDL. Therefore, even if the readout pad line ROPDL overlaps with the data pad line DPDL, the distortion of the optical sensing signal of the readout pad line ROPDL can be reduced.

[0316] The readout pad line ROPDL may be covered with the second dam layer BNL2.

[0317] Alternatively, when the layer BNK further includes the third dam layer BNL3 , the readout pad line ROPDL may be covered with the second dam layer BNL2 and the third dam layer BNL3 .

[0318] Meanwhile, since the display device 100 according to the embodiment includes the touch sensor layer 150, the circuit layer 120 may further include a touch sensor line TSL (see FIG. 1 ) disposed in the second sub-region SB2 and electrically connected to the touch sensor layer 150. Fig.11 ) and the touch driving circuit 400 between the touch sensor pad line TSPDL (see Fig.19 ). In this case, the light sensing signal of the readout pad line ROPDL may be distorted by the touch driving signal and the touch sensing signal (hereinafter collectively referred to as “touch signal”) of the touch sensor pad line TSPDL.

[0319] Accordingly, the embodiment provides the display device 100 capable of shielding electrical interference of the touch signal of the touch sensor pad line TSPDL to the light sensing signal of the readout pad line ROPDL.

[0320] Fig.18 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Floor plan of Section C. Fig.19 It is shown Fig.18 Floor plan of Section I. Fig. 20 yes Fig.19 An enlarged view of part J. Fig.21 is along Fig. 20 A cross-sectional view taken along line K-K'.

[0321] Reference Fig.18 and Fig.19, the circuit layer 120 of the display device 100 according to the embodiment (see Figure 4 ) may also include a touch sensor layer 150 (see Figure 4 ) of the touch sensor line TSL (see Fig.11 )'s touch sensor pad line TSPDL.

[0322] The touch sensor pad line TSPDL is electrically connected between the touch sensor line TSL of the touch sensor layer 150 and the touch driving circuit 400 .

[0323] The second sub-region SB2 may further include a fourth line group region LGA4 in which the touch sensor pad lines TSPDL are densely concentrated.

[0324] According to an embodiment, the fourth line group area LGA4 may overlap with the DC power pad line (DCPDL: VDPDL, VSPDL, VIPDL, VAIPDL). In addition, the third line group area LGA3 may include some areas overlapping with the fourth line group area LGA4. Accordingly, the portion of the third line group area LGA3 overlapping with the fourth line group area LGA4 may overlap with the touch sensor pad line TSPDL and the DC power pad line DCPDL of the fourth line group area LGA4.

[0325] Reference Fig. 20 and Fig.21 According to an embodiment, each of at least some of the direct current power supply pad lines DCPDL of the circuit layer 120 of the display device 100 may include a first line layer arranged on the second interlayer insulating layer 126 and a second line layer arranged on the second dam layer BNL2 covering the readout pad line ROPDL.

[0326] For example, among the direct current power pad lines DCPDL, the second power pad line VSPDL may include a first line layer VSPDL1 disposed on the second interlayer insulating layer 126 and a second line layer VSPDL2 disposed on the second dam layer BNL2 .

[0327] Among the DC power pad lines DCPDL, since the remaining first and second line layers except for the second power pad line VSPDL are the same as those of the second power pad line VSPDL, redundant description may be omitted below.

[0328] The second line layer VSPDL2 may overlap the first line layer VSPDL1 .

[0329] In addition, according to an embodiment, the touch sensor pad line TSPDL may be disposed on the buffer planarization layer 151 covering the second line layer VSPDL2 .

[0330] As another example, in the second sub-region SB2 , the second line layer VSPDL2 may be covered with the third dam layer BNL3 , and the buffer planarization layer 151 may be disposed on the third dam layer BNL3 .

[0331] The touch sensor pad line TSPDL may overlap at least a portion of the second line layer VSPDL2 among the direct current power supply pad lines DCPDL.

[0332] Accordingly, among the third line group area LGA3 where the readout pad lines ROPDL are densely concentrated, other regions overlapping with the fourth line group area LGA4 where the touch sensor pad lines TSPDL may be densely concentrated may overlap with the second line layer VSPDL2 .

[0333] In other words, in another part of the third line group area LGA3, the second line layer VSPDL2 may be interposed between the readout pad line ROPDL and the touch sensor pad line TSPDL. In this way, the touch signal of the touch sensor pad line TSPDL may be shielded from the light sensing signal of the readout pad line ROPDL. Therefore, it is possible to reduce or prevent the distortion of the light sensing signal of the readout pad line ROPDL caused by the touch signal of the touch sensor pad line TSPDL.

[0334] At the same time, the second line layer VSPDL2 may be electrically connected to the first line layer VSPDL1 by a connection groove CGR penetrating the first dam layer BNL1 and the second dam layer BNL2. For example, the connection groove CGR may be arranged in a linear form extending parallel to a portion of the overlapping region between the first line layer VSPDL1 and the second line layer VSPDL2. In this way, the resistance between the first line layer VSPDL1 and the second line layer VSPDL2 can also be reduced, and the line resistance can be reduced.

[0335] In addition, since outgassing of the organic insulating material included in the first and second dam layers BNL1 and BNL2 can be reduced or eliminated, a warping defect or an oxidation defect of the conductive layer due to outgassing can be reduced or prevented.

[0336] According to an embodiment, since the readout pad lines ROPDL densely concentrated in the third line group area LGA3 of the second sub-area SB2 may be arranged on the first dam layer BNL1, the connection groove CGR may be spaced apart from the third line group area LGA3 in order to arrange the readout pad lines ROPDL. In other words, in the third line group area LGA3, the second line layer VSPDL2 may not contact the first line layer VSPDL1 through the connection groove CGR, and the second line layer VSPDL2 may be arranged on the second dam layer BNL2.

[0337] According to an embodiment, the display device 100 according to an embodiment may further include holes HL arranged in the third line group area LGA3, spaced apart from each other, and penetrating the second line layer VSPDL2. Since the holes HL penetrate the second line layer VSPDL2 and expose the second dam layer BNL2, gas released from the organic insulating material included in the first dam layer BNL1 and the second dam layer BNL2 may be exhausted through the holes HL. According to an embodiment, defects caused by the capture of gas released by the organic insulating material can be reduced or eliminated.

[0338] In addition, according to an embodiment, the touch sensor pad line TSPDL may be spaced apart from the hole HL. In this way, it is possible to prevent the readout pad line ROPDL from directly overlapping the touch sensor pad line TSPDL through the hole HL. In an embodiment, the light sensing signal of the readout pad line ROPDL may not be distorted by the touch signal of the touch sensor pad line TSPDL.

[0339] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the embodiments without departing substantially from the principles of the invention. Therefore, the embodiments of the present invention are used only in a general and descriptive sense and not for a limiting purpose.

[0340] The effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: a substrate including a display area and a non-display area arranged at a periphery of the display area; A circuit layer, wherein the circuit layer is arranged on the substrate; as well as an element layer, the element layer being arranged on the circuit layer and comprising a plurality of light emitting elements and a plurality of light sensing elements, The substrate further comprises a sub-region, the sub-region protruding from the non-display region and the display driving circuit and the scan driving circuit are installed in the sub-region, Wherein, the circuit layer includes: a plurality of light-emitting pixel drivers, the plurality of light-emitting pixel drivers being electrically connected to the plurality of light-emitting elements; a plurality of light sensing pixel drivers, the plurality of light sensing pixel drivers being electrically connected to the plurality of light sensing elements; a plurality of data lines arranged in the display area and electrically connected to the plurality of light-emitting pixel drivers; a plurality of readout lines arranged in the display area and electrically connected to the plurality of light sensing pixel drivers; a plurality of data pad lines arranged in the sub-areas and electrically connected between the plurality of data lines and the display driving circuit; and a plurality of readout pad lines, the plurality of readout pad lines being arranged in the sub-area and electrically connected between the plurality of readout lines and the scan driving circuit, Wherein, the sub-area includes: A first line group region, wherein the plurality of data pad lines are arranged in the first line group region; a second line group region, the second line group region being arranged in the sub-region and spaced apart from the display driving circuit, wherein the second line group region is a dummy region; and a third line group region, the plurality of readout pad lines are arranged in the third line group region, At least a portion of the third line group area overlaps with the second line group area.

2. The display device according to claim 1, further comprising: a plurality of data dummy lines, the plurality of data dummy lines being arranged in the second line group region and being located at the same layer of the circuit layer as the plurality of data pad lines, wherein the second line group area is surrounded by the first line group area in the sub-area, wherein at least a portion of the third line group area overlaps with the first line group area, and The plurality of readout pad lines of the third line group region overlapping the second line group region are relatively sparsely concentrated, and the plurality of readout pad lines of the third line group region overlapping the first line group region are relatively densely concentrated.

3. The display device according to claim 2, wherein: The circuit layer also includes: a plurality of DC power supply lines extending from the non-display area to the sub-areas and transmitting DC power of different voltage levels; and a plurality of DC power supply pad lines, the plurality of DC power supply pad lines being arranged in the sub-areas and being electrically connected to the plurality of DC power supply lines, respectively, In the portion of the third line group area overlapping the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

4. The display device according to claim 3, further comprising: A plurality of holes are arranged in the third line group region and penetrate the plurality of DC power supply pad lines.

5. A display device, comprising: a substrate comprising a main region and a sub-region protruding from one side of the main region; A circuit layer, wherein the circuit layer is arranged on the substrate; as well as a component layer, the component layer being arranged on the circuit layer, wherein the main area includes a display area arranged at a central portion and a non-display area arranged at a periphery of the display area, Wherein, the sub-area includes: bending zone; a first sub-region, the first sub-region being arranged between the first side of the bending region and the main region; and a second sub-region, the second sub-region being connected to a second side of the bending region and in which a display driving circuit and a scan driving circuit are mounted, Wherein, the display area includes: a plurality of emission areas, the plurality of emission areas being spaced apart from one another; a non-emitting region, wherein the non-emitting region is a space between the plurality of emitting regions; and a plurality of light sensing regions, the plurality of light sensing regions being arranged in the non-emitting region, The element layer includes a plurality of light emitting elements arranged in the plurality of emission regions and a plurality of light sensing elements arranged in the plurality of light sensing regions. Wherein, the circuit layer includes: a plurality of light-emitting pixel drivers, the plurality of light-emitting pixel drivers being electrically connected to the plurality of light-emitting elements; a plurality of light sensing pixel drivers, the plurality of light sensing pixel drivers being electrically connected to the plurality of light sensing elements; a plurality of data lines arranged in the display area and electrically connected to the plurality of light-emitting pixel drivers; a plurality of readout lines arranged in the display area and electrically connected to the plurality of light sensing pixel drivers; a plurality of data pad lines arranged in the second sub-region and electrically connected between the plurality of data lines and the display driving circuit; and a plurality of readout pad lines, the plurality of readout pad lines being arranged in the second sub-area and electrically connected between the plurality of readout lines and the scan driving circuit, Wherein, the second sub-area includes: A first line group region, wherein the plurality of data pad lines are arranged in the first line group region; a plurality of second line group areas, the plurality of second line group areas being arranged in the second sub-area, extending from the bending area and spaced apart from the display driving circuit, wherein the second line group areas are dummy areas; and a third line group region in which the plurality of readout pad lines are arranged, and At least a portion of the third line group region overlaps with the plurality of second line group regions.

6. The display device according to claim 5, further comprising: a plurality of data dummy lines arranged in the plurality of second line group regions and extending from the bending region, The plurality of data dummy lines and the plurality of data pad lines are located at the same layer of the circuit layer, and Each of the plurality of second line group areas is surrounded by the bending area and the first line group area.

7. The display device according to claim 6, wherein: The circuit layer also includes: a plurality of DC power supply lines extending from the non-display area to the first sub-area and transmitting DC power of different voltage levels; and a plurality of DC power pad lines, the plurality of DC power pad lines being arranged in the second sub-area and being electrically connected to the plurality of DC power supply lines, respectively, In the portion of the third line group area overlapping the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

8. The display device according to claim 7, wherein: The plurality of DC power pad lines are arranged on an interlayer insulating layer covering the plurality of data pad lines and the plurality of data dummy lines, wherein the plurality of readout pad lines are arranged on a first dam layer covering the plurality of DC power supply pad lines, and Wherein, in the portion of the third line group area overlapping with the first line group area, the plurality of DC power pad lines are interposed between the plurality of readout pad lines and the plurality of data pad lines.

9. The display device according to claim 7, further comprising: A packaging layer, wherein the packaging layer is arranged on the component layer; as well as a touch sensor layer, the touch sensor layer being arranged on the encapsulation layer, The circuit layer further includes a plurality of touch sensor pad lines, which are arranged in the second sub-area and are respectively electrically connected to a plurality of touch sensor lines of the touch sensor layer. The second sub-area further includes a fourth line group area, and the plurality of touch sensor pad lines are arranged in the fourth line group area. At least one of the plurality of DC power pad lines comprises a first line layer and a second line layer overlapping each other, Wherein, the first line layer is arranged on an interlayer insulating layer covering the plurality of data pad lines and the plurality of data dummy lines, The plurality of readout pad lines are arranged on a first dam layer covering the first line layer. wherein the second line layer is arranged on the second dam layer covering the plurality of readout pad lines, and In the portion of the third line group area overlapping the fourth line group area, the plurality of readout pad lines overlap with the plurality of touch sensor pad lines and the second line layer of the fourth line group area.

10. The display device according to claim 9, wherein: The plurality of touch sensor pad lines are arranged on a buffer planarization layer covering the second line layer and overlapped with the second line layer, and Wherein, in the portion of the third line group region overlapping with the fourth line group region, the second line layer is interposed between the plurality of readout pad lines and the plurality of touch sensor pad lines.

11. The display device according to claim 10, further comprising: A plurality of holes are arranged in the third line group region, are spaced apart from each other, and penetrate the second line layer, wherein the plurality of touch sensor pad lines are spaced apart from the plurality of holes.

12. The display device according to claim 11, wherein: A portion of the second line layer spaced apart from the third line group region contacts the first line layer through a connection groove penetrating the first dam layer and the second dam layer.

13. The display device according to claim 7, wherein: The DC power supply comprises: A first power source and a second power source for driving a plurality of light-emitting pixels; A first initialization power source for initializing the plurality of light-emitting pixel drivers; and A second initialization power source is used to initialize the plurality of light sensing pixel drivers.

14. An electronic device comprising: Bracket; a display device, the display device being arranged on the support and emitting light for image display; as well as a cover window, the cover window being arranged on the display device, Wherein, the display device comprises: a substrate comprising a main region and a sub-region protruding from one side of the main region; A circuit layer, wherein the circuit layer is arranged on the substrate; a component layer, the component layer being arranged on the circuit layer; a packaging layer, the packaging layer being arranged on the component layer; and a touch sensor layer arranged on the encapsulation layer, wherein the main area includes a display area arranged at a central portion and a non-display area arranged at a periphery of the display area, Wherein, the sub-area includes: a curved region, the curved region having a curved form; a first sub-region, the first sub-region being arranged between the first side of the bending region and the main region; and a second sub-region, the second sub-region being connected to a second side of the bending region and in which a display driving circuit and a scan driving circuit are mounted, Wherein, the display area includes: a plurality of emission areas, the plurality of emission areas being spaced apart from one another; a non-emitting region, wherein the non-emitting region is a space between the plurality of emitting regions; and a plurality of light sensing regions, the plurality of light sensing regions being arranged in the non-emitting region, The element layer includes a plurality of light emitting elements arranged in the plurality of emission regions and a plurality of light sensing elements arranged in the plurality of light sensing regions. Wherein, the circuit layer includes: a plurality of light-emitting pixel drivers, the plurality of light-emitting pixel drivers being electrically connected to the plurality of light-emitting elements; a plurality of light sensing pixel drivers, the plurality of light sensing pixel drivers being electrically connected to the plurality of light sensing elements; a plurality of data lines arranged in the display area and electrically connected to the plurality of light-emitting pixel drivers; a plurality of readout lines arranged in the display area and electrically connected to the plurality of light sensing pixel drivers; a plurality of data pad lines, the plurality of data pad lines being arranged in the second sub-area and electrically connected between the plurality of data lines and the display driving circuit; a plurality of data dummy lines arranged in the second sub-region, extending from the bending region, and spaced apart from the display driving circuit; and a plurality of readout pad lines, the plurality of readout pad lines being arranged in the second sub-area and electrically connected between the plurality of readout lines and the scan driving circuit, Wherein, the second sub-area includes: A first line group region, wherein the plurality of data pad lines are arranged in the first line group region; a second line group region in which the plurality of data dummy lines are arranged and the second line group regions are spaced apart from each other; and a third line group region, the plurality of readout pad lines are arranged in the third line group region, At least a portion of the third line group area overlaps with the second line group area.

15. The electronic device as claimed in claim 14, wherein: The plurality of data dummy lines and the plurality of data pad lines are located at the same layer of the circuit layer, wherein the second wire group area is surrounded by the bending area and the first wire group area, and Wherein, the circuit layer further includes: a plurality of DC power supply lines extending from the non-display area to the first sub-area and transmitting DC power of different voltage levels; and a plurality of DC power pad lines, the plurality of DC power pad lines being arranged in the second sub-area and being electrically connected to the plurality of DC power supply lines, respectively, In the portion of the third line group area overlapping the first line group area, the plurality of readout pad lines overlap with the plurality of data pad lines and the plurality of DC power pad lines of the first line group area.

16. The electronic device as claimed in claim 15, wherein: The plurality of DC power pad lines are arranged on an interlayer insulating layer covering the plurality of data pad lines and the plurality of data dummy lines, wherein the plurality of readout pad lines are arranged on a first dam layer covering the plurality of DC power supply pad lines, and Wherein, in the portion of the third line group area overlapping with the first line group area, the plurality of DC power pad lines are interposed between the plurality of readout pad lines and the plurality of data pad lines.

17. The electronic device as claimed in claim 15, wherein: The circuit layer also includes: a plurality of touch sensor pad lines, the plurality of touch sensor pad lines being arranged in the second sub-area and being electrically connected to the plurality of touch sensor lines of the touch sensor layer, respectively, The second sub-area further includes a fourth line group area, and the plurality of touch sensor pad lines are arranged in the fourth line group area. At least one of the plurality of DC power pad lines comprises a first line layer and a second line layer overlapping each other, Wherein, the first line layer is arranged on an interlayer insulating layer covering the plurality of data pad lines and the plurality of data dummy lines, The plurality of readout pad lines are arranged on a first dam layer covering the first line layer. wherein the second line layer is arranged on the second dam layer covering the plurality of readout pad lines, and In the portion of the third line group area overlapping the fourth line group area, the plurality of readout pad lines overlap with the plurality of touch sensor pad lines and the second line layer of the fourth line group area.

18. The electronic device as claimed in claim 17, wherein: The plurality of touch sensor pad lines are arranged on a buffer planarization layer covering the second line layer and overlapped with the second line layer, and Wherein, in the portion of the third line group region overlapping with the fourth line group region, the second line layer is interposed between the plurality of readout pad lines and the plurality of touch sensor pad lines.

19. The electronic device as claimed in claim 18, wherein: The display device further includes a plurality of holes arranged in the third line group region, spaced apart from each other, and penetrating the second line layer, wherein the plurality of touch sensor pad lines are spaced apart from the plurality of holes in a horizontal direction, and A portion of the second line layer separated from the third line group region contacts the first line layer through a connection groove penetrating the first dam layer and the second dam layer.

20. The electronic device of claim 15, wherein: The DC power supply comprises: A first power source and a second power source for driving a plurality of light-emitting pixels; A first initialization power source for initializing the plurality of light-emitting pixel drivers; and A second initialization power source is used to initialize the plurality of light sensing pixel drivers.

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