Package, semiconductor device, and method for manufacturing package

Abstract

The present invention mitigates restrictions on a position at which a wire is led out from a chip. A package according to the present invention is provided with a first chip, a second chip, and an extended redistribution layer. The first chip has a first wiring layer formed on a surface thereof. The second chip is provided with a second wiring layer formed on the surface of the second chip; and at least the length of the second chip in the transverse direction is shorter than the length of the first chip. The extended redistribution layer extends in a lateral direction with respect to the second chip, and is electrically connected to the first wiring layer and the second wiring layer. A size of the extended redistribution layer may be equal to a size of a surface of the first chip. The extended redistribution layer may be directly bonded to the first wiring layer.

Description

Technical Field

[0001] The present technology relates to a package, a semiconductor device, and a method for manufacturing the package. In particular, the present technology relates to a package and a wiring structure of a semiconductor device. Background Art

[0002] In a package of a semiconductor chip, a three-dimensional integrated structure in which divided semiconductor chips are stacked can be used to suppress an increase in mounting area. As such a three-dimensional integrated structure, for example, there is a structure in which wiring layers of a first chip and a second chip having the same size are stacked to face each other (for example, see Patent Document 1). In addition, there is a structure in which a first chip and a second chip having the same size are stacked with an adhesive layer interposed therebetween (for example, see Patent Document 2).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 10651224

[0006] Patent Document 2: U.S. Patent No. 10734430 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] However, in the above-described conventional technology, in the case where the chip size is small, the wiring area of ​​the chip is also small, and therefore, there is a possibility that restrictions on the lead-out positions of the wiring from the chip increase.

[0009] The present technology has been made in view of such circumstances, and an object of the present technology is to relax restrictions on the lead-out positions of wirings from a chip.

[0010] Solution to the problem

[0011] The present technology has been made to solve the above-mentioned problems, and the first aspect of the present technology is a package, which includes: a first chip having a front surface on which a first wiring layer is formed; a second chip having a front surface on which a second wiring layer is formed and having a length in a lateral direction that is at least shorter than that of the first chip; and an extended redistribution layer extending from the second chip in a lateral direction and electrically connected to the first wiring layer and the second wiring layer. Thereby, the restriction on the lead-out position of the wiring from the second chip is relaxed.

[0012] In addition, in the first aspect, the size of the extended redistribution layer may be equal to the size of the front surface of the first chip. Thus, an effect is produced that the first chip, the second chip, and the extended redistribution layer are cut together.

[0013] In addition, in the first aspect, the extended redistribution wiring layer can be directly bonded to the first wiring layer, thereby producing an effect of reducing the gap between the first wiring layer and the second wiring layer.

[0014] In addition, the first aspect may further include a support member that supports the extended redistribution layer on an extended region extending in a lateral direction from the mounting region of the second chip, thereby producing an effect of forming the extended redistribution layer larger than the size of the second chip.

[0015] Furthermore, in the first aspect, the support member may include at least one of a protective film or a dummy chip. Thereby, an effect is produced in that the extended redistribution layer is supported on the extended region extending in the lateral direction from the mounting region of the second chip.

[0016] In addition, the first aspect may further include a through electrode formed in at least one of the first chip, the second chip, or the support member, whereby wirings of the first chip and the second chip are led out to the outside.

[0017] In addition, the first aspect may further include an external connection terminal connected to the extended redistribution layer via a through hole formed in the support member. Thus, the wiring of the first chip and the second chip is led out to the outside without the need for a through electrode.

[0018] In addition, the first aspect may further include an extended rear surface redistribution layer extending from the second chip in a lateral direction and formed on the rear surface side of the second chip, thereby producing an effect of leading the wiring of the second chip from the rear surface side of the second chip to the outside.

[0019] In addition, the first aspect may further include a third chip mounted on the extended rear surface redistribution layer in a flip chip manner and having a front surface on which the third wiring layer is formed, thereby achieving the effect of mounting the third chip without increasing the mounting area.

[0020] In addition, in the first aspect, the third wiring layer may be directly bonded to the extended rear surface redistribution layer or bonded to the extended rear surface redistribution layer via a bump, thereby producing an effect of electrically connecting the third chip to the second chip.

[0021] In addition, the first aspect may further include a rear surface support member that supports the extended rear surface redistribution layer on the rear surface side of the second chip in an extended area extending in a lateral direction from the mounting area of ​​the second chip, thereby producing an effect of forming an extended rear surface redistribution layer larger than the size of the second chip.

[0022] Furthermore, in the first aspect, the rear surface support member may include at least one of a protective film or a dummy chip, thereby producing the following effect: the rear surface redistribution layer is supported and extended on the rear surface side of the second chip in an extension region extending in a lateral direction from the mounting region of the second chip.

[0023] In addition, the first aspect may further include a through electrode formed in at least one of the third chip or the rear surface support member. Thus, wirings of the first chip and the second chip are led out to the outside from the rear surface side of the second chip.

[0024] In addition, the first aspect may further include a support substrate provided on the rear surface side of the third chip. Thus, an effect of reinforcing the stacked structure of the first chip, the second chip, and the third chip is produced.

[0025] Furthermore, in the first aspect, any one of the first chip or the second chip may be an optical chip arranged in the uppermost layer. Thus, the following effect is brought about: optical chips are stacked while allowing light to enter or leave the outside.

[0026] In addition, the first aspect may further include a transparent resin formed on the optical chip. Therefore, there is brought about the effect of sealing the optical chip while allowing light to enter or exit from the outside.

[0027] In addition, the first aspect may further include a transparent substrate disposed on the transparent resin. Therefore, there is brought about the effect of sealing the optical chip while allowing light to enter or exit the outside.

[0028] In addition, the first aspect may further include a fourth chip, wherein the fourth wiring layer is formed by stacking on the rear surface of the first chip via the adhesive layer. Therefore, there is an effect of increasing the number of stacked chips.

[0029] In addition, the first aspect may further include a light shielding film formed at a position in contact with the adhesive layer, thereby producing an effect of shielding light incident from the surface opposite to the light receiving surface.

[0030] In addition, the first aspect may further include a through electrode that penetrates the first chip and the adhesive layer and electrically connects the first wiring layer and the fourth wiring layer; and an insulating layer that insulates the through electrode from the semiconductor layer of the first chip, wherein the adhesive layer is retreated from the semiconductor layer of the first chip at the embedded position of the through electrode, and the film thickness of the insulating layer at the position of the adhesive layer is thicker than the film thickness of the insulating layer at the position of the semiconductor layer. Therefore, an effect of backfilling the retreated portion of the adhesive layer with the insulating layer is produced.

[0031] Furthermore, in the first aspect, when the film thickness of the adhesive layer is a and the film thickness of the insulating layer at the position of the semiconductor layer is b, the relationship of a<b can be satisfied. Thus, the retreated portion of the adhesive layer is completely backfilled by the insulating layer.

[0032] In addition, the first aspect may further include: a pad electrode, the through electrode connected to the pad electrode; and a plurality of vias connected to a surface of the pad electrode opposite to a surface to which the through electrode is connected. Thus, the effect of alleviating the influence of stress caused by the through electrode is achieved.

[0033] In addition, the first aspect may further include: a pad electrode to which the through electrode is connected; and a via hole connected to a surface of the pad electrode opposite to the surface to which the through electrode is connected at a position separated from the axis of the through electrode. Thus, the stress applied from the through electrode to the via hole is relieved.

[0034] In addition, the first aspect may further include: a pad electrode, the through electrode connected to the pad electrode; and an etching stopper layer formed on the pad electrode and provided with a through hole, the through electrode passing through the through hole. Thus, an effect of connecting the through electrode to the pad electrode by self-alignment is produced.

[0035] In addition, a second aspect is a semiconductor device including: a first chip having a front surface on which a first wiring layer is formed, and including through electrodes having different diameters and electrically connected to the first wiring layer; a second chip having a front surface on which a second wiring layer is formed, the second chip being stacked on the first chip so that the first wiring layer and the second wiring layer face each other. Thus, an effect of relaxing restrictions on the configuration of the through electrodes is produced.

[0036] In addition, the second aspect may further include a rear surface wiring formed on the rear surface of the first chip and a third chip mounted on the rear surface wiring in a flip chip manner, thereby achieving an effect of mounting the third chip without increasing the mounting area.

[0037] In addition, the second aspect may further include an embedded wire embedded in the semiconductor layer of the first chip, wherein the through-electrode with a smaller diameter among the through-electrodes with different diameters is electrically connected to the first wiring layer via the embedded wire. Thus, the following effect can be obtained: the aspect ratio of the through-electrode with a smaller diameter is reduced.

[0038] In the second aspect, the through-electrode may include a first through-electrode connected to the signal line and a second through-electrode connected to the power line and having a diameter larger than that of the first through-electrode. This can relax the constraints on the wiring position of the signal line and stabilize the power supply.

[0039] In addition, a third aspect is a semiconductor device, comprising: a first chip, a first wiring layer including a plurality of pad electrodes is formed on the front surface of the first chip, the first chip includes different numbers of through electrodes contacting the pad electrodes; a second chip, a second wiring layer is formed on the front surface of the second chip, the second chip is stacked on the first chip so that the first wiring layer and the second wiring layer face each other. Thus, the through electrodes can be uniformly buried, and the effect of setting the resistance for each through electrode can be obtained.

[0040] In addition, the third aspect may further include a rear surface wiring formed on the rear surface of the first chip and a third chip mounted on the rear surface wiring in a flip chip manner, thereby achieving an effect of mounting the third chip without increasing the mounting area.

[0041] In addition, the third aspect may further include an embedded wire embedded in the semiconductor layer of the first chip, wherein one through-electrode in contact with the pad electrode among the different numbers of through-electrodes in contact with the pad electrode is electrically connected to the first wiring layer via the embedded wire, thereby producing an effect of reducing the aspect ratio of one through-electrode in contact with the pad electrode among the plurality of through-electrodes in contact with the pad electrode.

[0042] In addition, in the third aspect, the diameter of the smaller number of through electrodes in contact with the pad electrode may be smaller than the diameter of the larger number of through electrodes in contact with the pad electrode among the different number of through electrodes in contact with the pad electrode. This has the effect of easing the restrictions on the configuration of the through electrodes.

[0043] In addition, the fourth aspect is a method for manufacturing a package, the method comprising the following steps: forming a first wiring layer on a wafer divided into solid pieces of a first chip; arranging a second chip on a supporting substrate wafer, the second chip having a second wiring layer and having a size smaller than the front surface of the first chip, forming a supporting member on the supporting substrate wafer, the supporting member being adjacent to the second chip so as to be equal in size to the front surface of the first chip and equal in height to the second chip, forming an extended redistribution layer having a size equal to the front surface of the first chip on the second wiring layer and the supporting member, electrically connecting the first wiring layer and the second wiring layer so that the first wiring layer and the second wiring layer face each other via the extended redistribution layer, and dividing the package into package solid blocks, wherein the second chip is stacked on the first chip via the extended redistribution layer. Thus, an effect of collectively dividing the first and second chips of different sizes into solid pieces in a stacked state is produced.

[0044] In addition, the fourth aspect may further include the following steps: forming a first through-electrode connected to the first wiring layer in the first chip, forming a second through-electrode connected to the second wiring layer in the second chip, forming an extended rear surface rewiring layer on the rear surface of the second chip and the rear surface of the supporting member, allowing the extended rear surface rewiring layer to be cut so that its size is equal to the front surface of the first chip, and mounting a third chip in a flip-chip manner, the third chip having a front surface on which a third wiring layer is formed on the extended rear surface rewiring layer, wherein the package is divided into a plurality of solid packages, in which the second chip is stacked on the first chip via the extended rear surface rewiring layer, and the third chip is stacked on the second chip via the extended rear surface rewiring layer. Thus, an effect of collectively dividing the first chip, the second chip, and the third chip of different sizes into solid blocks in a stacked state is produced.

[0045] In addition, the fourth aspect may also include: forming an extended rear surface rewiring layer on the rear surface of the second chip and the rear surface of the support member, allowing the extended rear surface rewiring layer to be cut so that its size is equal to the front surface of the first chip, mounting a third chip on the extended rear surface rewiring layer in a flip chip manner, the third chip having a third wiring layer and having a size smaller than the front surface of the first chip, forming a rear surface support member adjacent to the third chip on the extended rear surface so that the size of the rear surface support member is equal to the front surface of the first chip, and forming a through electrode in at least one of the third chip or the rear surface support member, wherein the package is divided into a package solid block, wherein the second chip is stacked on the first chip via the extended rear surface rewiring layer, and the third chip is stacked on the second chip via the extended rear surface rewiring layer. Thus, it has the effect of collectively dividing the first chip, the second chip, and the third chip of different sizes into a solid block in a stacked state while being able to make electrical connections from the rear surface side of the package to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a cross-sectional view showing a configuration example of the package according to the first embodiment.

[0047] Figure 2 is a plan view showing a configuration example of a virtual chip according to the first embodiment.

[0048] Figure 3 is a plan view showing another example of the dummy chip according to the first embodiment.

[0049] Figure 4is a plan view showing another example of the dummy chip according to the first embodiment.

[0050] Figure 5 are first cross-sectional views and plan views showing an example of a method for manufacturing a package according to the first embodiment.

[0051] Figure 6 is a second cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0052] Figure 7 is a third cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0053] Figure 8 is a fourth cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0054] Fig. 9 is a fifth cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0055] Fig.10 is a sixth cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0056] Fig.11 is a seventh cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0057] Fig.12 is an eighth cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0058] Fig.13 is a ninth cross-sectional view illustrating an example of the method for manufacturing the package according to the first embodiment.

[0059] Fig.14 is a tenth cross-sectional view showing an example of a method for manufacturing the package according to the first embodiment.

[0060] Fig.15 is an eleventh cross-sectional view showing an example of a method for manufacturing the package according to the first embodiment.

[0061] Fig.16 is a twelfth cross-sectional view showing an example of the method for manufacturing the package according to the first embodiment.

[0062] Fig.17 is a cross-sectional view showing a configuration example of a package according to the second embodiment.

[0063] Fig.18is a first cross-sectional view showing an example of a method for manufacturing a package according to the second embodiment.

[0064] Fig.19 is a second cross-sectional view showing an example of a method for manufacturing the package according to the second embodiment.

[0065] Fig. 20 is a third cross-sectional view showing an example of the method for manufacturing the package according to the second embodiment.

[0066] Fig.21 is a fourth cross-sectional view showing an example of a method for manufacturing the package according to the second embodiment.

[0067] Fig. 22 is a fifth cross-sectional view showing an example of a method for manufacturing the package according to the second embodiment.

[0068] Fig.23 is a cross-sectional view showing a configuration example of a package according to a third embodiment.

[0069] Fig.24 is a cross-sectional view showing a configuration example of a package according to a fourth embodiment.

[0070] Fig.25 is a sectional view showing a configuration example of a package according to a fifth embodiment.

[0071] Fig.26 is a cross-sectional view showing a configuration example of a package according to a sixth embodiment.

[0072] Fig. 27 is a sectional view showing a configuration example of a package according to a seventh embodiment.

[0073] Fig.28 is a sectional view showing a configuration example of a package according to an eighth embodiment.

[0074] Fig.29 is a first cross-sectional view showing an example of a method for manufacturing a package according to an eighth embodiment.

[0075] Fig.30 is a second cross-sectional view showing an example of the method for manufacturing the package according to the eighth embodiment.

[0076] Fig.31 is a third cross-sectional view showing an example of a method for manufacturing a package according to the eighth embodiment.

[0077] Fig.32 is a fourth cross-sectional view showing an example of a method for manufacturing a package according to the eighth embodiment.

[0078] Fig.33 is a fifth cross-sectional view showing an example of a method for manufacturing a package according to the eighth embodiment.

[0079] Fig.34 is a sixth cross-sectional view showing an example of a method for manufacturing a package according to the eighth embodiment.

[0080] Fig.35 is a seventh cross-sectional view showing an example of a method for manufacturing a package according to the eighth embodiment.

[0081] Fig.36 is a sectional view showing a configuration example of a package according to a ninth embodiment.

[0082] Fig.37 is an enlarged cross-sectional view showing a part of a package according to a ninth embodiment.

[0083] Fig.38 is a cross-sectional view showing an example of a method for manufacturing a through-electrode of a package according to a ninth embodiment.

[0084] Fig.39 is a cross-sectional view showing a configuration example of a pad electrode of a package according to a tenth embodiment.

[0085] Fig.40 is a cross-sectional view showing a configuration example of a pad electrode of a package according to an eleventh embodiment.

[0086] Fig.41 is a cross-sectional view showing a configuration example of a package according to a twelfth embodiment.

[0087] Fig.42 is a cross-sectional view showing a configuration example of a package according to a thirteenth embodiment.

[0088] Fig.43 is a cross-sectional view showing a configuration example of a package according to a fourteenth embodiment.

[0089] Fig.44 This is a block diagram showing a schematic configuration example of a vehicle control system.

[0090] Fig.45 It is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0091] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0092] 1. First Embodiment (Example in which the First Chip is Mounted on an Extended Rewiring Layer Extending from the Second Chip)

[0093] 2. Second Embodiment (An embodiment in which the first chip is mounted on an extended redistribution layer extending from the second chip, the third chip is mounted on an extended rear surface redistribution layer extending from the second chip, and the through-electrode connected to the extended rear surface redistribution layer is connected to the outside)

[0094] 3. Third embodiment (an embodiment in which the first chip is mounted on an extended redistribution layer extending from the second chip, the third chip is mounted on an extended rear surface redistribution layer extending from the second chip, and a through-electrode redistribution layer connected to the extended rear surface is formed on a protective film)

[0095] 4. Fourth Embodiment (Example in which the first chip is mounted on an extended redistribution layer extending from the second chip, and a through electrode connected to the extended redistribution layer is formed around the second chip)

[0096] 5. Fifth Embodiment (Example in which the second chip is mounted on an extended redistribution layer extending from the first chip, and external connection terminals formed around the first chip are connected to the extended redistribution layer)

[0097] 6. Sixth Embodiment (An Example in Which a First Chip and a Second Chip Are Directly Bonded, and an Extended Rewiring Layer Extended from a Third Chip Is Connected to a Rear Surface Wiring Layer of a Second Chip)

[0098] 7. Seventh Embodiment (Example of Forming a Five-Layer Stacked Structure of a Chip by Using an Extended Rewiring Layer and an Extended Rear Surface Rewiring Layer)

[0099] 8. Eighth Embodiment (Example in which the first chip and the second chip are bonded via an adhesive layer, and an extended redistribution layer extending from the third chip is connected to a wiring layer of the second chip)

[0100] 9. Ninth Embodiment (Example in which the first chip and the second chip are bonded via an adhesive layer, and an insulating layer of a penetration electrode penetrating the second chip is embedded in a receding portion of the adhesive layer)

[0101] 10. Tenth Embodiment (Example in which a via hole formed in a pad electrode connecting a through electrode is arranged to be separated from an axis of the through electrode)

[0102] 11. Eleventh Embodiment (Example in which an etching stopper layer is provided on a pad electrode connected to a through electrode and an opening is provided at a position connected to the through electrode)

[0103] 12. Twelfth Embodiment (Example of Providing Multiple Through-Electrodes with Different Diameters on a Chip)

[0104] 13. Thirteenth Embodiment (Example in which a plurality of through-electrodes having different diameters are provided on a chip and the through-electrodes are connected to embedded wires of the chip)

[0105] 14. Fourteenth Embodiment (Example in which the number of through electrodes connected to pad electrodes provided on a chip is different from each other)

[0106] 15. Application examples of mobile objects

[0107] <1. First Embodiment>

[0108] Figure 1 is a cross-sectional view showing a configuration example of the package according to the first embodiment.

[0109] In the drawings, the package 100 includes chips 111, 121, and 131, an extended redistribution layer 141, and an extended rear surface redistribution layer 151. The lengths of the chips 121 and 131 are at least shorter than the width direction DL of the chip 111. With respect to the length in the vertical direction DV, each of the chips 121 and 131 may be shorter, longer, or equal to the chip 111.

[0110] The chips 111, 121, and 131 may constitute a three-layer stacked structure stacked in the height direction DH. At this time, the extended redistribution layer 141 is disposed on the front surface side of the chip 121 and extends from the chip 121 in the lateral direction DL. The extended rear surface redistribution layer 151 is disposed on the rear surface side of the chip 121 and extends from the chip 121 in the lateral direction DL. Then, the chips 111 and 121 are electrically connected to each other via the extended redistribution layer 141, and the chips 121 and 131 are electrically connected to each other via the extended rear surface redistribution layer 151.

[0111] Each of the chips 111 , 121 , and 131 may be a semiconductor chip or may include an optical chip. At this time, the optical chip may be used as an uppermost chip disposed in the package 100 .

[0112] The optical element is formed on the optical chip. The optical element can be a solid-state imaging element, such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS). The light received by the solid-state imaging element can be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, etc. The optical element can be a light receiving element such as a photodiode (PD), or can be a light emitting element such as a laser diode (LD), a light emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL). The optical element can be a microelectromechanical system (MEMS) element such as an optical switch or a reflector device. As the substrate of the optical chip, semiconductors such as Si, GaAs, InGaAsP can be used, and dielectrics such as LiNbO3, glass, and transparent resin can also be used.

[0113] Semiconductor elements are formed on semiconductor chips. Semiconductor elements may include transistors, resistors, capacitors, etc. In a semiconductor chip, a memory may be formed, a processor may be formed, a signal processing circuit may be formed, a data processing circuit may be formed, an interface circuit may be formed, or an optical element may be formed. For example, in a semiconductor chip, a hardware circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) may be formed. The material of the matrix material for the semiconductor chip may be Si, GaAs, SiC, GaN, InGaAsP, etc.

[0114] In the following description, a case in which a rear surface irradiation type solid-state imaging element is formed on the chip 111 , and a semiconductor element is formed on each of the chips 121 and 131 will be taken as an example.

[0115] The chip 111 includes a semiconductor layer 112 and a wiring layer 113. The semiconductor layer 112 is provided with an imaging area and a non-imaging area. In the imaging area, pixels and pixel transistors arranged in a matrix along the row direction and the column direction are provided. In the non-imaging area, a peripheral circuit that drives the pixel transistor and outputs a signal read from the pixel is provided.

[0116] The wiring layer 113 is formed on the front surface side of the semiconductor layer 112. The wiring layer 113 is provided with wiring and a pad electrode 114 embedded in an insulating layer. In addition, a through electrode 116 is embedded in the semiconductor layer 112. The through electrode 116 is connected to the pad electrode 114 of the wiring layer 113. In addition, a protective film 115 is formed on the rear surface side of the semiconductor layer 112. At this time, the protective film 115 is formed in the semiconductor layer 112 in a manner surrounding the periphery of the through electrode 116, and the through electrode 116 can be insulated from the semiconductor layer 112. A bonding wire 118 is connected to the through electrode 116 so as to be connected to the outside.

[0117] For each pixel, an on-chip lens 117 is formed on the protective film 115. As a material of the on-chip lens 117, for example, a transparent resin such as acrylic resin or polycarbonate can be used. Note that a color filter may be provided for each pixel between the semiconductor layer 112 and the on-chip lens 117. At this time, the color filter may constitute, for example, a Bayer array.

[0118] The chip 121 includes a semiconductor layer 122 and a wiring layer 123. The wiring layer 123 is formed on the semiconductor layer 122. The wiring layer 123 is provided with wiring and a pad electrode 124 embedded in an insulating layer. In addition, a through electrode 126 is buried in the semiconductor layer 122. The through electrode 126 is connected to the pad electrode 124 of the wiring layer 123. In addition, a protective film 127 is formed in the lateral direction DL of the chip 121. The protective film 127 may be in contact with the side of the chip 121. The position of the front surface of the protective film 127 in the height direction DH may be made substantially equal to the position of the front surface of the chip 121 in the height direction DH. In addition, the position of the rear surface of the protective film 127 in the height direction DH may be made substantially the same as the position of the rear surface of the chip 121 in the height direction DH. The position of the end of the protective film 127 in the lateral direction DL may be consistent with the position of the end of the chip 111 in the lateral direction DL. The protective film 127 is an embodiment of a support member described in the claims.

[0119] The chip 131 includes a semiconductor layer 132 and a wiring layer 133. The wiring layer 133 is formed on the semiconductor layer 132. The wiring layer 133 is provided with a wiring 134 and a pad electrode 135 embedded in an insulating layer. A bump electrode 136 is formed on the pad electrode 135. Note that the bump electrode 136 may be a solder ball or a columnar electrode. In addition, each of the semiconductor layers 112, 122, and 132 may be a semiconductor substrate, a thinned semiconductor substrate, or a semiconductor layer for a silicon on insulator (SOI) substrate.

[0120] As a material for the insulating layer used in the wiring layers 113, 123, 133 and the protective film 115, for example, SiO2 can be used. As a material for each of the wiring and pad electrodes 114, 124 and 135 of the wiring layers 113, 123 and 133, for example, a metal such as Al or Cu can be used. As a material for the through electrodes 116 and 126, for example, a metal such as Cu, Ti, Ta, Al, W, Ni, Ru or Co can be used, and a stacked structure of a plurality of materials can be used. As a material for the bonding wire 118, for example, a metal such as Au or Al can be used.

[0121] The extended redistribution layer 141 extends from the chip 111 in the lateral direction DL so as to be equal to the length of the chip 121 in the lateral direction DL. At this time, the position of the end of the extended redistribution layer 141 in the lateral direction DL and the position of the end of the chip 111 in the lateral direction DL may coincide with each other. The extended redistribution layer 141 extends from the mounting area RA of the chip 121 to the extension area RB extending in the lateral direction DL.

[0122] The extended rewiring layer 141 includes an insulating layer 143 and rewiring 144. The rewiring 144 is embedded in the insulating layer 143. In addition, vias 145 that perform interlayer connection of the rewiring 144 may be formed in the extended rewiring layer 141.

[0123] The chip 121 is disposed on one surface of the extended redistribution layer 141, and the protective film 127 is disposed in the extended region RB of the surface. The redistribution layer 144 of the extended redistribution layer 141 may be connected to the wiring of the wiring layer 123 via the via 145. At this time, the extended redistribution layer 141 may be supported by the chip 121 and the protective film 127.

[0124] The chip 111 is arranged on the other surface of the extended redistribution layer 141. At this time, the chip 111 and the extended redistribution layer 141 can be directly bonded so that the wiring layer 113 of the chip 111 faces the extended redistribution layer 141. In this direct bonding, hybrid bonding can be used. In this hybrid bonding, wiring exposed on the front surface of the wiring layer 113 and wiring exposed on the front surface of the extended redistribution layer 141 are formed at positions facing each other. At this time, Cu can be used as the material of these wirings. In addition, each of the wiring of the wiring layer 113 and the wiring of the extended redistribution layer 141 is recessed from the front surface of the insulating layer of the wiring layer 113 and the front surface of the insulating layer of the extended redistribution layer 141 by about tens of nm. Then, after performing the front surface treatment of these insulating layers, the insulating layers are brought into contact facing each other so that the insulating layers are connected to each other. At this time, a small gap is formed between the wiring of the wiring layer 113 and the wiring of the extended redistribution layer 141. Then, heat treatment is performed in a state where the insulating layer of the wiring layer 113 and the insulating layer of the extended redistribution layer 141 are pressed against each other. Thereby, the wirings of the wiring layer 113 and the wirings of the extended redistribution layer 141 are extended, these wirings are in contact with each other, Cu is mutually diffused, and a junction between the wirings is formed.

[0125] The extended rear surface redistribution layer 151 extends from the chip 121 in the lateral direction DL so as to be equal to the length of the chip 111 in the lateral direction DL. At this time, the position of the end of the extended rear surface redistribution layer 151 in the lateral direction DL and the position of the end of the chip 111 in the lateral direction DL may coincide with each other. The extended rear surface redistribution layer 151 extends from the mounting area RA of the chip 121 to the extension area RB extending in the lateral direction DL.

[0126] The extended rear surface rewiring layer 151 includes an insulating layer 153, a rear surface rewiring layer 154 and a protective film 155. The insulating layer 153 is formed on the rear surface of the semiconductor layer 112 and the protective film 127. At this time, the insulating layer 153 is formed in the semiconductor layer 122 so as to surround the periphery of the through electrode 126, and the through electrode 126 can be insulated from the semiconductor layer 112. The rear surface rewiring 154 is formed on the insulating layer 153. The rear surface rewiring layer 154 can be electrically connected to the through electrode 126 and the bump electrode 136. The chip 131 is mounted on the extended rear surface rewiring layer 151 in a flip-chip manner via the bump electrode 136. Note that the chip 131 can be directly bonded to the extended rear surface rewiring layer 151. In addition, a protective film 155 is formed on the insulating layer 153 to cover the rear surface rewiring 154.

[0127] The size of the front surface of the extended redistribution layer 141 and the extended rear surface redistribution layer 151 may be equal to that of the front surface of the chip 111. The fact that the sizes of the front surfaces are equal means that not only the lengths in the lateral direction DL but also the lengths in the vertical direction DV are equal to each other.

[0128] The extended redistribution layer 141 and the extended back surface redistribution layer 151 may be formed in a similar manner to a redistribution layer for a fan-out wafer level package (FOWLP).

[0129] As materials for the insulating layers 143 and 153 of the extended rewiring layer 141 and the extended rear surface rewiring layer 151, for example, a photosensitive insulating resin having SiO2, SiON, SiN, SiOC or SiCN can be used in the case of an inorganic film, and a photosensitive insulating resin having silicone, polyimide, acrylic, epoxy resin, etc. as a skeleton can be used in the case of an organic film. As materials for the rewiring 144, the rear surface rewiring 154 and the via 145, for example, metals such as Cu, Ti, Ta, Al, W, Ni, Ru and Co can be used, and a laminated structure of a plurality of materials can be used.

[0130] An underfill 137 is provided between the extended rear surface redistribution layer 151 and the chip 131. The material of the underfill 137 is, for example, a thermosetting resin such as epoxy resin.

[0131] A dummy chip 138 is arranged around the chip 131. At this time, the dummy chip 138 can be mounted on the extended rear surface redistribution layer 151 separately from the chip 131. The dummy chip 138 can be fixed to the extended rear surface redistribution layer 151 via an adhesive layer. The front surface of the dummy chip 138 is flattened. The position of the plane of the dummy chip 138 in the height direction DH can be made substantially equal to the position of the top surface of the chip 131 in the height direction DH. The material of the dummy chip 138 can be a semiconductor such as Si or an inorganic material such as glass or ceramic. It should be noted that the chip 131 can be arranged at the center of the dummy chip 138, or the dummy chip 138 can be arranged in an area including the front end, the rear end, the left end and the right end. By arranging the dummy chip 138 on the extended rear surface redistribution layer 151, the mechanical strength and heat dissipation from the rear surface of the package 100 can be improved. It should be noted that the arrangement position of the dummy chip 138 can be determined so that the heat dissipation from the package 100 is uniform. There is no need to provide the dummy chip 138 .

[0132] In addition, a protective film 139 is formed on the extended rear surface redistribution layer 151 in such a manner as to cover the chip 131 and the dummy chip 138. The support substrate 161 is disposed on the protective film 139. At this time, the positions of the ends of the protective film 139 and the support substrate 161 in the lateral direction DL and the position of the ends of the chip 111 in the lateral direction DL may coincide with each other. By arranging the support substrate 161 on the protective film 139, the mechanical strength and the heat dissipation from the rear surface of the package 100 may be improved. The dummy chip 138 and the protective film 139 are embodiments of the rear surface support member described in the claims.

[0133] The material of the protective films 127 and 139 includes an insulating layer of an inorganic or organic material, and a plurality of films may be stacked. Examples of the films include inorganic films such as SiO2, SiON, SiN, SiOC, or SiCN, organic films such as resins having silicone, polyimide, acrylic, or epoxy resin as a skeleton, and filler-containing materials such as SiO2, Al2O3, AlN, or BN. The material of the support substrate 161 may be, for example, Si or glass. The material of the protective films 127 and 155 may be a molding material.

[0134] In addition, there may be multiple chips 121 and multiple chips 131. When multiple chips 121 are provided, the multiple chips 121 may be connected to each other via the extended redistribution layer 141. When multiple chips 131 are provided, the multiple chips 131 may be connected to each other via the extended rear surface redistribution layer 151.

[0135] Figures 2 to 4 is a plan view showing a modified example of the virtual chip according to the first embodiment.

[0136] exist Figure 2 In a, a dummy chip 138 is disposed on the extended rear surface redistribution layer 151 so as to surround the periphery of the chip 131.

[0137] exist Figure 2 In b, four dummy chips 129 are disposed on the extended rear surface redistribution layer 151 so as to be adjacent to the four corners of the chip 131 .

[0138] exist Figure 3 In a, four dummy chips 148 and 158 are arranged separately from each other on the extended rear surface redistribution layer 151 so as to surround the periphery of the chip 131. At this time, the length of the dummy chip 158 in the vertical direction DV is equal to the length of the chip 131 in the vertical direction DV.

[0139] exist Figure 3 In b, four dummy chips 168 and 178 are arranged separately from each other on the extended rear surface redistribution layer 151 so as to surround the periphery of the chip 131. At this time, the length of the dummy chip 178 in the horizontal direction DL is equal to the length of the chip 131 in the horizontal direction DL.

[0140] exist Figure 4 In a, two dummy chips 148 are arranged on the extended rear surface redistribution layer 151 so as to sandwich the chip 131 in the vertical direction DV. At this time, the length of the dummy chip 148 in the horizontal direction DL is longer than the length of the chip 131 in the horizontal direction DL.

[0141] exist Figure 4 In b, two dummy chips 168 are disposed on the extended rear surface redistribution layer 151 to sandwich the chip 131 in the lateral direction DL. At this time, the length of the dummy chip 168 in the up-down direction DV is longer than the length of the chip 131 in the up-down direction DV.

[0142] Figures 5 to 16 is a cross-sectional view showing an example of a method for manufacturing the package according to the first embodiment.

[0143] exist Figure 5 In a, a wiring layer 113 provided with wiring and pad electrodes 114 is formed on a semiconductor wafer 112'. A plurality of chips 111 for a plurality of packages 100 can be cut out from the semiconductor wafer 112'. At this time, in the semiconductor wafer 112', an optical element can be formed for each portion from which the chip 111 is cut out. For example, the semiconductor wafer 112' can be divided along a cutting line for dividing the package 100. In the case where a CMOS solid-state imaging element is formed on the chip 111, a photodiode and a pixel transistor can be formed for each portion from which the chip 111 is cut out.

[0144] In addition, Figure 5In b, a semiconductor chip 121 is formed in which a wiring layer 123 is provided on a semiconductor layer 122. In addition, the semiconductor chip 121 can be divided into solid blocks from a semiconductor wafer in which a plurality of semiconductor chips 121 are integrally formed.

[0145] Next, if Figure 6 As shown, the semiconductor chip 121 is temporarily bonded to the support substrate wafer 171 via the adhesive layer 172. Note that the support substrate wafer 171 may have the same shape and size as the semiconductor wafer 112'. At this time, a plurality of semiconductor chips 121 may be temporarily bonded to the support substrate wafer 171 for each package 100 to be divided into solid blocks. Next, a protective film 127 is formed on the support substrate wafer 171 to cover the semiconductor chips 121. The protective film 127 may be formed by chemical vapor deposition (CVD), may be formed by coating, or may be formed by molding.

[0146] Then, if Figure 7 As shown, the protective film 127 is thinned until the semiconductor layer 122 of the semiconductor chip 121 is exposed, and the front surface of the protective film 127 is flattened. In order to thin the protective film 127, a grinder, chemical mechanical polishing (CMP) or etch back can be used. Then, the semiconductor layer 122 and the protective film 127 are temporarily bonded to the support substrate wafer 173 via the adhesive layer 174. The support substrate wafer 173 may have the same shape and size as the semiconductor wafer 112'.

[0147] Then, if Figure 8 As shown, the support substrate wafer 171 on the wiring layer 123 side of the chip 121 is removed. Next, an extended redistribution layer 141 electrically connected to the wiring layer 123 of the chip 121 is formed on the chip 121 and the protective film 127. At this time, the extended redistribution layer 141 extends from the mounting area RA of the chip 121 to the extended area RB.

[0148] Next, if Fig. 9 As shown, the wiring layer 113 and the extended redistribution layer 141 are directly bonded, such that the wiring layer 113 formed on the semiconductor wafer 112 ′ faces the extended redistribution layer 141 .

[0149] Then, if Fig.10 As shown, the semiconductor wafer 112' is thinned from the rear surface side. In this thinning, for example, a grinder, CMP, dry etching, or wet etching can be used. In the case where a rear surface illumination type single imaging element is formed on the semiconductor wafer 112', the exposed surface of the thinned semiconductor wafer 112' becomes a light receiving surface.

[0150] Next, if Fig.11As shown, a through hole in which a through electrode 116 is embedded is formed in the semiconductor wafer 112' by using a method such as photolithography and dry etching, and the pad electrode 114 of the wiring layer 113 is exposed through the through hole. Next, a protective film 115 is formed on the rear surface side of the semiconductor wafer 112' in a manner covering the side wall of the through hole by a method such as CVD. Then, the through electrode 116 embedded in the semiconductor wafer 112' via the protective film 115 is formed. In addition, an on-chip lens 117 is formed on the protective film 115. Note that an anti-reflection film and a color filter may be formed below the on-chip lens 117.

[0151] Next, if Fig.12 As shown, the support substrate wafer 175 is bonded to the semiconductor wafer 112' side through the adhesive layer 176. The support substrate wafer 175 can have the same shape and size as the semiconductor wafer 112'. Note that the adhesive layer 176 can be peeled off from the on-chip lens 117. In order to make the adhesive layer 176 peelable from the on-chip lens 117, an adhesive material whose adhesive force rapidly decreases based on ultraviolet irradiation can be used as the adhesive layer 176. Next, the support substrate wafer 173 is removed from the semiconductor layer 122 and the protective film 127.

[0152] Next, if Fig.13 As shown, a through hole 128 is formed in the semiconductor layer 122 by using a method such as photolithography and dry etching, and the pad electrode 124 of the wiring layer 123 is exposed through the through hole 128. Then, an insulating layer 153 extending on the protective film 127 is formed on the rear surface side of the semiconductor layer 122 to cover the side wall of the through hole 128 by using a method such as plasma enhanced (PE)-CVD.

[0153] Next, if Fig.14 As shown, the through electrode 126 embedded in the through hole 128 via the insulating layer 153 is formed on the pad electrode 124. For the formation of the through electrode 126, for example, a method such as physical vapor deposition (PE-PVD), PE-CVD or electroplating can be used. Next, the rear surface rewiring 154 is formed on the insulating layer 153, and the protective film 155 is formed on the rear surface rewiring 154. The rear surface rewiring 154 can be electrically connected to the through electrode 126.

[0154] Next, if Fig.15As shown, the chip 131 is mounted on the extended rear surface redistribution layer 151 in a flip-chip manner via the bump electrode 136. At this time, the wiring layer 133 of the chip 131 can be electrically connected to the extended rear surface redistribution layer 151. Next, the bottom filler 137 is filled between the extended rear surface redistribution layer 151 and the chip 131. In addition, on the extended rear surface redistribution layer 151, a dummy chip 138 is configured around the chip 131. The dummy chip 138 may be bonded to the protective film 155 or may be bonded by using an adhesive layer.

[0155] Next, if Fig.16 As shown, a protection film 139 is formed on the extended rear surface redistribution layer 151 to cover the chip 131 and the dummy chip 138. In order to make the protection film 139 flat, the front surface of the protection film 139 may be polished. In addition, a support substrate wafer 161' is bonded to the protection film 139. The support substrate wafer 161' may have the same shape and size as the semiconductor wafer 112'.

[0156] Next, if Figure 1 As shown, the support substrate wafer 175 on the semiconductor wafer 112' is removed together with the adhesive layer 176. Then, by using a method such as dicing, the stacked wafer including the semiconductor wafer 112' on the support substrate wafer 161' is divided into solid blocks in the form of chips to form the package 100. Thereafter, the bonding wires 118 are connected to the through electrodes 116.

[0157] In this way, in the first embodiment, the package 100 includes the extended redistribution layer 141 connected to the chip 121. As a result, the wiring connected to the chip 121 can be led out from the outside of the wiring layer 123 of the chip 121. Therefore, in the case where the chip 121 is smaller than the chip 111, the wiring of the wiring layer 113 of the chip 111 will not extend to the position of the wiring layer 123, but can be electrically connected to the wiring of the wiring layer 123. As a result, the constraints on the wiring layout of the wiring layer 113 of the chip 111 and the wiring layer 123 of the chip 121 can be reduced, and the connection points of the wiring layer 113 of the chip 111 and the wiring layer 123 of the chip 121 can be increased.

[0158] In addition, the package 100 includes an extended rear surface redistribution layer 151 connected to the chip 121. Thus, the wiring connected to the chip 121 can be led out to the outside from the rear surface side of the chip 121. Therefore, it is possible to relax the constraints on the wiring layout of the wiring layer 123 of the chip 121 and the wiring layer 133 of the chip 131, and increase the connection points of the wiring layer 123 of the chip 121 and the wiring layer 133 of the chip 131.

[0159] In addition, in the package 100, the positions of the chip 111, the extended redistribution layer 141, the extended rear surface redistribution layer 151, the protective films 127 and 139, and the end portions of the support substrate 161 in the lateral direction DL are equal to each other. Therefore, a plurality of packages 100 can be formed together in a state where the plurality of packages 100 are integrated into a wafer shape, and then can be divided into solid blocks of individual packages 100, and the manufacturing efficiency of the package 100 can be improved.

[0160] Note that in the first embodiment, a three-layer structure in which three chips 111 , 121 , and 131 are stacked is taken as an example, but a two-layer structure in which two chips 111 and 121 are stacked or a two-layer structure in which two chips 121 and 131 are stacked may be used.

[0161] <2. Second Embodiment>

[0162] In the first embodiment, the through-electrode 116 is provided on the uppermost chip 111, and the external connection terminal is led out from the upper surface side of the package 100. In the second embodiment, the through-electrode led out to the lower surface side of the package 100 is provided, and the external connection terminal is led out from the lower surface side of the package.

[0163] Fig.17 is a cross-sectional view showing a configuration example of a package according to the second embodiment.

[0164] In the drawings, the package 200 includes chips 211 and 231, a dummy chip 238, and a protective film 239 instead of the chips 111 and 131, the dummy chip 138, and the protective film 139 of the first embodiment. In addition, in the package 200, a transparent resin 212, a transparent substrate 213, through electrodes 233 to 235, and a redistribution layer 261 are added to the package 100 of the first embodiment. The other configurations of the package 200 of the second embodiment are similar to those of the package 100 of the first embodiment.

[0165] The through-electrode 116 of the first embodiment is omitted from the chip 211. The other configuration of the chip 211 is similar to that of the chip 111 of the first embodiment.

[0166] On the rear surface side of the semiconductor layer 112, a transparent resin 212 is formed to cover the on-chip lens 117. A transparent substrate 213 is provided on the transparent resin 212. The material of the transparent resin 212 is, for example, silicone resin, acrylic resin, or polycarbonate. At this time, the refractive index of the transparent resin 212 can be made smaller than the refractive index of the on-chip lens 117. The material of the transparent substrate 213 can be, for example, quartz, glass, or Al2O3, CaF2, MgF2, LiF, etc., depending on the wavelength of the optical element. The transparent resin 212 can be used as an adhesive layer for bonding the transparent substrate 213.

[0167] The chip 231 includes a semiconductor layer 232 instead of the semiconductor layer 132 of the first embodiment. A through electrode 233 is embedded in the semiconductor layer 232 via an insulating layer 263. The through electrode 233 is connected to the pad electrode 134 of the wiring layer 133.

[0168] The dummy chip 238 is mounted separately from the chip 231 on the extended rear surface redistribution layer 151. A through electrode 234 is embedded in the dummy chip 238. The through electrode 234 is electrically connected to the rear surface redistribution layer 154 of the extended rear surface redistribution layer 151.

[0169] A protective film 239 is formed on the extended rear surface redistribution layer 151 to cover the chip 231 and the dummy chip 238. The through electrode 235 is embedded in the protective film 239 via the insulating layer 263. At this time, the through electrode 235 may be arranged at a position separated from the chip 231. The through electrode 235 is electrically connected to the rear surface redistribution layer 154 of the extended rear surface redistribution layer 151.

[0170] The redistribution layer 261 includes an insulating layer 263, a pad electrode 264, and a protective film 265. Redistribution can be formed in the redistribution layer 261. The insulating layer 263 is formed on the protective film 239. At this time, the insulating layer 263 is formed on the semiconductor layer 232 and the protective film 239 so as to surround the outer periphery of the through electrode 233. In addition, the insulating layer 263 is formed on the dummy chip 238 and the protective film 239 in a manner of surrounding the outer periphery of the through electrode 234. In addition, the insulating layer 263 is formed on the protective film 239 to surround the outer periphery of the through electrode 235. The pad electrode 264 is formed on the insulating layer 263. The pad electrode 264 is connected to the through electrodes 233, 234, and 235, respectively. A bump electrode 266 is formed on the pad electrode 264.

[0171] The other configurations of the chip 231 , the dummy chip 238 , and the protective film 239 are similar to those of the chip 131 , the dummy chip 138 , and the protective film 139 of the first embodiment.

[0172] Figures 18 to 22 is a cross-sectional view showing an example of a method for manufacturing the package according to the second embodiment.

[0173] Execution of the first embodiment Figures 6 to 10 Then, in the first embodiment Fig.11 In the step of , the formation of the through-electrode 116 embedded in the semiconductor wafer 112 ′ is omitted, and the on-chip lens 117 is formed on the protective film 115 .

[0174] Next, if Fig.18As shown, the transparent substrate wafer 213' is bonded to the semiconductor wafer 112' side via the transparent resin 212. The transparent substrate wafer 213' may have the same shape and size as the semiconductor wafer 112'.

[0175] Then, if Fig.19 As shown, the first embodiment is performed Figures 13 to 15 At this time, instead of the chip 131 and the dummy chip 138 , the chip 231 and the dummy chip 238 before each of the through electrodes 233 and 234 is formed are mounted on the extended rear surface rewiring layer 151 .

[0176] Next, if Fig. 20 As shown, a protective film 239 is formed on the extended rear surface redistribution layer 151 to cover the chip 231 and the dummy chip 238. In order to flatten the protective film 239, the front surface of the protective film 239 may be polished. Next, through holes 273 to 275 provided at the embedded positions of the through electrodes 233 to 235 are respectively formed in the protective film 239. At this time, if the protective film 239 includes a photosensitive material, the through holes 273 to 275 are formed by photolithography, and if the protective film 239 includes a non-photosensitive material, the through holes 273 to 275 are formed by photolithography and dry etching.

[0177] Then, if Fig.21 As shown, by using the protective film 239 formed with the through holes 273 to 275 as an etching mask, the semiconductor layer 232 and the dummy chip 238 are etched, thereby forming through holes 283 and 284 in the semiconductor layer 232 and the dummy chip 238 .

[0178] Then, if Fig. 22 As shown, an insulating layer 263 is formed on the protective film 239 by using a method such as PE-CVD so as to cover the side walls of the through holes 273 to 275 and the through holes 283 and 284. In addition, by dry etching the protective film 155 through the insulating layer 263, the pad electrode of the extended rear surface redistribution layer 151 is exposed.

[0179] Then, if Fig.17As shown, through electrodes 233 to 235 and through holes 283 and 284 embedded in through holes 273 to 275 via an insulating layer 263 are formed. For the formation of the through electrodes 233 to 235, for example, a method such as PE-PVD, PE-CVD or electroplating can be used. Next, a redistribution wiring and pad electrode 264 is formed on the insulating layer 263, and a protective film 265 is formed on the redistribution wiring and pad electrode 264. Next, an opening portion that exposes the pad electrode 264 is formed on the protective film 265, and a bump electrode 266 is formed on the pad electrode 264 through the opening portion. Thereafter, by using a method such as cutting, the stacked wafer including the semiconductor wafer 112' on the transparent substrate wafer 213' is divided into solid blocks in the form of chips to form a package 200.

[0180] In this way, in the second embodiment, by providing the through electrodes 233 to 235 led out to the lower surface side of the package 200, the wiring path to the lowermost chip 231 can be made shorter than the wiring path in the package 100 of the first embodiment. Therefore, the IR drop and signal delay of the lowest chip 231 can be reduced.

[0181] In addition, by providing through electrodes 233 to 235 extending to the lower surface side of the package 200, it is possible to electrically connect to the outside from the lower surface side of the package 200. Therefore, since it is not necessary to use wire bonding to electrically connect the package 200 to the outside and a bonding area surrounding the package 200 is not required, the mounting area of ​​the package 200 can be reduced.

[0182] In addition, a through electrode 234 connected to the redistribution layer 261 is formed in the dummy chip 238 around the chip 231. Therefore, even in the case where the size of the chip 211 is smaller than the size of the chip 231, the number of through electrodes 233 formed on the chip 231 can be reduced, while uniformizing the heat dissipation and internal stress of the package 200. Therefore, the reliability of the package 200 can be improved, and the reduction of the element area of ​​the chip 231 can be suppressed.

[0183] In addition, the through-electrode 235 connected to the redistribution layer 261 is formed on the protective film 239 around the chip 231. Therefore, even in the case where the size of the chip 211 is smaller than the size of the chip 231, the number of through-electrodes 233 formed on the chip 231 can be reduced while unifying the size and shape of the stacking surface of the chips to be three-dimensionally stacked. Therefore, a plurality of packages 200 can be integrally and collectively formed and then divided into solid blocks of individual packages 200, the manufacturing efficiency of the package 200 can be improved, and the reduction of the element area of ​​the chip 231 can be suppressed.

[0184] <3. Third Embodiment>

[0185] In the second embodiment, the through electrodes 233 and 234 are respectively provided in the chip 231 and the dummy chip 238, and the insulating layer 263 is provided so as to insulate the through electrodes 233 and 234 from the semiconductor layer 232 and the dummy chip 238, respectively. In the third embodiment, the through electrodes connected to the extended rear surface rewiring layer 151 are provided on the protective film 239, and the through electrodes 233 and 234 of the chip 231, the dummy chip 238, and the insulating layer 263 are omitted.

[0186] Fig.23 is a cross-sectional view showing a configuration example of a package according to a third embodiment.

[0187] In the drawings, the package 300 includes through electrodes 334 and 335, a chip 131, a dummy chip 138, and a protective film 339, instead of the through electrodes 233 to 235, the chip 231, the dummy chip 238, and the protective film 239 of the second embodiment. In addition, the package 300 includes a redistribution layer 361 instead of the redistribution layer 261 of the second embodiment. In addition, in the package 300, the insulating layer 263 of the second embodiment is omitted. The other configurations of the package 300 of the third embodiment are similar to those of the package 200 of the second embodiment.

[0188] On the extended rear surface rewiring layer 151, a protective film 339 is formed in such a manner as to cover the chip 131 and the dummy chip 138. The through electrodes 334 and 335 are embedded in the protective film 339. At this time, each of the through electrodes 334 and 335 may be in contact with the protective film 339. In addition, the through electrodes 334 and 335 may be provided at a position separated from the chip 131. Each of the through electrodes 334 and 335 is electrically connected to the wiring of the extended rear surface rewiring layer 151.

[0189] The redistribution layer 361 includes a pad electrode 364 and a protective film 365. Redistribution can be formed in the redistribution layer 361. The pad electrode 364 is formed on the protective film 339. At this time, each pad electrode 364 can be arranged at a position in contact with each through electrode 334, 335. A bump electrode 366 is formed on the pad electrode 364.

[0190] In this way, in the third embodiment, the redistribution layer 151 connected to the through electrodes 334 and 335 on the extended rear surface is formed on the protective film 365 around the chip 131. Therefore, the package 300 can be electrically connected to the outside from the lower surface side without forming an insulating layer that insulates the through electrodes 334 and 335 on the protective film 365, and the mounting area of ​​the package 300 can be reduced.

[0191] Furthermore, it is not necessary to form a through electrode on the chip 131 to lead out an external connection terminal from the lower surface side of the package 300. Therefore, it is not necessary to embed the through electrode in the semiconductor, the manufacturing steps can be simplified, and the element area of ​​the chip 131 can be increased.

[0192] <4. Fourth Embodiment>

[0193] In the first embodiment, the through electrode 126 connected to the extended redistribution layer 141 via the wiring layer 123 is provided in the chip 121. In the fourth embodiment, the through electrode connected to the extended redistribution layer 141 is provided in the protective film around the chip 121 and the dummy chip.

[0194] Fig.24 is a cross-sectional view showing a configuration example of a package according to a fourth embodiment.

[0195] In the drawings, the package 400 includes a chip 421, through electrodes 423 and 424, a protective film 427, and an extended rear surface redistribution layer 451, instead of the chip 121, through electrodes 126, protective film 127, and extended rear surface redistribution layer 151 of the first embodiment. In addition, in the package 400, a dummy chip 428 is added to the package 100 of the first embodiment. The other configurations of the package 400 of the fourth embodiment are similar to those of the package 100 of the first embodiment.

[0196] The through electrode 126 of the first embodiment is omitted from the chip 421. The extended redistribution layer 141 is formed on the front surface side of the chip 421, and the extended rear surface redistribution layer 451 is formed on the rear surface side of the chip 421. The other configuration of the chip 421 is similar to that of the chip 121 of the first embodiment.

[0197] The dummy chip 428 is arranged around the chip 421. At this time, the dummy chip 428 can be mounted on the extended redistribution layer 141 separately from the chip 421. The through electrode 424 is embedded in the dummy chip 428 via the insulating layer 453. The through electrode 424 is electrically connected to the redistribution 144 of the extended redistribution layer 141. The dummy chip 428 can be fixed to the extended redistribution layer 141 via an adhesive layer. The front surface of the dummy chip 428 is flat. The position of the flat surface of the dummy chip 428 in the height direction DH can be made substantially equal to the position of the top surface of the chip 421 in the height direction DH. The material of the dummy chip 428 can be a semiconductor such as Si or an inorganic material such as glass or ceramic. It should be noted that the chip 421 can be arranged in the center of the dummy chip 428, or the dummy chip 428 can be arranged in a region including the front end, the rear end, the left end and the right end. Mechanical strength and heat dissipation from the rear surface of the package 400 can be improved by arranging the dummy chip 428 on the extended redistribution layer 141. It is not necessary to provide the dummy chip 428. It should be noted that the dummy chip 428 is an example of a support member described in the claims.

[0198] The protective film 427 is formed in the lateral direction DL relative to the chip 421. The protective film 427 may be in contact with the side surface of the chip 421. The through electrode 423 is embedded in the protective film 427. At this time, the through electrode 423 may be set at a position separated from the chip 421. The position of the front surface of the protective film 427 in the height direction DH may be made substantially equal to the position of the front surface of the chip 421 in the height direction DH. In addition, the position of the rear surface of the protective film 427 in the height direction DH may be made substantially equal to the position of the rear surface of the chip 421 in the height direction DH. The position of the end of the protective film 427 in the lateral direction DL may coincide with the position of the end of the chip 111 in the lateral direction DL.

[0199] The extended rear surface rewiring layer 451 includes an insulating layer 453, a rear surface rewiring layer 454, and a protective film 455. The insulating layer 453 is formed on the rear surface of the semiconductor layer 122, the protective film 427, and the dummy chip 428. At this time, the insulating layer 453 is formed in the protective film 427 so as to surround the outer periphery of the through electrode 423. In addition, the insulating layer 453 is formed in the dummy chip 428 to surround the outer periphery of the through electrode 424, and the through electrode 424 can be insulated from the dummy chip 428. The rear surface rewiring 454 is formed on the insulating layer 453. The rear surface rewiring 454 can be connected to the through electrodes 423 and 424 and the bump electrode 136. The chip 131 is mounted on the extended rear surface rewiring layer 451 in a flip-chip manner via the bump electrode 136. Note that the chip 131 can be directly bonded to the extended rear surface rewiring layer 451. Furthermore, a protective film 455 is formed on the insulating layer 453 to cover the rear surface redistribution wiring 454. The size of the front surface extending the rear surface redistribution layer 451 may be equal to the size of the front surface of the chip 111.

[0200] In this manner, in the fourth embodiment, the through electrode 423 connected to the extended redistribution layer 141 is provided in the protective film 427 around the chip 121, and the through electrode 424 connected to the extended redistribution layer 141 is provided in the dummy chip 428 around the chip 121. Thus, it is not necessary to provide the through electrode 126 formed on the chip 121 in the first embodiment on the chip 421, and the number of elements formed on the chip 421 can be increased.

[0201] Note that a through electrode may also be formed in the semiconductor layer 122 of the chip 421. In this case, the through electrode 423 formed in the protective film 427 and the through electrode formed in the semiconductor layer 122 of the chip 421 may be used separately for the power supply line and the signal line. In addition, the through electrode around the chip 421 may be formed only in the protective film 427 around the chip 421, or may be formed only in the dummy chip 428 around the chip 421.

[0202] In addition, the through-electrode led out to the lower surface side of the package 400 may be provided to be electrically connected to the outside from the lower surface side of the package 400. For example, instead of the chips 111 and 131, the chips 211 and 231 of the second embodiment, the through-electrodes 234 and 235, and the redistribution layer 261 may be provided, and the support substrate 161 may be omitted. Alternatively, instead of the chip 111, the chip 211 of the third embodiment, the through-electrodes 334 and 335, and the redistribution layer 361 may be provided, and the support substrate 161 may be omitted.

[0203] <5. Fifth embodiment>

[0204] In the first embodiment, the size of the uppermost chip 111 is larger than that of the lower chip 121, and the protective film 127 is provided around the chip 121. In the fifth embodiment, the size of the uppermost chip is smaller than that of the lower chip, and the protective film is provided around the uppermost chip.

[0205] Fig.25 is a sectional view showing a configuration example of a package according to a fifth embodiment.

[0206] In the drawings, the package 500 includes chips 511 and 521, an extended redistribution layer 541, and a rear surface redistribution layer 551, instead of the chips 111 and 131, the extended redistribution layer 141, and the extended rear surface redistribution layer 151 of the first embodiment. The other configurations of the package 500 of the fifth embodiment are similar to those of the package 100 of the first embodiment.

[0207] The length of the chip 511 at least in the lateral direction DL is shorter than that of the chip 521. As for the length in the vertical direction DV, the chip 511 may be shorter, longer or equal to the chip 521.

[0208] Chips 511, 521, and 131 may constitute a three-layer stacked structure stacked in the height direction DH. At this time, an extended redistribution layer 541 is disposed on the front surface side of chip 511 and extends from chip 511 in the lateral direction DL. A rear surface redistribution layer 551 is disposed on the rear surface side of chip 521, and a length of the rear surface redistribution layer 551 in the lateral direction DL is equal to a length of chip 511 in the lateral direction DL. Then, chips 511 and 521 are electrically connected to each other via the extended redistribution layer 541, and chips 521 and 131 are electrically connected to each other via the rear surface redistribution layer 551. Each of chips 511 and 521 may be a semiconductor chip, and chip 511 may be an optical chip.

[0209] In the following description, a case in which a rear surface irradiation type solid-state imaging element is formed on the chip 511 and a semiconductor element is formed on each of the chips 521 and 131 will be taken as an example.

[0210] The optical chip 511 includes a semiconductor layer 512 and a wiring layer 513. The semiconductor layer 512 is provided with an imaging region and a non-imaging region. The wiring layer 513 is formed on the front surface side of the semiconductor layer 512. The wiring layer 513 is provided with wiring and a pad electrode 514 embedded in an insulating layer. A protective film 515 is formed on the rear surface side of the semiconductor layer 512. For each pixel, an on-chip lens 517 is formed on the protective film 515. In addition, a protective film 516 is formed in the lateral direction DL of the chip 511. The protective film 516 may be in contact with the side of the chip 511. The position of the front surface of the protective film 516 in the height direction DH may be substantially equal to the position of the front surface of the chip 511 in the height direction DH. The position of the end of the protective film 516 in the lateral direction DL may coincide with the position of the end of the chip 521 in the lateral direction DL. A through hole 517 is formed in the protective film 516. At the position of the through hole 517, the pad electrode 544 is exposed from the insulating layer 543 extending the redistribution layer 541. The bonding wire 518 is connected to the pad electrode 544 via the through hole 517 so as to be connected to the outside. Note that the bonding wire 518 is an example of an external connection terminal described in the claims.

[0211] The optical chip 521 includes a semiconductor layer 522 and a wiring layer 523. The wiring layer 523 is formed on the semiconductor layer 522. The wiring layer 523 is provided with wiring embedded in an insulating layer and a pad electrode 524. In addition, a through electrode 526 is embedded in the semiconductor layer 522. The through electrode 526 is connected to the pad electrode 524 of the wiring layer 523.

[0212] The extended redistribution layer 541 extends from the chip 511 in the lateral direction DL so as to be equal to the length of the chip 521 in the lateral direction DL. At this time, the position of the end of the extended redistribution layer 541 in the lateral direction DL and the position of the end of the chip 521 in the lateral direction DL may coincide with each other. The extended redistribution layer 541 extends from the mounting area RA of the chip 511 to the extension area RB extending in the lateral direction DL.

[0213] The extended rewiring layer 541 includes an insulating layer 543 and rewiring and pad electrodes 544. The rewiring and pad electrodes 544 are embedded in the insulating layer 543. In addition, a through hole 545 that performs interlayer connection of rewiring may be formed in the extended rewiring layer 541.

[0214] The chip 511 is disposed on one surface of the extended redistribution layer 541, and the protective film 516 is disposed in the extended region RB of the surface. The redistribution of the extended redistribution layer 541 may be connected to the wiring of the wiring layer 513 via the through hole 545. At this time, the extended redistribution layer 541 may be supported by the chip 511 and the protective film 516.

[0215] The chip 521 is disposed on the other surface of the extended redistribution layer 541. At this time, the chip 521 and the extended redistribution layer 541 may be directly bonded such that the wiring layer 523 of the chip 521 faces the extended redistribution layer 541.

[0216] The rear surface rewiring layer 551 includes an insulating layer 553, a rear surface rewiring layer 554, and a protective film 555. The insulating layer 553 is formed on the rear surface of the semiconductor layer 522. At this time, the insulating layer 553 is formed in the semiconductor layer 522 to surround the periphery of the through electrode 526, and can insulate the through electrode 526 from the semiconductor layer 522. The rear surface rewiring 554 is formed on the insulating layer 553. The rear surface rewiring 554 can be connected to the through electrode 526 and the bump electrode 136.

[0217] In this manner, in the fifth embodiment, the protective film 516 is provided around the uppermost chip 511 connected to the extended redistribution layer 541. Thus, even in the case where the size of the uppermost chip 511 is smaller than the size of the lower chip 521, the size of the stacking surface of the uppermost chip 511 of the package 500 can be consistent with the size of the lower chip 521. Therefore, a plurality of packages 500 can be integrally and collectively formed into a wafer shape and then divided into solid blocks of the individual packages 500, and the manufacturing efficiency of the packages 500 can be improved.

[0218] In addition, a plurality of chips may be arranged on the uppermost layer. In addition, a through electrode led out to the lower surface side of the package 500 may be provided so as to be electrically connected to the outside from the lower surface side of the package 500 .

[0219] <6. Sixth Implementation Method>

[0220] In the first embodiment, an extended redistribution layer 141 extending in the lateral direction DL from the middle layer chip 121 is provided and connected to the uppermost layer chip 111. In the sixth embodiment, an extended redistribution layer extending in the lateral direction DL from the lowermost layer chip is provided and connected to the middle layer chip.

[0221] Fig.26 is a cross-sectional view showing a configuration example of a package according to a sixth embodiment.

[0222] In the drawings, the package 600 includes chips 621 and 631 and an extended redistribution layer 651, instead of the chips 111 and 131 and the extended redistribution layer 141 of the first embodiment. In addition, in the package 600, the extended rear surface redistribution layer 151, the bottom filler 137 and the support substrate 161 of the first embodiment are omitted. The other configurations of the package 600 of the sixth embodiment are similar to those of the package 100 of the first embodiment.

[0223] Each of the chips 111 and 621 has an equal length at least in the lateral direction DL. At this time, the position of the end of the chip 621 in the lateral direction DL can be made equal to the position of the end of the chip 111 in the lateral direction DL. The length of the chip 631 at least in the lateral direction DL is shorter than that of the chip 111. The extended redistribution layer 651 is provided on the front surface of the chip 631 and extends from the chip 631 in the lateral direction DL. Then, the chips 111 and 621 are electrically connected to each other based on direct bonding, and the chips 621 and 631 are electrically connected to each other via the extended redistribution layer 651.

[0224] The chip 621 includes a semiconductor layer 622 and a wiring layer 623. The wiring layer 623 is formed on the semiconductor layer 622. The wiring layer 623 is provided with wiring and a pad electrode 624 embedded in an insulating layer. In addition, a through electrode 626 is embedded in the semiconductor layer 622. The through electrode 626 is connected to the pad electrode 624 of the wiring layer 623. An insulating layer 625 is formed on the rear surface side of the semiconductor layer 622. The insulating layer 625 is formed in the semiconductor layer 622 in a manner surrounding the periphery of the through electrode 626, and the through electrode 626 can be insulated from the semiconductor layer 622. The rear surface wiring and the pad electrode 627 are formed on the insulating layer 625. The pad electrode 627 is connected to the through electrode 626.

[0225] The chip 631 includes a semiconductor layer 632 and a wiring layer 633. The wiring layer 633 is formed on the semiconductor layer 632. The wiring layer 633 is provided with wirings 634 buried in an insulating layer.

[0226] The extended redistribution layer 651 extends from the chip 631 in the lateral direction DL so as to be equal to the length of the chip 111 in the lateral direction DL. At this time, the position of the end of the extended redistribution layer 651 in the lateral direction DL and the position of the end of the chip 111 in the lateral direction DL may coincide with each other. The extended redistribution layer 651 extends from the mounting region RC of the chip 631 to the extension region RD extending in the lateral direction DL.

[0227] The extended rewiring layer 651 includes an insulating layer 653 and a rewiring layer 654. The rewiring 654 is embedded in the insulating layer 653. Furthermore, a via 655 that performs interlayer connection of the rewiring 654 may be formed in the extended rewiring layer 651.

[0228] The chip 621 is disposed on one surface of the extended redistribution layer 651. At this time, the chip 621 and the extended redistribution layer 651 may be directly bonded so that the rear surface wiring of the chip 621 and the pad electrode 627 face the extended redistribution layer 651.

[0229] The chip 631 is arranged on the other surface of the extended redistribution layer 141, and the dummy chip 638 and the protective film 639 are arranged in the extended region RD on the other surface. The redistribution 654 of the extended redistribution layer 651 can be connected to the wiring 634 of the wiring layer 633 via the through hole 655. At this time, the extended redistribution layer 651 can be supported by the chip 631, the dummy chip 638 and the protective film 639.

[0230] The dummy chip 638 may be mounted on the extended redistribution layer 651 separately from the chip 631. The dummy chip 638 may be fixed to the extended redistribution layer 651 via an adhesive layer. The front surface of the dummy chip 638 is flat. The position of the flat surface of the dummy chip 638 in the height direction DH may be made substantially equal to the position of the top surface of the chip 631 in the height direction DH.

[0231] The protection film 639 is formed on the extended redistribution layer 651 to cover the chip 631 and the dummy chip 638. The position of the end of the protection film 639 in the lateral direction DL may coincide with the position of the end of the chip 111 in the lateral direction DL.

[0232] In this way, in the sixth embodiment, the package 600 includes the extended redistribution layer 651 connected to the chip 631. Thus, the wiring connected to the chip 631 can be led out from a position outside the wiring layer 633 of the chip 631. Therefore, even in the case where the chip 631 is smaller than the chip 621, the rear surface wiring of the chip 621 can be electrically connected to the wiring 634 of the wiring layer 633 of the chip 631 without extending the rear surface wiring of the chip 621 to the position of the wiring layer 633 of the chip 631. As a result, the connection points between the rear surface wiring of the chip 621 and the wiring 634 of the chip 631 can be increased while relaxing the restrictions on the layout of the rear surface wiring of the chip 621 and the wiring 634 of the chip 631.

[0233] In addition, in the package 600, the positions of the ends of the chips 111 and 621, the extended redistribution layer 651, and the protective film 639 in the lateral direction DL are equal to each other. Therefore, a plurality of packages 600 can be formed together in a state where the plurality of packages 600 are integrated into a wafer shape, and then can be divided into solid blocks of individual packages 600, and the manufacturing efficiency of the package 600 can be improved.

[0234] Note that the supporting substrates bonded to the protective film 639 may be stacked, or a plurality of chips may be arranged in the lowermost layer. In addition, the through-electrode led out to the lower surface side of the package 600 may be provided to be electrically connected to the outside from the lower surface side of the package 600. For example, an extended rewiring layer 141, an extended rear surface rewiring layer 151, and a rewiring layer 261 of the second embodiment may be provided instead of the chips 111 and 631, the chips 211 and 231, and the through-electrodes 234 and 235. Alternatively, instead of the chip 111 and the protective film 639, the chip 211, the through-electrodes 334 and 335, the extended rewiring layer 141, the extended rear surface rewiring layer 151, and the rewiring layer 261 and the protective film 639 of the third embodiment may be provided. Alternatively, instead of the chip 621, the chip 421 of the fourth embodiment, the protective film 427, the dummy chip 428, the through electrodes 423 and 424, the extended redistribution layer 141, and the extended rear surface redistribution layer 451 may be provided. Alternatively, instead of the chip 111, the chip 511 of the fifth embodiment, the extended redistribution layer 541, and the protective film 516 may be provided.

[0235] <7. Seventh Implementation Method>

[0236] In the first embodiment, a three-layer stack structure of chips 111, 121, and 131 is formed by using an extended redistribution layer 141 and an extended rear surface redistribution layer 151. In the seventh embodiment, a five-layer stack structure of chips is formed by using an extended redistribution layer and an extended rear surface redistribution layer.

[0237] Fig. 27 is a sectional view showing a configuration example of a package according to a seventh embodiment.

[0238] In the drawings, in package 700, chip 711, extended redistribution layer 721, and extended rear surface redistribution layer 751 are added to package 100 of the first embodiment. Chip 711 is shorter than chip 111 at least in length in lateral direction DL. Furthermore, in package 700, chip 621 of the sixth embodiment is added to package 100 of the first embodiment.

[0239] The chips 111, 121, 131, 621, and 711 may constitute a five-layer stacked structure stacked in the height direction DH. At this time, the extended rewiring layer 721 is disposed on the front surface side of the chip 121 and extends from the chip 121 in the lateral direction DL. The extended rear surface rewiring layer 751 is disposed on the rear surface side of the chip 711 and extends from the chip 711 in the lateral direction DL. Then, the chips 111 and 711 are electrically connected to each other via the extended rewiring layer 141, and the chips 711 and 621 are electrically connected to each other via the extended rear surface rewiring layer 751. In addition, the chips 621 and 121 are electrically connected to each other via the extended rewiring layer 721.

[0240] The chip 711 includes a semiconductor layer 712 and a wiring layer 713. The wiring layer 713 is formed on the semiconductor layer 712. The wiring layer 713 is provided with wiring embedded in an insulating layer and a pad electrode 714. In addition, a through electrode 716 is buried in the semiconductor layer 712. The through electrode 716 is connected to the pad electrode 714 of the wiring layer 713.

[0241] The extended redistribution layer 721 extends from the chip 121 in the lateral direction DL so as to be equal to the length of the chip 111 in the lateral direction DL. At this time, the position of the end of the extended redistribution layer 721 in the lateral direction DL and the position of the end of the chip 111 in the lateral direction DL may coincide with each other. The extended redistribution layer 721 extends from the mounting area RA of the chip 121 to the extension area RB extending in the lateral direction DL.

[0242] The extended rewiring layer 721 includes an insulating layer 723 and a rewiring layer 724. The rewiring 724 is embedded in the insulating layer 723. In addition, a via 725 that performs interlayer connection of the rewiring 724 may be formed in the extended rewiring layer 721.

[0243] The chip 621 is disposed on one surface of the extended redistribution layer 721. At this time, the chip 621 and the extended redistribution layer 721 may be directly bonded so that the rear surface wiring of the chip 621 and the pad electrode 627 face the extended redistribution layer 721.

[0244] The chip 121 is disposed on the other surface of the extended redistribution layer 721, and the protective film 127 is disposed in the extended region RB of the surface. The redistribution 724 of the extended redistribution layer 721 may be connected to the wiring of the wiring layer 123 via the through hole 725. At this time, the extended redistribution layer 721 may be supported by the chip 121 and the protective film 127.

[0245] The extended rear surface redistribution layer 751 extends from the chip 711 in the lateral direction DL so as to be equal to the length of the chip 111 in the lateral direction DL. At this time, the position of the end of the extended rear surface redistribution layer 751 in the lateral direction DL and the position of the end of the chip 111 in the lateral direction DL may coincide with each other. The extended rear surface redistribution layer 751 extends from the mounting area RA of the chip 121 to the extension area RB extending in the lateral direction DL.

[0246] The extended rear surface rewiring layer 751 includes an insulating layer 753 and a rear surface rewiring layer 754. The insulating layer 753 is formed on the rear surface of the semiconductor layer 712 and the protective film 717. At this time, the insulating layer 753 is formed in the semiconductor layer 712 in a manner of surrounding the periphery of the through electrode 716, and the through electrode 716 can be insulated from the semiconductor layer 712. The rear surface rewiring 754 is formed on the insulating layer 753. The rear surface rewiring 753 can be directly bonded to the wiring layer 623 of the chip 621.

[0247] The protective film 717 is formed along the lateral direction DL of the chip 711. The protective film 717 may be in contact with the side of the chip 711. The position of the front surface of the protective film 717 in the height direction DH may be substantially equal to the position of the front surface of the chip 711 in the height direction DH. The position of the end of the protective film 717 in the lateral direction DL may be consistent with the position of the end of the chip 111 in the lateral direction DL.

[0248] The through electrode 718 is embedded in the protective film 717. At this time, the through electrode 718 may be provided at a position separated from the chip 711. One end of the through electrode 718 is electrically connected to the redistribution 144 extending the rear surface redistribution layer 141, and the other end of the through electrode 718 is electrically connected to the rear surface redistribution 754 extending the rear surface redistribution layer 751.

[0249] In this way, in the seventh embodiment, the extended redistribution layers 141 and 721 and the extended rear surface redistribution layers 151 and 751 are used to form a five-layer stacked structure of chips 111, 121, 131, 621 and 711. Thus, it is possible to cope with an increase in the number of stacked chips having different chip sizes, and to increase the number of input and output terminals that can be configured between chips, and to unify the size and shape of the stacking surface of three-dimensionally stacked chips. Therefore, it is possible to suppress an increase in the number of manufacturing processes, and to increase the number of stacked chips, to suppress an increase in the size of the package, and to achieve a high degree of integration of components mounted on the package.

[0250] For example, the number of packages divided into solid blocks from a wafer is M (M is an integer greater than or equal to 2), and the number of stacked chips mounted on the packages is N (N is an integer greater than or equal to 2). At this time, in the method of stacking chips divided into solid blocks, M×(N-1) stacking steps are required to manufacture M packages. On the other hand, in the method of stacking chips in a wafer state before dividing the chips into solid blocks, N-1 stacking steps are sufficient, and the stacking steps can be reduced to 1 / M.

[0251] It should be noted that the through-electrode led out to the lower surface side of the package 700 may be provided to be electrically connected to the outside from the lower surface side of the package 700. For example, instead of the chips 111 and 131, the chips 221 and 232, the through-electrodes 234 and 235, the extended redistribution layer 141, and the extended rear surface redistribution layer 151 of the second embodiment may be provided.

[0252] Furthermore, in the above-mentioned embodiments, a three-layer structure using one extended redistribution layer and one extended rear surface redistribution layer, and a five-layer structure using two extended redistribution layers and two extended rear surface redistribution layers have been described. The present invention is not limited to the three-layer structure and the five-layer structure, and the number of stacked chips is not limited as long as the stacked structure has two or more layers. At this time, by increasing the number of extended redistribution layers and the number of extended rear surface redistribution layers used for one package, the number of stacked chips can be increased while the size and shape of the stacking surface of the integrated three-dimensional stacked chip are maintained.

[0253] In addition, in a package forming a stacked structure of two or more layers of chips, it is sufficient that there is at least one chip having a length equal to the length in the lateral direction DL of the package and at least one chip shorter than the length in the lateral direction DL of the package. In addition, the stacking position of the chip having the same length as the package in the lateral direction DL is not limited and may be in any layer.

[0254] <8. Eighth Implementation Method>

[0255] In the sixth embodiment, in order to electrically connect the upper chip 111 and the lower chip 631 via the intermediate chip 621, a rear surface wiring is provided on the rear surface side of the chip 621 provided with the through electrode 626. In the eighth embodiment, in order to electrically connect the upper chip 111 and the lower chip 631 via the intermediate chip, the through electrode penetrating the intermediate chip is bonded to the pad electrode 114 of the wiring layer 113 of the upper chip 111.

[0256] Fig.28 is a cross-sectional view showing a configuration example of a package according to an eighth embodiment.

[0257] In the drawings, the package 800 includes a chip 811 instead of the chip 621 of the sixth embodiment. In addition, in the package 800, an adhesive layer 821 and a light shielding layer 817 are added to the package of the sixth embodiment. The other configurations of the package 800 of the eighth embodiment are similar to those of the package 600 of the sixth embodiment.

[0258] The length of the chip 811 in the lateral direction DL is equal to the length of the chip 111 in the lateral direction DL. At this time, the position of the end of the chip 811 in the lateral direction DL can be made equal to the position of the end of the chip 111 in the lateral direction DL. The rear surface side of the chip 811 is bonded to the chip 111 through the adhesive layer 821. The front surface side of the chip 811 is electrically connected to the extended redistribution layer 651 based on direct bonding.

[0259] The chip 811 includes a semiconductor layer 812 and a wiring layer 813. The wiring layer 813 is formed on the semiconductor layer 812. The wiring layer 813 is provided with wiring and pad electrodes 814 embedded in an insulating layer. The wiring layer 813 is directly bonded to the extended redistribution layer 651. At this time, the wiring and pad electrodes 814 of the wiring layer 813 are electrically connected to the rear surface wiring 654 of the extended redistribution layer 651. In addition, a through electrode 816 is embedded in the semiconductor layer 812. The through electrode 816 penetrates the adhesive layer 821 and is connected to the pad electrode of the wiring layer 113. In addition, the through electrode 816 penetrates the insulating layer of the wiring layer 813 and is connected to the pad electrode 814 of the wiring layer 813. In the semiconductor layer 812, an insulating layer 815 is formed in a manner surrounding the periphery of the through electrode 816. The insulating layer 815 may penetrate the adhesive layer 821 and reach the pad electrode 114 of the wiring layer 113 , or may penetrate the insulating layer of the wiring layer 813 and reach the pad electrode 814 of the wiring layer 813 .

[0260] The adhesive layer 821 bonds the chips 111 and 811 to each other. The material of the adhesive layer 821 may be a resin adhesive layer, an inorganic film such as SiO2, SiON, SiN, SiOC, or SiCN, or a stack of the above.

[0261] The light shielding layer 817 shields light incident on the chip 111 from the surface opposite to the light receiving surface of the chip 111. The light shielding layer 817 may be formed on the entire rear surface of the semiconductor layer 812 except for the penetration position of the through electrode 816. The light shielding layer 817 may be formed in the adhesive layer 821 or may be formed at the interface between the chip 111 and the adhesive layer 821. The material of the light shielding layer 817 may be, for example, a black resin, a metal such as Cr, Al, Cu, or the like.

[0262] Figure 29 to Figure 35 is a cross-sectional view showing an example of a method for manufacturing a package according to an eighth embodiment.

[0263] exist Fig.29 In a, a wiring layer 113 provided with wiring and pad electrodes 114 is formed on a semiconductor wafer 112'. A plurality of chips 111 for a plurality of packages 800 may be cut from the semiconductor wafer 112'. At this time, the semiconductor wafer 112' may be cut along a cutting line for dividing the package 800 into solid blocks.

[0264] In addition, Fig.29 In b, a wiring layer 813 provided with wires and pad electrodes 814 is formed on a semiconductor wafer 812'. A plurality of chips 811 for a plurality of packages 800 may be cut out from the semiconductor wafer 812'. At this time, the semiconductor wafer 812' may be divided along a cutting line for dividing the package 800 into solid blocks.

[0265] Next, the wiring layer 813 on the semiconductor wafer 812' is temporarily bonded to the supporting substrate wafer 831 via the adhesive layer 832. Then, the semiconductor wafer 812' is thinned from the rear surface side by a method such as CMP. Then, a light shielding layer 817 is formed on the rear surface side of the semiconductor wafer 812'. Note that the light shielding layer 817 may be patterned so that the light shielding layer 817 is removed at the penetration position of the through electrode 816.

[0266] Next, if Fig.30 , the chip 631 and the dummy chip 638 are temporarily bonded to the support substrate wafer 841 via the adhesive layer 842. The plurality of chips 631 for the plurality of packages 800 may be temporarily bonded to the support substrate wafer 841. At this time, the support substrate wafer 841 may be divided along the cutting lines for dividing the packages 800 into solid blocks.

[0267] Next, if Fig.31 As shown, a protective film 639 is formed on a support substrate wafer 841 so as to cover the chip 631 and the dummy chip 638. In order to make the protective film 639 flat, the front surface of the protective film 639 may be polished. Next, the support substrate wafer 841 and the adhesive layer 842 are removed.

[0268] Then, if Fig.32 As shown, an extended redistribution layer 651 electrically connected to the wiring layer 633 of the chip 631 is formed on the chip 631, the dummy chip 638 and the protection film 639. At this time, the extended redistribution layer 651 extends from the mounting region RC of the chip 631 to the extended region RD.

[0269] Then, if Fig.33 As shown, the wiring layer 113 on the semiconductor wafer 112 ′ is bonded to the rear surface side of the semiconductor wafer 812 ′ through an adhesive layer 821 .

[0270] Then, if Fig.34 As shown, an insulating layer 815 is formed. The insulating layer 815 penetrates the insulating layer of the wiring layer 813, the semiconductor wafer 812', and the adhesive layer 821, and covers the side walls of the insulating layer of the wiring layer 813, the semiconductor wafer 812', and the adhesive layer 821. Then, a through electrode 816 is formed to be buried in the insulating layer of the wiring layer 813, the semiconductor wafer 812', and the adhesive layer 821 via the insulating layer 815. Thereafter, a pad electrode 814 connected to the through electrode 816 is formed on the front surface side of the wiring layer 813. At this time, the pad electrode 814 is exposed to the front surface side of the wiring layer 813.

[0271] Then, if Fig.35 As shown, the wiring layer 813 on the semiconductor wafer 812 ′ is directly bonded to the extended redistribution layer 651 . At this time, the pad electrode 814 is electrically connected to the redistribution 654 of the extended redistribution layer 651 .

[0272] Then, if Fig.28 As shown, the semiconductor wafer 112' is thinned from the back surface side by a method such as CMP. Then, a through hole in which the through electrode 116 is embedded is formed in the semiconductor wafer 112', and the pad electrode 114 of the wiring layer 113 is exposed through the through hole. Next, a protective film 115 is formed on the back surface side of the semiconductor wafer 112' in a manner covering the side wall of the through hole. Then, a through electrode 116 embedded in the semiconductor wafer 112' via the protective film 115 is formed. In addition, an on-chip lens 117 is formed on the protective film 115. Note that an anti-reflective film and a color filter may be formed under the on-chip lens 117. Thereafter, by using a method such as cutting, the stacked wafer including the semiconductor wafers 112' and 812' is divided into a solid block in the form of a chip to form a package 800.

[0273] In this manner, in the eighth embodiment, in order to electrically connect the upper chip 111 and the lower chip 631 via the intermediate chip 811, the through-electrode 816 penetrating the chip 811 is bonded to the pad electrode 114 of the wiring layer 113 of the upper chip 111. Thus, the upper chip 111 and the lower chip 631 can be electrically connected via the chip 811 without forming a rear surface wiring on the intermediate chip 811.

[0274] Note that the chip 511 of the fifth embodiment may be installed instead of the chip 111 of the eighth embodiment. In addition, the through-electrode led out to the lower surface side of the package 800 may be provided to be electrically connected to the outside from the lower surface side of the package 800. For example, instead of the chip 111, the chip 211 of the third embodiment may be provided, and the through-electrodes 234 and 235 may be provided on the protective film 639 and connected to the extended redistribution layer 651. Alternatively, instead of the chip 811, the chip 421 of the fourth embodiment and the protective film 427 may be provided, and the through-electrode 816 may be formed at the position of the protective film 427.

[0275] <9. Ninth Implementation Method>

[0276] In the eighth embodiment, the film thickness of the insulating layer 815 around the through electrode 816 is equal at the position of the semiconductor layer 812 and the position of the adhesive layer 821. In the ninth embodiment, at the embedded position of the through electrode 816, the adhesive layer is retreated from the semiconductor layer 812, and the film thickness of the insulating layer at the position of the adhesive layer is made greater than the film thickness of the insulating layer at the position of the semiconductor layer 812.

[0277] Fig.36 is a cross-sectional view showing a configuration example of a package according to a ninth embodiment, and Fig.37 is an enlarged cross-sectional view showing a part of a package according to a ninth embodiment.

[0278] exist Fig.36 , the package 900 includes an adhesive layer 921 and an insulating layer 915 instead of the adhesive layer 821 and the insulating layer 815 of the eighth embodiment. In addition, in the package 900, the light shielding layer 817 of the eighth embodiment is omitted. The other configurations of the package 900 of the ninth embodiment are similar to the configurations of the package 800 of the eighth embodiment described above.

[0279] The adhesive layer 921 adheres the chips 111 and 811 to each other. The adhesive layer 921 retreats from the semiconductor layer 812 at the embedding position of the through electrode 816.

[0280] The insulating layer 915 is formed in the semiconductor layer 812, the wiring layer 813, and the adhesive layer 921 so as to surround the outer periphery of the through electrode 816. Fig.37 As shown, the film thickness c of the insulating layer 915 at the position of the adhesive layer 921 is greater than the film thickness b of the insulating layer 915 at the position of the semiconductor layer 812. At this time, the retreated portion of the adhesive layer 921 may be embedded with the insulating layer 915. The thickness a of the adhesive layer 921 and the thickness b of the insulating layer 915 at the position of the semiconductor layer 812 near the adhesive layer 921 may satisfy the relationship a<2b. At the position of the adhesive layer 921, the insulating layer 915 may have a seam in the lateral direction DL. Note that although Fig.37 An example is shown in which the pad electrode 914 is embedded in the insulating layer of the wiring layer 113 , and the pad electrode 914 may be exposed from the insulating layer of the wiring layer 113 and may be in contact with the adhesive layer 921 .

[0281] In addition, a plurality of vias 917 are connected to the pad electrodes 114 bonded to the through-electrode 816 among the pad electrodes 914 provided in the wiring layer 113. The vias 917 may be connected to a surface opposite to a surface to which the through-electrode 816 is connected. By connecting a plurality of vias 917 to the through-electrode 816, the reliability of the connection of the through-electrode 816 via the vias 917 may be improved while coping with an increase in stress caused by the through-electrode 816.

[0282] Note that in the package 900 of the ninth embodiment, the light shielding layer 817 of the eighth embodiment is omitted, but the light shielding layer 817 may be provided.

[0283] Fig.38 is a cross-sectional view showing an example of a method for manufacturing a through-electrode of a package according to the ninth embodiment. Fig.38 In, similar to Fig.37 , shown in an enlarged manner Fig.36 A portion of package 900 in FIG.

[0284] In the drawing, the wiring layer 113 of the chip 111 is bonded to the semiconductor layer 812 of the chip 811 via an adhesive layer 921. In the wiring layer 113, a pad electrode 914 to which a plurality of vias 917 are connected is formed.

[0285] Next, as shown in b of the figure, the semiconductor layer 812 and the adhesive layer 921 are patterned by photolithography and dry etching to form through holes 922 and 923. In the case where the etching rate of the adhesive layer 921 is higher than the etching rate of the semiconductor layer 812, side etching is performed in the adhesive layer 921 compared to the semiconductor layer 812, and the adhesive layer retreats from the semiconductor layer 812.

[0286] Next, as shown in "C" of the drawing, an insulating layer 915 is formed in the through holes 922 and 923 to cover the sidewalls of the through hole 922 and the sidewalls of the through hole 923. At this time, a high coverage film formation method such as atomic layer deposition (ALD) can be used. In the case where the relationship of a < 2b is satisfied, the retreated portion of the adhesive layer 921 can be backfilled with the insulating layer 915.

[0287] Then, if Fig.37As shown, the bottom insulating layer 915 is removed by a method such as plasma etching, and the front surface of the pad electrode 914 is exposed. Then, a through electrode 916 is formed to be embedded in the semiconductor layer 812 and the adhesive layer 921 via the insulating layer 915. At this time, the through electrode 916 is connected to the pad electrode 914.

[0288] In this manner, in the ninth embodiment, the adhesive layer 921 is retreated from the semiconductor layer 812 at the embedding position of the through electrode 816, and the film thickness c of the insulating layer 916 at the position of the adhesive layer 921 is made larger than the film thickness b of the insulating layer 916 at the position of the semiconductor layer 812. Thus, the embedding properties of the through electrode 816 and the adhesive layer 921 embedded in the semiconductor layer 812 via the insulating layer 916 can be improved, and the reliability of the package 900 can be improved.

[0289] <10. Tenth Implementation Method>

[0290] In the ninth embodiment, a plurality of vias 917 connected to a surface opposite to a surface to which the through-electrode 816 is connected are uniformly arranged in the pad electrode 914. In the tenth embodiment, vias connected to a surface opposite to a surface to which the through-electrode 816 is connected are provided on the pad electrode so as to be separated from the axis of the through-electrode 816.

[0291] Fig.39 is a cross-sectional view showing a configuration example of a pad electrode of a package according to a tenth embodiment.

[0292] In the drawings, in the tenth embodiment, a pad electrode 934 and a via hole 937 are provided instead of the pad electrode 914 and the via hole 917 of the ninth embodiment. In addition, the pad electrode 934 is exposed from the insulating layer of the wiring layer 113 and is in contact with the adhesive layer 921. The other structures of the tenth embodiment are the same as those of the ninth embodiment.

[0293] The pad electrode 934 is embedded in the wiring layer 113. At this time, the pad electrode 934 may be exposed from the insulating layer of the wiring layer 113. The through electrode 816 is bonded to the pad electrode 934. In the pad electrode 934, the via 937 is connected to the surface opposite to the surface to which the through electrode 816 is connected. The via 937 is provided at a position separated from the axis of the through electrode 816. At this time, it is possible to prevent the through hole 937 from being formed on the axis of the through electrode 816. For example, the through electrode 816 may be bonded to the center of the pad electrode 934, and the via 937 may be bonded to the peripheral portion of the pad electrode 934.

[0294] In this manner, in the tenth embodiment, the via 937 is arranged at a position separated from the axis of the through electrode 816. Thereby, stress caused by the through electrode 816 can be made less likely to be applied to the via 937, and peeling of the via 937 can be suppressed.

[0295] <11. Eleventh Implementation Method>

[0296] In the ninth embodiment, the wiring layer 113 is bonded to the adhesive layer 921, and the through electrode 816 penetrates the adhesive layer 921 and is connected to the pad electrode 914. In the eleventh embodiment, the wiring layer 113 is bonded to the adhesive layer 921 via the etching stopper layer, and the through electrode 816 penetrates the adhesive layer 921 and the etching stopper layer and is connected to the pad electrode.

[0297] Fig.40 is a cross-sectional view showing a configuration example of a pad electrode of a package according to an eleventh embodiment.

[0298] In the figure, in the eleventh embodiment, a pad electrode 941 and a through hole 947 are provided instead of the pad electrode 914 and the via hole 917 of the ninth embodiment. In addition, in the eleventh embodiment, an etching stopper layer 944 is added to the configuration of the ninth embodiment. The other structure of the eleventh embodiment is the same as that of the ninth embodiment.

[0299] The pad electrode 941 is embedded in the wiring layer 113. At this time, the pad electrode 941 may be exposed from the insulating layer of the wiring layer 113. A plurality of vias 947 are connected to the pad electrode 941. The vias 947 may be connected to a surface opposite to a surface to which the through-electrode 816 is connected.

[0300] The etching stopper layer 944 may be provided between the wiring layer 113 and the adhesive layer 921. In the etching stopper layer 944, a through hole 945 is formed through which the through electrode 816 passes. At this time, the through electrode 816 may be bonded to the pad electrode 941 by self-alignment. The size of the bonding surface of the pad electrode 941 and the size of the bonding surface of the through electrode 816 may be equal to each other. As a material of the etching stopper layer 944, an inorganic film such as SiN may be used.

[0301] In this way, in the eleventh embodiment, the wiring layer 113 is bonded to the adhesive layer 921 via the etch stop layer 944, and the through electrode 816 penetrates the adhesive layer 921 and the etch stop layer 944 and is connected to the pad electrode 941. Therefore, excessive etching when forming a through hole in which the through electrode 816 is embedded can be suppressed, and the yield and reliability of the package can be improved. In addition, the through electrode 816 can be connected to the pad electrode 941 by self-alignment, and even if misalignment occurs, the reduction in yield and reliability can be suppressed and the area of ​​the pad electrode 941 can be reduced.

[0302] <12. Twelfth Implementation>

[0303] In the sixth embodiment, the diameters of the through electrodes 626 embedded in the chips 621 mounted on the package 600 are equal to each other. In the twelfth embodiment, chips embedded with through electrodes having different diameters are mounted on the package.

[0304] Fig.41 is a cross-sectional view showing a configuration example of a package according to a twelfth embodiment.

[0305] In the drawings, the package 1100 includes chips 1121 and 1131 instead of the chips 621 and 631 of the sixth embodiment. In addition, in the package 1100, the extended redistribution layer 651, the dummy chip 638, and the protective film 639 of the sixth embodiment are omitted. The other configurations of the package 1100 of the twelfth embodiment are similar to those of the package 600 of the sixth embodiment.

[0306] The length of the chip 1121 in the lateral direction DL is equal to that of the chip 111. At this time, the position of the end of the chip 1121 in the lateral direction DL can be made equal to the position of the end of the chip 111 in the lateral direction DL. The chip 1121 includes a semiconductor layer 1122 and a wiring layer 1123. The wiring layer 1123 is formed on the semiconductor layer 1122. The wiring layer 1123 is provided with wiring and pad electrodes 1124 and 1128 embedded in the insulating layer. In addition, through electrodes 1126 and 1129 are embedded in the semiconductor layer 1122. The diameter of the through electrode 1126 is larger than the diameter of the through electrode 1129. The through electrode 1126 can be electrically connected to the power line, and the through electrode 1129 can be electrically connected to the signal line. At this time, the through electrode 1126 can be arranged in the power wiring area of ​​the chip 1121, and the through electrode 1129 can be arranged in the element area of ​​the chip 1121. The through electrode 1126 is connected to the pad electrode 1124 of the wiring layer 1123. The through electrode 1129 is connected to the pad electrode 1128 of the wiring layer 1123. The insulating layer 1125 is formed on the rear surface side of the semiconductor layer 1122. The insulating layer 1125 is formed in the semiconductor layer 1122 in a manner surrounding the periphery of the through electrodes 1126 and 1129, and can insulate the through electrodes 1126 and 1129 from the semiconductor layer 1122. The rear surface wirings 1120 and 1127 and the pad electrode are formed on the insulating layer 1125. The through electrode 1126 is electrically connected to the rear surface wiring 1120, and the through electrode 1129 is electrically connected to the rear surface wiring 1127.

[0307] The chip 1131 is shorter in length in the lateral direction DL relative to the chip 111. The chip 1131 has a semiconductor layer 1132 and a wiring layer 1133. The wiring layer 1133 is formed on the semiconductor layer 1132. The wiring layer 1133 is provided with a wiring 1134 embedded in an insulating layer. In addition, pad electrodes 1135 and 1136 are provided on the insulating layer of the wiring layer 1133. The bump electrode 1137 is formed on the pad electrode 1135, and the bump electrode 1138 is formed on the pad electrode 1136. The pad electrode 1135 is electrically connected to the rear surface wiring 1120 via the bump electrode 1137, and the pad electrode 1136 is electrically connected to the rear surface wiring 1127 via the bump electrode 1138.

[0308] In this way, in the twelfth embodiment, the chip 1121 in which the through electrodes 1126 and 1129 having different diameters are embedded is mounted on the package 1100. Therefore, the through electrode 1129 having a smaller diameter can be used in a path in which the influence of signal delay is small and in which only a tiny current flows, and the through electrode 1126 having a larger diameter can be used in a path in which the influence of signal delay is large and in which a large current flows. Therefore, the through electrodes 1126 and 1129 can be embedded in the chip 1121 while suppressing a reduction in the number of elements that can be formed in the chip 1121, and low signal delay and low power consumption can be achieved.

[0309] Alternatively, a dummy chip may be disposed around the chip 1131 , and a protective film covering the chip 1131 may be formed on the rear surface side of the chip 1121 .

[0310] Furthermore, through electrodes having different diameters may be applied to through electrodes embedded in the chip 111 of the first embodiment, or may be applied to through electrodes embedded in the chip 121. Furthermore, through electrodes having different diameters may be applied to through electrodes embedded in the chip 231 of the second embodiment, may be applied to through electrodes embedded in the dummy chip 238, or may be applied to through electrodes embedded in the protective film 239. Furthermore, through electrodes having different diameters may be applied to through electrodes embedded in the protective film 339 of the third embodiment. Furthermore, through electrodes having different diameters may be applied to through electrodes embedded in the dummy chip 438 of the fourth embodiment, or may be applied to through electrodes embedded in the protective film 427. Furthermore, through electrodes having different diameters may be applied to through electrodes embedded in the chip 811 of the ninth embodiment.

[0311] <13. Thirteenth Implementation Method>

[0312] In the twelfth embodiment, through electrodes 1126 and 1129 having different diameters are respectively connected to pad electrodes 1124 and 1128 of the wiring layer 1123. In the thirteenth embodiment, among the through electrodes 1126 and 1129 having different diameters, the through electrode 1129 having a smaller diameter is connected to an embedded wire embedded in a semiconductor layer.

[0313] Fig.42 is a cross-sectional view showing a configuration example of a package according to a thirteenth embodiment.

[0314] In the drawing, a package 1200 includes a chip 1221 instead of the chip 1121 of the twelfth embodiment. Other configurations of the package 1200 of the thirteenth embodiment are similar to those of the package 1100 of the twelfth embodiment.

[0315] In the chip 1221, an embedded wire 1232 is added to the chip 1121 of the twelfth embodiment. In addition, the chip 1121 has an insulating layer 1231 surrounding the embedded wire 1232. The other configurations of the chip 1221 of the thirteenth embodiment are similar to those of the chip 1121 of the twelfth embodiment.

[0316] The insulating layer 1231 is embedded in the semiconductor layer 1122. The material of the insulating layer 1231 is, for example, SiO2. At least a portion of the insulating layer 1231 may be used for shallow trench isolation (STI). The embedded wire 1232 is embedded in the insulating layer 1231. The embedded wire 1232 may be connected to a wire of the wiring layer 1123. The material of the embedded wire 1232 may be a metal such as Al or Cu, or may be silicide.

[0317] The through electrode 1129 is connected to the embedded wiring 1232 . At this time, the embedded wiring 1232 may be exposed from the insulating layer 1231 at the connection point of the through electrode 1129 .

[0318] In this manner, in the thirteenth embodiment, of the through electrodes 1126 and 1129 having different diameters, the through electrode 1129 having the smaller diameter is connected to the embedded wire 1232 embedded in the semiconductor layer 1122. Therefore, the aspect ratio of the through electrode 1129 can be reduced, and a conduction failure of the through electrode 1129 can be suppressed while coping with miniaturization of the through electrode 1129.

[0319] In addition, the through-electrode connected to the buried wiring embedded in the semiconductor layer can be applied to both the through-electrode embedded in the chip 111 of the first embodiment and the through-electrode embedded in the chip 121. In addition, the through-electrode connected to the embedded wiring embedded in the semiconductor layer can be applied to the through-electrode embedded in the chip 231 of the second embodiment.

[0320] <14. Fourteenth Implementation Method>

[0321] In the twelfth embodiment, the chip 1121 in which the through electrodes 1126 and 1129 having different diameters are embedded is mounted on the package 1100. In the fourteenth embodiment, the chip in which different numbers of through electrodes connected to the pad electrodes are embedded is mounted on the package.

[0322] Fig.43 is a cross-sectional view showing a configuration example of a package according to a fourteenth embodiment.

[0323] In the drawing, a package 1300 includes a chip 1321 instead of the chip 1221 of the thirteenth embodiment. Other configurations of the package 1300 of the fourteenth embodiment are similar to those of the package 1200 of the thirteenth embodiment.

[0324] In the chip 1321, a through electrode 1323 is added to the chip 1221 of the thirteenth embodiment. The other configurations of the chip 1321 of the fourteenth embodiment are similar to those of the chip 1221 of the thirteenth embodiment.

[0325] The through electrode 1323 is buried in the semiconductor layer 1122. The insulating layer 1125 is formed around the through electrode 1323, and the through electrode 1323 is insulated from the semiconductor layer 1122 by the insulating layer 1125. The through electrode 1323 is connected to the pad electrode 1322 of the wiring layer 1123. The number of through electrodes 1323 connected to one pad electrode 1322 is different from the number of through electrodes 1126 connected to the pad electrode 1124. For example, a plurality of through electrodes 1323 may be connected to one pad electrode 1322, and one through electrode 1126 may be connected to the pad electrode 1124. In addition, the diameter of the through electrode 1323 may be smaller than the diameter of the through electrode 1126 or larger than the diameter of the through electrode 1129. The through electrode 1323 may be electrically connected to a power supply line. At this time, the through electrode 1323 may be provided in a power supply wiring region of the chip 1321. The through electrode 1323 is electrically connected to a rear surface wiring 1324 formed on the rear surface side of the semiconductor layer 1122. The rear surface wiring 1324 is connected to a pad electrode 1138 of the wiring layer 1131 via a bump electrode 1139.

[0326] In this way, in the fourteenth embodiment, the number of through electrodes 1323 connected to one pad electrode 1322 is greater than the number of through electrodes 1126 connected to the pad electrode 1124. Thus, the resistance of the through electrodes 1323 connected to the pad electrode 1322 can be reduced while suppressing an increase in the diameter of the through electrode 1323 connected to one pad electrode 1322. Therefore, uniform embedding of each through electrode 1126, 1129, 1323 embedded in the semiconductor layer 1122 can be achieved, and the resistance of the through electrodes 1126, 1129, 1323 can be set individually. As a result, the reliability of the through electrodes 1126, 1129, 1323 can be suppressed from being reduced, and low signal delay and low power consumption can be achieved, and the number of elements that can be formed in the chip 1321 can be increased.

[0327] Note that different numbers of through electrodes connected to the pad electrodes may be applied to the through electrodes embedded in the chip 111 of the first embodiment, or may be applied to the through electrodes embedded in the chip 121. Furthermore, different numbers of through electrodes connected to the pad electrodes may be applied to the through electrodes embedded in the chip 231 of the second embodiment, may be applied to the through electrodes embedded in the dummy chip 238, or may be applied to the through electrodes embedded in the protective film 239. Furthermore, different numbers of through electrodes connected to the pad electrodes may be applied to the through electrodes embedded in the protective film 339 of the third embodiment. Furthermore, different numbers of through electrodes connected to the pad electrodes may be applied to the through electrodes embedded in the dummy chip 438 of the fourth embodiment, or may be applied to the through electrodes embedded in the protective film 427. Furthermore, different numbers of through electrodes connected to the pad electrodes may be applied to the through electrodes embedded in the chip 811 of the ninth embodiment.

[0328] <15. Application examples of mobile objects>

[0329] The technology of the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure can be implemented in the form of a device installed on any kind of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0330] Fig.44 is a block diagram showing an embodiment of a schematic configuration of a vehicle control system as an embodiment of a mobile object control system to which the technology of the present disclosure can be applied.

[0331] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.44 In the illustrated embodiment, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0332] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0333] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0334] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0335] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

[0336] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0337] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0338] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0339] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0340] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.44 In the embodiment of the present invention, the audio speaker 12061, the display portion 12062 and the instrument panel 12063 are shown as embodiments of the output device. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0341] Fig.45 It is a diagram illustrating an embodiment of the installation position of the imaging unit 12031.

[0342] exist Fig.45 In the embodiment, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0343] The imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 provided at the front nose in the interior of the vehicle and the imaging unit 12105 provided at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The imaging unit 12105 provided at the upper portion of the windshield in the interior of the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0344] Please note that Fig.45An embodiment of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging portions 12102 and 12103 provided to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0345] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0346] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting objects that exist on the driving path of the vehicle 12100 and are traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can pre-set the following distance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the driver's operation, etc., can be performed.

[0347] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0348] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0349] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied not only to the imaging unit 12031 and the driver state detection unit 12041 in the above configuration, but also to realize at least some functions of the electronic control unit. Specifically, for example, Figure 1 The package 100 in the embodiment can realize at least some functions of the electronic control unit while being applied to the imaging portion 12031. By applying the technology of the present disclosure to the vehicle control system 12000, it is possible to obtain captured images while suppressing an increase in the installation area and realize at least some functions of vehicle control.

[0350] It should be noted that the above-mentioned embodiments illustrate embodiments for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the gist of the present technology. In addition, the effects described in this specification are only embodiments and are not limited, and other effects can be provided.

[0351] It should be noted that the present technology can also have the following configurations.

[0352] (1) A package comprising:

[0353] a first chip having a front surface on which a first wiring layer is formed,

[0354] a second chip having a front surface on which a second wiring layer is formed and having a length in a lateral direction at least shorter than that of the first chip, and

[0355] The extended redistribution layer extends from the second chip in a lateral direction and is electrically connected to the first wiring layer and the second wiring layer.

[0356] (2) The packaging according to (1), wherein

[0357] The size of the extended redistribution layer is equal to the size of the front surface of the first chip.

[0358] (3) A package according to (1) or (2), wherein

[0359] The extended redistribution layer is directly bonded to the first wiring layer.

[0360] (4) The package according to any one of (1) to (3), further including a support member that supports the extended redistribution layer on an extension region extending in a lateral direction from a mounting region of the second chip.

[0361] (5) The packaging according to (4), wherein

[0362] The support member includes at least one of a protection film or a dummy chip.

[0363] (6) The package according to (4) or (5), further including a through electrode formed in at least one of the first chip, the second chip, or the support member.

[0364] (7) The package according to any one of (4) to (6), further including an external connection terminal connected to the extended redistribution layer via a through hole formed in the support member.

[0365] (8) The package according to any one of (1) to (7), further including an extended rear surface redistribution layer extending in a lateral direction from the second chip and formed on a rear surface side of the second chip.

[0366] (9) The package according to (8), further comprising: a third chip mounted on the extended rear surface redistribution layer in a flip-chip manner and having a front surface, the third wiring layer being formed on the front surface.

[0367] (10) The packaging according to (9), wherein

[0368] The third wiring layer is directly bonded to the extended rear surface redistribution layer or bonded to the extended rear surface redistribution layer via a bump.

[0369] (11) The package according to any one of (8) to (10), further comprising: a rear surface support member that supports the extended rear surface redistribution layer on the rear surface side of the second chip in an extended region extending in a lateral direction from a mounting region of the second chip.

[0370] (12) The packaging according to (11), wherein

[0371] The rear surface supporting member includes at least one of a protective film or a dummy chip.

[0372] (13) The package according to (11) or (12), further including: a through electrode formed in at least one of the third chip or the rear surface support member.

[0373] (14) The package according to any one of (9) to (13), further including a support substrate provided on a rear surface side of the third chip.

[0374] (15) The package according to any one of (1) to (14), wherein

[0375] Either the first chip or the second chip is an optical chip arranged in the uppermost layer.

[0376] (16) The package according to (15), further comprising a transparent resin formed on the optical chip.

[0377] (17) The package according to (16), further comprising a transparent substrate provided on the transparent resin.

[0378] (18) The package according to any one of (1) to (17), further including a fourth chip in which a fourth wiring layer is formed by stacking on a rear surface of the first chip via an adhesive layer.

[0379] (19) The package according to (18), further including a light shielding film formed at a position in contact with the adhesive layer.

[0380] (20) The package according to (18) or (19), further comprising:

[0381] a through electrode that penetrates the first chip and the adhesive layer and electrically connects the first wiring layer and the fourth wiring layer, and

[0382] The insulating layer insulates the through electrode from the semiconductor layer of the first chip, wherein

[0383] The adhesive layer retreats from the semiconductor layer of the first chip at the embedding position of the through-electrode, and the film thickness of the insulating layer at the position of the adhesive layer is thicker than the film thickness of the insulating layer at the position of the semiconductor layer.

[0384] (21) The packaging according to (20), wherein

[0385] When the film thickness of the adhesive layer is a, and the film thickness of the insulating layer at the position of the semiconductor layer is b, a relationship of a<b is satisfied.

[0386] (22) The package according to (20) or (21), further comprising:

[0387] a pad electrode, a through electrode connected to the pad electrode, and

[0388] A plurality of via holes are connected to a surface of the pad electrode opposite to a surface to which the through-electrode is connected.

[0389] (23) The package according to any one of (20) to (22), further comprising:

[0390] a pad electrode, a through electrode connected to the pad electrode, and

[0391] The via hole is connected to a surface of the pad electrode opposite to a surface to which the through electrode is connected, at a position separated from an axis of the through electrode.

[0392] (24) The package according to any one of (20) to (23), further comprising:

[0393] a pad electrode, a through electrode connected to the pad electrode, and

[0394] An etching stopper layer is formed on the pad electrode and is provided with a through hole through which the through electrode passes.

[0395] (25) A semiconductor device comprising:

[0396] a first chip having a front surface on which a first wiring layer is formed and including through electrodes having different diameters and electrically connected to the first wiring layer; and

[0397] A second chip having a front surface on which a second wiring layer is formed is stacked on the first chip such that the first wiring layer and the second wiring layer face each other.

[0398] (26) The semiconductor device according to (25), further comprising:

[0399] a rear surface wiring formed on the rear surface of the first chip, and

[0400] A third chip is mounted on the rear surface wiring in a flip chip manner.

[0401] (27) The semiconductor device according to (25) or (26), further comprising an embedded wiring embedded in the semiconductor layer of the first chip, wherein

[0402] The through-electrode having a smaller diameter among the through-electrodes having different diameters is electrically connected to the first wiring layer via the embedded wiring.

[0403] (28) The semiconductor device according to any one of (25) to (27), wherein

[0404] The through-electrodes include:

[0405] a first through electrode connected to a signal line, and

[0406] The second through electrode is connected to the power line and has a diameter larger than that of the first through electrode.

[0407] (29) A semiconductor device comprising:

[0408] a first chip having a front surface on which a first wiring layer including a plurality of pad electrodes is formed, the first chip including different numbers of through electrodes contacting the pad electrodes, and

[0409] A second chip having a front surface on which a second wiring layer is formed is stacked on the first chip such that the first wiring layer and the second wiring layer face each other.

[0410] (30) The semiconductor device according to (29), further comprising:

[0411] a rear surface wiring formed on the rear surface of the first chip, and

[0412] A third chip is mounted on the rear surface wiring in a flip chip manner.

[0413] (31) The semiconductor device according to (29) to (30), further comprising an embedded wiring embedded in the semiconductor layer of the first chip, wherein

[0414] One through-electrode in contact with the pad electrode among the different numbers of through-electrodes in contact with the pad electrode is electrically connected to the first wiring layer via the embedded wiring.

[0415] (32) The semiconductor device according to any one of (29) to (31), wherein

[0416] The diameter of the through-electrodes that are in contact with a smaller number of pad electrodes is smaller than the diameter of the through-electrodes that are in contact with a larger number of pad electrodes that are in contact with a different number of pad electrodes.

[0417] (33) A method for manufacturing a package, the method comprising the following steps:

[0418] forming a first wiring layer on the wafer of the solid block divided into the first chips,

[0419] Arranging a second chip on the supporting substrate wafer, the second chip having a second wiring layer and having a size smaller than the front surface of the first chip,

[0420] forming a support member on the support substrate wafer, the support member being adjacent to the second chip so as to be equal in size to the front surface of the first chip and equal in height to the second chip,

[0421] forming an extended redistribution layer having a size equal to that of the front surface of the first chip on the second wiring layer and the support member,

[0422] electrically connecting the first wiring layer and the second wiring layer so that the first wiring layer and the second wiring layer face each other via the extended redistribution layer, and

[0423] The package is divided into package solid blocks, wherein the second chip is stacked on the first chip via an extended redistribution layer.

[0424] (34) The method for manufacturing a package according to (33), further comprising the following steps:

[0425] forming a first through electrode connected to the first wiring layer in the first chip,

[0426] forming a second through electrode connected to the second wiring layer in the second chip,

[0427] forming an extended rear surface redistribution layer on the rear surface of the second chip and the rear surface of the support member, allowing the extended rear surface redistribution layer to be cut to have a size equal to that of the front surface of the first chip, and

[0428] A third chip is mounted in a flip chip manner, the third chip having a front surface, on which a third wiring layer is formed on the extended rear surface, wherein

[0429] The package is divided into package solid blocks, wherein the second chip is stacked on the first chip via the extended redistribution layer, and the third chip is stacked on the second chip via the extended rear surface redistribution layer.

[0430] (35) The method for manufacturing a package according to (33), further comprising the following steps:

[0431] forming an extended rear surface redistribution layer on the rear surface of the second chip and the rear surface of the support member, allowing the extended rear surface redistribution layer to be cut to have a size equal to that of the front surface of the first chip,

[0432] mounting a third chip on the extended rear surface redistribution layer in a flip chip manner, the third chip having a third wiring layer and having a size smaller than the front surface of the first chip,

[0433] forming a rear surface support member adjacent to the third chip on the extended rear surface redistribution layer so as to have the same size as the front surface of the first chip, and

[0434] A through electrode is formed in at least one of the third chip or the rear surface support member, wherein

[0435] The package is divided into package solid blocks, wherein the second chip is stacked on the first chip via the extended redistribution layer, and the third chip is stacked on the second chip via the extended rear surface redistribution layer.

[0436] Reference Symbols List

[0437] 100 packs

[0438] 111, 121, 131 chips

[0439] 112, 122, 132 semiconductor layer

[0440] 115 Protective film

[0441] 141 Extended redistribution layer

[0442] 116, 126 through-electrode

[0443] 151 Extended rear surface redistribution layer

[0444] 113, 123, 133 wiring layers

[0445] 143, 153 insulation layer

[0446] 134, 144 wires

[0447] 117 On-chip lens

[0448] 118 bonding wire

[0449] 127, 139 protective film

[0450] 154 Rear surface rewind

[0451] 136 Bump Electrode

[0452] 137 Bottom Filler

[0453] 138 Virtual Chip

[0454] 161 Support substrate.

Claims

1. A package comprising: A first chip having a front surface, with a first wiring layer formed on the front surface; a second chip having a front surface on which a second wiring layer is formed, and having a length shorter than that of the first chip in a lateral direction at least; as well as An extended redistribution layer extends from the second chip in the lateral direction and is electrically connected to the first and second wiring layers.

2. The package according to claim 1, wherein: The size of the extended redistribution layer is equal to the size of the front surface of the first chip.

3. The package according to claim 1, wherein: The extended redistribution layer is directly bonded to the first wiring layer. 4 . The package according to claim 1 , further comprising a support member supporting the extended redistribution layer on an extended region extending from a mounting region of the second chip in the lateral direction.

5. The package according to claim 4, wherein: The supporting member includes at least one of a protection film and a dummy chip. 6 . The package according to claim 4 , further comprising a through-electrode formed in at least one of the first chip, the second chip, and the support member. 7 . The package according to claim 4 , further comprising an external connection terminal connected to the extended redistribution layer via a through hole formed in the support member. 8 . The package according to claim 1 , further comprising an extended rear surface redistribution layer extending from the second chip in the lateral direction and formed on a rear surface side of the second chip. 9 . The package according to claim 8 , further comprising a third chip mounted on the extended rear surface redistribution layer in a flip-chip manner, and having a front surface on which a third wiring layer is formed.

10. The package according to claim 8, wherein: The third wiring layer is directly bonded to the extended rear surface redistribution layer or bonded to the extended rear surface redistribution layer via a bump. 11 . The package according to claim 8 , further comprising a rear surface support member supporting the extended rear surface redistribution layer on the rear surface side of the second chip in an extended region extending from a mounting region of the second chip in the lateral direction.

12. The package according to claim 11, wherein: The rear surface supporting member includes at least one of a protective film and a dummy chip. 13 . The package according to claim 11 , further comprising a through electrode formed in at least one of the third chip and the rear surface support member. 14 . The package according to claim 9 , further comprising a support substrate provided on a rear surface side of the third chip.

15. The package according to claim 1, wherein: Either the first chip or the second chip is an optical chip disposed in an uppermost layer. 16 . The package according to claim 15 , further comprising a transparent resin formed on the optical chip. 17 . The package according to claim 16 , further comprising a transparent substrate disposed on the transparent resin. 18 . The package according to claim 14 , further comprising a fourth chip in which a fourth wiring layer is formed by being stacked on a rear surface of the first chip via an adhesive layer. 19 . The package according to claim 18 , further comprising a light shielding film formed at a position in contact with the adhesive layer.

20. The package of claim 18, further comprising: a through electrode penetrating the first chip and the adhesive layer and electrically connecting the first wiring layer and the fourth wiring layer; as well as The insulating layer insulates the through electrode from the semiconductor layer of the first chip, wherein: The adhesive layer retreats from the semiconductor layer of the first chip at the embedding position of the through electrode, and the film thickness of the insulating layer at the position of the adhesive layer is thicker than that at the position of the semiconductor layer.

21. The package according to claim 20, wherein: When the film thickness of the adhesive layer is a, and the film thickness of the insulating layer at the position of the semiconductor layer is b, a relationship of a<b is satisfied.

22. The package of claim 20, further comprising: a pad electrode, the through electrode being connected to the pad electrode; as well as A plurality of via holes are connected to a surface of the pad electrode opposite to a surface connected to the through electrode.

23. The package of claim 20, further comprising: a pad electrode, the through electrode being connected to the pad electrode; as well as A via hole is connected to a surface of the pad electrode opposite to a surface connected to the through electrode at a position separated from an axis of the through electrode.

24. The package of claim 18, further comprising: a pad electrode, to which the through electrode is connected; as well as An etching stopper layer is formed on the pad electrode and is provided with a through hole through which the through electrode passes.

25. A semiconductor device comprising: a first chip having a front surface on which a first wiring layer is formed, and comprising through electrodes having different diameters and electrically connected to the first wiring layer; as well as A second chip has a front surface on which a second wiring layer is formed, and the second chip is stacked on the first chip such that the first wiring layer and the second wiring layer face each other.

26. The semiconductor device according to claim 25, further comprising: A rear surface wiring formed on the rear surface of the first chip; as well as The third chip is mounted on the rear surface wiring in a flip chip manner.

27. The semiconductor device according to claim 25, further comprising an embedded wiring, the embedded wiring being embedded in the semiconductor layer of the first chip, wherein The through-electrode having a smaller diameter among the through-electrodes having different diameters is electrically connected to the first wiring layer via the embedded wiring.

28. The semiconductor device according to claim 25, wherein The through electrode comprises: a first through electrode connected to a signal line, and The second through-electrode is connected to the power supply line and has a diameter larger than that of the first through-electrode.

29. A semiconductor device comprising: A first chip having a front surface on which a first wiring layer including a plurality of pad electrodes is formed, the first chip including different numbers of through electrodes contacting the pad electrodes; as well as A second chip having a front surface on which a front surface of a second wiring layer is formed is stacked on the first chip such that the first wiring layer and the second wiring layer face each other.

30. The semiconductor device according to claim 29, further comprising: A rear surface wiring formed on the rear surface of the first chip; as well as The third chip is mounted on the rear surface wiring in a flip chip manner.

31. The semiconductor device according to claim 29, further comprising an embedded wiring, the embedded wiring being embedded in the semiconductor layer of the first chip, wherein One through-electrode in contact with the pad electrodes among the through-electrodes of different numbers in contact with the pad electrodes is electrically connected to the first wiring layer via the embedded wiring.

32. The semiconductor device according to claim 29, wherein: Among the different numbers of pad electrode contacts that contact the pad electrodes, a smaller number of through-electrodes that contact the pad electrodes have smaller diameters than a larger number of through-electrodes that contact the pad electrodes.

33. A method for manufacturing a package, the method comprising the steps of: forming a first wiring layer on a wafer, the wafer being segmented into solid blocks of first chips; Arranging a second chip on the supporting substrate wafer, the second chip having a second wiring layer and having a size smaller than a front surface of the first chip; forming a support member on the support substrate wafer, the support member being adjacent to the second chip to be equal in size to the front surface of the first chip and equal in height to the second chip; forming an extended redistribution layer having a size equal to that of the front surface of the first chip on the second wiring layer and the support member; electrically connecting the first wiring layer and the second wiring layer so that the first wiring layer and the second wiring layer face each other via the extended redistribution layer; and The package is divided into a plurality of package solid blocks, in which the second chip is stacked on the first chip via the extended redistribution layer.

34. The method for manufacturing a package according to claim 33, further comprising the steps of: forming a first through electrode connected to the first wiring layer in the first chip; forming a second through electrode connected to the second wiring layer in the second chip; forming an extended rear surface redistribution layer on the rear surface of the second chip and the rear surface of the support member, allowing the extended rear surface redistribution layer to be cut to be equal in size to the front surface of the first chip; and A third chip is mounted in a flip chip manner, the third chip having a front surface, on which a third wiring layer is formed on the extended rear surface redistribution layer, wherein: The package is divided into package solid blocks in which the second chip is stacked on the first chip via the extended redistribution layer, and the third chip is stacked on the second chip via the extended rear surface redistribution layer.

35. The method for manufacturing a package according to claim 33, further comprising the steps of: forming an extended rear surface redistribution layer on the rear surface of the second chip and the rear surface of the support member, allowing the extended rear surface redistribution layer to be cut to be equal in size to the front surface of the first chip; Mounting a third chip on the extended rear surface redistribution layer in a flip chip manner, wherein the third chip has a third wiring layer and has a size smaller than the front surface of the first chip; forming a rear surface support member adjacent to the third chip on the extended rear surface redistribution layer so that the rear surface support member has the same size as the front surface of the first chip; as well as A through electrode is formed in at least one of the third chip and the rear surface support member, wherein The package is divided into package solid blocks in which the second chip is stacked on the first chip via the extended redistribution layer, and the third chip is stacked on the second chip via the extended rear surface redistribution layer.

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