Array substrate and display device

Abstract

The invention discloses an array substrate. The array substrate comprises a substrate body, a signal line, a first insulating layer, an active layer and a first via hole. And the signal line is positioned on the substrate base plate. The first insulating layer is located on the side, away from the substrate, of the signal line. The active layer is positioned on one side, far away from the substrate, of the first insulating layer; the active layer comprises a first part, a second part and a channel structure located between the first part and the second part. The first via hole at least penetrates through the first insulating layer and at least exposes part of the signal line. The first part is configured to be connected with the signal line through the first via hole; the material of the second part and the first part is the same as the material of the channel structure; and the conductivity of the channel structure is different from the conductivity of the first part, and is different from the conductivity of the second part.

Description

Array substrate and display device

[0001] This application claims priority to international patent application No. PCT / CN2023 / 097164, filed on May 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0003] Liquid crystal display panels have been widely used. Generally, a liquid crystal display panel includes an opposing substrate and an array substrate that are arranged relative to each other, and a liquid crystal layer between the opposing substrate and the array substrate. The array substrate may include thin film transistors, gate lines, signal lines, pixel electrodes, and the opposing substrate or the array substrate may also include a common electrode and a common electrode signal line. With the continuous development of display technology, the requirements for liquid crystal display panels are getting higher and higher. Among them, high pixel density is an important development direction of display devices. Improving the aperture ratio of liquid crystal display panels is an important way to improve the pixel density of liquid crystal display panels. How to improve the aperture ratio of liquid crystal display panels is a technical problem that urgently needs to be solved.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate includes a base substrate, a signal line, a first insulating layer, an active layer, and a first via. The signal line is located on the base substrate. The first insulating layer is located on a side of the signal line away from the base substrate. The active layer is located on a side of the first insulating layer away from the base substrate; the active layer includes a first portion, a second portion, and a channel structure located between the first portion and the second portion. The first via at least penetrates the first insulating layer and exposes at least a portion of the signal line. The first portion is configured to be connected to the signal line through the first via; the material of the second portion and the first portion is the same as the material of the channel structure; and the conductivity of the channel structure is different from the conductivity of the first portion and different from the conductivity of the second portion.

[0006] In some embodiments, the array substrate further comprises a connecting electrode. The connecting electrode is located on a side of the active layer away from the base substrate, the connecting electrode being electrically connected to the signal line and the first portion, respectively; and the first portion is configured to be electrically connected to the signal line through the connecting electrode.

[0007] In some embodiments, the array substrate further includes a second insulating layer. The second insulating layer is located between the active layer and the connecting electrode. The first via penetrates the second insulating layer and the first insulating layer, and the first via also exposes at least a portion of the first portion. At least a portion of the connecting electrode is located within the first via, and an orthographic projection of the connecting electrode on the base substrate partially overlaps with an orthographic projection of the first portion on the base substrate, and also overlaps with an orthographic projection of the signal line on the base substrate.

[0008] In some embodiments, an orthographic projection of the first portion on the base substrate partially overlaps with an orthographic projection of the signal line on the base substrate.

[0009] In some embodiments, the array substrate includes a first connection area defined by the first via. The first connection area includes a first region, a second region, and a third region sequentially connected in a direction away from the channel structure. The orthographic projection of the first region on the substrate partially overlaps with the orthographic projection of the first portion on the substrate, and does not overlap with the orthographic projection of the signal line on the substrate. The orthographic projection of the second region on the substrate partially overlaps with the orthographic projection of the first portion on the substrate, and is located within the range of the orthographic projection of the signal line on the substrate. The orthographic projection of the third region on the substrate is located outside the orthographic projection of the first portion on the substrate, and at least partially overlaps with the orthographic projection of the signal line on the substrate. The connecting electrode covers at least part of the second region and the third region.

[0010] In some embodiments, in the first region, the array substrate includes the first insulating layer and the first portion, which are stacked together. In the second region, the array substrate includes the signal line, the first insulating layer, the first portion, and the connection electrode, which are stacked together. In the third region, the array substrate includes the signal line and the connection electrode, which are stacked together.

[0011] In some embodiments, the connecting electrode covers at least a portion of the first region. At the location of the first region, the array substrate further includes a connecting electrode located on a side of the first portion away from the base substrate.

[0012] In some embodiments, the connecting electrode exposes at least a portion of the first region. The first portion includes a groove portion that is concave toward a side closer to the base substrate, the groove portion is located in the first region, and an orthographic projection of the groove portion on the base substrate does not overlap with an orthographic projection of the connecting electrode on the base substrate.

[0013] In some embodiments, the signal line, the first insulating layer, the first portion, and the connecting electrode form a protruding structure in the second region that protrudes toward a side farther from the base substrate than the first region and the third region.

[0014] In some embodiments, the first portion and / or the second portion comprises a serrated structure at an edge of the second region close to the first region.

[0015] In some embodiments, an orthographic projection of the first portion on the base substrate does not overlap with an orthographic projection of the signal line on the base substrate.

[0016] In some embodiments, an orthographic projection of the first portion on the base substrate does not overlap with an orthographic projection of the signal line on the base substrate.

[0017] In some embodiments, the array substrate includes a first connection area defined by the first via. The first connection area includes a fourth region and a fifth region sequentially connected in a direction away from the channel structure. The orthographic projection of the fourth region on the base substrate at least partially overlaps with the orthographic projection of the first portion on the base substrate, and does not overlap with the orthographic projection of the signal line on the base substrate. The orthographic projection of the fifth region on the base substrate at least partially overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the first portion on the base substrate. The connecting electrode covers at least a portion of the fourth region and at least a portion of the fifth region.

[0018] In some embodiments, in the fourth region, the array substrate includes the first insulating layer, the first portion, and the connection electrode, which are stacked. In the fifth region, the array substrate includes the signal line and the connection electrode, which are stacked.

[0019] In some embodiments, the connecting electrode exposes at least a portion of the fourth region. The first portion includes a groove portion that is concave toward a side closer to the base substrate, the groove portion is located in the fourth region, and an orthographic projection of the groove portion on the base substrate does not overlap with an orthographic projection of the connecting electrode on the base substrate.

[0020] In some embodiments, the connecting electrode includes a step structure, wherein the step structure includes a first step located in the fourth region and a second step located in the fifth region, wherein the first step is farther from the base substrate than the second step.

[0021] In some embodiments, a material of the first portion is different from a material of the connection electrode.

[0022] In some embodiments, the channel structure, the first portion and the second portion are an integrated structure. The material of the first portion includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen, and N represents nitrogen. The material of the connecting electrode includes a metal material.

[0023] In some embodiments, at least a portion of the first portion extends into the connecting electrode.

[0024] In some embodiments, the array substrate further includes a second insulating layer and a gate. The second insulating layer is located between the active layer and the connecting electrode. The gate is located on a side of the second insulating layer away from the base substrate. The connecting electrode and the gate are located on the same layer and comprise the same material.

[0025] In some embodiments, the first via hole penetrates the first insulating layer, at least a portion of the first portion is located in the first via hole, and the first portion is in contact with and connected to the signal line through the first via hole.

[0026] In some embodiments, the channel structure, the first portion, and the second portion are an integrated structure. The material of the first portion includes M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen, and N represents nitrogen.

[0027] In some embodiments, the first portion, the channel structure, and the second portion are arranged substantially along a straight line.

[0028] In some embodiments, the array substrate further comprises a gate line and a gate electrode. The gate line is disposed on a side of the active layer away from the base substrate, and the gate line extends along the first direction. The gate electrode is located on the same layer as the gate electrode and comprises the same material. The gate electrode extends along the second direction, and one end of the gate electrode is connected to the gate line. The first portion, the channel structure, and the second portion are arranged substantially along the first direction. The first direction and the second direction intersect; and the signal line extends along the second direction.

[0029] In some embodiments, the gate line includes a first extension segment and a second extension segment, wherein an orthographic projection of the first extension segment on the substrate does not overlap with an orthographic projection of the signal line on the substrate, and an orthographic projection of the second extension segment on the substrate overlaps with an orthographic projection of the signal line on the substrate. Along the second direction, a dimension of the first extension segment is smaller than a dimension of the second extension segment.

[0030] In some embodiments, the dimension of the first extension segment along the second direction is D1, and the value range of D1 is 2 μm to 6 μm. The dimension of the second extension segment along the second direction is D2, and D2 = D1 + H, and the value range of H is 0.2 μm to 1.5 μm.

[0031] In some embodiments, the array substrate further comprises a third insulating layer, a planarization layer, a second via, and a pixel electrode. The third insulating layer is located on a side of the connecting electrode away from the base substrate. The planarization layer is located on a side of the third insulating layer away from the base substrate. The second via penetrates at least the third insulating layer and the planarization layer, and the orthographic projection of the second via on the base substrate at least partially overlaps with the orthographic projection of the second portion on the base substrate. The pixel electrode is disposed on a side of the planarization layer away from the base substrate, extending through the second via and electrically connected to the second portion.

[0032] In some embodiments, the second via includes a first sub-hole extending through the third insulating layer and a second sub-hole extending through the planarization layer. The orthographic projection of the second sub-hole on the base substrate overlaps the orthographic projection of the first sub-hole on the base substrate, and a center of the orthographic projection of the second sub-hole on the base substrate is spaced apart from the center of the orthographic projection of the first sub-hole on the base substrate.

[0033] In some embodiments, the first portion, the channel structure, and the second portion are substantially arranged along a first direction. A center of an orthographic projection of the second sub-hole on the base substrate is spaced apart from a center of an orthographic projection of the first sub-hole on the base substrate along the first direction.

[0034] In some embodiments, the second via includes a first sub-hole extending through the third insulating layer and a second sub-hole extending through the planarization layer. A boundary of an orthographic projection of the second sub-hole on the base substrate substantially coincides with a boundary of an orthographic projection of the first sub-hole on the base substrate, and a center of an orthographic projection of the second sub-hole on the base substrate substantially coincides with a center of an orthographic projection of the first sub-hole on the base substrate.

[0035] In some embodiments, the array substrate further includes a transfer electrode. The transfer electrode is located between the active layer and the third insulating layer and is electrically connected to the second portion. The second via hole exposes at least a portion of the transfer electrode, and the pixel electrode is electrically connected to the transfer electrode and is electrically connected to the second portion through the transfer electrode.

[0036] In some embodiments, the second via hole exposes at least a portion of the second portion, and the pixel electrode is in contact with the second portion.

[0037] In some embodiments, the array substrate further includes a spacer located on a side of the pixel electrode away from the base substrate, wherein an orthographic projection of the spacer on the base substrate at least partially overlaps with an orthographic projection of the second sub-hole on the base substrate, wherein the second sub-hole is at least partially filled with the spacer.

[0038] In some embodiments, the array substrate further includes a pixel electrode, the pixel electrode and the active layer are located in the same layer and made of the same material, and the pixel electrode and the second portion are an integrated structure.

[0039] In some embodiments, in a cross-section along a plane perpendicular to the substrate and perpendicular to the direction extending the length of the signal line and intersecting the signal line and the first via, the surface of the signal line other than the lower surface is exposed in the first via; the lower surface refers to the surface of the signal line that contacts the substrate.

[0040] In some embodiments, in the cross section, an upper surface of the signal line and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are completely covered by the first portion or the connecting electrode.

[0041] In some embodiments, in the cross section, only a portion of an upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first portion or the connection electrode.

[0042] In some embodiments, in a cross-section taken along a plane perpendicular to the substrate and perpendicular to the direction in which the signal line extends, and intersecting the signal line and the first via, at least a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and lower surface of the signal line are not exposed in the first via. The lower surface refers to the surface of the signal line that contacts the substrate.

[0043] In some embodiments, in the cross section, only a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first insulating layer.

[0044] In some embodiments, in the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first portion or the connection electrode.

[0045] In some embodiments, in the cross section, only the upper surface of the middle portion of the signal line is covered by the first portion or the connection electrode, and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first insulating layer.

[0046] In some embodiments, the signal line is configured to provide a data signal to the first portion.

[0047] In some embodiments, the active layer includes a metal oxide material having a Hall mobility greater than or equal to 30 cm 2 / Vs.

[0048] In some embodiments, the array substrate further comprises a light shielding member located on the base substrate, and a gate line located on a side of the active layer away from the base substrate. The light shielding member and the signal line are located on the same layer and comprise the same material. A ratio of a line width of the gate line to a line width of the light shielding member along a direction perpendicular to an extension direction of the gate line is in a range of 0.3 to 0.9.

[0049] In another aspect, a display device is provided. The display device includes a driving circuit board and an array substrate as described in any of the above embodiments. The driving circuit board is electrically connected to the array substrate and configured to transmit a control signal to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0051] FIG1 is a planar structural diagram of a display device according to some embodiments;

[0052] FIG2 is a cross-sectional structural diagram of a display device according to some embodiments;

[0053] FIG3 is a planar structural diagram of an array substrate according to some embodiments;

[0054] FIG4 is a cross-sectional view taken along section line A-A1 in FIG3 ;

[0055] FIG5 is a partial enlarged view of the S1 region in FIG3 ;

[0056] FIG6 is another cross-sectional view along the section line A-A1 in FIG3;

[0057] FIG7A is a partial enlarged view of the S2 region in FIG3 ;

[0058] FIG7B is another partial enlarged view of the S2 region in FIG3 ;

[0059] FIG7C is another partial enlarged view of the S2 region in FIG3 ;

[0060] FIG7D is another partial enlarged view of the S2 region in FIG3 ;

[0061] FIG8A is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0062] FIG8B is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0063] FIG8C is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0064] FIG8D is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0065] FIG9 is another planar structural diagram of an array substrate according to some embodiments;

[0066] FIG10A is another planar structural diagram of an array substrate according to some embodiments;

[0067] FIG10B is another planar structural diagram of an array substrate according to some embodiments;

[0068] FIG10C is another planar structural diagram of an array substrate according to some embodiments;

[0069] FIG10D is another planar structural diagram of an array substrate according to some embodiments;

[0070] FIG10E is another planar structural diagram of an array substrate according to some embodiments;

[0071] FIG10F is another planar structural diagram of an array substrate according to some embodiments;

[0072] FIG10G is a planar structural diagram of another embodiment of an array substrate;

[0073] FIG11A is a cross-sectional structural diagram along the section line A-A2 in FIG10A;

[0074] FIG11B is a cross-sectional structural diagram along the section line A-A3 in FIG10D;

[0075] FIG11C is a cross-sectional structural diagram along the section line A-A4 in FIG10E;

[0076] FIG12A is another planar structural diagram of an array substrate according to some embodiments;

[0077] FIG12B is another planar structural diagram of an array substrate according to some embodiments;

[0078] FIG12C is another planar structural diagram of an array substrate according to some embodiments;

[0079] FIG12D is another planar structural diagram of an array substrate according to some embodiments;

[0080] FIG13 is a structural diagram of a first portion and a connecting electrode according to some embodiments;

[0081] FIG14 is a schematic diagram of a sawtooth structure according to some embodiments;

[0082] FIG15 is another planar structural diagram of an array substrate according to some embodiments;

[0083] FIG16 is a cross-sectional view taken along section line A-A5 in FIG15;

[0084] FIG17 is another planar structural diagram of an array substrate according to some embodiments;

[0085] FIG18 is a cross-sectional view taken along section line A-A6 in FIG17;

[0086] FIG19 is another planar structural diagram of an array substrate according to some embodiments;

[0087] FIG20 is a cross-sectional view taken along section line A-A7 in FIG19;

[0088] FIG21A is another planar structural diagram of an array substrate according to some embodiments;

[0089] FIG21B is another planar structural diagram of an array substrate according to some embodiments;

[0090] FIG21C is another planar structural diagram of an array substrate according to some embodiments;

[0091] FIG21D is another planar structural diagram of an array substrate according to some embodiments;

[0092] FIG21E is another planar structural diagram of an array substrate according to some embodiments;

[0093] FIG22A is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0094] FIG22B is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0095] FIG23A is another planar structural diagram of an array substrate according to some embodiments;

[0096] FIG23B is another planar structural diagram of an array substrate according to some embodiments;

[0097] FIG24 is a cross-sectional view taken along section line CC in FIG23A or FIG23B;

[0098] FIG25 is another planar structural diagram of an array substrate according to some embodiments;

[0099] FIG26 is a cross-sectional view taken along section line DD in FIG25;

[0100] FIG27 is another planar structural diagram of an array substrate according to some embodiments;

[0101] FIG28 is a cross-sectional view taken along section line EE in FIG27;

[0102] FIG29A is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0103] FIG29B is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0104] FIG29C is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0105] FIG29D is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0106] 30A to 30C are diagrams showing steps of a manufacturing process of an array substrate according to some embodiments;

[0107] 31A to 31C are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0108] 32A to 32B are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0109] 33A to 33C are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0110] 34A to 34C are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0111] 35A to 35B are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0112] 36A to 36C are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments;

[0113] 37A to 37C are diagrams showing steps of another manufacturing process of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0114] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0115] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0116] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0117] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0118] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0119] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0120] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0121] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0122] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0123] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0124] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0125] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0126] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0127] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0128] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0129] 1 , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0130] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0131] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be a liquid crystal display (LCD), or an organic light-emitting diode (OLED), a quantum dot electroluminescent display (QLED), or a mini / micro light-emitting diode (MLED). From the perspective of the form of the display device 1000, the display device 1000 may be a flat display, a curved display, or a foldable display. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular. Some embodiments of the present disclosure are schematically described below using a rectangular and flat liquid crystal display as an example. However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0132] In some embodiments, the display device 1000 includes a display panel 1100 and a driver circuit board. The driver circuit board may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board may also include other circuit structures, which are not listed here one by one. The driver circuit board is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0133] In the case where the display device 1000 is a liquid crystal display device, referring to FIG2 , the display device 1000 may further include a backlight source 1200 disposed on the backlight side of the display panel 1100. For example, the backlight source 1200 may be a direct-lit backlight source or an edge-lit backlight source, etc. The backlight source 1200 is used to provide backlight for the display panel 1100. The display panel can adjust the amount of light passing through the display panel 1100 to display different grayscales.

[0134] Continuing to refer to FIG2 , in the case where the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and an opposing substrate 200 (also referred to as a color filter substrate or packaging substrate) disposed opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the opposing substrate 200. The opposing substrate 200 may filter the light incident on the opposing substrate 200 so that each sub-pixel emits light of a color (e.g., red, green, and blue). Different sub-pixels may emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. Of course, the display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may further include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the opposing substrate close to the liquid crystal layer 300.

[0135] The array substrate 100 may include a display area and a peripheral area surrounding the display area. The display area may include a plurality of pixel circuits, pixel electrodes, and common electrodes, and the peripheral area may include, for example, a gate driver on array (GOA).

[0136] Figure 3 is a partially enlarged plan view of the array substrate within the display area AA. Figure 4 is a cross-sectional structural diagram of the array substrate within the display area AA. In some embodiments, referring to Figures 3 and 4, the array substrate 100 includes a base substrate 110, a signal line DL, a first insulating layer BUF, an active layer ACT, and a first via V1.

[0137] For example, the base substrate 110 can be a transparent substrate, such as a glass substrate. This allows light emitted by the backlight source to pass through the base substrate 110, thereby improving the light transmittance of the array substrate 100. Signal lines DL are disposed on the base substrate 110 and can be data signal lines configured to transmit data signals. Of course, in other embodiments, the signal lines can also be used to transmit other signals, as long as the same technical principles are employed.

[0138] The first insulating layer BUF is disposed on a side of the signal line DL away from the base substrate 110. The first insulating layer BUF may include an insulating material and may be used to cover at least a portion of the signal line DL to prevent the signal line DL from short-circuiting with a conductive structure (such as a gate line GL) disposed above the signal line DL.

[0139] The active layer ACT is located on a side of the first insulating layer BUF away from the base substrate 110. By way of example, the active layer ACT includes a plurality of active layer patterns, each of which is configured to form a thin film transistor (TFT). In other words, a thin film transistor may include one active layer pattern. FIG3 and FIG4 both exemplarily illustrate one thin film transistor and one active layer pattern.

[0140] The active layer ACT may include a first portion 31, a second portion 32, and a channel structure 33 located between the first portion 31 and the second portion 32. The channel structure 33 is configured to form a channel structure of a TFT, one of the first portion 31 and the second portion 32 is configured to form a source electrode (or a source connection region) of the TFT, and the other is configured to form a drain electrode (or a drain connection region) of the TFT.

[0141] The first via hole V1 penetrates at least the first insulating layer BUF and exposes at least a portion of the signal line DL to facilitate connecting the first portion 31 to the signal line DL. The first portion 31 is configured to be connected to the signal line DL through the first via hole V1 so that the signal line DL can transmit a signal to the first portion 31.

[0142] In related art, signal lines are typically located on the side of the active layer away from the substrate, that is, on the upper side of the active layer. This creates a small gap between the signal line and other electrodes or electrode traces, such as the common electrode (located on the side of the active layer away from the substrate), resulting in a large parasitic capacitance between the signal line and the common electrode. Furthermore, this parasitic capacitance, while limiting the array substrate's ability to increase pixel density and refresh rate, also increases the array substrate's power consumption.

[0143] In the array substrate 100 provided by the embodiment of the present disclosure, as shown in Figures 3 and 4, the signal line DL is arranged on the side of the active layer ACT close to the base substrate 110. This is beneficial to increasing the spacing between the signal line DL and the common electrode, thereby reducing the parasitic capacitance between the signal line DL and the common electrode, which is beneficial to improving the pixel density and refresh rate of the array substrate 100, and is beneficial to reducing the power consumption of the signal line DL, thereby reducing the overall power consumption of the array substrate 100.

[0144] In some embodiments, the material of the signal line DL may include a conductive material, and the conductive material may include a metal material, for example, one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and alloys thereof, or the signal line DL may be a metal stacked structure. For example, the signal line DL may include a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum-niobium-titanium (MoNb / Ti) stacked structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) stacked structure, a molybdenum-neodymium-copper stacked structure, a MoNb-copper-MoNb stacked structure, and an AlNb-molybdenum-AlNd stacked structure. Of course, the embodiments of the present disclosure are not limited thereto, and the signal line DL may also consider any other suitable metal or metal stacked structure. In addition, the thickness of the signal line DL may be 1000 angstroms (1 angstrom = 10 -10 For example, the thickness of the signal line DL may be 1000 angstroms, 2000 angstroms, 5500 angstroms or 10000 angstroms, etc., which will not be listed one by one in the embodiments of the present disclosure.

[0145] For example, the material of the first insulating layer BUF may include a silicon oxide compound (SiOx, x>0). In some embodiments, the value of x may be 1 or 2. The material of the first insulating layer BUF may also include a silicon nitride compound (SiNy, y>0). In some embodiments, the value of y may be 1-2, such as SiN and SiN1.33. The first insulating layer BUF may be a single layer or a stacked layer structure. In some embodiments, the first insulating layer BUF is a stacked layer structure including a silicon oxide compound and a silicon nitride compound. In addition, the thickness of the first insulating layer BUF may be 100 nm to 700 nm. For example, the thickness of the first insulating layer BUF may be 100 nm, 300 nm, 550 nm, or 700 nm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0146] In some embodiments, the active layer ACT includes a Hall mobility of 10-30 cm 2 In some embodiments, the active layer ACT includes a metal oxide material with a Hall mobility greater than or equal to 30 cm 2 / Vs metal oxide materials.

[0147] For example, the channel structure 33 may be manufactured using various suitable semiconductor materials and various suitable manufacturing methods. In other words, the material of the channel structure 33 may include at least one of various suitable semiconductor materials. In some embodiments, the semiconductor material includes M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents oxygen, and N represents nitrogen. In other words, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth-doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel structure 33 can be amorphous, partially crystalline, single crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0148] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the channel structure 33 includes indium gallium zinc oxide (IGZO).

[0149] In some embodiments, the second portion 32, the first portion 31, and the channel structure 33 may be an integral structure. In this case, the material of the second portion 32 and the first portion 31 is the same as the material of the channel structure 33, that is, the first portion 31, the second portion 32, and the channel structure 33 are located in the same layer and include the same material. Based on this, the conductive material used to manufacture the first portion 31 and the second portion 32 also includes M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen, and N represents nitrogen. That is, the material of the second portion 32 and the first portion 31 may be a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth-doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel structure 33 can be amorphous, partially crystalline, single crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0150] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The first portion 31 or the second portion 32 and the channel structure 33 may be made of the same material. In one example, the first portion 31 and the second portion 32 may be made of indium gallium zinc oxide (IGZO).

[0151] When the first portion 31, the second portion 32, and the channel structure 33 are an integral structure, and the materials of the channel structure 33, the first portion 31, and the second portion 32 all include M1OaNb, the first portion 31 and the second portion 32 differ from the channel structure 33 in that the first portion 31 and the second portion 32 are subjected to a process to make them more conductive. The conductivity of the channel structure 33 is different from the conductivity of the first portion 31 and the conductivity of the second portion 32.

[0152] For example, the channel structure 33 may include a semiconductor material, and the second portion 32 and the first portion 31 may include a doped semiconductor material. In this way, the second portion 32 and the first portion 31 may form a conductor, and the channel structure 33 may form a semiconductor.

[0153] In one example, when the materials of the channel structure 33, the first portion 31, and the second portion 32 all include M1OaNb, the M1OaNb in the first portion 31 and the second portion 32 undergo a light doping process (e.g., a light doping ion implantation process). In another example, when the materials of the channel structure 33, the first portion 31, and the second portion 32 include M1OaNb, the M1OaNb in the first portion 31 and the second portion 32 undergo an annealing process. In another example, when the materials of the channel structure 33, the first portion 31, or the second portion 32 include M1OaNb, the M1OaNb in the first portion 31 or the second portion 32 undergoes an oxide replenishment process. Exemplarily, a process in the range of about 1×10 15 atoms / cm 3 to about 1×10 20 atoms / cm 3 The doping concentration range is about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 , about 1×10 17 atoms / cm 3 to about 1×10 18 atoms / cm 3 , about 1×10 18 atoms / cm 3 to about 1×10 20 atoms / cm 3 , and about 1×10 19 atoms / cm 3 to about 1×10 20 atoms / cm 3 , to perform a light doping process. Exemplarily, the light doping process is performed using an N-type dopant to enhance conductivity. Examples of N-type dopants may include elements from Group VA of the periodic table, including but not limited to nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Protective gas elements such as argon (Ar), helium (He), and oxygen (O) may also be used to perform the light doping process.

[0154] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the first portion 31, the second portion 32, and the channel structure 33 are formed as a result of one or more steps of the same patterning process performed on materials deposited in the same deposition process, the first portion 31, the second portion 32, and the channel structure 33 are located in the same layer. The term "same layer" does not always mean that the thickness or height of the layer in a cross-sectional view is the same.

[0155] In other embodiments, the first portion 31 and the second portion 32 may also be made of different materials from the channel structure 33. For example, various suitable conductive materials and various suitable manufacturing methods may be used to manufacture the first portion 31 or the second portion 32. Suitable conductive materials may include metals, alloys, metal oxides, and any combination thereof. For example, suitable conductive materials include, but are not limited to, molybdenum, aluminum, titanium, gold, copper, hafnium, tantalum, alloys (e.g., aluminum neodymium (AlNd), molybdenum niobium (MoNb)), and laminated materials, such as, molybdenum-neodymium-copper laminated structure, molybdenum-nickel-titanium (MTD) laminated structure, molybdenum-nickel-titanium-copper laminated structure, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium laminated structure, molybdenum-neodymium-copper laminated structure, molybdenum-aluminum-aluminum laminated structure, molybdenum-aluminum-molybdenum laminated structure, MoNb-copper-MoNb laminated structure, and AlNb-molybdenum-AlNd laminated structure. At this time, the first portion 31 , the second portion 32 and the channel structure 33 can be manufactured and formed separately in different steps.

[0156] In some embodiments, referring to FIG4 , the array substrate 100 further includes a light shielding member 23 located on the base substrate 110. Optionally, the light shielding member 23 is located on the same layer as the signal line SL. For example, the light shielding member 23 and the signal line SL are formed using the same mask and / or the same material in the same patterning process. The light shielding member 23 is configured to prevent light from irradiating the channel structure 33. Exemplarily, the orthographic projection of the light shielding member 23 on the base substrate 110 overlaps at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99% or 100%) with the orthographic projection of the channel structure 33 on the base substrate 110.

[0157] In one example, as shown in FIG3 , the orthographic projection of the light shading member 23 on the base substrate 110 completely covers the orthographic projection of the channel structure 33 on the base substrate 110, and at least part of the boundary of the orthographic projection of the light shading member 23 on the base substrate 110 does not overlap with the boundary of the orthographic projection of the channel structure 33 on the base substrate 110, that is, the area of ​​the light shading member 23 is larger than the area of ​​the channel structure 33, so that the light shading member 23 can block as much light as possible from being directed to the channel structure 33.

[0158] 4 , the array substrate 100 further includes a second insulating layer GI. The second insulating layer GI is located on a side of the active layer ACT away from the first insulating layer BUF. For example, the second insulating layer GI is located on a side of the first portion 31, the channel structure 33, and the second portion 32 away from the first insulating layer BUF.

[0159] The material of the second insulating layer GI may include an insulating material, and the insulating material may be, for example, silicon oxide. Of course, the second insulating layer GI is not limited thereto, and any other suitable material may be used. The second insulating layer GI may be a single-layer or multi-layer structure. In addition, the thickness of the second insulating layer GI may be 600 angstroms to 2000 angstroms. For example, the thickness of the second insulating layer GI may be 600 angstroms, 1000 angstroms, 1500 angstroms, or 2000 angstroms, etc., which will not be listed one by one in the embodiments of the present disclosure.

[0160] 3 and 4 , the array substrate 100 further includes a gate electrode 22 and a gate line GL. The gate electrode 22 and the gate line GL are both located on a side of the second insulating layer GI away from the channel structure 33 .

[0161] The material of the gate 22 may include a metal material. For example, the gate 22 may be a metal stacked structure. The metal stacked structure may refer to the metal stacked structure of the signal line DL mentioned above and will not be described in detail here. The material of the gate 22 may be the same as that of the signal line DL, or the material of the gate 22 may be different from that of the signal line DL. In addition, the thickness of the gate 22 may be 200 nm to 1200 nm. For example, the thickness of the gate 22 may be 200 nm, 500 nm, 950 nm or 1200 nm, etc. The embodiments of the present disclosure will not list them one by one.

[0162] The size of the gate 22 may define the area of ​​the channel structure 33. Exemplarily, the orthographic projection of the channel structure 33 on the base substrate 110 is within the range of the orthographic projection of the gate 22 on the base substrate 110. In other words, the portion of the active layer ACT where the orthographic projection of the active layer ACT on the base substrate 110 overlaps with the orthographic projection of the gate 22 on the base substrate 110 is the channel structure 33. The portion of the active layer ACT located on the side of the channel structure 33 close to the first via V1 is the first portion 31, and the portion of the active layer ACT located on the side of the channel structure 33 away from the first via V1 is the second portion 32.

[0163] The gate 22, first portion 31, second portion 32, and channel structure 33 together form a thin film transistor. One of the first portion 31 and second portion 32 forms the source of the thin film transistor (for example, the first portion 31 forms the source), and the other forms the drain of the thin film transistor (for example, the second portion 32 forms the drain). The channel structure 33 forms the channel of the thin film transistor, and the gate 22 forms the gate of the thin film transistor. The thin film transistor is turned on or off under the control of the gate 22. In other words, the channel structure 33 electrically connects the first portion 31 and the second portion 32 under the control of the gate 22 (the thin film transistor is turned on), or the channel structure 33 electrically isolates the first portion 31 and the second portion 32 under the control of the gate 22 (the thin film transistor is turned off).

[0164] The gate line GL is configured to provide a gate drive signal to the thin film transistor. In some embodiments, the gate line GL is interconnected with the gate 22. For example, the gate line GL and the gate 22 are located on the same layer and comprise the same material, and the gate line GL and the gate 22 are an integral structure. The gate 22 can be considered a branch structure extending outward (perpendicular to the gate line GL extension direction X) from the gate line GL.

[0165] In the embodiment of the present disclosure, the length direction (extension direction) of the gate line GL is a first direction Y, and the length direction (extension direction) of the signal line DL is a second direction X. The first direction Y and the second direction X intersect with each other. Exemplarily, the first direction Y and the second direction X are perpendicular to each other.

[0166] In some embodiments, along the extension direction of the length of the signal line DL (the second direction X), the ratio of the line width of the gate line GL to the line width of the light shielding member 23 is in the range of 0.3 to 0.9. For example, the ratio of the line width of the gate line GL to the line width of the light shielding member 23 is 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. The inventors of the present disclosure have found that, through such a layout, light shielding can be ensured, the aperture ratio in the array substrate can be maintained, and a short circuit between the gate line GL and the light shielding member 23 can be avoided.

[0167] In some embodiments, the first portion 31, the channel structure 33, and the second portion 32 are arranged substantially in a straight line. That is, the first portion 31, the channel structure 33, and the second portion 32 extend substantially in a straight line. This helps reduce the width of the thin film transistor, thereby reducing the area of ​​the black matrix on the counter substrate, and helps increase the aperture ratio of the array substrate, thereby increasing the pixel density of the array substrate.

[0168] It should be noted that the counter substrate may include a black matrix, the orthographic projection of which on the array substrate at least covers the thin film transistors. The black matrix can reduce ambient light incident on the thin film transistors, thereby reducing the reflection of ambient light by the thin film transistors and improving the display quality of the display panel.

[0169] In some embodiments, referring to FIG. 3 , the first portion 31, the channel structure 33, and the second portion 32 extend substantially along a first direction Y. That is, the arrangement direction of the first portion 31, the channel structure 33, and the second portion 32 is substantially parallel to the extension direction of the gate line GL, and the first portion 31, the channel structure 33, and the second portion 32 are disposed close to the gate line GL. This can significantly reduce the space occupied by the thin-film transistors and the gate line GL in the second direction X, and thus significantly reduce the area of ​​the black matrix on the opposing substrate, thereby improving the aperture ratio of the array substrate and, consequently, the pixel density of the array substrate.

[0170] Continuing to refer to Figures 3 and 5, the orthographic projection of the gate line GL on the substrate 110 partially overlaps with the orthographic projection of the signal line DL on the substrate 110. The gate line GL includes a first extension segment GL1 and a second extension segment GL2. The orthographic projection of the first extension segment GL1 on the substrate 110 does not overlap with the orthographic projection of the signal line DL on the substrate 110, and the orthographic projection of the second extension segment GL2 on the substrate 110 overlaps with the orthographic projection of the signal line DL on the substrate 110. In this way, the surface where the first extension segment GL1 and the second extension segment GL2 are located has a height difference. In other words, the connection position of the first extension segment GL1 and the second extension segment GL2 has an undulating morphology compared to the substrate. Along the second direction X, the dimension D1 of the first extension segment GL1 is smaller than the dimension D2 of the second extension segment. In this way, the risk of a sudden change in resistance or connection failure (such as breakage) at the connection position of the first extension segment GL1 and the second extension segment GL2 can be reduced, thereby improving the reliability of the gate line GL.

[0171] For example, as shown in FIG5 , the dimension of the first extension segment GL1 along the second direction X is D1, and the value range of D1 is 2μm to 6μm. The dimension of the second extension segment GL2 along the second direction X is D2, D2=D1+H, and the value range of H is 0.2μm to 1.5μm. In other words, the line width of the first extension segment GL1 is 2μm to 6μm, and the line width of the second extension segment GL2 is 0.2μm to 1.5μm wider than the line width of the first extension segment GL1. For example, as the line width of the first extension segment GL1 increases, the risk of the gate line GL breaking or suddenly changing in resistance at the junction of the first extension segment GL1 and the second extension segment GL2 decreases. Based on this, the value of H can decrease as the line width of the first extension segment GL1 increases.

[0172] Exemplarily, the line width of the first extension segment GL1 can be 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 6 μm. For example, to improve the pixel density and aperture ratio of the array substrate, the line width of the first extension segment GL1 can be 2 μm to 2.5 μm. Exemplarily, the value of H can be 0.2 μm, 0.5 μm, 1 μm, or 1.5 μm.

[0173] In some embodiments, the array substrate may further include a gate drive circuit located in the peripheral region and at least one second gate line for driving the gate drive circuit. The gate drive circuit may include multiple thin film transistors, and the second gate line is used to control the multiple thin film transistors of the gate drive circuit. Since the wiring space in the peripheral region is relatively large, the line width of the second gate line may be greater than the line width of the gate line. In other words, the line width of the second gate line located in the peripheral region is greater than the line width of the gate line located in the display area AA.

[0174] In some embodiments, along the length direction of the second gate line, the line width of the second gate line is uniform. In other words, in the area where the second gate line overlaps with the underlying signal line (the signal line located on the side of the second gate line close to the substrate), the second gate line is not widened. Alternatively, in some embodiments, along the length direction of the second gate line, at least part of the line width of the second gate line is wider than other parts. For example, the part where the second gate line overlaps with the underlying signal line (the signal line located on the side of the second gate line close to the substrate) is wider than the line width of other parts. Alternatively, no routing is provided on the side of the second gate line close to the substrate in the peripheral area.

[0175] In some embodiments, referring to Figures 3 and 4 , the array substrate 100 further includes a third insulating layer PVX1, a planarization layer PLN, a common electrode 24, a fourth insulating layer PVX2, a pixel electrode 25, and a second via V2. The third insulating layer PVX1 is located on the side of the gate electrode 22 away from the base substrate 110. The planarization layer PLN is located on the side of the third insulating layer PVX1 away from the base substrate 110. The common electrode 24 is located on the side of the planarization layer PLN away from the base substrate 110. The fourth insulating layer PVX2 is located on the side of the common electrode 24 away from the base substrate 110. The pixel electrode 25 is located on the side of the fourth insulating layer PVX2 away from the base substrate 110.

[0176] In some other embodiments, the array substrate may not include the planarization layer PLN, and the common electrode may be directly arranged on the third insulating layer. Alternatively, in some other embodiments, the pixel electrode 25 may also be located in the same layer as the active layer ACT and include the same material (not shown in the figure); in this case, the pixel electrode 25 and the second part 32 are an integrated structure, which is conducive to reducing the number of film layers of the array substrate, thinning the thickness of the array substrate, and reducing the preparation cost of the array substrate. Of course, the film layer structure and film layer sequence of the array substrate of the embodiment of the present disclosure are not limited to this, and it may be considered to include other suitable film layers or structures, or it may be considered to reduce at least one film layer or structure, as long as the same technical ideas are adopted. In the following embodiments of the present disclosure, the array substrate 100 including the film layer structure shown in Figure 4 is used as an example for exemplary description.

[0177] In some embodiments, when the array substrate 100 is a liquid crystal display array substrate, the pixel electrode 25 is a pixel electrode in each of the multiple sub-pixels in the liquid crystal display array substrate. The common electrode 24 is a common electrode in the liquid crystal display array substrate. In one example, the common electrode 24 is an electrode extending over the multiple sub-pixels in the liquid crystal display array substrate.

[0178] In some embodiments, when the array substrate is a light-emitting diode display array substrate, the pixel electrode 25 is the anode of each light-emitting diode in the light-emitting diode display array substrate. The common electrode 24 is the cathode in the light-emitting diode display array substrate. In one example, the common electrode is a cathode extending over multiple sub-pixels in the light-emitting diode display array substrate. In another example, the common electrode 24 is located on a side of the light-emitting layer and the pixel electrode PE away from the base substrate 110.

[0179] The second via hole V2 penetrates at least the third insulating layer PVX1 and the planarization layer PLN. For example, as shown in FIG4 , the second via hole V2 also penetrates the fourth insulating layer PVX2 and the third insulating layer GI. The orthographic projection of the second via hole V2 on the base substrate 110 at least partially overlaps with the orthographic projection of the second portion 32 on the base substrate 110, facilitating connection between the pixel electrode 25 and the second portion 32. The pixel electrode 25 extends into the second via hole V2 and is electrically connected to the second portion 32.

[0180] 4 , the second via hole V2 further penetrates the second insulating layer GI and the fourth insulating layer PVX2, and the second via hole V2 exposes at least a portion of the second portion 32. The pixel electrode 25 extends into the second via hole V2, and the pixel electrode 25 is in contact with and connected to the second portion 32 through the second via hole V2, that is, the pixel electrode 25 is directly connected to the second portion 32.

[0181] In other embodiments, as shown in FIG6 , the array substrate 100 further includes a transfer electrode 26. The transfer electrode 26 is located between the active layer ACT and the third insulating layer PVX1 and is electrically connected to the second portion 32. The second via hole V2 also penetrates the fourth insulating layer PVX2, exposing at least a portion of the transfer electrode 26. The pixel electrode 25 extends into the second via hole V2, and the pixel electrode 25 is in contact with and connected to the transfer electrode 26 through the second via hole V2. In other words, the pixel electrode 25 is electrically connected to the second portion 32 via the transfer electrode 26.

[0182] The transfer electrode 26 can be located in the same layer as the gate electrode 22 and the gate line GL and comprise the same material. That is, the transfer electrode 26, the gate electrode 22, and the gate line GL can be formed using the same mask and / or the same material in the same patterning process. The material and thickness of the transfer electrode 26 refer to the material and thickness of the gate electrode 22 described above and are not further described here.

[0183] Figures 7A to 7D can be viewed as partial enlarged views of the third insulating layer PVX1 and the planarization layer PLN in region S2 of Figure 3 , respectively. Referring to Figures 4 and 7A , in some embodiments, the second via hole V2 includes a first sub-hole V21 extending through the third insulating layer PVX1 and a second sub-hole V22 extending through the planarization layer PLN. The orthographic projection of the second sub-hole V22 on the base substrate 110 overlaps the orthographic projection of the first sub-hole V21 on the base substrate 110, and the center Q1 of the orthographic projection of the second sub-hole V22 on the base substrate is spaced from the center Q2 of the orthographic projection of the first sub-hole V21 on the base substrate 110. In other words, the first sub-hole V21 and the second sub-hole V22 are arranged non-centrosymmetrically. This helps reduce the overall area of ​​the orthographic projection of the second via hole V2 on the base substrate 110, and the area of ​​the black matrix on the opposing substrate (the orthographic projection of the black matrix on the array substrate needs to overlap the second via hole to prevent light leakage), thereby improving the aperture ratio of the array substrate.

[0184] Exemplarily, the first sub-hole V21 and the second sub-hole V22 can be formed by using two steps in manufacturing the third insulating layer PVX1 and the planarization layer PLN, respectively. For example, the method for preparing the array substrate may include forming an entire layer of the third insulating layer PVX1, patterning the entire layer of the third insulating layer PVX1 to form the first sub-hole V21, forming an entire layer of the planarization layer PLN on a side of the third insulating layer PVX1 away from the base substrate, patterning the entire layer of the planarization layer PLN to form the second sub-hole V22, wherein the second sub-hole V22 exposes the first sub-hole V21.

[0185] In some embodiments, referring to FIG3 and FIG7A , the center Q2 of the orthographic projection of the second sub-hole V22 on the base substrate 110 is spaced apart from the center Q1 of the orthographic projection of the first sub-hole V21 on the base substrate 110 along the first direction Y. In other words, the center Q2 of the second sub-hole V22 and the center Q1 of the first sub-hole V21 are staggered along the square extending from the gate line GL, thereby greatly improving the aperture ratio of the array substrate.

[0186] It should be noted that the orthographic projection of the black matrix on the array substrate covers the gate line. Based on this, the orthographic projection of at least part of the black matrix on the array substrate passes through the array substrate along the first direction Y, and the center Q2 of the second sub-hole V22 and the center Q1 of the first sub-hole V21 are staggered along the square extending along the gate line GL. The size of the black matrix in the second direction X can be reduced without increasing the size of the black matrix in the first direction Y, which can greatly reduce the area of ​​the black matrix and thereby improve the aperture ratio of the array substrate.

[0187] In one example, as shown in FIG7A , the first sub-hole V21 may be completely within the range of the second sub-hole V22 . Alternatively, in other examples, referring to FIG7B , the first sub-hole V21 may be partially within the range of the second sub-hole V22 and partially outside the range of the second sub-hole V22 .

[0188] In other embodiments, referring to FIG7C and FIG8A , the boundary of the orthographic projection of the second sub-hole V22 on the base substrate 110 substantially coincides with the boundary of the orthographic projection of the first sub-hole V21 on the base substrate 110, and the center Q2 of the orthographic projection of the second sub-hole V22 on the base substrate 110 substantially coincides with the center Q1 of the orthographic projection of the first sub-hole V21 on the base substrate 110. In this way, the second sub-hole V22 and the first sub-hole V21 can be simultaneously formed using a single etching process, i.e., the masks of the second sub-hole V22 and the first sub-hole V21 are merged, which helps to simplify the array substrate manufacturing process and improve the array substrate manufacturing efficiency.

[0189] For example, the first sub-hole V21 and the second sub-hole V22 can be simultaneously formed in the same process during the manufacturing of the third insulating layer PVX1 and the planarization layer PLN. For example, the method for manufacturing the array substrate may include forming an entire layer of the third insulating layer PVX1, forming an entire layer of the planarization layer PLN on a side of the third insulating layer PVX1 away from the base substrate, and patterning the entire layer of the planarization layer PLN and the entire layer of the third insulating layer PVX1 to form the second sub-hole V22 and the first sub-hole V21.

[0190] In some embodiments, referring to Figures 7D and 8B , the array substrate 100 further includes a spacer 29. The spacer 29 is configured to support a spacer PS, which is a structure disposed between the array substrate and the opposing substrate to maintain a stable thickness of the liquid crystal layer. The spacer 29 is located on the side of the pixel electrode 25 away from the base substrate 110. The orthographic projection of the spacer 29 on the base substrate 110 at least partially overlaps with the orthographic projection of the second sub-aperture V2 on the base substrate 110. The second sub-aperture V2 is at least partially filled with the spacer 29.

[0191] In some embodiments, the material of the third insulating layer PVX1 may include one or more of silicon oxide, silicon oxynitride, and silicon nitride, or the third insulating layer PVX1 may include a stacked insulating layer structure. For example, the third insulating layer PVX1 includes a stacked silicon oxide and silicon oxynitride. Furthermore, the thickness of the third insulating layer PVX1 may be 200 nm to 400 nm. For example, the thickness of the third insulating layer PVX1 may be 200 nm, 300 nm, 350 nm, or 400 nm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0192] The material of the planarization layer PLN may include an organic insulating material, such as polyimide. Furthermore, the thickness of the planarization layer PLN may be 2 μm to 3 μm. For example, the thickness of the planarization layer PLN may be 2 μm, 2.5 μm, 2.8 μm, or 3 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0193] The common electrode 24 may be made of, for example, a transparent conductive material to allow light emitted from the backlight source to pass through the common electrode 24. The transparent conductive material may be, for example, at least one of IGZO and IZO. Furthermore, the common electrode 24 may have a thickness of 40 nm to 135 nm. For example, the thickness of the common electrode 24 may be 40 nm, 80 nm, 100 nm, or 135 nm, etc. These thicknesses are not listed in detail in the embodiments of the present disclosure.

[0194] The material of the pixel electrode 25 may include, for example, a transparent conductive material so that light emitted from the backlight source can pass through the pixel electrode 25. The transparent conductive material may be, for example, at least one of ITO and IZO. In addition, the thickness of the common electrode 24 may be 40 nm to 135 nm. For example, the thickness of the common electrode 24 may be 40 nm, 80 nm, 100 nm, or 135 nm, etc., which are not listed in detail in the embodiments of the present disclosure. The materials of the common electrode 24 and the pixel electrode 25 may be the same or different, and the thicknesses of the common electrode 24 and the pixel electrode 25 may be the same or different.

[0195] The material of the fourth insulating layer PVX2 refers to the material of the third insulating layer PVX1 and is not repeated here.

[0196] 4 , 6 , 8A and 8B , the second insulating layer GI extends substantially over the entire array substrate 100. For example, an orthographic projection of the second insulating layer GI on the base substrate 110 at least partially does not overlap with an orthographic projection of the gate electrode 22 and the gate line GL on the base substrate 110.

[0197] 8C and 8D , the second insulating layer GI does not substantially extend over the entire array substrate 100. For example, the orthographic projection of the second insulating layer GI on the base substrate 110 substantially overlaps with the projections of the gate 22 and the gate line GL on the base substrate 110.

[0198] In some embodiments, referring to Figures 3, 4, 6, and 8A to 8D, the array substrate 100 further includes a connecting electrode 21, which is located on a side of the active layer ACT away from the base substrate 110. In this case, the first via V1 also penetrates the second insulating layer GI. At least a portion of the connecting electrode 21 is located within the first via V1, and the orthographic projection of the connecting electrode 21 on the base substrate 110 at least partially overlaps with the orthographic projection of the first portion 31 on the base substrate 110, and at least partially overlaps with the orthographic projection of the signal line DL on the base substrate 110. Based on this, the connecting electrode 21 can be electrically connected to the signal line DL and the first portion 31, respectively, thereby electrically connecting the signal line DL and the first portion 31. In other words, the first portion 31 is configured to be electrically connected to the signal line DL via the connecting electrode 21, and the first portion 31 is indirectly electrically connected to the signal line DL via the connecting electrode 21.

[0199] In some embodiments, the connecting electrode 21 can be located on the same layer and comprise the same material as the gate 22. For example, the connecting electrode 21 and the gate 22 can be formed using the same mask and / or the same material in the same patterning process. Compared to separately forming the connecting electrode 21, the connecting electrode 21 can be located on the same layer and comprise the same material as the gate 22, which helps simplify the array substrate manufacturing process. The material and thickness of the connecting electrode 21 refer to the material and thickness of the gate 22 above and are not further described here.

[0200] In some embodiments, as shown in Figures 3, 4, 6, and 8A, the orthographic projection of the first portion 31 on the substrate 110 partially overlaps with the orthographic projection of the signal line DL on the substrate. For example, the orthographic projection of the end of the first portion 31 away from the channel structure 33 (the left end in the figure) on the substrate 110 is within the orthographic projection of the signal line DL on the substrate. Furthermore, within the first via V21, at least a portion of the orthographic projection of the signal line DL on the substrate 110 does not overlap with the orthographic projection of the first portion 31 on the substrate. That is, the first via V1 at least exposes a portion of the signal line DL.

[0201] 8A and 8B , in some embodiments, when the second insulating layer GI substantially extends over the entire array substrate 100 , in the first via hole V1 , the orthographic projection of the connecting electrode 21 on the base substrate does not overlap with the orthographic projection of the second insulating layer GI on the base substrate.

[0202] Of course, in other embodiments, when the connecting electrode 21 covers the entire first via hole V1 and at least partially exceeds the range of the first via hole V1 (for example, Figures 10D and 11B), outside the range of the first via hole V1, the orthographic projection of the connecting electrode 21 on the base substrate may also partially overlap with the orthographic projection of the second insulating layer GI on the base substrate.

[0203] In other embodiments, referring to FIG8C and FIG8D , when the second insulating layer GI does not substantially extend over the entire array substrate 100, within the first via hole V1, referring to FIG8C , the orthographic projection of the connecting electrode 21 on the base substrate does not overlap with the orthographic projection of the second insulating layer GI on the base substrate. Alternatively, referring to FIG8D , the orthographic projection of the connecting electrode 21 on the base substrate partially overlaps with the orthographic projection of the second insulating layer GI on the base substrate.

[0204] For example, when the second insulating layer GI does not substantially extend over the entire array substrate 100, the array substrate preparation process may include forming an entire second insulating layer GI, patterning the entire second insulating layer GI to expose at least a portion of the signal line DL, and preparing the connecting electrode 21. In this case, the connecting electrode may not overlap with the second insulating layer GI (forming the structure shown in FIG8C ), or the connecting electrode may partially overlap with the second insulating layer GI outside the range of the first via hole V1 (forming the structure shown in FIG8D ).

[0205] In any of the following embodiments of the present disclosure, the second insulating layer GI shown in the figure substantially extends over the entire array substrate 100, or the second insulating layer GI substantially does not extend over the entire array substrate 100. This is for illustrative purposes only and does not constitute a limitation of the present application. Furthermore, based on the illustrated structure, whether the second insulating layer GI extends over the entire array substrate can be arbitrarily determined as needed.

[0206] Referring to FIG9 , which is a partial enlarged view of the area where the first via V1 is located, in some embodiments, the array substrate 100 includes a first connection region Z defined by the first via V1. The first connection region Z includes a first region Z1, a second region Z2, and a third region Z3 that are sequentially connected in a direction away from the channel structure 33.

[0207] As shown in Figure 9, the orthographic projection of the first region Z1 on the substrate 110 partially overlaps with the orthographic projection of the first portion 31 on the substrate 110, but does not overlap with the orthographic projection of the signal line DL on the substrate 110. The orthographic projection of the second region Z2 on the substrate 110 partially overlaps with the orthographic projection of the first portion 31 on the substrate 110 and is located within the orthographic projection of the signal line DL on the substrate 110. The orthographic projection of the third region Z3 on the substrate 110 is located outside the orthographic projection of the first portion 31 on the substrate 110 and at least partially overlaps with the orthographic projection of the signal line DL on the substrate 110. That is, along the first direction Y, the boundary of the first region Z1 overlaps with the boundary of the first via V1, and its lower boundary overlaps with the upper boundary of the signal line DL. The upper boundary of the second region Z2 overlaps with the upper boundary of the signal line DL, and its lower boundary overlaps with the lower boundary of the first portion 31. The upper boundary of the third zone Z3 coincides with the lower boundary of the first portion 31 , and the lower boundary of the third zone Z3 coincides with the lower boundary of the first via hole V1 .

[0208] In some embodiments, the connection electrode 21 covers at least a portion of the second zone Z2 and the third zone Z3 , so that the connection electrode 21 can be connected to the first portion 31 and the signal line DL, respectively.

[0209] In some embodiments, referring to FIG. 10A to FIG. 10D , a lower boundary of an orthographic projection of the first via hole V1 on the base substrate 110 is located outside a range of an orthographic projection of the signal line DL on the base substrate 110 .

[0210] As shown in Figures 10A and 11A, Figure 11A can be viewed as a cross-sectional structural diagram along section line A-A2 in Figure 10A. In the first connection region Z, the connection electrode 21 covers the second region Z2, a portion of the third region Z3 adjacent to the second region Z2, and a portion of the first region Z1 adjacent to the second region Z2. The connection electrode 21 also exposes a portion of the third region Z3 distal to the second region Z2, and a portion of the first region Z1 distal to the second region Z2.

[0211] Continuing with Figures 10A and 11A , in a cross-section (the cross-section shown in Figure 11A ) taken along a plane perpendicular to the base substrate 110 and the direction (X) extending along the signal line, and intersecting the signal line DL and the first via V1, at least a portion of the upper surface of the signal line DL and at least one of the two side surfaces connecting the upper and lower surfaces of the signal line DL are not exposed in the first via. The lower surface refers to the surface of the signal line DL that contacts the base substrate 110.

[0212] Referring to FIG. 11A , in the cross-section shown in FIG. 11A , only the upper surface of the middle portion of the signal line DL is covered by the first portion or connection electrode 21. The upper surface of the portion of the signal line DL away from the channel structure 33 (the left portion) is covered by a third insulating layer (not shown), while the upper surface of the portion of the signal line DL near the channel structure 33 is covered by the first insulating layer BUF. Furthermore, one side surface (the right side surface) connecting the upper and lower surfaces of the signal line DL is covered by the first insulating layer BUF, and the other side surface is covered by the third insulating layer.

[0213] In some embodiments, as shown in FIG10B , in the first connection region Z, the connection electrode 21 covers the second region Z2 and a portion of the third region Z3 close to the second region Z2 , and the connection electrode 21 exposes a portion of the third region Z3 away from the second region Z2 and the first region Z1 .

[0214] In some embodiments, as shown in FIG10C , in the first connection region Z, the connection electrode 21 covers the second area Z2 , a portion of the third area Z3 close to the second area Z2 , and the first area Z1 , and the connection electrode 21 exposes a portion of the third area Z3 away from the second area Z2 .

[0215] As shown in Figures 10B and 10C , when the connection electrode 21 exposes a portion of the third region Z3 away from the second region Z2, in a cross-section along a plane perpendicular to the substrate 110 and perpendicular to the direction (X) extending the length of the signal line and intersecting the signal line DL and the first via V1 (as shown in the cross-section of Figure 11A ), only the upper surface of the middle portion of the signal line DL is covered by the first portion or the connection electrode 21, and the upper surface of the portion of the signal line DL away from the channel structure 33 is covered by the third insulating layer (not shown in the figure), and the upper surface of the portion close to the channel structure 33 is covered by the first insulating layer BUF. Furthermore, one side surface (the right side surface) connecting the upper and lower surfaces of the signal line DL is covered by the first insulating layer BUF, and the other side surface is covered by the third insulating layer.

[0216] It should be noted that, in all embodiments of the present disclosure, when the array substrate 100 includes the connecting electrode 21, the description of “a certain surface of the signal line DL is covered by the first part 31 or the connecting electrode 21” means that a certain surface of the signal line DL is covered by the connecting electrode 21. When the array substrate 100 does not include the connecting electrode 21, and the first part 31 is directly connected to the signal line DL, the description of “a certain surface of the signal line DL is covered by the first part 31 or the connecting electrode 21” means that a certain surface of the signal line DL is covered by the first part 31. In other words, “a certain surface of the signal line DL is covered by the first part 31 or the connecting electrode 21” means that a certain surface of the signal line DL is covered by the first part 31 or the connecting electrode 21 that is in direct contact with it.

[0217] The “coverage” mentioned herein may refer to the spatial relationship between the film layers themselves, or the spatial relationship between the orthographic projections of the film layers on the substrate.

[0218] In some embodiments, as shown in Figures 10D and 10E , in the first connection zone Z, the connection electrode 21 covers the second area Z2, the third area Z3, and at least a portion of the first area Z1. For example, as shown in Figure 10D , the connection electrode 21 covers the entire first area Z1, or, as shown in Figure 10E , the connection electrode 21 covers a portion of the first area Z1.

[0219] Referring to FIG11B , when the orthographic projection of the first via hole V1 on the base substrate 110 is within the range of the orthographic projection of the signal line DL on the base substrate 110, and the connection electrode 21 covers the third region Z3, in a cross section (the cross section shown in FIG11B ) taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction (X) extending the length of the signal line and intersecting the signal line DL and the first via hole V1, the upper surface of the portion of the signal line DL away from the channel structure 33 is covered by the third insulating layer PVX1, and the upper surface of the portion of the signal line DL near the channel structure 33 is covered by the first insulating layer BUF. Furthermore, one side surface (the right side surface) connecting the upper and lower surfaces of the signal line DL is covered by the first insulating layer BUF, and the other side surface (the left side surface) is covered by the third insulating layer PVX1.

[0220] Referring to FIG11C , when at least a portion of the orthographic projection of the first via V1 on the base substrate 110 is located on a side of the orthographic projection of the signal line DL on the base substrate 110 that is away from the channel structure 33, and the connection electrode 21 covers the third region Z3, in a cross-section (the cross-section shown in FIG11C ) taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction (X) extending the length of the signal line and intersecting the signal line DL and the first via V1, the upper surface of the portion of the signal line DL away from the channel structure 33 (the portion of the upper surface away from the channel structure 33) is covered by the connection electrode 21, and the upper surface of the portion near the channel structure 33 is covered by the first insulating layer BUF. Furthermore, one side surface (the right side surface) connecting the upper and lower surfaces of the signal line DL is covered by the first insulating layer BUF, and the other side surface (the left side surface) is covered by the connection electrode 21.

[0221] 10E and 10F , the orthographic projection of the lower boundary of the first via hole V1 on the base substrate 110 is located within the range of the orthographic projection of the signal line DL on the base substrate 110 .

[0222] 10E , in the first connection region Z, the connection electrode 21 covers the second area Z2 , the third area Z3 , and a portion of the first area Z1 close to the second area Z2 , and the connection electrode 21 covers a portion of the first area Z1 away from the second area Z2 .

[0223] In some embodiments, referring to FIG. 10F , in the first connection zone Z, the connection electrode 21 covers the second area Z2 , the third area Z3 , and the first area Z1 .

[0224] In some embodiments, as shown in Figures 10E and 10F , when the orthographic projection of the lower boundary of the first via V1 on the base substrate 110 is within the orthographic projection of the signal line DL on the base substrate 110, and the connection electrode 21 covers the third region Z3, referring to Figure 11C , in a cross-section taken along a plane perpendicular to the base substrate 110 and the direction (X) extending along the signal line, and intersecting the signal line DL and the first via V1 (the cross-section shown in Figure 11C ), only the middle portion of the upper surface of the signal line DL is exposed in the first via V1, and both side surfaces connecting the upper and lower surfaces of the signal line DL are covered by the first insulating layer BUF. In this case, the portion of the upper surface of the signal line DL exposed by the first via V1 is covered by the connection electrode 21, while the portion of the upper surface not exposed by the first via V1 is covered by the first insulating layer BUF.

[0225] Figure 10G is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 11C can also be viewed as a cross-sectional view along Figure 10G. Referring to Figures 10G and 11C, in some embodiments, in a cross-section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (e.g., the cross-section shown in Figure 11C), at least a portion of the signal line DL is covered by the first insulating layer BUF, and at least a portion of the upper surface of the signal line DL is not exposed in the first via V1. For example, in the cross-section shown in Figure 11C, the first portion of the signal line DL is not covered by the first insulating layer BUF, and the second portion of the signal line DL is covered by the first insulating layer BUF. In the cross-section shown in Figure 11C, the upper surface of the first portion of the signal line DL is exposed by the first via V1, while the upper surface of the second portion of the signal line DL is not exposed in the first via V1. The first portion is located on the side of the second portion away from the channel structure 33.

[0226] In the cross section shown in FIG11C , the upper surface of the signal line DL is partially covered by the connection electrode 21 and partially covered by the first insulating layer BUF. In one example, in the cross section shown in FIG11C , the upper surface of a first portion of the signal line DL is covered by the connection electrode 21, while the upper surface of a second portion of the signal line DL is covered by the first insulating layer BUF. The first portion is located on a side of the second portion away from the channel structure 33.

[0227] 11B , the first side of the signal line DL is covered by the connection electrode 21 , and the second side of the signal line DL is covered by the first insulating layer BUF.

[0228] Referring to Figures 10G and 11C , in some embodiments, in a cross-section taken along a plane perpendicular to the base substrate 110 and perpendicular to the length of the signal line DL (the second direction X) and intersecting the signal line DL and the first via V1 (e.g., the cross-section shown in Figure 11C ), at least a portion of the signal line DL is covered by the first insulating layer BUF, and at least a portion of the upper surface of the signal line DL is not exposed in the first via V1. For example, in the cross-section shown in Figure 11C , the middle portion of the signal line DL is not covered by the first insulating layer BUF, while portions on both sides of the signal line DL are covered by the first insulating layer BUF. In the cross-section shown in Figure 11C , the upper surface of the middle portion of the signal line DL is exposed by the first via V1, while the upper surfaces of portions on both sides of the signal line DL are not exposed in the first via V1.

[0229] In the cross section shown in FIG11C , the upper surface of the signal line DL is partially covered by the connection electrode 21 and partially covered by the first insulating layer BUF. In one example, in the cross section shown in FIG11C , the upper surface of the middle portion of the signal line DL is covered by the connection electrode 21, while the upper surfaces of the two side portions of the signal line DL are covered by the first insulating layer BUF. In one example, in the cross section shown in FIG11C , both side surfaces of the signal line DL are covered by the first insulating layer BUF.

[0230] In some embodiments, referring to FIG. 10A to FIG. 10D and FIG. 10F , the maximum width of the connecting electrode 21 along the second direction X is greater than the maximum width of the first portion 31 along the second direction X.

[0231] In some other embodiments, referring to FIG. 10E and FIG. 10G , the maximum width of the connecting electrode 21 along the second direction X is less than or equal to the maximum width of the first portion 31 along the second direction X.

[0232] In some embodiments, referring to FIG10D , the connection electrode 21 intersects the signal line DL. The orthographic projection of the connection electrode 21 on the base substrate 110 intersects the orthographic projection of the signal line DL on the base substrate. For example, as shown in FIG10D , the maximum width of the connection electrode 21 along the first direction Y is greater than the maximum width of the first portion 31 along the first direction Y.

[0233] The connecting electrode 21 can be arranged in various positions relative to the first part 31, the signal line DL and the first via V1. Figures 10A to 10G, and Figures 12A to 12D show various arrangements of the connecting electrode 21 in the array substrate relative to adjacent components in some embodiments of the present disclosure. Among them, the orthographic projection of the connecting electrode 21 on the base substrate partially overlaps with the orthographic projection of the first part 31 on the base substrate, and partially overlaps with the orthographic projection of the signal line DL on the base substrate. The orthographic projection of the first via V1 on the base substrate partially overlaps with the orthographic projection of the first part 31 on the base substrate, and partially overlaps with the orthographic projection of the signal line DL on the base substrate. It can be understood that the embodiments of the present disclosure are not exhaustive, as long as the same technical ideas are adopted.

[0234] In some embodiments, referring to Figures 11A to 11C , in a first region Z1, the array substrate 100 includes at least a stacked first insulating layer BUF and a first portion 31. Furthermore, when the connecting electrode 21 covers at least a portion of the first region Z1, the first region Z1 further includes the connecting electrode 21 disposed on a side of the first portion 31 away from the base substrate 110. In a second region Z2, the array substrate 100 includes a stacked signal line DL, a first insulating layer BUF, a first portion 31, and a connecting electrode 21. In a third region Z3, the array substrate 100 includes at least a stacked signal line DL and a connecting electrode 21.

[0235] Based on the above-described stacked structure in the first region Z1, referring to Figures 11A to 11C, the signal line DL, the first insulating layer BUF, the first portion 31, and the connecting electrode 21 can form a raised structure in the second region Z2, compared to the first region Z1 and the third region Z3. In other words, referring to Figures 11A to 11C, the third insulating layer PVX1 covers the first connection region Z. The third insulating layer PVX1 includes a first surface 27 located on a side closer to the base substrate 110. The portion of the first surface 27 located in the second region Z2 protrudes toward the side (upper side) away from the base substrate 110, compared to the portion of the first surface 27 located in the first region Z1 and the third region Z3, forming a raised structure.

[0236] In some embodiments, referring to FIG10D , FIG11B and FIG13 , FIG13 can be considered as a structural diagram of the connecting electrode 21 and the first portion 31 in FIG11B . Part of the first portion 31 extends into the connecting electrode 21 .

[0237] For example, during the process of patterning the second insulating layer GI to form the first via 31, a portion of the first insulating layer BUF located on the side of the first portion 31 close to the base substrate 110 is removed, and the end of the first portion 31 away from the channel structure 33 forms a suspended structure. Then, during the process of preparing and forming the connecting electrode 21, the connecting electrode 21 fills the removed portion of the first insulating layer BUF, and the connecting electrode 21 covers the suspended portion of the first portion 31, forming a structure as shown in FIG13 , in which a portion of the first portion 31 extends into the connecting electrode 21.

[0238] In some embodiments, referring to FIG14 , the edge of the second region Z2 near the first region Z1 includes a plurality of irregular undulating structures, similar to the sawtooth structure 28. The first insulating layer BUF has an undulating structure at the boundary of the signal line DL, whereby at least one of the film layers roughly arranged in the second region Z2 near the first region Z1 includes a sawtooth structure 28. Exemplarily, the edge of the first portion 31 in the second region Z2 near the first region Z1 may be serrated, and / or the edge of the connecting electrode 21 in the second region Z2 near the first region Z1 may be serrated. It should be noted that FIG14 is only used to show the morphology of the serrated structure, and does not specifically refer to a certain film layer. For example, the serrated structure shown in FIG14 may be located on the first portion 31 and / or the connecting electrode 32.

[0239] In some embodiments, referring to Figures 4, 6, 8A, and 11A, when the connecting electrode 21 exposes at least a portion of the first region, that is, the connecting electrode 21 exposes at least a portion of the first portion 31 located within the first via hole V1. In this case, the first portion 31 includes a groove portion 311 that is recessed toward the side closer to the base substrate 110. The groove portion 311 is located in the first region, and the orthographic projection of the groove portion 311 on the base substrate 110 does not overlap with the orthographic projection of the connecting electrode 21 on the base substrate 110. In other words, the first portion 31 located within the first via hole V1 and exposed by the connecting electrode 21 forms the groove portion 311. For example, during the process of patterning the gate electrode 22 and the gate line GL, at least a portion of the first portion 31 within the first via hole V1 and exposed by the connecting electrode 21 may be removed, thereby forming the groove portion 311.

[0240] 15 , in some embodiments, the orthographic projection of the first portion 31 on the base substrate 110 does not overlap with the orthographic projection of the signal line DL on the base substrate 110. For example, the orthographic projection of the end of the first portion 31 away from the channel structure 33 (the left end in the figure) on the base substrate 110 is spaced apart from the orthographic projection of the signal line DL on the base substrate 110.

[0241] 15 and 16 , the array substrate 100 includes a first connection region Z defined by a first via hole V1 . The first connection region Z includes a fourth region Z4 and a fifth region Z5 sequentially connected in a direction away from the channel structure 33 .

[0242] The orthographic projection of the fourth region Z4 on the base substrate 110 at least partially overlaps with the orthographic projection of the first portion 31 on the base substrate 110, and does not overlap with the orthographic projection of the signal line DL on the base substrate 110. The orthographic projection of the fifth region Z5 on the base substrate 110 at least partially overlaps with the orthographic projection of the signal line DL on the base substrate 110, and does not overlap with the orthographic projection of the first portion 31 on the base substrate 110. Exemplarily, the fourth region Z4 and the fifth region Z5 are demarcated by the boundary of the signal line DL. That is, the lower boundary of the fourth region Z4 overlaps with the upper boundary of the signal line DL, and the upper boundary of the fifth region Z5 overlaps with the upper boundary of the signal line DL.

[0243] The connection electrode 21 covers at least a portion of the fourth zone Z4 and at least a portion of the fifth zone Z5 , so that the connection electrode 21 can be connected to the signal line DL and the connection electrode 21 respectively, thereby electrically connecting the signal line DL and the connection electrode 21 .

[0244] Exemplarily, referring to FIG. 15 and FIG. 16 , the connecting electrode 21 covers a portion of the fourth region Z4 and a portion of the fifth region Z5 , and exposes a portion of the fourth region Z4 and a portion of the fifth region Z5 .

[0245] In some embodiments, referring to FIG15 , the orthographic projection of the first via V1 on the base substrate, away from the boundary of the channel structure (the lower boundary in FIG15 ), is located within the signal line DL. Referring to FIG16 , in a cross-section taken along a plane perpendicular to the base substrate 110 and the direction (X) extending along the signal line and intersecting the signal line DL and the first via V1 (the cross-section shown in FIG16 ), at least a portion of the upper surface of the signal line DL and at least one of the two side surfaces connecting the upper and lower surfaces of the signal line DL are not exposed within the first via V1. The lower surface refers to the surface of the signal line DL that contacts the base substrate 110.

[0246] For example, as shown in FIG16 , the right side of the upper surface of the signal line DL is exposed in the first via hole V1, and the first side of the two side surfaces connecting the upper surface and the lower surface of the signal line DL is exposed in the first via hole V1. The left side of the upper surface of the signal line DL is not exposed in the first via hole V1, and the second side of the two side surfaces is not exposed in the first via hole V1. The first side surface is located on the side of the second side surface that is closer to the channel structure.

[0247] In some embodiments, as shown in FIG16 , in the cross section, the left side portion of the upper surface of the signal line DL and one of the two side surfaces connecting the upper surface and the lower surface of the signal line DL (the left side surface) are covered by the first insulating layer BUF. For example, as shown in FIG16 , only a portion of the upper surface of the signal line DL and one of the two side surfaces connecting the upper surface and the lower surface of the signal line (the right side surface) are covered by the connection electrode 21.

[0248] In some embodiments, as shown in Figures 15 and 16, the connection electrode 21 can cover a portion of the fifth region Z5 and expose a portion of the fifth region Z5. In this way, the connection electrode 21 can cover the portion of the upper surface of the signal line DL exposed in the first via hole V1, but does not cover the portion of the upper surface of the signal line DL exposed in the first via hole V1. For example, the portion of the upper surface of the signal line DL exposed in the first via hole V1 near the channel structure 33 is covered by the connection electrode 21, and the portion away from the channel structure 33 is covered by the first insulating layer BUF.

[0249] In some embodiments, referring to Figures 17 and 18, in a cross-section along a plane perpendicular to the base substrate 110 and perpendicular to the direction extending the length of the signal line (the second direction X) and intersecting the signal line DL and the first via V1 (the cross-section shown in Figure 18), the surface of the signal line DL except the lower surface is exposed in the first via V1; the lower surface refers to the surface of the signal line DL that contacts the base substrate 110.

[0250] In some embodiments, referring to Figures 17 and 18, the upper surface of the signal line DL and the two side surfaces respectively connecting the upper surface and the lower surface of the signal line are completely covered by the connection electrode 21. The connection electrode 21 can cover the fifth zone Z5, that is, the connection electrode 21 covers the portion of the signal line DL exposed by the first via V1. For example, in the cross-section shown in Figure 18, only a portion of the upper surface of the signal line DL and only one side surface (the right side surface) of the two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the connection electrode 21.

[0251] In some embodiments, referring to Figures 19 and 20, in a cross-section along a plane perpendicular to the base substrate 110 and perpendicular to the direction extending the length of the signal line (the second direction X) and intersecting the signal line DL and the first via V1 (the cross-section shown in Figure 20), the surface of the signal line DL except the lower surface is exposed in the first via V1; the lower surface refers to the surface of the signal line DL that contacts the base substrate 110.

[0252] In some embodiments, the connecting electrode 21 may cover a portion of the fifth region Z5 and expose a portion of the fifth region Z5, so that the connecting electrode 21 may cover a portion of the surface of the signal line DL exposed in the first via hole V1 and not cover the portion of the surface of the signal line DL exposed in the first via hole V1.

[0253] For example, in the cross-section shown in FIG20 , the surfaces of the signal lines DL are exposed within the first vias V1. The portion of the upper surface of the signal line DL near the channel structure 33 is covered by the connection electrode 21, while the portion away from the channel structure 33 is covered by the third insulating layer PVX1. Of the two side surfaces connecting the upper and lower surfaces of the signal line, one side (the right side) is covered by the connection electrode 21, while the other side (the left side) is covered by the third insulating layer PVX1.

[0254] In the embodiments of the present disclosure, as shown in Figures 15, 17 and 19, the connecting electrode 21 and the first via V1 can be arranged at various positions relative to the signal line DL and the first part 31. Of course, the embodiments of the present disclosure are not limited to this, and any other suitable arrangement positions can be considered as long as the same technical concept is adopted.

[0255] In some embodiments, referring to Figures 16 and 18, the connecting electrode 21 exposes at least a portion of the fourth region Z4. The first portion 31 includes a groove portion 311 that is recessed toward the side closest to the base substrate 110. The groove portion 311 is located in the fourth region Z4, and the orthographic projection of the groove portion 311 on the base substrate 110 does not overlap with the orthographic projection of the connecting electrode 21 on the base substrate 110. In other words, the first portion 31 located within the first via hole V1 and exposed by the connecting electrode 21 forms the groove portion 311. For example, during the process of patterning the gate 22 and the gate line GL, at least a portion of the first portion 31 within the first via hole V1 and exposed by the connecting electrode 21 may be removed, thereby forming the groove portion 311.

[0256] Of course, in some other embodiments, referring to FIG. 20 , when the connecting electrode 21 exposes at least a portion of the fourth region Z4 , the first portion 31 may not form the groove 311 .

[0257] 16 , 18 and 20 , in the fourth region Z4 , the array substrate 100 includes a stacked first insulating layer BUF, a first portion 31 and a connection electrode 21 . In the fifth region Z5 , the array substrate 100 includes a stacked signal line DL and a connection electrode 21 .

[0258] Continuing with Figures 16, 18, and 20, the connecting electrode 21 comprises a stepped structure. The stepped structure includes a first step 211 located in the fourth zone Z4 and a second step 212 located in the fifth zone Z5. The first step 211 is further away from the base substrate 110 than the second step 212. In other words, the distance between the connecting electrode 21 and the base substrate 110 in the fourth zone Z4 is greater than the distance between the connecting electrode 21 and the base substrate 110 in the fifth zone Z5. Consequently, the stepped structure is formed at the boundary between the fourth zone Z4 and the fifth zone Z5.

[0259] Figure 21A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 22A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 22A can be viewed as a cross-sectional view along section line B-B1 in Figure 21A.

[0260] In other embodiments, referring to Figures 21A and 22A, the first via hole V1 only penetrates the first insulating layer BUF, at least a portion of the first portion 31 is located within the first via hole V1, and the first portion 31 is in contact with and connected to the signal line DL through the first via hole BV1. In other words, the array substrate does not include the connecting electrode 21, and the first portion 31 is directly electrically connected to the signal line DL.

[0261] In some embodiments, referring to Figures 21A and 22A , when the first portion 31 is directly electrically connected to the signal line DL, in a cross-section taken along a plane perpendicular to the base substrate 110 and extending perpendicular to the length of the signal line DL (second direction Y) and intersecting the signal line DL and the first via V1 (e.g., the cross-section shown in Figure 7A ), all surfaces of the signal line DL, except for the surface in contact with the base substrate 110, are exposed in the first via V1. For example, in the cross-section, the upper surface of the signal line DL and two side surfaces connecting the upper and lower surfaces of the signal line DL, respectively, are completely exposed in the first via V1. The lower surface is the surface of the signal line DL in contact with the base substrate 110.

[0262] 21A and 22A , in a cross section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (e.g., the cross section shown in FIG22A ), the surface of the signal line DL, except for the surface in contact with the base substrate 110, is covered by the first portion 31. For example, in the cross section shown in FIG22A , the upper surface of the signal line DL and the two side surfaces connecting the upper surface and the lower surface of the signal line DL are completely covered by the first portion 31.

[0263] 21A , in some embodiments, the first portion 31 intersects the signal line DL. The orthographic projection of the first portion 31 on the substrate intersects the orthographic projection of the signal line DL on the substrate.

[0264] Figure 21B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 22B is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 22B may be a cross-sectional view along section line B-B2 in Figure 21B.

[0265] Referring to Figures 21B and 22B , in some embodiments, the array substrate 100 includes a first via hole V1 extending through the first insulating layer BUF. A portion of the first portion 31 extends into the first via hole V1 and connects to the signal line DL. Exemplarily, the first portion 31 extends through the first via hole V1 to connect to the signal line DL.

[0266] In some embodiments, referring to Figures 21B and 22B , in a cross section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (such as the cross section shown in Figure 22B ), the surface of the signal line DL, except for the surface in contact with the base substrate 110, is exposed in the first via V1. For example, in the cross section shown in Figure 22B , the upper surface of the signal line DL and the two side surfaces respectively connecting the upper surface and the lower surface of the signal line DL are completely exposed in the first via V1.

[0267] 21B and 22B , in some embodiments, in a cross section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (the cross section shown in FIG22B ), the surface of the signal line DL other than the surface in contact with the base substrate 110 is only partially covered by the first portion 31. For example, in the cross section shown in FIG22B , only a portion of the upper surface of the signal line DL and only one of the two side surfaces connecting the upper surface and the lower surface of the signal line DL are covered by the first portion 31.

[0268] In some embodiments, referring to FIG. 21B , only a portion of the orthographic projection of the end portion of the first portion 31 along the first direction Y on the substrate is within the range of the orthographic projection of the signal line DL on the substrate, for example, the lower end portion of the first portion 31 does not extend beyond the edge of the signal line DL.

[0269] Referring to Figures 21A and 21B , in some embodiments, the orthographic projection of the first portion 31 on the base substrate only partially overlaps with the orthographic projection of the first via V1 on the base substrate. For example, in the orthographic projections of the first portion 31 and the first via V1 on the base substrate, a portion of the first portion 31 is located within V1, and at least a portion of the first via V1 is not filled by the first portion 31.

[0270] Referring to FIG. 21A , in some embodiments, the orthographic projection of the first portion 31 on the substrate coincides with the orthographic projection of the middle portion of the first via V1 on the substrate, but does not coincide with the orthographic projection of the upper portion of the first via V1 on the substrate, nor does it coincide with the orthographic projection of the lower portion of the first via V1 on the substrate. The upper portion, the middle portion, and the lower portion are arranged sequentially along the length direction Y of the signal line DL.

[0271] Figure 21C is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 22A can also be viewed as a cross-sectional view taken along section line B-B3 in Figure 21C. Referring to Figures 21C and 22A, in some embodiments, the orthographic projection of the first portion 31 on the base substrate 110 completely covers the orthographic projection of the first via V1 on the base substrate 110.

[0272] FIG21D is a plan view of an array substrate according to some embodiments of the present disclosure. FIG22A can also be viewed as a cross-sectional view along section line B-B4 in FIG21D . Referring to FIG21D and FIG22A , in some embodiments, the orthographic projection of the first portion 31 on the base substrate 110 coincides with the orthographic projection of the upper portion of the first via V1 (the portion away from the channel structure 33) on the base substrate 110, and does not coincide with the orthographic projection of the lower portion of the first via V1 (the portion close to the channel structure 33) on the base substrate 110. The upper portion and the lower portion are arranged sequentially along the length direction Y of the gate line GL.

[0273] Figure 21E is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 22A can also be viewed as a cross-sectional view along section line B-B5 in Figure 21E. Referring to Figures 21E and 22A, in some embodiments, the orthographic projection of the first portion 31 on the base substrate 110 coincides with the orthographic projection of the lower portion of the first via V1 (the portion away from the channel structure 33) on the base substrate, and does not coincide with the orthographic projection of the upper portion of the first via V1 (the portion close to the channel structure 33) on the base substrate. The upper portion and the lower portion are arranged sequentially along the length direction Y of the signal line DL.

[0274] Referring to Figures 21A to 21E, in some embodiments, the array substrate 100 further includes a gate line GL. In some embodiments, the gate line GL is configured to provide a gate drive signal to the thin film transistor. In some embodiments, the gate line GL is interconnected with the gate 22. Exemplarily, the gate line GL and the gate 22 are located on the same layer and include the same material, and the gate line GL and the gate 22 are an integral structure. The gate 22 can be viewed as a branch structure extending outward (perpendicular to the gate line GL extension direction X) from the gate line GL.

[0275] In some embodiments, referring to Figures 22A and 22B , the array substrate 100 further includes a light shielding member 23 located on the base substrate 110 and a gate line GL located on a side of the light shielding member 23 away from the base substrate 110. Referring to Figures 21A to 21E , along the direction X extending along the length of the signal line DL, the ratio of the line width of the gate line GL to the line width of the light shielding member 23 is in a range of 0.3 to 0.9. Exemplarily, the ratio of the line width of the gate line GL to the line width of the light shielding member 23 is 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. The inventors of the present disclosure have discovered that, through this layout, light shielding can be ensured, the aperture ratio in the array substrate can be maintained, and short circuits between the gate line GL and the light shielding member 23 can be avoided.

[0276] Figure 23A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 23B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 24 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 24 may be a cross-sectional view taken along section line CC in Figure 23A or along section line CC in Figure 23B.

[0277] Referring to Figures 23A, 23B, and 24, in some embodiments, in a cross-section taken along a plane perpendicular to the substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (e.g., the cross-section shown in Figure 24), at least a portion of the signal line DL is covered by the first insulating layer BUF, and at least a portion of the upper surface of the signal line DL is not exposed in the first via V1. For example, in the cross-section shown in Figure 24, the first portion of the signal line DL is covered by the first insulating layer BUF, while the second portion of the signal line DL is not covered by the first insulating layer BUF. In the cross-section shown in Figure 24, the upper surface of the first portion of the signal line DL is not exposed in the first via V1, while the upper surface of the second portion of the signal line DL is exposed by the first via V1. The first portion is located on the side of the second portion away from the channel structure 33 (the left side).

[0278] 23A, 23B, and 24, in some embodiments, in a cross section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (e.g., the cross section shown in FIG24), the surface of the signal line DL other than the surface in contact with the base substrate 110 is only partially covered by the first portion 31. For example, in the cross section shown in FIG24, only a portion of the upper surface of the signal line DL and only one of the two side surfaces connecting the upper and lower surfaces of the signal line DL are covered by the first portion 31.

[0279] Fig. 25 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig. 26 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0280] Referring to Figures 25 and 26 , in some embodiments, in a cross-section taken along a plane perpendicular to the substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (as shown in the cross-section in Figure 26 ), at least a portion of the signal line DL is covered by the first insulating layer BUF, and at least a portion of the upper surface of the signal line DL is not exposed in the first via V1. For example, in the cross-section shown in Figure 26 , the first portion of the signal line DL is not covered by the first insulating layer BUF, while the second portion of the signal line DL is covered by the first insulating layer BUF. In the cross-section shown in Figure 26 , the upper surface of the first portion of the signal line DL is exposed by the first via V1, while the upper surface of the second portion of the signal line DL is not exposed in the first via V1. The first portion is located on the side of the second portion away from the channel structure 33.

[0281] In some embodiments, referring to Figures 25 and 26 , in a cross-section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (such as the cross-section shown in Figure 26 ), the surface of the signal line DL, except for the surface in contact with the base substrate 110, is only partially covered by the first portion 31. For example, in the cross-section shown in Figure 26 , only a portion of the upper surface of the signal line DL and only one of the two side surfaces connecting the upper and lower surfaces of the signal line DL are covered by the first portion 31. The lower surface is the surface of the signal line DL in contact with the base substrate 110.

[0282] Figure 27 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 28 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 28 may be a cross-sectional view along section line EE in Figure 27 .

[0283] 27 and 28 , in some embodiments, in a cross-section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending along the length of the signal line DL and intersecting the signal line DL and the first via V1 (e.g., the cross-section shown in FIG28 ), at least a portion of the signal line DL is covered by the first insulating layer BUF, and at least a portion of the upper surface of the signal line DL is not exposed in the first via V1. For example, in the cross-section shown in FIG28 , the central portion of the signal line DL is not covered by the first insulating layer BUF, while portions on both sides of the signal line DL are covered by the first insulating layer BUF. In the cross-section shown in FIG28 , the upper surface of the central portion of the signal line DL is exposed by the first via V1, while the upper surfaces of portions on both sides of the signal line DL are not exposed in the first via V1.

[0284] In some embodiments, referring to Figures 27 and 28 , in a cross-section taken along a plane perpendicular to the base substrate 110 and perpendicular to the direction Y extending the length of the signal line DL and intersecting the signal line DL and the first via V1 (as shown in the cross-section of Figure 28 ), only the upper surface of a portion of the signal line DL is covered by the first portion 31. The upper surface of the remaining portion of the signal line DL and the two side surfaces connecting the upper and lower surfaces of the signal line DL are not covered by the first portion 31. The lower surface is the surface of the signal line DL that contacts the base substrate 110.

[0285] In some embodiments, the second insulating layer GI extends substantially over the entire array substrate, as shown in FIG. 21A to FIG. 21E , FIG. 22A, FIG. 22B, FIG. 23A, FIG. 23B, and FIG. 24 to FIG. 28 .

[0286] In some embodiments, the second insulating layer does not substantially extend across the entire array substrate. For example, the orthographic projection of the second insulating layer on the base substrate substantially overlaps with the orthographic projections of the gate electrode 22 and the gate line GL on the base substrate. Furthermore, the orthographic projection of the second insulating layer on the base substrate at least partially does not overlap with the orthographic projection of the signal line on the base substrate, and at least partially does not overlap with the orthographic projection of the first portion or the second portion on the base substrate.

[0287] FIG29A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. The structure shown in FIG29A is similar to the structure shown in FIG22A , but differs from the structure shown in FIG22A in that at least the second insulating layer GI does not substantially extend over the entire array substrate, as shown in FIG29A .

[0288] Figure 29B is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. The structure shown in Figure 29B is similar to the structure shown in Figure 22B, but differs from the structure shown in Figure 22B in that the second insulating layer GI does not substantially extend over the entire array substrate, as shown in Figure 29B.

[0289] FIG29C is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. The structure shown in FIG29C is similar to the structure shown in FIG24 , but differs from the structure shown in FIG24 in that at least the second insulating layer GI does not substantially extend over the entire array substrate, as shown in FIG29C .

[0290] Figure 29D is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. The structure shown in Figure 29D is similar to the structure shown in Figure 26, but differs from the structure shown in Figure 26 in that at least the second insulating layer GI does not substantially extend over the entire array substrate, as shown in Figure 29D.

[0291] In some embodiments, in the peripheral area of ​​the array substrate, the thin film transistor (GOA-TFT) structure of the gate drive circuit, the source and drain of the GOA-TFT are located on the side of the semiconductor layer of the GOA-TFT away from the base substrate, and the source and drain of the GOA-TFT are overlapped with the electrode area of ​​the semiconductor layer by opening a second insulating layer, that is, the second insulating layer covers the semiconductor layer of the GOA-TFT, and the second insulating layer includes a third via hole, the third via hole passes through the second insulating layer, and the GOA-TFT is electrically connected to the semiconductor layer of the GOA-TFT through the third via hole.

[0292] In some embodiments, the second insulating layer may include a plurality of third vias. For example, the number of third vias connected to the source (or drain) may be multiple, and the plurality of third vias are spaced apart, and a protruding structure formed by at least part of the second insulating layer is included between adjacent third vias. The source is connected to the semiconductor layer of the GOA-TFT through a plurality of third vias. In other words, the source covers a plurality of third vias, and the source portions located in the plurality of third vias are arranged in parallel. The source also covers the second insulating layer between adjacent third vias, and the source also forms a protruding structure on the second insulating layer between the third vias. The drain can be arranged in the same manner as the source, and will not be described in detail here.

[0293] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a signal line on a base substrate; forming a first insulating layer on a side of the signal line away from the base substrate; forming an active layer on a side of the first insulating layer away from the base substrate; the active layer includes a first portion, a second portion, and a channel structure located between the first portion and the second portion; the first portion includes a first portion, and the second portion includes a second portion. Exemplarily, the method also includes forming a via extending at least through the first insulating layer; and the first portion is formed to extend through the via to connect to the signal line. Optionally, the material of at least a portion of the second portion and the first portion is the same as the material of the channel structure and is subjected to a process to make them conductive. The conductivity of the channel structure is different from the conductivity of the first portion and different from the conductivity of the second portion.

[0294] 30A to 30C illustrate a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0295] Referring to FIG30A , a signal line DL and a light shielding member 23 are formed on a substrate 110. A first insulating layer BUF is formed on the side of the signal line DL and the light shielding member 23 facing away from the substrate 110. A semiconductor material layer SML is formed on the side of the first insulating layer BUF facing away from the substrate 110. A second insulating layer GI is formed on the side of the semiconductor material layer SML facing away from the substrate 110. A photoresist layer PR is formed on the side of the second insulating layer GI facing away from the substrate 110. A lightly doped drain process is then performed to make the portions of the semiconductor material layer SML corresponding to the first and second portions more conductive. The orthographic projection of the photoresist layer PR on the substrate 110 overlaps with the orthographic projection of the portion of the semiconductor material layer SML corresponding to the channel structure on the substrate 110. After the lightly doped drain process, the portions of the semiconductor material layer SML corresponding to the first and second portions become more conductive.

[0296] Referring to FIG30B , the photoresist layer PR is removed, and a first via hole V1 is formed. The first via hole V1 extends through the second insulating layer GI and the first insulating layer BUF, exposing the upper surface of at least a portion of the signal line DL (e.g., the middle portion of the signal line DL shown in FIG30B ). A portion of the second insulating layer BUF located at the bottom of the first portion may be removed, allowing the end of the first portion to extend into the first via hole V1, forming a cantilever structure. In other words, the portion of the semiconductor material layer SML corresponding to the first portion extends into the first via hole V1.

[0297] 30C , electrode material is deposited and patterned to form a gate 22 and a connecting electrode 21. The connecting electrode 21 is electrically connected to the first portion 31 (a portion of the semiconductor material layer SML that has undergone the lightly doped drain process) and is at least partially located within the first via hole V1 and electrically connected to the signal line DL.

[0298] During the patterning of the electrode material, the area of ​​the first portion 31 located within the first via hole V1 and not covered by the connecting electrode 21 may be damaged, thereby forming a groove portion 311 on the surface of the first portion 31 away from the base substrate 110. The groove portion 311 is recessed toward the side closer to the base substrate 110 to form a groove, or in other words, the thickness of the groove portion 311 is less than the thickness of other portions of the first portion 31.

[0299] Figures 31A to 31C illustrate a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 31A to 31C illustrate a process of manufacturing an array substrate using a half-tone mask.

[0300] Referring to FIG31A , a signal line DL and a light shielding member 23 are formed on a substrate 110. A first insulating layer BUF is formed on the side of the signal line DL and light shielding member 23 facing away from the substrate 110. A semiconductor material layer SML is formed on the side of the first insulating layer BUF facing away from the substrate 110. A second insulating layer GI is formed on the side of the semiconductor material layer SML facing away from the substrate 110. A first photoresist layer PR1 is formed on the side of the second insulating layer GI facing away from the substrate 110. The first photoresist layer PR1 is exposed using a halftone mask and developed to form a photoresist pattern. The photoresist pattern includes a first portion corresponding to the first via hole and a second portion outside the first portion. The first portion includes a first region corresponding to the channel structure and a second region corresponding to the remaining portion of the first portion. The depth of the first region is greater than that of the second region. The photoresist material is removed from the second portion. The process also includes etching the second insulating layer GI and the first insulating layer BUF in the second portion to expose the upper surface of at least a portion of the signal line DL in the second portion, thereby forming a first via hole V1. The process also includes ashing the developed photoresist layer to remove the photoresist material in the second area while retaining the photoresist material in the first area; thereby forming a second photoresist layer PR2 in the area corresponding to the channel structure.

[0301] Referring to FIG. 31B , a lightly doped drain process is performed to make the portions of the semiconductor material layer SML corresponding to the first and second portions more conductive. The orthographic projection of the second photoresist layer PR2 on the base substrate 110 overlaps with the orthographic projection of the portion of the semiconductor material layer SML corresponding to the channel structure on the base substrate 110. After the lightly doped drain process, the portions of the semiconductor material layer SML corresponding to the first and second portions become more conductive.

[0302] 31C , electrode material is deposited and patterned to form the gate 22 and the connecting electrode 21 . The connecting electrode 21 and the first portion 31 (a portion of the semiconductor material layer SML that has undergone the lightly doped drain process) constitute the first portion 31 .

[0303] 32A to 32B illustrate a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0304] Referring to FIG32A , a signal line DL and a light shielding member 23 are formed on a base substrate 110. A first insulating layer BUF is formed on the side of the signal line DL and the light shielding member 23 facing away from the base substrate 110. A semiconductor material layer SML is formed on the side of the first insulating layer BUF facing away from the base substrate 110. A second insulating layer GI is formed on the side of the semiconductor material layer SML facing away from the base substrate 110. A first via V1 is formed, extending through the second insulating layer GI and the first insulating layer BUF, thereby exposing the upper surface of at least a portion of the signal line DL (e.g., the middle portion shown in FIG32A ). The portion of the semiconductor material layer SML corresponding to the first portion extends into the first via V1. A gate 22 is formed on the side of the second insulating layer GI facing away from the base substrate 110.

[0305] Referring to FIG. 32A , a lightly doped drain process is performed using gate 22 as a mask to make the portions of semiconductor material layer SML corresponding to the first and second portions more conductive. The orthographic projection of gate 22 on substrate 110 overlaps with the orthographic projection of the portion of semiconductor material layer SML corresponding to the channel structure on substrate 110. After the lightly doped drain process, the portions of semiconductor material layer SML corresponding to the first and second portions become more conductive.

[0306] 32B , electrode material is deposited and patterned to form connecting electrodes 21. Connecting electrodes 21 are electrically connected to first portion 31 (the portion of semiconductor material layer SML that has undergone the lightly doped drain process) and signal line DL exposed by first via V1, thereby electrically connecting first portion 31 to signal line DL.

[0307] In some embodiments, the second insulating layer GI is formed to extend substantially over the entire array substrate, as shown in FIGS. 30A to 30C , 31A to 31C , and 32A to 32B .

[0308] In some embodiments, the second insulating layer GI is not formed to extend substantially over the entire array substrate. For example, the orthographic projection of the second insulating layer GI on the base substrate does not at least partially overlap with the orthographic projection of the signal line on the base substrate, and does not at least partially overlap with the orthographic projection of the first portion or the second portion on the base substrate.

[0309] Figures 33A to 33C illustrate a process for manufacturing an array substrate according to some embodiments of the present disclosure. The process shown in Figures 33A to 33C is similar to the process shown in Figures 30A to 30C, but differs from the process shown in Figures 30A to 30C in that at least the second insulating layer GI is not formed to extend substantially over the entire array substrate.

[0310] Figures 34A to 34C illustrate a process for manufacturing an array substrate according to some embodiments of the present disclosure. The process shown in Figures 34A to 34C is similar to the process shown in Figures 31A to 31C, but differs from the process shown in Figures 31A to 31C in that the second insulating layer GI is not formed to extend substantially over the entire array substrate.

[0311] Figures 35A to 35B illustrate a process for manufacturing an array substrate according to some embodiments of the present disclosure. The process shown in Figures 35A to 35B is similar to the process shown in Figures 32A to 32B, but differs from the process shown in Figures 32A to 32B in that the second insulating layer GI is not formed to extend substantially over the entire array substrate.

[0312] Figures 36A to 36C illustrate a process for manufacturing an array substrate according to some embodiments of the present disclosure. The process illustrated in Figures 36A to 36C is similar to the process illustrated in Figures 30A to 30C, but differs from the process illustrated in Figures 30A to 30C in at least one aspect: a lightly doped drain process is performed using a mask. In one example, the lightly doped drain process is performed only on a portion of the semiconductor material layer SML extending into the first via V1 and a portion of the semiconductor material layer SML corresponding to the second portion.

[0313] Figures 37A to 37C illustrate a process for manufacturing an array substrate according to some embodiments of the present disclosure. The process shown in Figures 37A to 37B is similar to the process shown in Figures 36A to 36C, but differs from the process shown in Figures 36A to 36C in that the second insulating layer GI is not formed to extend substantially over the entire array substrate.

[0314] Example 1. In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material may include but is not limited to a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a first insulating layer having a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the substrate to a thickness between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; forming an insulating layer on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; performing a lightly doped drain process on the semiconductor material layer; etching the insulating layer and the first insulating layer to form a via hole extending through the insulating layer and the first insulating layer and exposing an upper surface of at least a portion of the signal line DL; and An electrode material layer with a thickness between 200 nm and 1200 nm is sputtered on the side of the insulating layer and the first insulating layer away from the substrate, wherein the electrode material includes a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; the electrode material layer is patterned to form a second portion and a gate; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200 nm and 400 nm; a 2 μm thick layer is coated on the first passivation layer. A resin layer with a thickness of between 100 nm and 3 μm is deposited on the resin layer; a conductive material layer with a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness of between 100 nm and 300 nm; a conductive material layer with a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 1 corresponds to the process described in Figures 30A to 30C.

[0315] Example 2. In another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a first insulating layer with a thickness between 100 nm and 700 nm; sputtering amorphous silicon on the base substrate; sputtering indium gallium zinc oxide to a thickness between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; forming an insulating layer on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; performing a lightly doped drain process on the semiconductor material layer; etching the insulating layer and the first insulating layer to form a via hole extending through the insulating layer and the first insulating layer and exposing an upper surface of at least a portion of the signal line DL; sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the insulating layer and the first insulating layer away from the substrate, the electrode material comprising molybdenum-neodymium-copper The invention relates to a stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second portion and a gate; patterning the insulating material layer to form an insulating layer, wherein the insulating layer substantially does not extend over the entire array substrate, and the orthographic projection of the insulating layer on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate at least in part, and does not overlap with the orthographic projection of the first portion or the second portion on the base substrate at least in part; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a gate having a thickness of 200 nm to 400 nm. A first passivation layer having a thickness of between 100 nm and 300 nm is formed; a resin layer having a thickness of between 2 μm and 3 μm is coated on the first passivation layer; a conductive material layer having a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer having a thickness of between 100 nm and 300 nm; a conductive material layer having a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 2 corresponds to the process described in Figures 31A to 31C.

[0316] Example 3. In yet another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer having a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or nitrogen oxide) on the base substrate; sputtering indium gallium zinc oxide on the substrate to a thickness of between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; forming an insulating layer on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; forming a first photoresist layer on a side of the insulating layer away from the substrate; and exposing and developing the first photoresist layer using a halftone mask. The insulating layer and the first insulating layer are etched to form a via extending through the insulating layer and the first insulating layer to expose the upper surface of at least a portion of the signal line; a second photoresist layer is formed in a region corresponding to the channel structure; a lightly doped drain process is performed on the semiconductor material layer using the second photoresist layer as a mask; an electrode material layer having a thickness between 200 nm and 1200 nm is sputtered on a side of the insulating layer and the first insulating layer away from the substrate, the electrode material comprising a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; the electrode material layer is patterned to form a second portion and a gate; an insulating material (oxygen) is deposited on the substrate (e.g., by a plasma enhanced chemical vapor deposition process) A first passivation layer having a thickness of 200 nm to 400 nm is formed by depositing silicon oxide or silicon nitride / silicon oxide; a resin layer having a thickness of 2 μm to 3 μm is coated on the first passivation layer; a conductive material layer having a thickness of 40 nm to 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer having a thickness of 100 nm to 300 nm; a conductive material layer having a thickness of 40 nm to 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 3 corresponds to the process described in Figures 33A to 33C.

[0317] Example 4. In another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a first insulating layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm ; patterning indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on the side of the semiconductor material layer away from the substrate; forming a first photoresist layer on the side of the insulating layer away from the substrate; using a halftone mask to expose and develop the first photoresist layer; etching the insulating layer and the first insulating layer to form a via extending through the insulating material layer and the first insulating layer to expose at least a portion of the upper surface of the signal line; forming a second photoresist layer in an area corresponding to the channel structure; using the second photoresist layer as a mask, performing a lightly doped drain process on the semiconductor material layer; A layer of electrode material with a thickness between 200 nm and 1200 nm is sputtered on one side of the plate, wherein the electrode material includes a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; the electrode material layer is patterned to form a second portion and a gate; the insulating material layer is patterned to form an insulating layer, wherein the insulating layer does not substantially extend over the entire array substrate, and the orthographic projection of the insulating layer on the substrate substrate does not at least partially overlap with the orthographic projection of the signal line on the substrate substrate, and does not at least partially overlap with the orthographic projection of the first portion or the second portion on the substrate substrate; an insulating material (silicon oxide or silicon nitride) is deposited on the substrate substrate (for example, by a plasma enhanced chemical vapor deposition process) The invention relates to a method for manufacturing a pixel electrode of a pixel-shaped substrate. The method comprises the following steps: depositing a first passivation layer with a thickness of 200 nm to 400 nm using silicon / silicon oxide; coating a resin layer with a thickness of 2 μm to 3 μm on the first passivation layer; depositing a conductive material layer with a thickness of 40 nm to 100 nm on the resin layer using indium gallium zinc oxide or indium zinc oxide, and patterning the conductive material layer to form a common electrode; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a second passivation layer with a thickness of 100 nm to 300 nm; depositing a conductive material layer with a thickness of 40 nm to 135 nm on the second passivation layer using indium zinc oxide, and patterning the conductive material layer to form a pixel electrode.The process described in Example 4 corresponds to the process described in Figures 34A to 34C.

[0318] Example 5. In yet another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a layer with a thickness between 100 nm and 700 nm. sputtering indium gallium zinc oxide on the substrate to a thickness of 10 nm to 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating layer on a side of the semiconductor material layer away from the substrate; etching the insulating layer and the first insulating layer using a mask to form a via hole extending through the insulating layer and the first insulating layer and exposing at least a portion of the upper surface of the signal line DL; using the same mask used to form the first via hole V1, etching the semiconductor material layer extending to the first via hole V2. A lightly doped drain process is performed on the portion in the hole V1; an electrode material layer with a thickness between 200nm and 1200nm is sputtered on the side of the insulating material layer and the first insulating layer away from the substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; the electrode material layer is patterned to form a second portion and a gate; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a plasma chemical vapor deposition process) to form a first passivation layer with a thickness between 200nm and 400nm; A resin layer having a thickness of 2 μm to 3 μm is coated on the layer; a conductive material layer having a thickness of 40 nm to 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer having a thickness of 100 nm to 300 nm; a conductive material layer having a thickness of 40 nm to 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 5 corresponds to the process described in Figures 36A to 36C.

[0319] Example 6. In another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a first insulating layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 700 nm. The method further comprises the steps of: patterning an indium gallium zinc oxide material to form a semiconductor material layer; forming an insulating layer on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; etching the insulating layer and the first insulating layer using a mask to form a via hole extending through the insulating layer and the first insulating layer and exposing an upper surface of at least a portion of the signal line DL; performing a lightly doped drain process on a portion of the semiconductor material layer extending into the first via hole V1 using the same mask used to form the first via hole V1; and sputtering a thin film having a thickness between 200 nm and 1200 nm on a side of the insulating layer and the first insulating layer away from the substrate. nm, wherein the electrode material layer comprises a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second portion and a gate; patterning the insulating material layer to form an insulating layer, wherein the insulating layer substantially does not extend over the entire array substrate, and the orthographic projection of the insulating layer on the substrate substrate does not at least partially overlap with the orthographic projection of the signal line on the substrate substrate, and does not at least partially overlap with the orthographic projection of the first portion or the second portion on the substrate substrate; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate to form A first passivation layer having a thickness of between 200 nm and 400 nm is formed; a resin layer having a thickness of between 2 μm and 3 μm is coated on the first passivation layer; a conductive material layer having a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer having a thickness of between 100 nm and 300 nm; a conductive material layer having a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 6 corresponds to the process described in Figures 37A to 37C.

[0320] Example 7. In another example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member 23 and a signal line DL on the base substrate 110; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a first insulating layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on a side of the semiconductor material layer away from the substrate; etching the insulating layer and the first insulating layer to form a via hole extending through the insulating layer and the first insulating layer and exposing the upper surface of at least a portion of the signal line DL; sputtering an electrode material layer with a thickness between 200nm and 1200nm on a side of the insulating material layer and the first insulating layer away from the substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a gate; using the gate as a mask, performing a lightly doped drain process on the semiconductor material layer; sputtering a layer with a thickness between 200nm and 1200nm. nm, wherein the electrode material layer comprises a molybdenum-neodymium-copper laminate structure, an MTD-copper laminate structure, or an MTD-copper-MTD laminate structure; patterning the electrode material layer to form a second portion at least partially in the first via hole V1; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a first passivation layer with a thickness between 200 nm and 400 nm; coating a resin layer with a thickness between 2 μm and 3 μm on the first passivation layer; and A conductive material layer having a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (e.g., by chemical vapor deposition) to form a second passivation layer having a thickness of between 100 nm and 300 nm; a conductive material layer having a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 7 corresponds to the process described in Figures 35A and 35B.

[0321] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate substrate; A signal line, located on the substrate; A first insulating layer, located on a side of the signal line away from the substrate; as well as An active layer is located on a side of the first insulating layer away from the substrate; the active layer comprises a first portion, a second portion and a channel structure located between the first portion and the second portion; A first via hole at least passing through the first insulating layer and exposing at least a portion of the signal line; The first portion is configured to be connected to the signal line through the first via; the material of the second portion and the first portion is the same as the material of the channel structure; and the conductivity of the channel structure is different from the conductivity of the first portion and different from the conductivity of the second portion.

2. The array substrate according to claim 1, further comprising: A connecting electrode, located on a side of the active layer away from the base substrate, the connecting electrode being electrically connected to the signal line and the first portion respectively; The first portion is configured to be electrically connected to the signal line through the connection electrode.

3. The array substrate according to claim 2, further comprising: a second insulating layer, located between the active layer and the connecting electrode; Wherein, the first via hole penetrates the second insulating layer and the first insulating layer, and the first via hole also exposes at least a portion of the first portion; At least a portion of the connecting electrode is located in the first via hole, and an orthographic projection of the connecting electrode on the base substrate overlaps with an orthographic projection of the first portion on the base substrate and overlaps with an orthographic projection of the signal line on the base substrate.

4. The array substrate according to claim 3, wherein: The orthographic projection of the first portion on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate.

5. The array substrate according to claim 4, wherein: The array substrate includes a first connection area defined by the first via hole, the first connection area includes a first region, a second region, and a third region sequentially connected in a direction away from the channel structure; an orthographic projection of the first region on the base substrate partially overlaps with an orthographic projection of the first portion on the base substrate, and does not overlap with an orthographic projection of the signal line on the base substrate; The orthographic projection of the second area on the base substrate partially overlaps with the orthographic projection of the first portion on the base substrate, and is located within the range of the orthographic projection of the signal line on the base substrate; The orthographic projection of the third region on the substrate is located outside the orthographic projection of the first portion on the substrate, and at least partially overlaps with the orthographic projection of the signal line on the substrate; The connection electrode covers at least a portion of the second region and the third region.

6. The array substrate according to claim 5, wherein: In the first region, the array substrate includes the first insulating layer and the first portion which are stacked; In the second area, the array substrate includes the signal line, the first insulating layer, the first portion and the connecting electrode which are stacked; In the third area, the array substrate includes the signal lines and the connection electrodes which are stacked.

7. The array substrate according to claim 6, wherein: The connecting electrode covers at least a portion of the first region; At the location of the first region, the array substrate further includes a connecting electrode located on a side of the first portion away from the base substrate.

8. The array substrate according to claim 5 or 6, wherein: The connecting electrode exposes at least a portion of the first region; The first portion includes a groove portion that is concave toward a side close to the base substrate. The groove portion is located in the first region, and an orthographic projection of the groove portion on the base substrate does not overlap with an orthographic projection of the connection electrode on the base substrate.

9. The array substrate according to any one of claims 5 to 8, further comprising: The signal line, the first insulating layer, the first portion, and the connecting electrode form a protruding structure in the second region that protrudes toward a side farther from the base substrate than the first region and the third region.

10. The array substrate according to any one of claims 5 to 9, wherein: The first portion and / or the second portion comprises a sawtooth structure at an edge of the second region close to the first region.

11. The array substrate according to claim 3, wherein: An orthographic projection of the first portion on the base substrate does not overlap with an orthographic projection of the signal line on the base substrate.

12. The array substrate according to claim 11, wherein: The array substrate includes a first connection area defined by the first via hole, the first connection area includes a fourth area and a fifth area sequentially connected in a direction away from the channel structure; the orthographic projection of the fourth area on the base substrate at least partially overlaps with the orthographic projection of the first portion on the base substrate, and does not overlap with the orthographic projection of the signal line on the base substrate; The orthographic projection of the fifth region on the base substrate at least partially overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the first portion on the base substrate; The connecting electrode covers at least a portion of the fourth region and at least a portion of the fifth region.

13. The array substrate according to claim 12, wherein: In the fourth region, the array substrate includes the first insulating layer, the first portion, and the connecting electrode which are stacked; In the fifth region, the array substrate includes the signal lines and the connection electrodes which are stacked.

14. The array substrate according to claim 12 or 13, wherein: The connecting electrode exposes at least a portion of the fourth region; The first portion includes a groove portion that is concave toward a side close to the base substrate, the groove portion is located in the fourth region, and an orthographic projection of the groove portion on the base substrate does not overlap with an orthographic projection of the connection electrode on the base substrate.

15. The array substrate according to any one of claims 12 to 14, wherein: The connecting electrode comprises a step structure; the step structure comprises a first step located in the fourth region, and a second step located in the fifth region; the first step is farther away from the base substrate than the second step.

16. The array substrate according to any one of claims 2 to 15, wherein: The material of the first portion is different from the material of the connection electrode.

17. The array substrate according to claim 16, wherein: The channel structure, the first portion and the second portion are an integrated structure; The material of the first part includes M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element; The material of the connecting electrode includes a metal material.

18. The array substrate according to any one of claims 2 to 17, wherein: At least a portion of the first portion extends into the connecting electrode.

19. The array substrate according to any one of claims 2 to 18, further comprising: a second insulating layer, located between the active layer and the connecting electrode; A gate, located on a side of the second insulating layer away from the substrate; The connecting electrode and the gate are located in the same layer and include the same material.

20. The array substrate according to claim 1, wherein: The first via hole penetrates the first insulating layer; At least a portion of the first portion is located in the first via hole, and the first portion is in contact with and connected to the signal line through the first via hole.

21. The array substrate according to claim 20, wherein: The channel structure, the first portion and the second portion are an integrated structure; The material of the first part includes M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element.

22. The array substrate according to any one of claims 1 to 21, wherein: The first portion, the channel structure, and the second portion are arranged substantially along a straight line.

23. The array substrate according to claim 22, further comprising: A gate line is arranged on a side of the active layer away from the base substrate, and the gate line extends along a first direction; a gate, located in the same layer as the gate and comprising the same material as the gate, the gate extending along a second direction, and one end of the gate connected to the gate line; the first direction intersects the second direction; Wherein, the signal line extends along the second direction; The first portion, the channel structure, and the second portion are substantially arranged along the first direction.

24. The array substrate according to claim 23, wherein: The gate line comprises a first extension segment and a second extension segment, the orthographic projection of the first extension segment on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate, and the orthographic projection of the second extension segment on the base substrate overlaps with the orthographic projection of the signal line on the base substrate; Along the second direction, a size of the first extension segment is smaller than a size of the second extension segment.

25. The array substrate according to claim 24, wherein: The dimension of the first extension section along the second direction is D1, and the value range of D1 is 2 μm to 6 μm; The dimension of the second extension section along the second direction is D2, D2=D1+H, and the value range of H is 0.2 μm to 1.5 μm.

26. The array substrate according to any one of claims 1 to 25, further comprising: A third insulating layer is located on a side of the connecting electrode away from the substrate; A planarization layer, located on a side of the third insulating layer away from the substrate; a second via hole at least passing through the third insulating layer and the planarization layer, and an orthographic projection of the second via hole on the base substrate at least partially overlaps with an orthographic projection of the second portion on the base substrate; A pixel electrode is disposed on a side of the planarization layer away from the base substrate, and the pixel electrode extends through the second via hole and is electrically connected to the second portion.

27. The array substrate according to claim 26, wherein: The second via hole includes a first sub-hole penetrating the third insulating layer, and a second sub-hole penetrating the planarization layer; The orthographic projection of the second sub-hole on the base substrate covers the orthographic projection of the first sub-hole on the base substrate, and the center of the orthographic projection of the second sub-hole on the base substrate is spaced from the center of the orthographic projection of the first sub-hole on the base substrate.

28. The array substrate according to claim 27, wherein: The first portion, the channel structure and the second portion are arranged substantially along a first direction; The center of the orthographic projection of the second sub-hole on the base substrate is spaced apart from the center of the orthographic projection of the first sub-hole on the base substrate along the first direction.

29. The array substrate according to claim 26, wherein: The second via hole includes a first sub-hole penetrating the third insulating layer, and a second sub-hole penetrating the planarization layer; The boundary of the orthographic projection of the second sub-hole on the base substrate roughly coincides with the boundary of the orthographic projection of the first sub-hole on the base substrate, and the center of the orthographic projection of the second sub-hole on the base substrate roughly coincides with the center of the orthographic projection of the first sub-hole on the base substrate.

30. The array substrate according to any one of claims 26 to 29, further comprising: a switching electrode, located between the active layer and the third insulating layer, and electrically connected to the second portion; The second via hole exposes at least a portion of the switching electrode, the pixel electrode is electrically connected to the switching electrode, and is electrically connected to the second portion through the switching electrode.

31. The array substrate according to any one of claims 26 to 29, wherein: The second via hole exposes at least a portion of the second portion, and the pixel electrode is in contact with the second portion.

32. The array substrate according to any one of claims 26 to 31, further comprising: A spacer block is located at a side of the pixel electrode away from the base substrate, and an orthographic projection of the spacer block on the base substrate at least partially overlaps with an orthographic projection of the second sub-hole on the base substrate; Wherein, at least a portion of the second sub-hole is filled with the spacer.

33. The array substrate according to any one of claims 1 to 25, further comprising: The pixel electrode is located in the same layer as the active layer and comprises the same material, and the pixel electrode and the second portion are an integrated structure.

34. The array substrate according to any one of claims 11 to 33, wherein: In a cross section along a plane perpendicular to the substrate and perpendicular to the direction in which the signal line extends in length and intersecting the signal line and the first via hole, a surface of the signal line other than a lower surface is exposed in the first via hole; The lower surface refers to a surface of the signal line that contacts the base substrate.

35. The array substrate according to claim 34, wherein: In the cross section, the upper surface of the signal line and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are completely covered by the first portion or the connection electrode.

36. The array substrate according to claim 34, wherein: In the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first portion or the connection electrode.

37. The array substrate according to any one of claims 11 to 33, wherein: In a cross section along a plane perpendicular to the substrate and perpendicular to the direction in which the signal line extends in length and intersecting the signal line and the first via hole, at least a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are not exposed in the first via hole; as well as The lower surface refers to a surface of the signal line that contacts the base substrate.

38. The array substrate according to claim 37, wherein: In the cross section, only a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first insulating layer.

39. The array substrate according to claim 37, wherein: In the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first portion or the connection electrode.

40. The array substrate according to claim 37, wherein: In the cross section, only the upper surface of the middle portion of the signal line is covered by the first portion or the connection electrode; as well as Two side surfaces of the upper surface and the lower surface respectively connected to the signal line are covered by the first insulating layer.

41. The array substrate according to any one of claims 1 to 40, wherein: The signal line is configured to provide a data signal to the first portion.

42. The array substrate according to claim 1, wherein: The active layer includes a metal oxide material having a Hall mobility greater than or equal to 30 cm2 / Vs.

43. The array substrate according to claim 1, further comprising: A light shielding member located on the substrate, and a gate line located on a side of the active layer away from the substrate; Wherein, the light shielding member and the signal line are located in the same layer and comprise the same material; and Along a direction perpendicular to an extension direction of the length of the gate line, a ratio of a line width of the gate line to a line width of the light shielding member is in a range of 0.3 to 0.

9.

44. A display device comprising: The array substrate according to any one of claims 1 to 43; The driving circuit board is electrically connected to the array substrate and is configured to transmit a control signal to the array substrate.

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