Voltage regulator

Abstract

A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage source terminal; an output terminal; a reference end; a feed-forward Wilson current mirror; an input current source; a feed-forward capacitor; and an output current transistor; and a flip voltage follower (FVF) including: a channel transistor including a conductive channel coupled between a supply voltage terminal and an output terminal; a first FVF transistor having a conductive channel coupled between the output voltage and the FVF node; a second FVF transistor having a conductive channel coupled between the gate of the channel transistor and the FVF node; a third FVF transistor having a conductive channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein the gate of the third FVF transistor is coupled to the gate of the output current transistor; and an FVF current source coupled between the FVF node and a reference terminal.

Description

Technical Field

[0001] The present disclosure relates to a voltage regulator, and more particularly, to a voltage regulator for outputting a regulated output voltage to an integrated circuit. Background Art

[0002] The Controller Area Network (CAN bus) is a message-based protocol designed to enable the electronic control units (ECUs) of a vehicle to communicate with each other. The ECU may be coupled to a transceiver for sending and receiving messages on the CAN bus. The ECU may include a microcontroller for controlling specific subcircuits (sensors, actuators, etc.). The microcontroller operates at a low voltage ranging from 5V to 1.8V. The transceiver typically includes a low-power digital section that is always powered on and includes an integrated circuit that can communicate with the microcontroller. The low-power section of the transceiver may include a low-dropout (LDO) voltage regulator (hereinafter referred to as LDO) for providing a low voltage for use in the always-on digital domain within the transceiver chip. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising:

[0004] A voltage source terminal, used for receiving a power supply voltage;

[0005] an output terminal, which is used to output the regulated output voltage;

[0006] Reference terminal;

[0007] Feed-forward Wilson current mirror, including:

[0008] A Wilson current mirror having an input current terminal and an output current terminal;

[0009] an input current source coupled between the power supply voltage terminal and the input current terminal of the Wilson current mirror;

[0010] a feedforward capacitor arranged in parallel with the input current source; and

[0011] an output current transistor having a conductive channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and

[0012] The flip voltage follower FVF comprises:

[0013] a pass transistor including a conductive channel coupled between the supply voltage terminal and the output terminal;

[0014] a first FVF transistor having a conductive channel coupled between the output voltage and a FVF node;

[0015] a second FVF transistor having a conductive channel coupled between a gate of the pass transistor and the FVF node;

[0016] a third FVF transistor having a conductive channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein the gate of the third FVF transistor is coupled to the gate of the output current transistor; and

[0017] A FVF current source is coupled between the FVF node and the reference terminal.

[0018] The feed-forward Wilson current mirror may cause the pole at the gate of the pass transistor of the FVF to move in response to voltage transients and advantageously help the voltage at the output to remain stable.

[0019] In one or more embodiments, the FVF further includes a pull-down transistor having a conductive channel coupled between the output terminal and the reference terminal and a gate terminal coupled to the FVF node.

[0020] In one or more embodiments, the pull-down transistor is configured to be activated in response to a supply voltage transient at the supply voltage terminal or a load transient at the output terminal.

[0021] In one or more embodiments, the pull-down transistor includes an activation threshold such that the pull-down transistor is configured to activate in response to a supply voltage transient at the supply voltage terminal or a load transient at the output terminal.

[0022] In one or more embodiments, the pull-down transistor comprises an NMOS transistor.

[0023] In one or more embodiments, the feed-forward capacitor comprises a PMOS transistor.

[0024] In one or more embodiments, the FVF includes a channel capacitor coupled between the gate of the channel transistor and the output voltage terminal, wherein the channel capacitor includes a PMOS transistor.

[0025] In one or more embodiments, the feed-forward capacitor comprises a PMOS transistor of the same type as the pass capacitor.

[0026] In one or more embodiments, the voltage regulator is adapted to suppress voltage transients having a specific ramp rate, wherein a capacitance of the feed-forward capacitor is based on the ramp rate.

[0027] In one or more embodiments, the output current transistor and the third FVF transistor form a current mirror. In one or more embodiments, the size ratio of the third FVF transistor to the output current transistor determines a scaling factor of the current mirror.

[0028] In one or more embodiments, the feed-forward Wilson current mirror includes a source follower circuit coupled between the supply voltage terminal and the reference terminal. In one or more embodiments, the source follower circuit is configured to prevent the voltage at the input current terminal from dropping below a threshold current value.

[0029] In one or more embodiments, the voltage regulator includes a bandgap reference circuit including a bandgap-based current reference source configured to provide a control voltage to a gate terminal of the first FVF transistor.

[0030] In one or more embodiments, the pass transistor comprises a PMOS transistor. In one or more embodiments, the first FVF transistor comprises a PMOS transistor. In one or more embodiments, the third FVF transistor comprises a PMOS transistor. In one or more embodiments, the output current transistor comprises a PMOS transistor. In one or more embodiments, the second FVF transistor comprises an NMOS transistor.

[0031] In one or more embodiments, the voltage regulator comprises a low dropout voltage regulator.

[0032] According to a second aspect of the present disclosure, there is provided a transceiver for a controller area network, comprising any voltage regulator described herein.

[0033] Although the present disclosure allows various modifications and alternative forms, the details have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments other than the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed.

[0034] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0036] Figure 1A voltage regulator for outputting a regulated output voltage to an integrated circuit according to an embodiment of the present disclosure is shown;

[0037] Figure 2 The relationship between the feedforward transfer function and frequency of the feedforward Wilson current mirror is shown.

[0038] Figure 3 schematically illustrating which loop is active during a transient peak in the output voltage at the output terminal;

[0039] Figure 4 FIG. 1 shows a circuit diagram of a circuit having additional control and output circuitry according to an embodiment of the present disclosure. Figure 1 LDO;

[0040] Figure 5 shows the performance of an LDO according to an embodiment of the present disclosure;

[0041] Fig. 6A Show Figure 4 a response of an LDO to a transient on a supply voltage terminal, the transient comprising a square wave transient having an increased amplitude;

[0042] Figure 6B Show Figure 4 The response of the LDO during load and line step events. DETAILED DESCRIPTION

[0043] The automotive environment is typically a harsh operating environment, and the length of the CAN bus can be tens of meters. This can cause the supply voltage of the LDO to be noisy via mutual inductance and electromagnetic interference (EMI) with other signals. The LDO should provide a stable low-voltage output for a wide range of supply voltages (including EMI spikes) to avoid damaging the integrated circuit (IC) of the digital section of the transceiver. The LDO should also maintain a stable output voltage in response to rapid changes in the output load. The LDO should also have a low consumption current because it is always on.

[0044] The voltage regulator of the present disclosure can: respond to fast line and load transients and address electromagnetic compatibility (EMC) immunity issues; operate from a wide range of power supplies; and consume low quiescent current.

[0045] Figure 1 A voltage regulator 100 is shown for outputting a regulated output voltage to an integrated circuit according to an embodiment of the present disclosure. In this example, the voltage regulator is an LDO.

[0046] The voltage regulator 100 includes: a power supply voltage terminal 102 (labeled as VDD) for receiving a power supply voltage; an output voltage terminal 104 (labeled as 1.5V) for outputting a regulated output voltage; and a reference terminal 106, which is a ground voltage in this example.

[0047] The voltage regulator 100 additionally includes a feed-forward Wilson current mirror 108 coupled to a flip voltage follower (FVF) 110. The feed-forward Wilson current mirror 108 includes a feed-forward capacitor 112 (labeled Cff) coupled in parallel with an input current source 114 between the supply voltage terminal 102 and the Wilson current mirror 116. The feed-forward capacitor 112 generates a current through the Wilson current mirror 116 that is proportional to any voltage transient dV / dt at the supply voltage terminal 102. As a result, a pole at the gate of a pass transistor 118 (labeled MP) of the FVF 110 moves in response to the voltage transient and advantageously helps the voltage at the output terminal 104 remain stable.

[0048] In more detail, the feedforward Wilson current mirror 108 includes: a Wilson current mirror 116; an input current source 114; a feedforward capacitor 112 and an output current transistor 120 (labeled as M4). The Wilson current mirror 116 includes an input current terminal 122 and an output current terminal 124. In this example, the Wilson current mirror 116 is coupled to the reference terminal 106. The input current source 114 is coupled between the power supply voltage terminal 102 and the input current terminal 122 of the Wilson current mirror 116. In this example, the input current source 114 provides an input current of 62.5 nA. The feedforward capacitor 112 is coupled in parallel with the input current source 114 (between the power supply voltage terminal 102 and the input current terminal 122). The output current transistor 120 includes a conductive channel, which is coupled between the power supply voltage terminal 102 and the output current terminal 124 of the Wilson current mirror 116. In this example, the output current transistor 120 comprises a PMOS (p-type metal oxide semiconductor) transistor having a source coupled to the power supply voltage terminal 102 and a drain coupled to the output current terminal 124 .

[0049] The FVF 110 includes: a pass transistor 118, a first FVF transistor 126 (labeled as M2); a second FVF transistor 128 (labeled as M2); and a third FVF transistor 130 (labeled as M3); and a FVF current source 132. The pass transistor 118 includes a conductive channel coupled between the power supply voltage terminal 102 and the output terminal 104. In this example, the pass transistor 118 is a PMOS transistor having a source coupled to the power supply voltage terminal 102 and a drain coupled to the output terminal 104. The first FVF transistor 126 includes a conductive channel coupled between the output voltage terminal 104 and the FVF node n2. In this example, the first FVF transistor 126 is a PMOS transistor having a source coupled to the output voltage terminal 104 and a drain coupled to the FVF node n2. The second FVF transistor 128 includes a conductive channel coupled between the gate of the pass transistor 118 and the FVF node n2. In this example, the second FVF transistor 128 is an NMOS (n-type metal oxide semiconductor) transistor having a source coupled to the FVF node n2 and a drain coupled to the gate of the pass transistor 118. The third FVF transistor 130 includes a conductive channel coupled between the power supply voltage terminal 102 and the gate of the pass transistor 118. In this example, the third FVF transistor 130 is a PMOS transistor having a source coupled to the power supply voltage terminal 102 and a drain coupled to the gate of the pass transistor 118. The gate of the third FVF transistor 130 is coupled to the gate of the output current transistor 120 to form a current mirror. The FVF current source 132 is coupled between the FVF node n2 and the reference terminal 104.

[0050] In this example, the gate of the first FVF transistor 126 is configured to receive a control voltage Vctrl, which provides a reference for the FVF 110. The gate of the second FVF transistor 128 is configured to receive a bias voltage Vb, discussed further below.

[0051] In this example, the size ratio of the output current transistor 120 to the third FVF transistor 130 is selected to provide a scaling factor of 2 for the current mirror formed by the output current transistor 120 and the third FVF transistor 130. Therefore, a nominal current of 125 nA flows in each branch (M3-M2 and MP-M1) of the FVF 110. The FVF current source includes a current source of 250 nA (equal to the sum of the 2×125 nA branches).

[0052] In operation, the feed-forward Wilson current mirror 108 can generate a current through the output current transistor 120 and the third FVF transistor 130 that is proportional to any power supply voltage transient dV / dt on the power supply voltage terminal 102. In the event of a large transient on the power supply voltage terminal 102, such as from 1.7V to 5.5V at a ramp rate of 10V / us, the feed-forward capacitor 112 can generate a proportional transient current. This proportional current is added to the input current of the input current source 114, and the Wilson current mirror 116 outputs the proportional transient current and the input current to the output current transistor 120. This increased transient current is mirrored through the third FVF transistor 130. Therefore, the main pole vg at the node at the gate of the pass transistor 118 moves with appropriate dv / dt and suppresses the transient effect at the output terminal 104. In other words, the current gain from the feed-forward capacitor 112 adjusts the gate voltage vg at the gate of the pass transistor 118 to follow any supply voltage transients at the supply voltage terminal 102 (which is coupled to the source of the pass transistor 118). Therefore, transients in the source gate voltage of the pass transistor 118 and transients in the output voltage at the output voltage terminal 104 are suppressed.

[0053] During a direct power injection (DPI) event on the CAN bus, the internal supply voltage on the supply voltage terminal 102 and the reference voltage at the reference terminal 104 may be quite unstable due to the mutual coupling of the bond wires and may include supply transients of about 10V / us and having a magnitude of several volts. The feed-forward Wilson current mirror 108 helps resolve the transients without requiring significant bias currents or circuits with complex and / or interacting loops that may make the design very difficult to manage.

[0054] Figure 2 The relationship between the feedforward transfer function Gmff(Iout / VDD) and the frequency of the feedforward Wilson current mirror 108 is shown, where Iout is the current at the output terminal 124 of the Wilson current mirror 126. The capacitance Cff of the feedforward capacitor 112 can be tuned to achieve a targeted supply voltage transient dv / dt in the supply voltage VDD on the supply voltage terminal 102.

[0055] To respond to a 10V / us supply voltage transient dv / dt with 5V amplitude and meet EMC targets, we can write:

[0056]

[0057] 5ω=10 6

[0058]

[0059] Figure 2 A first curve 234 is included that shows the relationship between the transfer function peak and frequency for a capacitance Cff of 300 fF. A second curve 236 shows the relationship between the transfer function peak and frequency for Cff=500 fF. A third curve 238 shows the relationship between the transfer function peak and frequency for Cff=800 fF. These curves show that when we increase the capacitance Cff of the feed-forward capacitor 112 from 300 fF to 800 fF, the peak of the Gmff transfer function moves to the left to a lower frequency. In this way, the capacitance Cff of the feed-forward capacitor 112 can be selected for a frequency corresponding to a specific target power supply voltage transient (defined by A and dv / dt).

[0060] Return to Figure 1 , the additional current generated by the feed-forward capacitor 112 and mirrored by the Wilson current mirror 116 charges the channel capacitor 140 having a capacitance Cm at the gate of the channel transistor. The channel capacitor 140 is coupled between the gate terminal of the channel transistor 118 and the output terminal 104 (and the drain terminal of the channel transistor 118). As referred to herein, the channel capacitor may refer to a discrete capacitor coupled between the gate terminal and the drain terminal of the channel transistor 118 and / or any inherent capacitance between the gate terminal and the drain terminal of the channel transistor 118 (i.e., it is the total gate-drain capacitance). In some examples, the feed-forward capacitor 112 is provided as a PMOS transistor. In some examples, the channel capacitor 140 is provided as a PMOS transistor. In some examples, the feed-forward capacitor 112 is formed using the same type of PMOS transistor as the channel capacitor 140. Therefore, the capacitances of the two capacitors 112, 140 can track each other across process corners and cancel each other. This can provide almost perfect cancellation.

[0061] However, due to the inherent delay of the Wilson current mirror 116, perfect cancellation is not possible. Therefore, there are some spikes in the output voltage at the output voltage terminal 104. In this example, the FVF 110 includes a pull-down transistor 142 (labeled MN). The pull-down transistor 142 includes a conductive channel coupled between the output terminal 104 and the reference terminal 106. The pull-down transistor 112 includes a gate terminal coupled to the FVF node n2. In this example, the pull-down transistor includes an NMOS transistor having a source terminal coupled to the reference terminal 106 and a drain terminal coupled to the output terminal 104. The first FVF transistor 126 and the pull-down transistor 142 form a super source follower (SSF) that is used to quickly pull down any transient increase in the output voltage at the output voltage terminal 104.

[0062] The feed-forward Wilson current mirror and the FVF with super source follower can be combined to provide an LDO solution that can be tuned for any supply voltage transient dv / dt to achieve EMC requirements.

[0063] FVF 110 is biased with a low current of 250 nA from FVF current source 132. Pass transistor 118 can provide the DC load current required by the switching digital logic of the IC.

[0064] The additional pull-down transistor 142 can provide a pull-down on the output terminal 104 during a load release event. When the DC load current decreases very quickly from full load to no load and / or during a transient event on the supply voltage terminal 102, the output voltage at the output terminal 104 of the LDO 100 tends to become higher and in some cases can become as high as the supply voltage VDD itself. This can seriously endanger the downstream digital logic of the IC connected to the output terminal 104, making it unable to handle the high voltage and may be damaged or cause a shortened service life dependent on voltage exposure. The first FVF transistor 126 and the pull-down transistor 142 form a super source follower loop that is activated during this output voltage peak scenario. When the output voltage at the output terminal 104 goes high, the voltage at the FVF node n2 also goes high, thereby activating the pull-down transistor 142. Therefore, the output voltage at the output voltage terminal is maintained within acceptable limits for transistors in the digital domain of the IC. When the FVF node n2 goes high, the second FVF transistor 128 turns off, and thus only the super source follower loop actively pulls down the output voltage at the output terminal 104. In some examples, the pull-down transistor 142 may include a relatively high threshold voltage to ensure that the pull-down transistor 142 is activated only during transient events to specifically pull down the output voltage, and that the pull-down transistor 142 is inactive and does not actively consume DC current at other times. The super source follower loop consisting of transistors M1 and MN (the first FVF transistor 126 and the pull-down transistor 142) and the main FVF loop consisting of transistors M1, M2, M3, and MP (the first FVF transistor 126, the second FVF transistor 128, and the third FVF transistor 130 and the pass transistor 118) are mutually exclusive and do not interact with each other.

[0065] Figure 3Schematically showing which loop is active during a transient peak in the output voltage at the output 104. At the beginning of the transient peak, the FVF loop is active, providing a DC load current. As the voltage increases, the voltage at the FVF node n2 becomes high, activating the pull-down transistor 142 (and the SSF loop) and deactivating the second FVF transistor (and the FVF loop). The SSF suppresses the voltage transient peak at the output 104. As the voltage at the output decreases to the nominal operating value, the voltage at the FVF node n2 becomes low, deactivating the pull-down transistor (and the SSF loop) and activating the second FVF transistor 128 (and the FVF loop).

[0066] LDO 100 consumes very low current (about 500nA) and is suitable for low power applications. For some applications, the output capacitance may include the parasitic capacitance of the on-chip decoupling capacitor (decap) (power supply decoupling capacitor (from power supply to ground)) and the digital load of the IC. Therefore, the capacitance may be about 100pF to 500pF. Therefore, the second pole is at the output terminal 104 and the main pole vg is at the gate of the channel transistor 118. During a load transient event, the gate node vg must move quickly in response to a sudden drop in the output. This is achieved using the channel capacitor Cm. For example, when the load changes from 0mA to 1mA in a step, the output voltage Vout at the output voltage terminal 104 drops and is coupled to the gate of the channel transistor 118 through the channel capacitor Cm, which in turn causes a sudden drop in the gate voltage Vg at the gate terminal of the channel transistor 118. This provides additional current through the channel transistor 118, which is supplied to the output load.

[0067] In this example, FVF 110 includes a startup transistor 131 (labeled as M5). Startup transistor 131 includes a PMOS transistor having: a source coupled to power supply voltage terminal 104; a drain coupled to the gate of pass transistor 118; and a gate configured to receive a power supply from a startup circuit (described below). Figure 4 The gate terminal of the startup signal of the LDO 110 is connected to the gate terminal of the startup signal of the LDO 110 (described in detail). When the control voltage Vctrl has not reached the nominal value, the startup transistor 131 is enabled (via the startup signal) during the startup of the LDO. When the control voltage Vctrl reaches the nominal value, the startup transistor 131 is disabled (via the startup signal). Once the startup transistor 131 is disabled, the FVF 110 starts to power on.

[0068] The design of the Wilson current mirror 116 is known and is only briefly described here for the sake of completeness. In this example, the Wilson current mirror 116 includes a first NMOS transistor 144, a second NMOS transistor 146, and a third NMOS transistor 148. The drain of the first NMOS transistor 144 is connected to the output current terminal 124. The gate of the first NMOS transistor 144 is connected to the input current terminal 122. The source of the first NMOS transistor 144 is connected to the drain of the second NMOS transistor 146. The source of the second NMOS transistor 146 is connected to the reference terminal 106. The gate of the second NMOS transistor 146 is connected to the drain of the second NMOS transistor 146 and the gate of the third NMOS transistor 148. The source of the third NMOS transistor 148 is connected to the reference terminal 106. The drain of the third NMOS transistor is connected to the input current terminal 122 (and the gate of the first NMOS transistor 144). The Wilson current mirror 116 additionally includes a mirror capacitor 150 connected between a node connecting the gates of the second NMOS transistor 146 and the third NMOS transistor 148 and the reference terminal 106 .

[0069] In this example, the feedforward Wilson current mirror 108 further includes a source follower circuit 152 coupled between the power supply voltage terminal 102 and the reference terminal 106. The source follower circuit 152 includes an NMOS source follower transistor 154, including: a drain terminal connected to the voltage source terminal 102; and a source terminal connected to the input current terminal 122. A source follower capacitor 156 is connected between the gate terminal of the source follower transistor 154 and the reference terminal 106. Two diode-connected NMOS transistors 158-1, 158-2 are connected between the gate terminal of the source follower transistor 154 and the reference terminal. A source follower current source 160 is connected between the power supply voltage terminal and the gate of the source follower transistor 154. In this example, the source follower current source 160 provides the same current as the input current source 114. Two diode-connected NMOS transistors 158-1, 158-2 provide a bias voltage Vb at the gate of the source follower transistor 154 and the gate of the second FVF transistor 128. In the event of a transient drop in the supply voltage at the supply voltage terminal 102, the source follower circuit 152 maintains the voltage at the input current terminal 122 and prevents it from going negative. In this way, the source follower circuit prevents the voltage at the input current terminal from dropping below a threshold current value.

[0070] Figure 4 FIG. 1 shows a circuit diagram of a circuit having additional control and output circuitry according to an embodiment of the present disclosure. Figure 1 LDO voltage regulator. Figure 4 Already in Figure 1Some features appearing in have been given corresponding numbers in the 400 series and will not necessarily be described again here.

[0071] LDO 400 includes the above Figure 1 A feed forward Wilson current mirror 408 and a FVF 410 are depicted. In this example, the LDO further includes a bias core circuit 462 and startup circuitry 464,466.

[0072] The bias core circuit 462 generates a control voltage Vctrl, which is coupled to the gate of the first FVF transistor and used as a reference for the FVF 410. The bias core circuit 462 includes a (precise) bandgap-based current reference source 468 coupled between the voltage source terminal 402 and a reference node 470 (labeled 1.2V). In this example, the current reference source 468 provides a precise current of 125nA. A first reference resistor 472 (labeled R1) is connected between the reference node 470 and the reference terminal 406. In this example, a reference capacitor is coupled in parallel with the first reference resistor 472. The first reference resistor has a resistance R1 to provide a reference voltage of 1.2V at the reference node 470 (R1=1.2 / 62.5e-9=19.2MΩ).

[0073] In this example, the bias core circuit includes another reference circuit system 480 for providing another reference circuit to a fast POR (power on reset) circuit (not shown) that can be coupled to the output terminal 404 of the LDO. The reference circuit system includes a reference transistor 479, which includes a PMOS transistor having: a source coupled to the reference node 470; a drain coupled to the second reference node 471; and a gate coupled to the second reference node 471. The second reference node 471 is coupled to the reference terminal 406 through a third bandgap-based reference current source 473, which provides a current of 125nA in this example. Another reference capacitor is coupled in parallel with the third bandgap-based reference current source 473.

[0074] In this example, the bias core circuit 462 includes: a second bandgap-based reference current source 474 coupled between the voltage source terminal 402 and the control voltage node; and a second reference resistor 478 coupled between the control voltage node 476 and the second reference voltage node 471. The second reference resistor is used to generate a 300mV voltage increase from the second reference node 471 to the control voltage node 476. In this way, the control voltage will include a vgs_ref of 1.5V, where vgs_ref is the gate-source voltage of the reference transistor 479. In this example, the second resistor includes a resistance of 4.8MΩ (R2=0.3 / 62.5e-9). The control voltage Vctrl providing a vgs_ref of 1.5 can provide a nominal output voltage of 1.5V at the output terminal 404 (due to the gate-source voltage step at the first FVF transistor 426).

[0075] In other examples, other known reference voltage generation methods may be used to generate the control voltage Vctrl and / or other reference voltages.The illustrated method using a bandgap reference current source advantageously provides a temperature compensated control voltage Vctrl.

[0076] In this example, the startup circuit system includes a startup circuit 456 and a bandgap startup reference circuit 464. The startup circuit 456 provides a startup signal to the gate of the startup transistor 431, as described above. The bandgap startup reference circuit 464 provides a bandgap startup signal (labeled as BG_SU) to the startup circuit. When the bandgap reference current sources 468, 474, 473 of the bias core circuit 462 rise, the bandgap startup reference current source 465 also rises and flows through the bandgap startup reference resistor RHIGH, thereby generating a bandgap startup signal BG_SU, which indicates that the bandgap current reference is rising (and Vctrl is at a nominal value (vgs_ref of 1.5V)). The startup circuit 466 is configured to receive the bandgap startup signal BG_SU and provide a corresponding startup signal to the gate of the startup transistor 431 of the FVF 410 to enable / disable the startup transistor 431 accordingly.

[0077] Figure 5 1 shows the performance of a voltage regulator according to an embodiment of the present disclosure. The voltage regulator may include Figure 1 or 4 LDOs.

[0078] The upper curve 582 shows the voltage transient of the supply voltage VDD at the supply terminal, including a voltage step from 1.8V to 5.4V when the LDO provides full load current. The two middle curves 584, 586 show the response of the gate voltage vg at the gate of the pass transistor to the supply voltage transient. The first middle curve 584 shows the voltage transient for Figure 14. The second intermediate curve 586 shows the response of the gate voltage vg for the same circuit but without the feed-forward capacitor. The first intermediate curve 584 and the second intermediate curve 586 indicate that the gate voltage vg increases as the power supply voltage VDD increases. The first intermediate curve 584 increases faster than the second intermediate curve 586 because the feed-forward capacitor helps the gate voltage vg track the power supply voltage VDD.

[0079] The two lower curves 588, 590 show the response of the output voltage at the output terminal to a supply voltage transient. The first lower curve 588 shows the Figure 1 The second lower curve 590 shows the output voltage response of the LDO of 4 or 1.5V. A small transient ripple can be found with a peak of less than 2V and a fast settling (<1us) to the nominal output voltage of 1.5V. Figure 1 or Figure 4 Figure 2. Response of the output voltage of the same circuit without the feed-forward capacitor. The output voltage rises above 4V and takes a long time (24us) to drop back to 1.5V.

[0080] Fig. 6A Show Figure 4 The response of an LDO to a transient on the supply voltage terminal, the transient comprising a square wave transient with increasing amplitude.

[0081] The first curve 691 shows the output voltage Vout of the LDO. The second curve 692 shows the power supply voltage on the power supply voltage terminal. The third curve 693 shows the output voltage check signal Vout_OK, which indicates that the output voltage of the LDO is normal. This is a combination of a fast POR and a slow POR (AND function). The fourth curve 694 shows the voltage of the fast POR circuit. The fifth curve 695 shows the voltage of the slow POR circuit.

[0082] The graph shows that the transient in the output voltage 691 remains below 2V and quickly settles back to 1.5V until the square wave amplitude becomes uncontrollable with respect to the supply voltage.

[0083] Figure 6B Show Figure 4 Figure 2. Response of an LDO during load and line step events. Specifically, the response to a test sequence (power on, load step, line boost, line buck, load release, line boost, line buck, and power off) is shown.

[0084] A first curve 691 shows the output voltage at the output terminal. A second curve 692 shows the supply voltage at the supply voltage terminal. A third curve 694 shows the voltage of the fast POR circuit. A fourth curve 696 shows the application and removal of a load current Iload of 1 mA. A fifth curve 697 shows the change of the voltage at the FVF node n2. A sixth curve 698 shows the change of the gate voltage vg of the pass transistor. A seventh curve 699 shows the voltage at the input current terminal.

[0085] The curve shows that the output voltage 699 remains close to 1.5V even in response to large voltage transients on the supply voltage 692 or in the load current 696. Small ripples in the output voltage 699 remain below 2.4V and quickly return to the nominal value of 1.5V.

[0086] The present disclosure provides a voltage regulator including a feedforward Wilson current mirror to generate a compensation current in response to a voltage transient. The compensation current can be used to control the gate voltage of a pass transistor of a FVF to reduce transients at the output. The FVF may include an SSF loop to quickly pull down the transient peak at the output. The feedforward Wilson current mirror and the FVF with SSF can be tuned to meet EMI requirements.

[0087] The disclosed voltage regulator can provide a stable, EMI-tolerant, low-power PMOS LDO that can withstand fast supply voltage changes and load transients and maintain proper regulation. The disclosed voltage regulator can operate at a low consumption current, thereby providing a low-power solution for the LDO of a CAN bus transceiver, which should always be available in a low-power mode.

[0088] Unless a specific order is explicitly stated, the instructions and / or flow chart steps in the above figures may be performed in any order. In addition, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to also produce other examples, and should be understood within the context provided in this detailed description.

[0089] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed with and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or to multiple components.

[0090] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. A non-transitory machine or computer usable medium as defined herein does not include signals, but such a medium is capable of receiving and processing information from signals and / or other transient media.

[0091] Example embodiments of the materials discussed in this specification may be implemented in whole or in part through a network, computer or data-based device and / or service. The network, computer or data-based device and / or service may include a cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0092] In one example, one or more instructions or steps discussed herein are automated. The term automation or automatic (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision making.

[0093] It should be understood that any components that are said to be coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled.

[0094] In this specification, example embodiments have been presented according to a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments may be practiced that include different sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A voltage regulator for outputting a regulated output voltage to an integrated circuit, characterized in that: The voltage regulator comprises: A voltage source terminal, used for receiving a power supply voltage; an output terminal, which is used to output the regulated output voltage; Reference terminal; Feed-forward Wilson current mirror, including: A Wilson current mirror having an input current terminal and an output current terminal; an input current source coupled between the power supply voltage terminal and the input current terminal of the Wilson current mirror; a feedforward capacitor arranged in parallel with the input current source; and an output current transistor having a conductive channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and The flip voltage follower FVF comprises: a pass transistor including a conductive channel coupled between the supply voltage terminal and the output terminal; a first FVF transistor having a conductive channel coupled between the output voltage and a FVF node; a second FVF transistor having a conductive channel coupled between a gate of the pass transistor and the FVF node; a third FVF transistor having a conductive channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein the gate of the third FVF transistor is coupled to the gate of the output current transistor; and A FVF current source is coupled between the FVF node and the reference terminal.

2. The voltage regulator according to claim 1, characterized in that The FVF additionally includes a pull-down transistor having a conductive channel coupled between the output terminal and the reference terminal and a gate terminal coupled to the FVF node.

3. The voltage regulator according to claim 1 or claim 2, characterized in that: The pull-down transistor is configured to activate in response to a supply voltage transient at the supply voltage terminal or a load transient at the output terminal.

4. The voltage regulator according to claim 3, characterized in that: The pull-down transistor includes an activation threshold such that the pull-down transistor is configured to activate in response to a supply voltage transient at the supply voltage terminal or a load transient at the output terminal.

5. The voltage regulator according to any one of claims 2 to 4, characterized in that: The pull-down transistor comprises an NMOS transistor.

6. A voltage regulator according to any preceding claim, characterised in that The feed-forward capacitor includes a PMOS transistor.

7. A voltage regulator according to any one of the preceding claims, characterised in that The FVF includes a channel capacitor coupled between the gate of the channel transistor and the output voltage terminal, wherein the channel capacitor includes a PMOS transistor.

8. The voltage regulator according to claim 7, characterized in that: The feed-forward capacitor includes a PMOS transistor of the same type as the pass capacitor.

9. A voltage regulator according to any preceding claim, characterised in that The voltage regulator is adapted to suppress voltage transients having a specific ramp rate, wherein a capacitance of the feed-forward capacitor is based on the ramp rate.

10. A transceiver for a controller area network, characterized in that: Comprising a voltage regulator according to any preceding claim.

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