Mobile device, envelope tracking system, and method of radio frequency signal amplification in mobile device

Abstract

To provide an envelope tracking system in which changes in power amplifier supply voltage arising from envelope tracking are compensated.SOLUTION: An envelope tracking system includes a power amplifier 250 that receives power from a power amplifier supply voltage VPA and amplifies a radio frequency (RF) signal RFIN. The power amplifier includes: an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal; a Wilson current minor 232; and a field-effect transistor NFET 231 for amplifying the RF signal. The Wilson current mirror includes: an input that receives a reference current IREF from a reference current source 236; and an output connected to the power amplifier supply voltage. The NFET amplifies an RF input signal to generate an RF output signal RFOUT. Additionally, a gate of the NFET is biased by an internal voltage of the Wilson current mirror and a source receives a ground voltage, while a drain receives the power amplifier supply voltage from a choke inductor 235.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic systems, and more particularly to power amplifiers for use in radio frequency (RF) electronic devices.

Background Art

[0002] Power amplifiers are used to amplify RF signals for transmission via an antenna in a radio frequency (RF) communication system. It is important to manage the power of RF signal transmission to extend battery life and / or provide an appropriate transmission power level.

[0003] Examples of RF communication systems having one or more power amplifiers include, but are not limited to, mobile phones, tablets, base stations, network access points, customer premise equipment (CPE), laptops, and wearable electronic devices. For example, in wireless devices that communicate using cellular standards, wireless local area network (WLAN) standards, and / or any other suitable communication standards, power amplifiers can be used for RF signal amplification. The RF signal can have a frequency in the range of about 30 kHz to about 300 GHz, such as, for example, in the range of about 410 MHz to about 7.125 GHz for 5G cellular communication in frequency range 1 (FR1) or in the range of about 24.250 GHz to about 52.600 GHz for frequency range 2 (FR2) of the 5G communication standard.

Summary of the Invention

[0004] In certain embodiments, the present disclosure relates to a portable device. The portable device includes a transceiver configured to generate a radio frequency signal and associated with the envelope of the radio frequency signal. ​​​​​​​​​​​​Power management including an envelope tracker configured to generate a varying power amplifier supply voltage A system and a front-end system including a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage. The power amplifier Includes an input configured to receive a reference current and a current mirror having an output electrically connected to the power amplifier supply voltage, and a field effect A transistor configured to amplify the radio frequency signal and having a gate biased based on the internal voltage of the current mirror. In various embodiments, the internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage and decreases in response to an increase in the power amplifier supply voltage. In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor. In some embodiments, the power amplifier further includes a choke inductor electrically connected between the power amplifier supply voltage section and the drain of the field effect transistor.

[0005] In some embodiments, the current mirror is a Wilson current mirror. In various embodiments, the power amplifier further includes a buffer configured to buffer the internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor. According to some embodiments, the buffer has zero shift for buffering.

[0006] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor. In some embodiments, the power amplifier further includes a choke inductor electrically connected between the power amplifier supply voltage section and the drain of the field effect transistor.

[0007] In some embodiments, the current mirror is a Wilson current mirror. In various embodiments, the power amplifier further includes a buffer configured to buffer the internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor.

[0008] In some embodiments, the current mirror is a Wilson current mirror.

[0009] In various embodiments, the power amplifier further includes a buffer configured to buffer the internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor. In some embodiments, the buffer is configured to buffer the internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor. According to some embodiments, the buffer has zero shift for buffering. A first depletion mode transistor and a second depletion mode transistor configured to provide a bias. Including.

[0010] In some embodiments, the current mirror includes a first mirror transistor having a drain configured to output an internal voltage, a second mirror transistor, a third mirror transistor, and a fourth mirror transistor. The third mirror transistor and the first mirror transistor are serially connected between the input portion of the current mirror and the ground voltage portion, and the fourth mirror transistor and the second mirror transistor are serially connected between the output portion of the current mirror and the ground voltage portion. According to a certain number of embodiments, the gate of the first mirror transistor is connected to the gate of the second mirror transistor, and the gate of the third mirror transistor is connected to the gate of the fourth mirror transistor. According to various embodiments, the drain of the second mirror transistor is connected to the gate of the second mirror transistor, and the drain of the third mirror transistor is connected to the gate of the third mirror transistor. Having a drain. Including a transistor and a fourth mirror transistor. The first mirror transistor is serially connected between the input portion of the current mirror and the ground voltage portion, and the fourth mirror transistor and the second mirror transistor are serially connected between the output portion of the current mirror and the ground voltage portion. In some embodiments, the power amplifier further includes a current source configured to generate a reference current. In some embodiments, the envelope tracker includes a DC / DC converter configured to output a plurality of regulated voltages, a modulator configured to generate a modulator output voltage at the output based on the plurality of regulated voltages and the envelope of the radio frequency signal, and a modulator output filter coupled between the output portion of the modulator and the power amplifier supply voltage portion. Connected to the gate of the second mirror transistor. Connected to the gate of the fourth mirror transistor. Connected to the gate of the second mirror transistor. Connected to the gate of the third mirror transistor.

[0011] In some embodiments, the power amplifier further includes a current source configured to generate a reference current. Including.

[0012] In some embodiments, the envelope tracker includes a DC / DC converter configured to output a plurality of regulated voltages, a modulator configured to generate a modulator output voltage at the output based on the plurality of regulated voltages and the envelope of the radio frequency signal, and a modulator output filter coupled between the output portion of the modulator and the power amplifier supply voltage portion. Based on the plurality of regulated voltages and the envelope of the radio frequency signal. To generate a modulator output voltage at the output. Including a modulator output filter coupled between the output portion of the modulator and the power amplifier supply voltage portion.

[0013] In various embodiments, the envelope tracker includes a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate a power amplifier supply voltage.

[0014] In a particular embodiment, the present disclosure relates to an envelope tracking system. The envelope tracking system includes an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to the envelope of a radio frequency signal, and a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage. The power amplifier includes an input configured to receive a reference current, and an output electrically connected to the power amplifier supply voltage, a current mirror, and a field effect transistor configured to amplify the radio frequency signal and having a gate biased based on an internal voltage of the current mirror.

[0015] In various embodiments, the internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage and decreases in response to an increase in the power amplifier supply voltage.

[0016] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor.

[0017] In some embodiments, the power amplifier further includes a choke inductor electrically connected between the power amplifier supply voltage section and the drain of the field effect transistor.

[0018] In various embodiments, the current mirror is a Wilson current mirror.

[0019] In some embodiments, the power amplifier further comprises a gate barrier of the field effect transistor. Configured to buffer the internal voltage of the current mirror to generate a bias voltage According to a number of embodiments, the buffer includes a zero buffer for buffering. A first depletion mode transistor and a second depletion mode transistor configured to provide a Includes a region-mode transistor.

[0020] In some embodiments, the current mirror is configured to output the internal voltage. A first mirror transistor having a drain, a second mirror transistor, and a third mirror transistor. a third mirror transistor and a fourth mirror transistor; The first transistor is connected in series between the input section of the current mirror and the ground voltage section. The fourth mirror transistor and the second mirror transistor are connected to the output of the current mirror and to ground. In a number of embodiments, the first mirror transistor is connected in series with the voltage section. The gate of the second mirror transistor is connected to the gate of the third mirror transistor. In various embodiments, the gate of the second mirror transistor is connected to the gate of the fourth mirror transistor. The drain of the first mirror transistor is connected to the gate of the second mirror transistor, and the drain of the second mirror transistor is connected to the gate of the third mirror transistor. The drain of the transistor is connected to the gate of a third mirror transistor.

[0021] In some embodiments, the power amplifier is further configured to generate a reference current. Includes a current source that is

[0022] In some embodiments, the envelope tracker is configured to output a plurality of regulated voltages. a DC / DC converter to be formed, and based on the plurality of adjusted voltages and the envelope of the radio frequency signal a modulator configured to generate a modulator output voltage in an output section accordingly, and a modulator output filter coupled between an output section of the modulator and a power amplifier supply voltage section. It includes.

[0023] In some embodiments, the envelope tracker includes a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate a power amplifier supply voltage.

[0024] In a given embodiment, the present disclosure relates to a method for amplifying a radio frequency signal in a portable device. The method includes generating a power amplifier supply voltage that varies in relation to the envelope of the radio frequency signal using an envelope tracker, supplying power to a power amplifier using the power amplifier supply voltage, amplifying the radio frequency signal using a field effect transistor of the power amplifier, and generating a gate bias voltage of the field effect transistor using an internal voltage of a current mirror of the power amplifier, wherein a reference current is supplied to an input section of the current mirror and the power amplifier supply voltage is supplied to an output section of the current mirror. It includes.

[0025] In various embodiments, the method includes increasing an internal voltage of the current mirror in response to a decrease in the power amplifier supply voltage and decreasing the internal voltage of the current mirror in response to an increase in the power amplifier supply voltage.

[0026] In some embodiments, the field effect transistor is a short-channel metal oxide semiconductor transistor.

[0027] In certain embodiments, the method further includes using a choke inductor for a power amplifier applying a supply voltage to the drain of the field effect transistor.

[0028] In some embodiments, the current mirror is a Wilson current mirror.

[0029] In various embodiments, the method further includes buffering an internal voltage of a current mirror to generate a gate bias voltage for the field effect transistor.

[0030] In certain embodiments, the method further includes using a current source to generate a reference current and the like.

[0031] In some embodiments, generating a power amplifier supply voltage includes outputting a plurality of regulated voltages from a DC / DC converter and using a modulator to generate a modulator output voltage based on the plurality of regulated voltages and an envelope of a radio frequency signal and using a modulator output filter to filter the modulator output voltage to generate the power amplifier supply voltage. and the like.

[0032] In some embodiments, generating a power amplifier supply voltage includes tracking an envelope using a parallel operating DC / DC converter and an error amplifier.

Brief Description of the Drawings

[0033]

Figure 1

Figure 2

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Figure 12

Best Mode for Carrying Out the Invention

[0034] The following detailed description of a particular embodiment represents various descriptions of the particular embodiment. However, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Although, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this description, drawings are referred to in which the same reference numerals may indicate identical or functionally similar elements. It is understood that the elements shown in the drawings are not necessarily to scale. It is further understood that a particular embodiment may include more elements than shown in the drawings and / or may include a subset of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings.

[0035] Figure 1 is a schematic diagram of an example of a portable device 100. The portable device 100 includes a baseband system 1, a transceiver 2, a front-end system 3, an antenna 4, a power management system 5, a memory 6, a user interface 7, and a battery 8. Figure 1 is a schematic diagram of an example of a portable device 100. The portable device 100 includes a baseband system 1, a transceiver 2, a front-end system 3, an antenna 4, a power management system 5, a memory 6, a user interface 7, and a battery 8. Figure 1 is a schematic diagram of an example of a portable device 100. The portable device 100 includes a baseband system 1, a transceiver 2, a front-end system 3, an antenna 4, a power management system 5, a memory 6, a user interface 7, and a battery 8.

[0036] The portable device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax), and / or GPS technology. The portable device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax), and / or GPS technology. The portable device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax), and / or GPS technology. The portable device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax), and / or GPS technology. The portable device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax), and / or GPS technology.

[0037] The transceiver 2 generates RF signals for transmission and receives incoming RF signals received from the antenna 4. Process the number. It is understood that various functions associated with the transmission and reception of RF signals can be achieved by one or more components collectively represented in FIG. 1 as transceiver 2. In one example, a separate component (e.g., a separate circuit or die) can be provided to handle a predetermined type of RF signal. (For example, a separate circuit or die) can be provided.

[0038] The front-end system 3 assists in conditioning the signals transmitted to and / or received from the antenna 4. In the illustrated embodiment, the front-end system 3 includes a power amplifier (PA) 11, a low-noise amplifier (LNA) 12, a filter 13, a switch 14, and a duplexer 15. However, other implementations are possible. In the illustrated embodiment, the front-end system 3 includes a power amplifier (PA) 11, a low-noise amplifier (LNA) 12, a filter 13, a switch 14, and a duplexer 15. However, other implementations are possible. For example, the front-end system 3 can provide a certain number of functions including, but not limited to, signal amplification for transmission, amplification of received signals, filtering of signals, switching between different bands, switching between different power modes, switching between transmission and reception modes, signal duplexing, signal multiplexing (e.g., diplexing or triplexing), or some combination thereof. However, other implementations are possible.

[0039] For example, the front-end system 3 can provide a certain number of functions including, but not limited to, signal amplification for transmission, amplification of received signals, filtering of signals, switching between different bands, switching between different power modes, switching between transmission and reception modes, signal duplexing, signal multiplexing (e.g., diplexing or triplexing), or some combination thereof. For example, the front-end system 3 can provide a certain number of functions including, but not limited to, signal amplification for transmission, amplification of received signals, filtering of signals, switching between different bands, switching between different power modes, switching between transmission and reception modes, signal duplexing, signal multiplexing (e.g., diplexing or triplexing), or some combination thereof. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels.

[0040] In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. In a given implementation, the mobile device 100 supports carrier aggregation, so flexibility is obtained to increase the peak data rate. Carrier aggregation can be used for both frequency-division duplexing (FDD) and time-division duplexing (TDD), and can be used to aggregate multiple carriers or channels. Carrier aggregation includes adjacent aggregation in which adjacent carriers within the same operating frequency band are aggregated. Carrier aggregation may also be discontinuous and may include carriers with frequencies separated within a common band and / or in different bands. / or may include carriers with frequencies separated in different bands.

[0041] Antenna 4 may include antennas used for a variety of types of communication. For example, antenna 4 may include antennas related to transmitting and / or receiving signals associated with a variety of frequencies and communication standards.

[0042] In a given implementation, antenna 4 supports MIMO communication and / or switch diversity communication. For example, MIMO communication uses multiple antennas to communicate multiple data streams via a single radio frequency channel. MIMO communication benefits from a high signal-to-noise ratio, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the wireless environment. Switch diversity refers to communication in which a specific antenna is selected to operate at a specific time. For example, a switch can be used to select a specific antenna from a group of antennas based on various factors such as the observed bit error rate and / or signal strength indicator.

[0043] antennas based on various factors such as the observed bit error rate and / or signal strength indicator.

[0043] In a given implementation, mobile device 100 may operate with beamforming. For example, the front-end system 3 may include a phase shifter whose variable phase is controlled by transceiver 2. Additionally, the phase shifter is controlled to provide beamforming and directivity for transmitting and / or receiving signals using antenna 4. For example, the letter is controlled to provide beamforming and directivity for transmitting and / or receiving signals using antenna 4. For example, the letter In the context of signal transmission, the phase of the transmission signal applied to antenna 4 is such that the signal radiated from antenna 4 is combined using constructive and destructive interference to generate a focused transmission signal that exhibits a beam-like quality of signal strength propagating in a given direction. In the context of signal reception, the phase is controlled such that when the signal arrives at antenna 4 from a specific direction, a large amount of signal energy is received. In a given implementation example, antenna 4 includes one or more arrays of a plurality of antenna elements to improve beamforming. The signal radiated from is combined using constructive and destructive interference to generate a focused transmission signal that exhibits a beam-like quality of signal strength propagating in a given direction. In the context of signal reception, the phase is controlled such that when the signal arrives at antenna 4 from a specific direction, a large amount of signal energy is received. In a given implementation example, antenna 4 includes one or more arrays of a plurality of antenna elements to improve beamforming. In the context of signal reception, the phase is controlled such that when the signal arrives at antenna 4 from a specific direction, a large amount of signal energy is received. In a given implementation example, antenna 4 includes one or more arrays of a plurality of antenna elements to improve beamforming. In a given implementation example, antenna 4 includes one or more arrays of a plurality of antenna elements to improve beamforming.

[0044] Baseband system 1 is coupled to user interface 7 to facilitate the processing of various user inputs and outputs (I / O), such as voice and data. Baseband system 1 processes the digital representation of the transmission signal to provide it to transceiver 2 to generate an RF signal for transmission. Baseband system 1 also processes the digital representation of the received signal provided by transceiver 2. As shown in FIG. 1, baseband system 1 is coupled to memory 6 to facilitate the operation of mobile device 100. Baseband system 1 is coupled to user interface 7 to facilitate the processing of various user inputs and outputs (I / O), such as voice and data. Baseband system 1 processes the digital representation of the transmission signal to provide it to transceiver 2 to generate an RF signal for transmission. Baseband system 1 processes the digital representation of the transmission signal to provide it to transceiver 2 to generate an RF signal for transmission. Baseband system 1 also processes the digital representation of the received signal provided by transceiver 2. As shown in FIG. 1, baseband system 1 is coupled to memory 6 to facilitate the operation of mobile device 100. Baseband system 1 also processes the digital representation of the received signal provided by transceiver 2. As shown in FIG. 1, baseband system 1 is coupled to memory 6 to facilitate the operation of mobile device 100.

[0045] Memory 6 can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of mobile device 100 and / or to provide storage for user information. Memory 6 can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of mobile device 100 and / or to provide storage for user information. Memory 6 can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of mobile device 100 and / or to provide storage for user information.

[0046] Power management system 5 provides a number of power management functions for mobile device 100. The power management system 5 of FIG. 1 includes an envelope tracker 60. As shown in FIG. 1, power management system 5 receives the battery voltage from battery 8. Battery 8 is used in mobile device 100. Power management system 5 provides a number of power management functions for mobile device 100. The power management system 5 of FIG. 1 includes an envelope tracker 60. As shown in FIG. 1, power management system 5 receives the battery voltage from battery 8. Power management system 5 provides a number of power management functions for mobile device 100. The power management system 5 of FIG. 1 includes an envelope tracker 60. As shown in FIG. 1, power management system 5 receives the battery voltage from battery 8. The battery may be any suitable battery, including, for example, a lithium ion battery.

[0047] The mobile device 100 of FIG. 1 includes a power amplifier implemented in accordance with one or more aspects of the present disclosure. 1 illustrates an example of an RF communication system that may include a The present invention is applicable to RF communication systems implemented in a variety of ways.

[0048] FIG. 2 illustrates an embodiment of a transmission system 130 for transmitting RF signals from a mobile device. 1 is a schematic diagram of a transmission system 130 including a battery 101, an envelope tracker 102, a power amplifier 103, and a power amplifier 104. amplifier 103, directional coupler 104, diplexing switching circuit 105, antenna 106, a baseband processor 107, a signal delay circuit 108, and a digital predistortion A differential photodiode (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, and an intermodulation detection circuit circuit 112, an envelope delay circuit 121, a coordinate rotation digital computation (CORDIC) circuit 122, It includes a shaping circuit 123 , a digital-to-analog converter 124 and a reconstruction filter 125 .

[0049] The transmitter system 130 of FIG. 2 includes a power amplifier implemented in accordance with one or more aspects of the present disclosure. 1 illustrates an example of an RF communication system that may include a The present invention is applicable to RF communication systems implemented in a variety of ways.

[0050] The baseband processor 107 generates a sinusoidal wave or signal of the desired amplitude, frequency and phase. The system operates to generate I and Q signals corresponding to signal components. For example, the I signal is The A signal is used to represent the in-phase component of a sine wave, and the Q signal is used to represent the quadrature component of the sine wave. These can be taken as equivalent representations of sine waves. In a given implementation, the I signal And the Q signal is provided to the I / Q modulator 110 in digital format. The baseband pro cessor 107 may be any suitable processor configured to process the baseband signal. For example, the baseband processor 107 may include a digital signal processor, a micro processor, a programmable core, or any combination thereof.

[0051] The signal delay circuit 108 provides an adjustable delay to the I and Q signals for the IN purpose of assisting in controlling the relative alignment between the envelope signal and the RF signal RF. The amount of delay provided by the signal delay circuit 1 08 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112.

[0052] The DPD circuit 109 operates to digitally shape the delayed I and Q signals from the signal delay circuit 108 to generate digitally pre-distorted I and Q signals. In the illus trated embodiment, the DPD provided by the DPD circuit 109 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112. The DPD circuit 109 serves to reduce the distortion of the power amplifier 1 03 and / or increase the efficiency of the power amplifier 103.

[0053] The I / Q modulator 110 receives the digitally pre-distorted I and Q signals, and these IN signals are processed to generate the RF signal RF. For example, the I / Q mod ulator 110 includes a DAC configured to convert the I and Q signals to analog format, a mixer that up-converts the I and Q signals to radio frequency, and an up-conversion Combine the processed I and Q signals into an RF signal suitable for amplification by the power amplifier 103 and may include a signal combiner. In a given implementation example, the I / Q modulator 110 may include one or more filters configured to filter the frequency content of the signal to be processed .

[0054] The envelope delay circuit 121 delays the I and Q signals from the baseband processor 107 . Additionally, the CORDIC circuit 122 processes the delayed I and Q signals and generates a digital envelope signal representing the envelope of the RF signal RF IN . Although FIG. 2 shows an implementation example using the CORDIC circuit 122, the envelope signal can also be obtained in other ways .

[0055] The shaping circuit 123 operates to shape the digital envelope signal to improve the performance of the transmission system 130. In a given implementation example, the shaping circuit 123 includes a shaping table that maps each level of the digital envelope signal to a corresponding level of the shaped envelope signal. Shaping the envelope can assist in controlling the linearity, distortion, and / or efficiency of the power amplifier 103 . . .

[0056] In the illustrated embodiment, the shaped envelope signal is a digital signal that is converted to an analog envelope signal by the DAC 124. Additionally, the analog envelope signal is filtered by the reconstruction filter 125 to generate an envelope signal suitable for use by the envelope tracker 102. In a given implementation example, the reconstruction filter 125 includes a low-pass filter . . .

[0057] ​​​​​Continuing to refer to FIG. 2, the envelope tracker 102 receives an envelope signal from the reconstruction filter 125 and the battery voltage V from the battery 101 BATT and uses the envelope signal to generate a power amplifier supply voltage V for the power amplifier 103 that varies in relation to the envelope of the RF signal RF IN . The power amplifier 103 receives the RF signal RF from the I / Q modulator 110 and, in this example, supplies the amplified RF signal RF to the antenna 106 via the duplexing switching circuit 105 PA . IN OUT

[0058] The directional coupler 104 is disposed between the output of the power amplifier 103 and the input of the duplexing switching circuit 105. This allows the output power of the power amplifier 103, excluding the insertion loss of the duplexing switching circuit 105, to be measured. The detected output signal from the directional coupler 104 is supplied to the observation receiver 111. The observation receiver 111 includes a mixer that downconverts the I signal component and the Q signal component of the detected output signal, and a DAC that generates an I observation signal and a Q observation signal from the downconverted signal.

[0059] The intermodulation detection circuit 112 determines the intermodulation product between the I observation signal and the Q observation signal and the I signal and the Q signal from the baseband processor 107. Additionally, the intermodulation detection circuit 112 controls the relative alignment between the envelope signal and the RF signal RF by controlling the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108. IN

[0060] ​​​​​​​​​​​​​​​ By including the output section of the power amplifier 103 and the feedback path from the baseband, the I and Q signals can be dynamically adjusted to optimize the operation of the transmission system 130. For example, by configuring the transmission system 130 in this manner, power control can be provided, compensating for transmitter failures, and / or performing DPD can be facilitated.

[0061] Although the power amplifier 103 is shown as a single stage, it may include one or more stages. Furthermore, an RF communication system such as a mobile device may include multiple power amplifiers. In such an implementation, separate envelope trackers can be provided for different power amplifiers, and / or one or more shared envelope trackers can be used.

[0062] Adaptive biasing for power amplifiers operating with envelope tracking

[0063] Envelope tracking is a technique that can be used to increase the power added efficiency (PAE ) of a power amplifier by efficiently controlling the voltage level of the power supply voltage in relation to the envelope of the RF signal amplified by the power amplifier. That is, when the envelope of the RF signal rises, the voltage supplied to the power amplifier can also rise. Similarly, when the envelope of the RF signal falls, the voltage supplied to the power amplifier also falls and power consumption decreases.

[0064] In one example, the envelope tracker includes a DC / DC converter that operates in combination with an error amplifier to generate the power amplifier supply voltage based on the envelope signal. For example, the DC / D C converter and the error amplifier can be electrically connected in parallel with each other, and the DC While the / DC converter can track the low-frequency components of the envelope signal, the error amplifier can track the high-frequency components of the envelope signal. For example, the switching frequency of the DC / DC converter can be reduced to be lower than the maximum frequency component of the envelope signal, and the error amplifier can operate to smooth the gap at the output of the converter to generate the power amplifier supply voltage. In a given implementation example, the DC / DC converter and the error amplifier can be coupled via a coupler. In other examples, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of multiple switches that controls the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage. An envelope tracking application has a power amplifier with an adaptive bias provided here. In a given embodiment, the envelope tracking system includes a power amplifier that amplifies an RF signal, the power amplifier receiving power from a power amplifier supply voltage section, and an envelope tracker that generates the power amplifier supply voltage based on the envelope of the RF signal. The power amplifier includes a field effect transistor (FET) that amplifies the RF signal, an input section that receives a reference current, and a current mirror that includes an output section connected to the power amplifier supply voltage. The internal voltage of the current mirror is used to bias the gate of the FET, so that the FET compensates for changes in the power amplifier supply voltage resulting from envelope tracking. The error amplifier can operate to smooth the gap at the output of the converter to generate the power amplifier supply voltage. In a given implementation example, the DC / DC converter and the error amplifier can be coupled via a coupler. In a given implementation example, the DC / DC converter and the error amplifier can be coupled via a coupler. In a given implementation example, the DC / DC converter and the error amplifier can be coupled via a coupler.

[0065] In other examples, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of multiple switches that controls the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage. In other examples, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of multiple switches that controls the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage. In other examples, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of multiple switches that controls the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage. In other examples, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of multiple switches that controls the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage.

[0066] An envelope tracking application has a power amplifier with an adaptive bias provided here. In a given embodiment, the envelope tracking system includes a power amplifier that amplifies an RF signal, the power amplifier receiving power from a power amplifier supply voltage section, and an envelope tracker that generates the power amplifier supply voltage based on the envelope of the RF signal. In a given embodiment, the envelope tracking system includes a power amplifier that amplifies an RF signal, the power amplifier receiving power from a power amplifier supply voltage section, and an envelope tracker that generates the power amplifier supply voltage based on the envelope of the RF signal. The power amplifier includes a field effect transistor (FET) that amplifies the RF signal, an input section that receives a reference current, and a current mirror that includes an output section connected to the power amplifier supply voltage. The power amplifier includes a field effect transistor (FET) that amplifies the RF signal, an input section that receives a reference current, and a current mirror that includes an output section connected to the power amplifier supply voltage. The power amplifier includes a field effect transistor (FET) that amplifies the RF signal, an input section that receives a reference current, and a current mirror that includes an output section connected to the power amplifier supply voltage. The internal voltage of the current mirror is used to bias the gate of the FET, so that the FET compensates for changes in the power amplifier supply voltage resulting from envelope tracking. The internal voltage of the current mirror is used to bias the gate of the FET, so that the FET compensates for changes in the power amplifier supply voltage resulting from envelope tracking.

[0067] By implementing an adaptive bias in a power amplifier, the non-idealities of the FETs in the power amplifier are compensated for. For example, such an adaptive bias helps to compensate for channel length modulation and / or drain-induced barrier lowering. Otherwise, high variations in RF gain versus power amplifier supply voltage are introduced. In a given implementation example, the FET is implemented as a short-channel metal-oxide-semiconductor (MOS) transistor. Despite the short-channel MOS transistor suffering from a certain number of transistor non-idealities, compensation is obtained by the adaptive bias such that the short-channel MOS transistor can be used in the power amplifier without significantly degrading the performance of the power amplifier. Since the short-channel MOS transistor can be fabricated in a process that is low-cost and / or enables high integration, it is desirable to implement the power amplifier using the short-channel MOS transistor in a number of applications. In a given implementation example, further, a buffer is included for buffering the internal voltage of a current mirror for generating the gate bias voltage of the FET. By including the buffer, the bandwidth can be improved and the transient response of the bias of the power amplifier can be speeded up, thereby improving amplitude distortion and phase distortion. The current mirror can be implemented in a wide variety of manners. In a given implementation example, the current mirror is implemented as a Wilson current mirror. For example, the current mirror is arranged as a four-transistor Wilson current mirror of n-type field-effect transistors.

[0068] In a given implementation example, the FET is implemented as a short-channel metal-oxide-semiconductor (MOS) transistor. Despite the short-channel MOS transistor suffering from a certain number of transistor non-idealities, compensation is obtained by the adaptive bias such that the short-channel MOS transistor can be used in the power amplifier without significantly degrading the performance of the power amplifier. Since the short-channel MOS transistor can be fabricated in a process that is low-cost and / or enables high integration, it is desirable to implement the power amplifier using the short-channel MOS transistor in a number of applications. In a given implementation example, further, a buffer is included for buffering the internal voltage of a current mirror for generating the gate bias voltage of the FET. By including the buffer, the bandwidth can be improved and the transient response of the bias of the power amplifier can be speeded up, thereby improving amplitude distortion and phase distortion.

[0069] The current mirror can be implemented in a wide variety of manners. In a given implementation example, the current mirror is implemented as a Wilson current mirror. For example, the current mirror is arranged as a four-transistor Wilson current mirror of n-type field-effect transistors. Since the short-channel MOS transistor can be fabricated in a process that is low-cost and / or enables high integration, it is desirable to implement the power amplifier using the short-channel MOS transistor in a number of applications.

[0070] The current mirror can be implemented in a wide variety of manners. In a given implementation example, the current mirror is implemented as a Wilson current mirror. For example, the current mirror is arranged as a four-transistor Wilson current mirror of n-type field-effect transistors. It can be implemented using a transistor (NFET). For example, four transistors The drain-source voltage of the first NFET of the Wilson mirror decreases as the output voltage decreases and increases, so as the power amplifier supply voltage decreases, the gain of the power amplifier increases and is well suited for this.

[0071] FIG. 3 is a schematic diagram of a power amplifier 250 according to an embodiment. The power amplifier 250 , NFET 231, Wilson current mirror 232, input DC block capacitor 2 33, output DC block capacitor 234, choke inductor 235 and reference current source 2 36.

[0072] Although FIG. 3 depicts an embodiment of a power amplifier with adaptive bias, the teachings herein are also applicable to power amplifiers implemented in a variety of ways.

[0073] The power amplifier 250 receives an RF input signal RF at an RF input terminal IN and provides an amplified RF output signal RF OUT to an RF output terminal. In the illustrated embodiment, the input DC block capacitor 233 is connected between the RF input terminal and the gate of the NFET 231 to allow biasing of the gate voltage of the NFET 231 separately from the DC voltage of the RF input terminal. Additionally, the output DC block capacitor 234 is connected between the drain of the NFET 231 and the RF output terminal to decouple the drain voltage of the NFET 231 from the DC voltage of the RF output terminal. As shown in FIG. 3, the choke inductor 235 supplies the power amplifier supply voltage V to the drain of the NFET 231

[0074] As shown in FIG. 3, the choke inductor 235 supplies power amplifier supply voltage V to the drain of the NFET 231 PA ​​to provide. Power amplifier supply voltage V PA is generated by an envelope tracking device including, but not limited to, any of the envelope tracking devices disclosed herein can be.

[0075] NFET231 amplifies the RF input signal RF IN to generate an RF output signal RF OUT is generated In addition, the gate of NFET231 is biased by the internal voltage of the Wilson current mirror 232. Further, while the source of NFET231 receives the ground voltage (ground) the drain of NFET231 receives the power amplifier supply voltage V from the choke inductor 235 PA In a given implementation example, NFET231 is implemented as an n-type metal oxide semiconductor (NMOS) transistor. For example, NFET231 may be a short-channel NMOS transistor.

[0076] The Wilson current mirror 232 has an input section that receives a reference current I REF from a reference current source 236 and an output section connected to the power amplifier supply voltage V PA . The Wilson current mirror 232 includes a first current mirror NFET241, a second current mirror NF ET242, a third current mirror NFET243, and a fourth current mirror NFET244 .

[0077] As shown in FIG. 3, the first current mirror NFET241 and the second current mirror 2 42 each include a source connected to the ground. In addition, the gate of the first current mirror NFET241 is connected to the gate and drain of the second current mirror NFET242 ​​​is connected and is connected to the source of the fourth current mirror NFET244. Additionally the output of the Wilson current mirror 232 is connected to the drain of the fourth current mirror NFET244, while the input of the Wilson current mirror 232 is connected to the gate of the fourth current mirror NFET244 and to the gate and drain of the third current mirror NFET243. Further, the drain of the first current mirror NFET241 and the drain of the third current mirror NFET243 are connected to each other.

[0078] In the illustrated embodiment, the internal voltage of the Wilson current mirror 232 is applied to the gate of the NFET231 to provide an adaptive bias. The internal voltage corresponds to the drain voltage of the first current mirror NFET241 in this embodiment.

[0079] The Wilson current mirror 232 operates to mirror the reference current I received at the input and generate an output current at the output. As the power amplifier supply voltage V changes due to envelope tracking, the drain voltage of the first current mirror NFET241 also changes such that the output current tracks the input current. As a result of the adjustment of the Wilson current mirror 232, the voltage across the drain and source of the first current source NFET241 increases as the power amplifier supply voltage V decreases. REF PA PA

[0080] The drain voltage of the first current mirror NFET241 is well-suited to increasing the gain of the power amplifier as the power amplifier supply voltage V decreases, and the power amplifier supply voltage V PA PA ​​​​​​​​​​​​​​​​​is well suited for reducing the gain of the power amplifier as [the relevant quantity] increases. That is , the Wilson current mirror 232 provides an adaptive bias to the NFET231 to compensate for gain variations resulting from power supply variations . Such an adaptive bias is well suited for compensating for short-channel effects (e.g ., channel length modulation and / or drain-induced barrier lowering) when the NFET 231 is implemented as a short-channel NMOS transistor .

[0081] FIG. 4A is a graph of an example of power gain versus output power of a power amplifier without an adaptive bias .

[0082] FIG. 4B is a graph of an example of power gain versus output power of a power amplifier with an adaptive bias .

[0083] As shown by comparison of FIGS. 4A and 4B, the adaptive bias reduces gain variations (e.g., reduced from about 15 dB to about 3 dB in this example).

[0084] FIG. 4C is a graph of an example of quiescent drain current versus supply voltage of a power amplifier without an adaptive bias .

[0085] FIG. 4D is a graph of an example of quiescent drain current versus supply voltage of a power amplifier with an adaptive bias .

[0086] As shown by comparison of FIGS. 4C and 4D, the adaptive bias reduces variations in quiescent drain current (e.g., reduced from about 12× to about 1.25× in this example ).

[0087] FIG. 5 is a schematic diagram of a power amplifier 280 according to another embodiment. The power amplifier 280 is , NFET231, Wilson current mirror 232, input DC block capacitor 2 33, output DC block capacitor 234, choke inductor 235, reference current source 27 0 and buffer 270.

[0088] The power amplifier 280 in FIG. 5 is similar to the power amplifier 250 in FIG. 3, but the power amplifier 280 further includes a buffer 270 for buffering the drain voltage of the first current mirror NFET 241 to generate the gate bias voltage of NFET231.

[0089] In the illustrated embodiment, the buffer 270 is implemented as a zero-shift buffer. This zero-shift buffer includes a first depletion mode (d-mode) FET 271 and a second d-mode FET 272. These may be, for example, junction field effect transistors (JFETs ETs) or Schottky gate FETs. The drain of the first d-mode FET 271 receives the battery voltage V BATT , while the gate of the first d-mode FET 271 receives the internal voltage of the Wilson · current mirror 232. Additionally, while the gate and source of the second d-mode FET 272 are connected to ground, the drain of the second d-mode FET 272 is connected to the source of the first d-mode FET 271 at the node that outputs the gate bias voltage to bias the NFET 231 of the power amplifier. Including the buffer 270 achieves an improved bandwidth and an improved transient response of the bias circuit of the power amplifier.

[0090] Including the buffer 270 achieves an improved bandwidth and an improved transient response of the bias circuit of the power amplifier.

[0091] FIG. 6A shows the amplitude distortion versus load power (l) of a power amplifier with an adaptive bias but without a buffer It is a graph of an example of (load power).

[0092] Figure 6B is a graph of an example of the amplitude distortion versus load power (load power) of a power amplifier with an adaptive bias and a buffer. It is a graph of an example of (load power).

[0093] As shown by the comparison between Figure 6A and Figure 6B, by using a buffer in combination with an adaptive bias, the amplitude distortion is reduced (AM / AM). By using it in combination with an adaptive bias, the amplitude distortion is reduced (AM / AM).

[0094] Figure 6C is a graph of an example of the phase distortion versus load power of a power amplifier with an adaptive bias but no buffer. It is a graph of an example.

[0095] Figure 6D is a graph of an example of the phase distortion versus load power of a power amplifier with an adaptive bias and a buffer. It is a graph of an example.

[0096] As shown by the comparison between Figure 6C and Figure 6D, by combining a buffer with an adaptive bias, the phase distortion is reduced (AM / PM). By combining it with an adaptive bias, the phase distortion is reduced (AM / PM).

[0097] Figure 7A is a graph of an example of the drain current versus drain voltage of a short-channel MOS transistor. Various plots of the drain current versus drain voltage at different gate-source voltages of the short-channel MOS transistor are depicted. Both plots are included when channel length modulation is not considered (dashed plot) and when channel length modulation is considered (solid plot). Plots of the drain current versus drain voltage at different gate-source voltages of the short-channel MOS transistor are depicted. Both plots are included when channel length modulation is not considered (dashed plot) and when channel length modulation is considered (solid plot). When channel length modulation is not considered (dashed plot) and when channel length modulation is considered (solid plot). Both plots are included when channel length modulation is not considered (dashed plot) and when channel length modulation is considered (solid plot). Both plots are included when channel length modulation is not considered (dashed plot) and when channel length modulation is considered (solid plot).

[0098] Figure 7B is a graph of an example of the drain current versus gate voltage of a short-channel MOS transistor. An example of the shift of the transistor threshold voltage resulting from drain-induced barrier lowering is depicted in the graph. An example of the shift of the transistor threshold voltage resulting from drain-induced barrier lowering is depicted in the graph. An example of the shift of the transistor threshold voltage resulting from drain-induced barrier lowering is depicted in the graph.

[0099] Figures 8A and 8B show two examples of power amplifier supply voltage versus time.

[0100] In Figure 8A, graph 447 shows an example of the voltage of RF signal 441 and power amplifier supply voltage 443 versus time. The RF signal 441 has an envelope 442.

[0101] Importantly, the power amplifier supply voltage 443 of the power amplifier has a voltage greater than that of the RF signal 441 . For example, applying power to the power amplifier using a power amplifier supply voltage having an amplitude smaller than the amplitude of the RF signal clips the RF signal and can result in signal distortion and / or other problems. That is, it may be important to keep the power amplifier supply voltage 4 43 larger than the envelope 442. However, the voltage difference between the power amplifier supply voltage 443 and the envelope 442 of the RF signal 441 is desirably reduced . This is because the area between the power amplifier supply voltage 443 and the envelope 442 can represent lost energy that reduces battery life and increases the heat generated in the wireless device .

[0102] In Figure 8B, graph 448 shows an example of the voltage of RF signal 441 and power amplifier supply voltage 444 versus time. In contrast to the power amplifier supply voltage 443 in Figure 8A, the power amplifier supply voltage 444 in Figure 8B changes in relation to the envelope 442 of the RF signal 441. Since the area between the power amplifier supply voltage 444 and the envelope 442 in Figure 8B is smaller than the area between the power amplifier supply voltage 443 and the envelope 442 in Figure 8A, the graph 4 48 in Figure 8B can be associated with a power amplifier with high energy efficiency.

[0103] ​​​​​​ FIG. 9A is a schematic diagram of an envelope tracking system 500 according to an embodiment. The envelope tracking system 500 includes a power amplifier 501 and an envelope tracker 502. The power amplifier 50 1 amplifies a radio frequency signal 503.

[0104] The envelope tracker 502 receives an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 502 generates a power amplifier supply voltage V to supply power to the power amplifier 501. PA

[0105] The illustrated envelope tracker 502 includes a DC / DC converter 511 and an error amplifier 512, which are combined with each other and operate to generate a power amplifier supply voltage V PA based on the envelope signal 504. In the illustrated embodiment, the output of the DC / DC converter 511 and the output of the error amplifier 512 are combined using a coupler 515.

[0106] The envelope tracker 502 in FIG. 9A shows an example of analog envelope tracking where switching regulators operate in parallel with each other to track the envelope of an RF signal.

[0107] FIG. 9B is a schematic diagram of an envelope tracking system 540 according to another embodiment. The envelope tracking system 540 includes a power amplifier 501 and an envelope tracker 532. The power amplifier 50 1 amplifies a radio frequency signal 503.

[0108] The envelope tracker 532 receives an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 532 generates a power amplifier supply voltage V to supply power to the power amplifier 501. PA ​

[0109] The illustrated envelope tracker 532 includes a multi-level switching circuit 535. In a given implementation example, the multi-level switching circuit generates regulated voltages of different voltage levels and includes a multi-output DC / DC converter, a plurality of switches that control the selection of an appropriate regulated voltage over time based on an envelope signal, and a filter that filters the output of the switches to generate a power amplifier supply voltage.

[0110] The envelope tracker 532 of FIG. 9B shows an example of MLS envelope tracking.

[0111] FIG. 10 is a schematic diagram of an envelope tracking system according to another embodiment. The envelope tracking system 600 includes a power amplifier 501 and an envelope tracker 602. The power amplifier 501 amplifies a radio frequency signal 503.

[0112] The envelope tracker 602 receives an envelope signal corresponding to the envelope of the radio frequency signal 503. In this example, the envelope signal is differential. Additionally, the envelope tracker 602 generates a power amplifier supply voltage V PA to supply power to the power amplifier 501.

[0113] The illustrated envelope tracker 602 includes an envelope amplifier 611, a first comparator 621, a second comparator 622, a third comparator 623, a coding / dithering circuit 624, a multi-output boost switcher 625, a filter 626, a switch bank 627, and a capacitor bank 630. The capacitor bank 630 includes a first capacitor 631, a second capacitor 632, and a third capacitor 633. Additionally, the switch bank 627 includes a first switch 641, a It includes a second switch 642 and a third switch 643.

[0114] The envelope amplifier 611 amplifies the envelope signal and supplies the amplified envelope signal to the first comparator 621 to the third comparator 623. The first comparator 621 to the third comparator 623 compare the amplified envelope signal with the first threshold value T1, the second threshold value T2, and the third threshold value T3 respectively. The result of the comparison is supplied to the coding and dithering circuit 624. The coding and dithering circuit 624 processes the result to control the selection of the switches in the switch bank 627. The coding and dithering circuit 624 can reduce the artifacts generated from the opening and closing of the switches while activating the switches by using coding and / or dithering. Although an example having three comparators is shown, more or fewer comparators may be used. Further, the coding and dithering circuit 624 may be omitted and other aspects may be selected to control the switch bank. In the first example, coding is used but dithering is not used. In the second example, dithering is used but coding is not used. In the third example, neither coding nor dithering is used.

[0115]

[0116]

[0116] The multi-output boost switch 625 generates a first regulated voltage V BATT based on providing DC / DC conversion of the battery voltage V, a second regulated voltage V MLS1 and a third regulated voltage V MLS2 and a third regulated voltage V MLS3 Although an example having three regulated voltages is shown, Rather, the multi-output boost switch 625 can generate a greater or lesser regulated voltage. In certain implementations, at least some of these regulated voltages are boosted relative to the battery voltage V BATT . In some configurations, one or more of these regulated voltages are buck voltages having a voltage lower than the battery voltage V BATT .

[0117] The capacitor bank 630 assists in stabilizing the regulated voltage generated by the multi-output boost switch 625. For example, capacitors 631-633 operate as decoupling capacitors.

[0118] The filter 626 processes the output of the switch bank 627 to generate the power amplifier supply voltage V PA . By controlling the selection of switches 641-643 over time based on an envelope signal, a power amplifier supply voltage V PA that tracks the envelope signal is generated.

[0119] FIG. 11A is a schematic diagram of one embodiment of a packaged module 800. FIG. 11 B is a schematic cross-sectional view of the packaged module 800 taken along line 11B-11B of FIG. 11A.

[0120] The packaged module 800 includes an IC or die 801, surface mount components 80 3, wire bonds 808, a package substrate 820, and an encapsulation structure 840. The package substrate 820 includes pads 806 formed from conductors disposed thereon. Additionally, the die 801 includes pads 804, and the wire bonds 808 couple the pads 804 of the die 801 to It is used to be electrically connected to the pad 806 of the package substrate 820.

[0121] The die 801 can be implemented according to any of the embodiments herein and includes a power amplifier 846.

[0122] The package substrate 820 can be configured to receive a plurality of components, including the die 801 and surface mount components 803 that may include, for example, surface mount capacitors and / or inductors. It can be configured to accommodate.

[0123] As shown in FIG. 11B, the package module 800 is shown to include a plurality of contact pads 832 disposed on the side opposite to the side of the package module 800 where the die 801 is to be attached. By configuring the package module 800 in this manner, it is assisted in connecting the package module 800 to a circuit board such as a telephone board of a wireless device. Examples of the contact pads 832 can be configured to provide RF signals, bias signals, power low voltage and / or power high voltage to the die 801 and / or the surface mount components 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. It can be configured to facilitate connecting the package module 800 to a circuit board such as a telephone board of a wireless device. Examples of the contact pads 832 can be configured to provide RF signals, bias signals, power low voltage and / or power high voltage to the die 801 and / or the surface mount components 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate. 803. As shown in FIG. 11B, the electrical connection between the contact pads 832 and the die 801 can be facilitated by a connection 833 through the package substrate 820. The connection 833 can represent an electrical path formed to pass through the package substrate 820, such as a connection associated with vias and conductors of a multilayer laminated package substrate.

[0124] In some embodiments, the package module 800 may also include one or more package structures that provide protection for and / or facilitate handling of, for example, the package module 800. may include a package structure. Such a package structure may include a package substrate 820 and an overmold or encapsulation structure 840 formed to cover components and dies disposed thereon. It should be understood that although the packaged module 800 is described in the context of wire bond-based electrical connection, one or more features of the present disclosure can also be implemented in other package configurations including, for example, a flip chip configuration.

[0125]

[0126] FIG. 12 is a schematic diagram of an embodiment of a telephone substrate. The telephone substrate 900 includes the module 800 shown in FIGS. 11A and 11B attached hereto. Although not shown in FIG. 12 for clarity, the telephone substrate 900 may include additional components and structures.

[0127] Application

[0128] Some of the embodiments described above have given examples related to wireless devices or mobile phones. However, the principles and advantages of those embodiments can be used in any other system or device that requires a power amplifier.

[0129] Such an envelope tracker can be implemented in various electronic devices. Examples of electronic devices can include, but are not limited to, consumer electronics products, components of such consumer electronics products, electronic test equipment, etc. Examples of electronic devices can also include, but are not limited to, memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. Consumer electronics products include mobile phones, telephones, televisions, computers ​ a data monitor, a computer, a handheld computer, a personal digital assistant (PDA), a microwave oven, a refrigerator, an automobile, a stereo system, a cassette recorder or a player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a video camera, a camera, a digital camera, a portable memory chip, a washing machine, a dryer, a washing / drying machine, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wristwatch, a table clock, etc., but not limited thereto. Further, the electronic device may include an unfinished product. Summary

[0130] Throughout this specification and the entire scope of the claims, unless the context clearly dictates otherwise

[0131] terms such as "including" are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to". The commonly used term "coupled" herein refers to two or more elements that can be either directly connected or connected through one or more intermediate elements. Similarly, the commonly used term "connected" herein refers to two or more elements that can be either directly connected or connected through one or more intermediate elements. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular, individual part of the application. Where the context permits, the terms in the above detailed description using the singular or plural may each also include the plural or singular. The words "or" and "or alternatively" referring to a list of two or more items cover all of the following interpretations of that word; that is, the list ​​​​​​​​​​​​​Any item of the list, all items of the list, and any combination of items of the list is as follows.

[0132] Furthermore, conditional language described herein such as, among others, "can," "is capable of," "may," "might," "for example," "such as," etc. generally is not intended to convey that a given embodiment includes a given feature, element, and / or state while other embodiments do not, unless specifically stated otherwise or understood from the context of use to be so. That is, such conditional language is generally not intended to suggest that a feature, element, and / or state is in any way required for one or more embodiments, or that one or more embodiments necessarily include or perform such feature, element, and / or state, with or without the author's input or prompting, and determine whether such feature, element, and / or state is included in or performed by any particular embodiment or not.

[0133] The above detailed description of embodiments of the invention is not intended to be exclusive, i.e., to limit the invention to the exact forms disclosed. Specific embodiments of the invention and examples thereof have been described above for illustrative purposes, but as will be recognized by those skilled in the art, various equivalent modifications are possible within the scope of the invention. For example, although a process or block is presented in a given order, alternative embodiments can perform routines having steps in a different order or use systems having blocks, and some processes or blocks can be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in a variety of different ways. Also, although processes or blocks are performed serially​ Although they may be shown as being sequential, these processes or blocks may instead be performed in parallel or at different times.

[0134] The teachings of the invention provided herein are not necessarily limited to the systems described above, and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments.

[0135] Although several embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. In fact, the novel methods and systems described herein can be embodied in a variety of other forms. Further, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the disclosure. ​

Claims

1. 1. A mobile device comprising: a transceiver configured to generate a radio frequency signal; configured to generate a power amplifier supply voltage that varies in relation to the envelope of the radio frequency signal. a power management system including an envelope tracker configured to a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; A front-end system including a power amplifier configured as a Including, The power amplifier includes: an input configured to receive a reference current; and a power amplifier supply voltage; a current mirror including an output section having a A current mirror is configured to amplify the radio frequency signal and to provide an internal voltage to the current mirror. a field effect transistor having a gate biased based on the , including mobile devices.

2. The internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage.

2. The portable device of claim 1, wherein the power amplifier supply voltage is decreased in response to an increase in the power amplifier supply voltage.

3. 2. The method of claim 1, wherein the field effect transistor is a short channel metal oxide semiconductor transistor. on your mobile device.

4. The power amplifier further comprises a power amplifier supply voltage section and a drain of the field effect transistor. The portable device of claim 1 , further comprising a choke inductor electrically connected between the

5. The portable device of claim 1 , wherein the current mirror is a Wilson current mirror.

6. The power amplifier further buffers the internal voltage of the current mirror to a buffer configured to generate a gate bias voltage for the effect transistor, The mobile device of claim 1.

7. The buffer includes a first depletion buffer configured to provide a zero shift to the buffer ring.

7. The method of claim 6, further comprising: on your mobile device.

8. The current mirror includes: a first mirror transistor having a drain configured to output the internal voltage; A second mirror transistor; and A third mirror transistor; and A fourth mirror transistor; Including, The third mirror transistor and the first mirror transistor are connected to the input of the current mirror. connected in series between the power section and the ground voltage section, The fourth mirror transistor and the second mirror transistor are connected to the output of the current mirror. The hand-held device of claim 1 , wherein the power supply is connected in series between the power supply and the ground voltage.

9. The gate of the first mirror transistor is connected to the gate of the second mirror transistor. 、 The gate of the third mirror transistor is connected to the gate of the fourth mirror transistor. The mobile device of claim 8.

10. The drain of the second mirror transistor is connected to the gate of the second mirror transistor. R, The drain of the third mirror transistor is connected to the gate of the third mirror transistor. The mobile device of claim 9.

11. The power amplifier further comprises a current source configured to generate the reference current. Item 1. A mobile device.

12. 1. An envelope tracking system comprising: configured to generate a power amplifier supply voltage that varies in relation to the envelope of a radio frequency signal; an envelope tracker for a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; A power amplifier and Including, The power amplifier includes: an input configured to receive a reference current; and a power amplifier supply voltage; a current mirror including an output section having a A current mirror is configured to amplify the radio frequency signal and to provide an internal voltage to the current mirror. a field effect transistor having a gate biased based on the An envelope tracking system comprising:

13. The internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage.

13. The envelope tracking system of claim 12, wherein the envelope tracking frequency decreases in response to an increase in the power amplifier supply voltage.

14. 2. The method of claim 1, wherein the field effect transistor is a short channel metal oxide semiconductor transistor. 2 envelope tracking system.

15. 13. The envelope tracking system of claim 12, wherein the current mirror is a Wilson current mirror. Tem.

16. The power amplifier further buffers the internal voltage of the current mirror to a buffer configured to generate a gate bias voltage for the effect transistor, The envelope tracking system of claim 12.

17. The current mirror includes: a first mirror transistor having a drain configured to output the internal voltage; A second mirror transistor; and A third mirror transistor; and A fourth mirror transistor; Including, The third mirror transistor and the first mirror transistor are connected to the input of the current mirror. connected in series between the power section and the ground voltage section, The fourth mirror transistor and the second mirror transistor are connected to the output of the current mirror.

13. The envelope tracking system of claim 12, wherein the power supply is connected in series between the power supply and the ground voltage.

18. 1. A method of radio frequency signal amplification in a mobile device, comprising: An envelope tracker is used to track the power amplifier supply voltage which varies in relation to the envelope of the radio frequency signal. Generating pressure; powering a power amplifier using the power amplifier supply voltage; amplifying the radio frequency signal using a field effect transistor of the power amplifier; 、 The internal voltage of the current mirror of the power amplifier is used to drive the gate of the field effect transistor. a reference current is applied to the input of the current mirror to generate a bias voltage; and providing said power amplifier supply voltage to an output of said current mirror. The method includes:

19. increasing an internal voltage of the current mirror in response to a decrease in the power amplifier supply voltage. And, decreasing an internal voltage of the current mirror in response to an increase in the power amplifier supply voltage. Toto The method of claim 18 further comprising:

20. of the current mirror to generate a gate bias voltage of the field effect transistor.

20. The method of claim 18, further comprising buffering the internal voltage.

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