Cache management method and device, cache, electronic device and storage medium

Abstract

The invention discloses a cache management method and device, a cache, an electronic device and a storage medium. The cache comprises a plurality of groups, and each group comprises multiple paths of data blocks which are not 2 integer power. The cache management method comprises the steps that a binary tree structure corresponding to multiple paths of data blocks of each group in multiple groups is obtained, each leaf node of the binary tree structure corresponds to one path of multiple paths, replacement information is recorded in non-leaf nodes of the binary tree structure, and at least one path of the multiple paths belongs to two partitions of the bottom layer of the binary tree structure at the same time; and in response to replacement operation on the multi-path data blocks of any one of the multiple groups, starting to search from a root node of the binary tree structure until a target path meeting a replacement strategy is searched. According to the cache management method, through multiplexing of leaf nodes in a binary tree structure, a replacement strategy of a non-2 integer power path is realized.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a cache management method and device, a cache, an electronic device, and a storage medium. Background Art

[0002] In high-performance computer systems, memory performance plays an important role. Cache is the simplest and most cost-effective way to achieve higher memory performance. When implementing a large-capacity cache, a multi-way set associative approach is generally adopted. When the data block size is fixed, the number of sets and ways of the multi-way set associative structure cache is determined according to the specific performance requirements and hardware overhead constraints during processor design.

[0003] In order to achieve a good balance between performance and cost, it is generally necessary to perform adaptive cache management on the multi-way data blocks of each of the multiple groups in the cache to achieve different functions such as cache replacement and cache access. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a cache management method, wherein the cache includes multiple groups, each of the multiple groups includes multi-way data blocks of non-integer power of 2, and the cache management method includes: obtaining a binary tree structure corresponding to the multi-way data blocks of each of the multiple groups, wherein each leaf node of the binary tree structure corresponds to one of the multiple ways, replacement information is recorded in the non-leaf nodes of the binary tree structure, and at least one of the multiple ways simultaneously belongs to two partitions at the bottom layer of the binary tree structure; in response to a replacement operation on the multi-way data blocks of any one of the multiple groups, searching from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found.

[0005] For example, the cache management method provided by at least one embodiment of the present disclosure further includes: in response to an access operation to a multi-way data block of each of the multiple groups, updating the replacement information recorded in the non-leaf node of the binary tree structure.

[0006] For example, in the cache management method provided by at least one embodiment of the present disclosure, the access operation includes a data block read, a data block write, or a data block allocation operation.

[0007] For example, in the cache management method provided by at least one embodiment of the present disclosure, in response to the access operation of the multi-way data blocks of each group in the multiple groups, the replacement information recorded in the non-leaf node of the binary tree structure is updated, including: for each non-leaf node in the binary tree structure: in response to the leaf node where the target data block of the access operation is located in the left half partition of the non-leaf node, the replacement information of the non-leaf node is set to a first value; in response to the leaf node where the target data block of the access operation is located in the right half partition of the non-leaf node, the replacement information of the non-leaf node is set to a second value different from the first value; in response to the leaf node where the target data block of the access operation is located in both the left and right half partitions of the non-leaf node, the replacement information of the non-leaf node is set to remain unchanged.

[0008] For example, in the cache management method provided by at least one embodiment of the present disclosure, in response to performing a replacement operation on a multi-way data block of any one of the multiple groups, searching starts from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found, including: for each non-leaf node in the binary tree structure: in response to the replacement information of the non-leaf node being the first value, searching the right half partition of the non-leaf node; in response to the replacement information of the non-leaf node being the second value, searching the left half partition of the non-leaf node.

[0009] For example, in the cache management method provided by at least one embodiment of the present disclosure, each leaf node also stores tag information, validity information, and dirty bit information of the corresponding data block.

[0010] For example, the cache management method provided by at least one embodiment of the present disclosure, in response to performing a replacement operation on multi-way data blocks of any one of the multiple groups, searching from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found, further includes: in response to dirty bit information of the data block of the target way being true, performing a write-back operation on the data block of the target way, and then backfilling data on the data block of the target way.

[0011] For example, the cache management method provided by at least one embodiment of the present disclosure, in response to performing a replacement operation on a multi-way data block of any one of the multiple groups, starts searching from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found, and also includes: determining that the valid bit information of each data block in the multi-way data block is valid.

[0012] For example, in the cache management method provided by at least one embodiment of the present disclosure, the binary tree structure is a full binary tree.

[0013] For example, in the cache management method provided by at least one embodiment of the present disclosure, obtaining the binary tree structure of the multi-way data blocks corresponding to each group in the multiple groups includes: using an array to record the binary tree structure, wherein the number of bits of the array is the same as the number of non-leaf nodes of the binary tree structure.

[0014] At least one embodiment of the present disclosure further provides a cache management device, wherein the cache includes multiple groups, each of the multiple groups includes multi-way data blocks of a non-integer power of 2, and the cache management device includes: an acquisition unit, configured to acquire a binary tree structure corresponding to the multi-way data blocks of each group in the multiple groups, wherein each leaf node of the binary tree structure corresponds to one of the multiple ways, replacement information is recorded in the non-leaf nodes of the binary tree structure, and at least one of the multiple ways simultaneously belongs to two partitions at the bottom of the binary tree structure; and an operation unit, configured to, in response to a replacement operation on the multi-way data blocks of any one of the multiple groups, search from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found.

[0015] For example, in the cache management device provided by at least one embodiment of the present disclosure, the operation unit is also configured to update the replacement information recorded in the non-leaf node of the binary tree structure in response to the access operation of the multi-way data blocks of each group in the multiple groups.

[0016] At least one embodiment of the present disclosure further provides a cache, comprising: a plurality of groups, wherein each of the plurality of groups comprises multi-way data blocks of a non-integer power of 2; a cache management device, comprising: an acquisition unit, configured to acquire a binary tree structure corresponding to the multi-way data blocks of each of the plurality of groups, wherein each leaf node of the binary tree structure corresponds to one of the multi-ways, replacement information is recorded in non-leaf nodes of the binary tree structure, and at least one of the multi-ways simultaneously belongs to two partitions at the bottom layer of the binary tree structure; an operation unit, configured to, in response to a replacement operation being performed on the multi-way data blocks of any one of the plurality of groups, search from the root node of the binary tree structure until a target way satisfying the replacement strategy is found.

[0017] At least one embodiment of the present disclosure further provides an electronic device, comprising the cache provided by any embodiment of the present disclosure.

[0018] At least one embodiment of the present disclosure further provides a cache management device, comprising: at least one processing unit; and at least one memory storing computer executable instructions, wherein the computer executable instructions, when executed by the at least one processing unit, implement the cache management method of any embodiment of the present disclosure.

[0019] At least one embodiment of the present disclosure further provides a non-volatile storage medium storing computer executable instructions, wherein the computer executable instructions, when executed by at least one processing unit, implement the cache management method of any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 Schematic diagram of a full binary tree structure used for 2-way data blocks in a pLRU strategy.

[0022] Figure 2 for Figure 1 Schematic diagram of the replacement strategy for 2-way data blocks in the pLRU strategy shown.

[0023] Figure 3 A schematic diagram of a full binary tree structure used for 8-way data blocks in a pLRU strategy.

[0024] Figure 4 Schematic diagram of a non-full binary tree structure used for 3-way data blocks in a pLRU strategy.

[0025] Figure 5 for Figure 4 Schematic diagram of the replacement strategy for 3-way data blocks in the pLRU strategy shown.

[0026] Figure 6 A flowchart of a cache management method provided by at least one embodiment of the present disclosure.

[0027] Figure 7 A schematic diagram of a process for updating and replacing information provided in at least one embodiment of the present disclosure.

[0028] Figure 8 A schematic diagram of a process of searching a target path through a binary tree structure is provided for at least one embodiment of the present disclosure.

[0029] Fig. 9 A schematic diagram of a replacement strategy for a 3-way data block is provided as a specific example of a cache management method provided by at least one embodiment of the present disclosure.

[0030] Fig.10 A schematic diagram of a binary tree structure used for a 10-way data block is another specific example of the cache management method provided in at least one embodiment of the present disclosure.

[0031] Fig.11 A schematic block diagram of a cache management device provided in at least one embodiment of the present disclosure.

[0032] Fig.12 A schematic block diagram of yet another cache management device provided for at least one embodiment of the present disclosure.

[0033] Fig.13 A schematic block diagram of an electronic device provided according to at least one embodiment of the present disclosure.

[0034] Fig.14 A schematic diagram of a non-volatile storage medium provided for at least one embodiment of the present disclosure.

[0035] Fig.15 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Cache is a high-speed memory used to temporarily store frequently accessed data to reduce the number of times the main memory is accessed, thereby improving system performance. The capacity of the cache is very small, and the content stored in the cache is only a subset of the main memory content, and the data exchange between the cache and the main memory is in blocks. The smallest operating unit of the cache is the cache line (also referred to as "data block" in this disclosure). The array of cache blocks usually adopts a set-associative organization and addressing method, in which the cache is organized in the form of an array of cache blocks, a column of cache blocks forms a way, and multiple cache blocks at the same position in multiple columns of cache blocks form a set; the location of the data or instruction in the cache is obtained through the physical address of the data or instruction to be read (set, way, byte), and each physical address is divided into three parts:

[0039] (a) Index: used to select a set in the cache. All cache lines in the same set are selected by the index.

[0040] (b) Tag, used to select a specific cache line in a set. The tag of the physical address is compared with the tag of each cache line. If they match, it is a cache hit, thus selecting this cache line. Otherwise, it is a cache miss.

[0041] (c) Offset: This is used to select the corresponding address in the cache line. It indicates the first byte of the physical address in the cache line. The corresponding data or instruction is read from the position of this byte.

[0042] Cache replacement refers to how to select and replace cache blocks in the cache when the cache itself is full, in order to make room for new data, thereby improving cache hit performance. Common cache replacement strategies include First-In-First-Out (FIFO), Least Recently Used (LRU), Least Frequently Used (LFU), Random Replacement (RAND), Pseudo-LRU (PLRU), and Least Frequently Used with Aging (LFU). Different strategies are suitable for different application scenarios and performance requirements.

[0043] Each cache block has a valid bit, which indicates whether the data in the cache block is valid. For example, if the valid bit is 1, the data in the cache block is valid; if it is 0, the cache block is empty or invalid. If there is an invalid way in the same group in the cache, when writing (such as backfilling) data to the cache block, the invalid way can be directly selected for allocation, and no cache block replacement is required.

[0044] Each cache block also has a dirty bit. During the operation of the cache, when a cache block is marked as "dirty", it means that the data in the cache block has been modified, but these modifications have not yet been written back to the main memory. When such a cache block needs to be replaced, the dirty data must first be written back to the main memory. This process is called a write back operation. After the write back operation is completed, the dirty bit is cleared and set to 0. The write back strategy allows the data in the cache to remain consistent during multiple read and write operations, improving the cache hit rate.

[0045] At present, cache replacement strategies in most scenarios are improved based on the cache replacement strategy (Least-Recently-Used, referred to as LRU). Pseudo-LRU is a cache replacement strategy that approximates LRU. It uses less storage space to record the usage of multiple data blocks, thereby achieving an effect similar to LRU at a lower cost.

[0046] A cache management method adopted by LRU or pLRU is summarized as follows.

[0047] For multi-way data blocks with integer power of 2 paths, a full binary tree is generally used for cache management. In this binary tree structure, non-leaf nodes store 1 bit of replacement information. When a data block needs to be replaced, 1 path is selected for replacement based on the replacement information; the data block replacement information is updated when the data block is accessed; access operations for data blocks include data block reads, data block writes, and data block allocation operations.

[0048] For example, Figure 1 Figure 1 is a schematic diagram of a full binary tree structure used for a 2-way data block in a pLRU strategy. Figure 1 In the example shown, 2-way data blocks are organized and managed using a full binary tree with a depth of 2. Non-leaf nodes are represented by circles, leaf nodes are represented by rectangles, and each leaf node corresponds to a data block. The two leaf nodes correspond to way 0 and way 1, respectively. Non-leaf nodes store 1 bit of replacement information, where when way 0 is accessed, the replacement information is set to 1, and when way 1 is accessed, the replacement information is set to 0; when replacement is required, if the replacement information bit is 0, the data block in way 0 is selected for replacement, and if the replacement information bit is 1, the data block in way 1 is selected for replacement.

[0049] Figure 2 for Figure 1 The schematic diagram of the replacement strategy of 2-way data blocks using the pLRU strategy is shown in FIG. Figure 2 In the example shown, the initial state is Figure 2 The left figure in the figure, that is, the replacement information is 0, the data with address A is stored in way 0, and the data with address B is stored in way 1; suppose the data to be accessed next is the data with address A, at this time the data with address A is already stored in way 0 of the cache, that is, the way 0 in the cache is hit, after the access, the identification replacement information is set to 1, and we get Figure 2 The middle figure in ; Assuming that the data to be accessed next is the data at address C, since the cache does not yet store the data at address C, that is, the cache does not hit, then the data at address C needs to be written into the cache first, but the cache is full, so the cache needs to be replaced. Since the replacement information is 1, the data block in way 1 needs to be replaced, and the data at address B in way 1 is replaced with the data at address C. After the access, the identification replacement information is set to 0, and we get Figure 2 Right picture in .

[0050] When the number of paths increases (but still satisfies the integer power of 2), the depth of the binary tree is greater than 2, and the replacement information and replacement strategy are expanded accordingly.

[0051] Figure 3 This is a schematic diagram of the full binary tree structure used by 8-way data blocks in the pLRU strategy. Figure 3 In the example shown, 8-way data blocks (i.e., way 0 to way 7) are organized and managed using a full binary tree with a depth of 4 (4 layers). In each layer, non-leaf nodes manage the data blocks corresponding to the leaf nodes connected to them, and manage their left and right partitions differently. For each non-leaf node, when accessing its left half partition, the replacement information is set to 1; when accessing its right half partition, the replacement information is set to 0. When replacement is required, when selecting the target way of the replacement strategy, the search starts from the root node. For each non-leaf node, when the replacement information is 0, the left half partition is selected to continue searching, otherwise the right half partition is selected to continue searching until the target way is found. In addition, the replacement information of each non-leaf node can be managed with a 7-bit data (or array), each bit corresponds to a non-leaf node, for example, bit 0 corresponds to the root node, bit 1 corresponds to the node on the left of the root node, bit 2 corresponds to the node on the right of the root node, and so on. Although the above cache management method ensures cache replacement performance and a balanced cache hit rate of each data block, it needs to save more replacement information to participate in the decision of the replacement strategy. If the number of ways is n, at least n*(n-1) / 2 bits of replacement information are required. The storage complexity of replacement information increases with the number of ways in the cache. In the case of multiple ways, a large amount of hardware resources are required to maintain and store to ensure cache replacement performance.

[0052] In addition, for multi-way data blocks with non-integer power of 2 paths, a non-full binary tree can be used for cache management. The binary tree has unbalanced partitions.

[0053] For example, Figure 4 This is a schematic diagram of the non-full binary tree structure used by the 3-way data block in the pLRU strategy. Figure 4 In the example shown, a 3-way data block is organized and managed using a non-full binary tree with a depth of 3. The two non-leaf nodes 0 and 1 are represented by circles (for Figure 4 , non-leaf node 0 is also the root node), three leaf nodes are represented by rectangles, and each leaf node corresponds to a data block. The three leaf nodes correspond to paths 0 to 2 respectively. The method for setting the replacement information in each non-leaf node in a non-2-integer power path is similar to the cache replacement method for the above-mentioned 2-integer power path, that is, for each non-leaf node, when accessing its left half partition, the replacement information is set to 1; when accessing its right half partition, the replacement information is set to 0.

[0054] Figure 5 for Figure 4 Schematic diagram of the replacement strategy of 3-way data blocks in the pLRU strategy shown in FIG. Figure 5 In the example shown, it is assumed that the data to be accessed are the data at the following addresses: address A, address B, address C, address D, address E, address F, and address G. Figure 5 As shown, assuming that the cache is initially empty and the initial value of the replacement information of non-leaf node 0 and non-leaf node 1 is 0:

[0055] When first accessing the data at address A (hereinafter referred to as data A), data A is filled into the currently empty way 0. At this time, the replacement information of non-leaf node 0 and non-leaf node 1 are both kept at 0.

[0056] Next, when accessing data B at address B, the still empty way 1 is selected, that is, data B is filled into way 1, that is, way 1 is accessed. At this time, the replacement information of non-leaf node 0 and the replacement information of non-leaf node 1 are both set to 1.

[0057] Next, when accessing data C at address C, the still empty way 2 is selected, that is, data C is filled into way 2, that is, way 2 is accessed. At this time, the replacement information of non-leaf node 0 is set to 0, and the replacement information of non-leaf node 1 remains 1.

[0058] Next, when accessing data D at address D, the cache misses and the cache is full, then data D needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 0 of non-leaf node 0 and the replacement information 1 of non-leaf node 1, way 1 is selected, that is, data D is filled into way 1. At this time, the replacement information of non-leaf node 0 is set to 1, and the replacement information value of non-leaf node 1 is 0.

[0059] Next, when accessing data E at address E, the cache misses and the cache is full, then data E needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 1 of non-leaf node 0 and the replacement information 0 of non-leaf node 1, way 2 is selected, that is, data E is filled into way 2. At this time, the replacement information of non-leaf node 0 is set to 0, and the replacement information of non-leaf node 1 remains 0.

[0060] Next, when accessing data F with address F, the cache does not hit and the cache is full, then data F needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 0 of non-leaf node 0 and the replacement information 0 of non-leaf node 1, way 0 is selected, that is, data F is filled into way 0. At this time, the replacement information of non-leaf node 0 is set to 1, and the replacement information of non-leaf node 1 is set to 1.

[0061] Next, when accessing data G with address G, the cache does not hit and the cache is full, then data G needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 1 of non-leaf node 0 and the replacement information 1 of non-leaf node 1, way 2 is selected, that is, data G is filled into way 2. At this time, the replacement information of non-leaf node 0 is set to 0, and the replacement information of non-leaf node 1 remains at 1.

[0062] It can be seen that if the above replacement strategy is still followed, when the address is not repeated, the allocation probability of each path is not even. The effect of reducing the number of replacement information by relying on a non-full binary tree is very limited, and there is still a phenomenon that too many hardware resources are needed to maintain and store to ensure cache replacement performance. In addition, non-full binary trees also have unbalanced partitions, which affects the cache hit rate of each data block. Although there is a solution that adds weight logic to the nodes of the binary tree structure to achieve approximate balance, the weight update logic and the calculation logic when selecting the replacement path add additional hardware overhead and power consumption. In particular, when the actual implementation involves bypass forwarding of different pipeline levels, it further increases additional hardware overhead and power consumption.

[0063] In summary, for multi-way data blocks with non-integer power of 2 paths, the existing pLRU has technical problems including limited effect of reducing the number of replacement information by relying on non-full binary trees, and the need to further improve the cache strategy to prevent excessive consumption of storage and hardware resources. Furthermore, there may also be a technical problem of uneven cache hit rates for each data block.

[0064] At least one embodiment of the present disclosure provides a cache management method, the cache includes multiple groups, each of the multiple groups includes multi-way data blocks of non-integer power of 2, the cache management method includes: obtaining a binary tree structure corresponding to the multi-way data blocks of each group in the multiple groups, wherein each leaf node of the binary tree structure corresponds to one way in the multi-way, non-leaf nodes of the binary tree structure record replacement information, and at least one way in the multi-way simultaneously belongs to two partitions at the bottom of the binary tree structure; in response to a replacement operation on the multi-way data blocks of any group in the multiple groups, searching from the root node of the binary tree structure until a target way that meets the replacement strategy is found.

[0065] Some embodiments of the present disclosure also provide a cache management device, a cache, an electronic device, and a storage medium corresponding to the above method.

[0066] The cache management method provided by at least one of the above-mentioned embodiments of the present disclosure, when constructing a binary tree structure for multiple data blocks in each group, a data block of a certain path, when serving as a leaf node, can simultaneously belong to the two bottom partitions of the binary tree structure, that is, can simultaneously belong to two incompletely duplicated parent nodes. The replacement information required for a large-capacity cache can be reduced through the reuse of leaf nodes, and then a cache replacement strategy for non-integer power of 2 paths can be implemented through simpler logic and fewer non-leaf nodes, thereby achieving a pLRU effect under an approximate integer power of 2 path, and reducing storage consumption and hardware resource consumption.

[0067] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0068] The cache management method provided by at least one embodiment of the present disclosure can be used to manage any existing cache with a set associative structure or a fully associative structure. For example, it can be applied to L1 data cache (DCache), L1 instruction cache (ICache), L2 cache, BTB cache, etc., and the embodiments of the present disclosure are not limited to this.

[0069] For example, the cache management method can be implemented in the form of software, hardware, firmware or any combination thereof, and can be loaded and executed by a processor in a device such as a mobile phone, a digital camera, a tablet computer, a laptop computer, a desktop computer, a network server, etc.

[0070] For example, the cache management method is applicable to a computing device with a cache function, such as a mobile phone, a digital camera, a laptop, a tablet computer, a desktop computer, a network server, etc., which can load and execute the cache management method, and the embodiments of the present disclosure are not limited to this. For example, the computing device may include a cache and a central processing unit (CPU) or a graphics processing unit (GPU), a digital signal processor (DSP), and other processing units with data processing capabilities and / or instruction execution capabilities, a storage unit, etc., and the computing device is also installed with an operating system, an application programming interface (for example, OpenGL (OpenGraphics Library), Metal), etc.

[0071] Figure 6 A flowchart of a cache management method provided by at least one embodiment of the present disclosure. The cache includes multiple groups, each of which includes multiple data blocks of a non-integer power of 2. Figure 6 The cache management method provided by at least one embodiment of the present disclosure is introduced in detail. For example, in some examples, the cache management method includes steps S110 to S120.

[0072] Step S110: Obtain a binary tree structure corresponding to the multiple data blocks of each group in the above-mentioned multiple groups, wherein each leaf node of the binary tree structure corresponds to one of the above-mentioned multiple paths, replacement information is recorded in the non-leaf nodes of the binary tree structure, and at least one of the above-mentioned multiple paths belongs to the two bottom partitions of the binary tree structure at the same time.

[0073] Step S120: In response to performing a replacement operation on the multi-way data blocks of any of the above-mentioned multiple groups, searching starts from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found.

[0074] In some other examples, the cache management method also includes step S130.

[0075] Step S130: in response to the access operation to the multi-way data block of each of the plurality of groups, updating the replacement information recorded in the non-leaf node of the binary tree structure.

[0076] It should be noted that in the above-mentioned embodiments of the present disclosure, the execution order of step S120 and step S130 of the cache management method is not limited. Although the execution process of each step is described in a specific order above, this does not constitute a limitation on the embodiments of the present disclosure.

[0077] For step S110, when a binary tree structure is constructed corresponding to multiple data blocks, a data block of a certain path can belong to two incompletely repeated parent nodes at the same time as a leaf node. Step S120 selects a target path for search based on the replacement information of each non-leaf node based on the binary tree structure. Step S130 updates the replacement information of each non-leaf node based on the binary tree structure.

[0078] For example, the binary tree structure can be a full binary tree or a non-full binary tree. A full binary tree is a special type of binary tree. Except for the last layer which has no child nodes, all parent nodes (non-leaf nodes) on each layer have two child nodes (non-leaf nodes). Compared with a full binary tree, a non-full binary tree allows some nodes to be missing. Organizing and managing multiple data blocks in a full binary tree or a non-full binary tree with leaf node reuse can reduce the number of replacement information compared to the existing replacement LRU or pLRU strategies described above, and can also ensure cache performance and achieve a balanced cache hit rate for each data block.

[0079] For example, in the binary tree structure, there may be a situation where non-leaf nodes are reused on the same layer, or there may be a situation where non-leaf nodes are reused on different layers. For example, in the binary tree structure, there may be a situation where at least one non-leaf node (child node) belongs to two completely non-repeating non-leaf nodes (parent nodes) on the layer above the non-leaf node, so as to further reduce replacement information, use fewer storage units to store replacement information, and implement simpler logic. As an implementation method, the binary tree structure uses a full binary tree with both leaf node reuse and non-leaf node reuse, so as to further reduce replacement information while ensuring a balanced cache hit rate, and improve cache performance from the perspectives of cache hit rate and the number of replacement information.

[0080] For example, the partitioning method of each level of the binary tree structure is described by taking the left and right partitions as an example, which may also be called the front and back partitions, etc., and the embodiments of the present disclosure are not limited to this.

[0081] For example, a binary tree structure corresponding to a multi-way data block of each of the above-mentioned multiple groups is obtained, and an array can also be used to record the binary tree structure, wherein the number of bits of the array is the same as the number of non-leaf nodes of the binary tree structure. For this step, the non-leaf nodes of the binary tree structure can be recorded through an array, so as to facilitate recording the replacement information of each non-leaf node for judging replacement in subsequent processes. For example, the replacement information can be stored using only 1 bit, and in other examples, the bit width can also be increased to record more information required for judging the target path.

[0082] For example, each leaf node may also store the tag information, validity information (tag) and dirty information (Dirty) of the corresponding data block, where the tag information is used for hit judgment, the validity information is used for hit judgment, and the dirty information is used for replacement data write-back judgment.

[0083] It should be noted that the storage method of replacement information stored in non-leaf nodes and the storage method of label information, validity information and dirty bit information stored in leaf nodes for corresponding data blocks are not fixed and can be stored through but not limited to registers, latches, etc. The embodiments of the present disclosure do not impose any restrictions on this.

[0084] For step S130, for example, the access operation includes data block reading, data block writing, or data block allocation operations, etc. For example, different implementations may select some access operations or add other operations to implement data block access according to specific circumstances. For example, when there is an invalid way in the same group in the cache, the invalid way can be directly selected for allocation when backfilling data, and no data block replacement is required at this time. This part of the implementation may adopt different strategies depending on the specific implementation, and the embodiments of the present disclosure do not limit this. When there is no invalid way in the same group in the cache, it is necessary to select a data block to replace when backfilling data.

[0085] Figure 7 A schematic diagram of a process for updating and replacing information provided by at least one embodiment of the present disclosure. That is, Figure 7 for Figure 6 A flowchart of at least one example of step S130 in FIG. Figure 7 As shown, the process of updating and replacing information includes steps S131 to S133:

[0086] Step S131: For each non-leaf node in the binary tree structure: in response to the leaf node where the target data block of the access operation is located in the left half partition of the non-leaf node, the replacement information of the non-leaf node is set to a first value.

[0087] Step S132: For each non-leaf node in the binary tree structure: in response to the leaf node where the target data block of the access operation is located in the right half partition of the non-leaf node, the replacement information of the non-leaf node is set to a second value different from the first value.

[0088] Step S133: For each non-leaf node in the binary tree structure: in response to the leaf node where the target data block of the access operation is located is located in both the left and right half partitions of the non-leaf node, the replacement information of the non-leaf node is set to remain unchanged.

[0089] It should be noted that the execution order of step S131, step S132, and step S133 is not restricted. Although the execution process of each step is described in a specific order above, this does not constitute a limitation on the embodiment of the present disclosure. The replacement information is set to a first value, indicating that the access operation only involves the left half partition of the non-leaf node; it is set to a second value, indicating that the access operation only involves the half partition of the non-leaf node; the setting remains unchanged, indicating that the access operation does not involve the non-leaf node or involves both the left and right half partitions of the non-leaf node. The update time of the replacement information in each non-leaf node can be at various stages of the actual data block access, and is not fixed at a certain pipeline level or specific time. For example, in an embodiment of the present disclosure, the first value is 1, and the second value is 0.

[0090] Figure 8 A schematic diagram of a process of searching a target path through a binary tree structure is provided for at least one embodiment of the present disclosure. That is, Figure 8 yes Figure 6 In some examples, the process of searching for a target path through a binary tree structure includes steps S121 and S122.

[0091] Step S121: For each non-leaf node in the binary tree structure: in response to the replacement information of the non-leaf node being a first value, searching the right half partition of the non-leaf node.

[0092] Step S122: For each non-leaf node in the binary tree structure: in response to the replacement information of the non-leaf node being the second value, searching the left half partition of the non-leaf node.

[0093] It should be noted that the execution order of step S121 and step S122 is not limited. Although the execution process of each step is described in a specific order above, this does not constitute a limitation on the embodiments of the present disclosure. Step S121 and step S122 describe that when selecting a target path for replacement, if the replacement information of the non-leaf node is a first value, then the non-leaf node of the right half partition of the child node is selected. If the replacement information of the non-leaf node is a second value, then the non-leaf node of the left half partition of the child node is selected, and the search continues until the target path is found.

[0094] In some other examples, the buffer management method further includes step S123 after step S122.

[0095] Step S123: in response to the dirty bit information of the data block of the target way being true, performing a write-back operation on the data block of the target way, and then performing data backfilling on the data block of the target way.

[0096] For step S123, as described above, the dirty bit information is a parameter that identifies whether the current cache data is consistent with the downstream storage. For example, when performing cache replacement, the dirty bit information is used to identify that the current cache data is inconsistent with the downstream storage (ie, true), and the current cache data is written back to the downstream storage.

[0097] At least one embodiment of the present disclosure provides another cache management method, in which Figure 8 Based on the example shown, before step S121, it also includes: determining that the valid bit information of each data block in the multiple data blocks is valid (not shown in the figure).

[0098] Fig. 9 A specific example of the cache management method provided by at least one embodiment of the present disclosure is a schematic diagram of a replacement strategy for a 3-way data block. In this example, the sequence of addresses for accessing a data block in a 3-way cache is: address A, address B, address C, address D, address E, address F, and address G. A full binary tree is used, and the replacement information recorded in the non-leaf nodes is the result of the update of each non-leaf node. The partitions corresponding to the non-leaf nodes overlap, such as Fig. 9 As shown, way 1 belongs to two partitions of the bottom layer (i.e., the last layer of non-leaf nodes) of the full binary tree structure, namely, the right half partition of non-leaf node 1 and the left half partition of non-leaf node 2. At the same time, assuming that the cache is initially empty and the initial value of the replacement information of the root node and non-leaf node 1 is 0, the operations for the above sequence are as follows:

[0099] When the data at address A (hereinafter referred to as data A) is first accessed, data A is filled into the currently empty way 0. At this time, the replacement information of non-leaf nodes 0-2 is kept at 0.

[0100] Next, when accessing data B at address B, the still empty way 1 is selected, that is, data B is filled into way 1, that is, way 1 is accessed. At this time, the replacement information of non-leaf nodes 0 and 1 is kept as 0, and the replacement information of non-leaf node 2 is set to 1.

[0101] Next, when accessing data C at address C, the still empty way 2 is selected, that is, data C is filled into way 2, that is, way 2 is accessed. At this time, the replacement information of non-leaf nodes 0 and 1 is kept as 0, and the replacement information of non-leaf node 2 is set to 0.

[0102] Next, when accessing data D at address D, the cache misses and the cache is full, then data D needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 0, 0, and 0 of non-leaf nodes 0-2, way 0 is selected, that is, data D is filled into way 0. At this time, the replacement information of non-leaf nodes 0 and 1 are both set to 1, and the replacement information of non-leaf node 2 is kept at 0.

[0103] Next, when accessing data E at address E, the cache does not hit and the cache is full, then data E needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 1, 1 and 0 of non-leaf nodes 0-2, way 1 is selected, that is, data E is filled into way 1. At this time, the replacement information of non-leaf nodes 1 and 2 is set to 0 and 1 respectively, and the replacement information of non-leaf node 0 is kept at 1.

[0104] Next, when accessing data F at address F, the cache does not hit and the cache is full, then data F needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 1, 0, and 1 of non-leaf nodes 0-2, way 2 is selected, that is, data F is filled into way 2. At this time, the replacement information of non-leaf nodes 0 and 1 are set to 1 respectively, and the replacement information of non-leaf node 1 is kept at 0.

[0105] Next, when accessing data G at address G, the cache does not hit and the cache is full, then the data G needs to be read into the cache and a replacement operation needs to be performed. According to the replacement information 0, 0, and 0 of non-leaf nodes 0-2, way 0 is selected, that is, data G is filled into way 0. At this time, the replacement information of non-leaf nodes 0 and 1 are set to 1 respectively, and the replacement information of non-leaf node 1 is kept at 0.

[0106] Fig.10 Another specific example of the cache management method provided by at least one embodiment of the present disclosure is a schematic diagram of a binary tree structure used by a 10-way data block. The binary tree structure has 5 layers and needs to maintain 12 bits of replacement information. The non-leaf node [0] is the root node, and its child nodes are the non-leaf nodes [1] and non-leaf nodes [2] of the second layer. Fig.10 When the accessed data block is only the left leaf node, the corresponding replacement information is set to 1; when the accessed data block is only the right leaf node, the corresponding replacement information is set to 0; when the accessed data block has no connection relationship with the current non-leaf node, or the accessed data block is both the left leaf node and the right leaf node, the replacement information remains unchanged. When selecting a replacement path, if the replacement information of a non-leaf node is 0, select its left child node to continue searching; if the replacement information of a non-leaf node is 1, select its right child node to continue searching; until the data block of the target path is finally selected.

[0107] Fig.10 The update of the replacement information of the 10-way data block is shown in Table 1, which shows the search path of the target way for replacement confirmed according to the replacement information of the non-leaf node.

[0108] Table 1: Update of replacement information of 10-way data blocks

[0109]

[0110] Fig.11 A schematic block diagram of a cache management device provided in at least one embodiment of the present disclosure.

[0111] For example, in Fig.11 In the example shown, the cache management device 100 includes an acquisition unit 110 and an operation unit 120. For example, these units can be implemented by hardware (such as circuits), software, firmware, or any combination of the three. For example, these units can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a field programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities and corresponding computer instructions.

[0112] The acquisition unit 110 is configured to acquire a binary tree structure corresponding to a multi-way data block of each of the multiple groups, wherein, for example, each group includes a multi-way data block of a non-integer power of 2 (e.g., 3, 5, 9, 15, etc.), each leaf node of the binary tree structure corresponds to one of the multiple ways, and replacement information is recorded in the non-leaf nodes of the binary tree structure, and at least one of the multiple ways simultaneously belongs to two partitions at the bottom of the binary tree structure. For example, the binary tree structure is a full binary tree or a non-full binary tree, and for each of the multiple cached groups, cache management within the group is performed through a matching binary tree structure. For example, step S110 can be implemented by the acquisition unit 110, and its specific implementation method can refer to the relevant description of step S110, which will not be repeated here.

[0113] The operation unit 120 is configured to perform a replacement operation on the multi-way data blocks of any group of the multiple groups, and search from the root node of the binary tree structure until a target way that satisfies the replacement strategy is found. For example, the operation unit 120 can implement step S120, and the specific implementation method thereof can refer to the relevant description of step S120, which will not be repeated here.

[0114] At least one embodiment of the present disclosure provides another cache management device, Fig.11 Based on the example shown, the operation unit is further configured to, in response to the access operation of the multi-way data block of each group in the plurality of groups, update the replacement information recorded in the non-leaf node of the binary tree structure. For example, the operation unit 120 can also implement step S130, and its specific implementation method can refer to the relevant description of step S130, which will not be repeated here.

[0115] It should be noted that in the embodiments of the present disclosure, the cache management device 100 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or in other applicable ways.

[0116] Fig.12 A schematic block diagram of another cache management device provided by at least one embodiment of the present disclosure. Fig.12 In the example shown, the cache management device 200 includes: at least one processing unit 210 and at least one memory 220, the memory 220 stores computer executable instructions, wherein the computer executable instructions, when executed by the at least one processing unit 210, implement the cache management method provided by at least one embodiment of the present disclosure.

[0117] For example, the processing unit 210 is in communication with the memory 220. For example, one or more computer executable instructions are stored in the memory 220. For example, the one or more computer executable instructions include instructions for executing the cache management method provided by any embodiment of the present disclosure. For example, the one or more computer executable instructions can be executed by the processing unit 210. For example, the bus can be a commonly used serial or parallel communication bus, etc., and the embodiments of the present disclosure are not limited to this.

[0118] For example, the processing unit 210 may be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units having data processing capabilities and / or instruction execution capabilities, may be a general-purpose processor or a special-purpose processor, and may cache other components in the management device 200 to perform desired functions.

[0119] For example, the memory 220 may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processing unit 210 may execute the program instructions to implement the functions (implemented by the processing unit 210) in the embodiments of the present disclosure and / or other desired functions.

[0120] It should be noted that, for the sake of clarity and brevity, the embodiments of the present disclosure do not provide all the components of the cache management device 200. In order to realize the necessary functions of the cache management device 200, those skilled in the art may provide and set other components not shown according to specific needs, and the embodiments of the present disclosure are not limited to this. The functions described in the above units herein may be at least partially performed by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate array (FPGA), application specific integrated circuit (ASIC), application specific standard product (ASSP), system on chip (SOC), complex programmable logic device (CPLD), etc.

[0121] At least one embodiment of the present disclosure further provides an electronic device. Fig.13 A schematic block diagram of an electronic device provided according to at least one embodiment of the present disclosure.

[0122] like Fig.13 As shown, the electronic device 1 includes a cache management device 100 / 200 provided by any embodiment of the present disclosure. For example, the electronic device may be a cache or a processing device with a cache, such as a central processing unit (CPU), an image processor, etc. The cache management device is used to manage the cache. The electronic device can be used for mobile phones, digital cameras, laptops, tablet computers, desktop computers, network servers, etc., and can load and execute the above-mentioned cache management method. The embodiments of the present disclosure are not limited to this. For example, the central processing unit can be a single-core or multi-core processor, each processor core has a private cache, or the central processing unit has a public cache for multiple processor cores. Whether it is a private cache or a public cache, it can be applicable to the cache management device of the embodiments of the present disclosure.

[0123] In at least one example, the electronic device is a cache, and in addition to the above-mentioned cache management device, the cache also includes multiple data blocks, the multiple data blocks include multiple groups and each group includes multiple ways, each way corresponds to a data block, for example, each group includes multiple data blocks of a non-integer power of 2.

[0124] In at least one example, the electronic device is a processor, and the processor includes the above-mentioned cache. The processor can be a single-core processor or a multi-core processor, and the cache can be a private cache in the processor (such as an L1 cache or an L2 cache), or can be a shared cache (such as a last-level cache), etc., and the embodiments of the present disclosure are not limited to this. At the same time, the embodiments of the present disclosure are not limited to the instruction set (such as an X86 instruction set, an Arm instruction set, etc.) applicable to the processor, the microarchitecture adopted, etc.

[0125] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device 1, those skilled in the art may provide and set other components not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0126] Regarding the technical effects of the electronic device 1 in the above embodiment, reference may be made to the technical effects of the cache management method provided in any embodiment of the present disclosure, which will not be repeated here.

[0127] At least one embodiment of the present disclosure further provides a nonvolatile storage medium. Fig.14 A schematic diagram of a non-volatile storage medium provided by at least one embodiment of the present disclosure. Fig.14As shown, the non-volatile storage medium 400 stores computer executable instructions 401, wherein the computer executable instructions, when executed by at least one processing unit, implement the cache management method provided by any embodiment of the present disclosure.

[0128] For example, the storage medium may include random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other applicable storage media.

[0129] At least some embodiments of the present disclosure also provide an electronic device, which includes the processor of any of the above embodiments. Fig.15 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0130] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.15 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0131] For example, Fig.15 As shown, in some examples, the electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which may include a processor of any of the above-mentioned embodiments, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003. Various programs and data required for the operation of the computer system are also stored in the RAM 1003. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0132] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Fig.15 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0133] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0134] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0135] There are a few points to note:

[0136] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0137] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0138] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A cache management method, wherein: The cache includes a plurality of groups, each of the plurality of groups includes a plurality of data blocks that are not an integer power of 2, and the cache management method includes: Acquire a binary tree structure of multiple data blocks corresponding to each of the multiple groups, wherein each leaf node of the binary tree structure corresponds to one of the multiple paths, replacement information is recorded in non-leaf nodes of the binary tree structure, and at least one of the multiple paths belongs to two partitions at the bottom of the binary tree structure at the same time; In response to performing a replacement operation on the multi-way data blocks of any one of the plurality of groups, a search is started from the root node of the binary tree structure until a target way satisfying the replacement strategy is found.

2. The cache management method according to claim 1, further comprising: In response to an access operation to the multi-way data block of each of the plurality of groups, the replacement information recorded in the non-leaf nodes of the binary tree structure is updated.

3. The cache management method according to claim 2, wherein: The access operation includes a data block read, a data block write or a data block allocation operation.

4. The cache management method according to claim 2 or 3, wherein: The updating of the replacement information recorded in the non-leaf nodes of the binary tree structure in response to the access operation of the multi-way data blocks of each group in the plurality of groups comprises: For each non-leaf node in the binary tree structure: In response to the leaf node where the target data block of the access operation is located being located in the left half partition of the non-leaf node, setting the replacement information of the non-leaf node to a first value; In response to the leaf node where the target data block of the access operation is located being located in the right half partition of the non-leaf node, setting the replacement information of the non-leaf node to a second value different from the first value; In response to the leaf node where the target data block of the access operation is located is located in both the left and right half partitions of the non-leaf node, the replacement information of the non-leaf node is set to remain unchanged.

5. The cache management method according to claim 4, wherein: In response to performing a replacement operation on the multi-way data blocks of any group of the multiple groups, searching from the root node of the binary tree structure until a target way satisfying the replacement strategy is found includes: For each non-leaf node in the binary tree structure: In response to the replacement information of the non-leaf node being the first value, searching the right half partition of the non-leaf node; In response to the replacement information of the non-leaf node being the second value, searching the left half partition of the non-leaf node.

6. The cache management method according to claim 1, wherein: Each leaf node also stores label information, validity information and dirty bit information of the corresponding data block.

7. The cache management method according to claim 6, wherein in response to performing a replacement operation on a multi-way data block of any of the plurality of groups, searching from the root node of the binary tree structure until a target way satisfying the replacement strategy is found, further comprising: In response to the dirty bit information of the data block of the target way being true, a write-back operation is performed on the data block of the target way, and then data backfill is performed on the data block of the target way.

8. The cache management method according to claim 6, wherein in response to performing a replacement operation on a multi-way data block of any of the plurality of groups, searching from the root node of the binary tree structure until a target way satisfying the replacement strategy is found, further comprising: It is determined that the valid bit information of each data block in the multiple data blocks is valid.

9. The cache management method according to any one of claims 1 to 8, wherein: The binary tree structure is a full binary tree.

10. The cache management method according to any one of claims 1 to 8, wherein: The step of obtaining a binary tree structure of a multiplexed data block corresponding to each of the multiple groups comprises: An array is used to record the binary tree structure, wherein the number of bits of the array is the same as the number of non-leaf nodes of the binary tree structure.

11. A cache management device, wherein: The cache includes a plurality of groups, each of the plurality of groups includes a plurality of data blocks that are not an integer power of 2, and the cache management device includes: an acquisition unit configured to acquire a binary tree structure of a multi-way data block corresponding to each of the plurality of groups, wherein each leaf node of the binary tree structure corresponds to one way in the multi-way, replacement information is recorded in a non-leaf node of the binary tree structure, and at least one way in the multi-way simultaneously belongs to two partitions at the bottom of the binary tree structure; The operation unit is configured to, in response to performing a replacement operation on the multi-way data blocks of any group of the multiple groups, start searching from the root node of the binary tree structure until a target way that meets the replacement strategy is found.

12. The cache management device according to claim 11, wherein: The operation unit is further configured to update the replacement information recorded in the non-leaf nodes of the binary tree structure in response to an access operation to the multi-way data blocks of each of the plurality of groups.

13. A cache comprising: A plurality of groups, wherein each of the plurality of groups includes a number of multiple data blocks that is not an integer power of 2; The cache management device comprises: an acquisition unit configured to acquire a binary tree structure of a multi-way data block corresponding to each of the plurality of groups, wherein each leaf node of the binary tree structure corresponds to one way in the multi-way, replacement information is recorded in a non-leaf node of the binary tree structure, and at least one way in the multi-way simultaneously belongs to two partitions at the bottom of the binary tree structure; The operation unit is configured to, in response to performing a replacement operation on the multi-way data blocks of any group of the multiple groups, start searching from the root node of the binary tree structure until a target way that meets the replacement strategy is found.

14. An electronic device comprising the cache according to claim 13.

15. A cache management device, comprising: at least one processing unit; At least one memory stores computer executable instructions, wherein the computer executable instructions, when executed by the at least one processing unit, implement the cache management method according to any one of claims 1-10.

16. A non-volatile storage medium storing computer executable instructions, wherein: When the computer executable instructions are executed by at least one processing unit, the cache management method according to any one of claims 1-10 is implemented.

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