Shared cache capacity adjustment method and storage system

Abstract

The present invention provides a shared cache capacity adjustment method and storage system. The method includes: configuring a shared cache in the memory of a host system, and a storage device is used to perform a preset operation based on data cached in the shared cache; detecting whether there is a specific mapping table item corresponding to a specific application in at least one mapping table item currently cached in the shared cache; if the specific mapping table item exists in at least one mapping table item currently cached in the shared cache, determining a target capacity from multiple candidate capacities; and adjusting the capacity of the shared cache according to the target capacity. In this way, the performance of the storage device or the entire storage system can be effectively improved without affecting the operating performance of the host system itself as much as possible.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a shared cache capacity adjustment method and a storage system. Background Art

[0002] NAND flash memory is a non-volatile memory technology widely used in various storage devices. It stores charge by using floating gate transistors, each transistor represents a storage unit. NAND flash memory cells usually organize data in the form of pages, each page contains multiple bytes, and multiple pages form a block. Data is read and programmed in pages, while erase operations are performed in blocks. This organization makes NAND flash memory very suitable for large-capacity storage and has a high write speed.

[0003] However, as the storage capacity of storage devices continues to increase, the amount of management data used to manage the storage devices also continues to increase, resulting in the small capacity memory of the storage devices themselves being insufficient. Summary of the invention

[0004] The present invention provides a shared cache capacity adjustment method and a storage system, which can effectively improve the performance of a storage device or the entire storage system without affecting the operating performance of a host system as much as possible.

[0005] An embodiment of the present invention provides a shared cache capacity adjustment method, which is used in a storage system, wherein the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache capacity adjustment method includes: configuring a shared cache in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache; detecting whether there is a specific mapping table entry corresponding to a specific application in at least one mapping table entry currently cached in the shared cache; if there is the specific mapping table entry corresponding to the specific application in the at least one mapping table entry currently cached in the shared cache, determining a target capacity from multiple candidate capacities; and adjusting the capacity of the shared cache according to the target capacity.

[0006] An embodiment of the present invention further provides a storage system, which includes a host system and a storage device. The storage device is connected to the host system. The host system is used to: configure a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on the data cached in the shared cache area; detect whether there is a specific mapping table entry corresponding to a specific application in at least one mapping table entry currently cached in the shared cache area; if there is a specific mapping table entry corresponding to the specific application in at least one mapping table entry currently cached in the shared cache area, determine a target capacity from multiple candidate capacities; and adjust the capacity of the shared cache area according to the target capacity.

[0007] Based on the above, a shared cache area can be configured in the memory of the host system, and the storage device can perform preset operations based on the data cached in the shared cache area. When the storage system is operating, it can be determined whether there is a specific mapping table entry corresponding to a specific application in at least one mapping table entry currently cached in the shared cache area. In particular, if there is a specific mapping table entry corresponding to the specific application in at least one mapping table entry currently cached in the shared cache area, the target capacity can be determined from multiple candidate capacities, and the capacity of the shared cache area can be automatically adjusted according to the target capacity. In this way, the performance of the storage device or the entire storage system can be effectively improved without affecting the operating performance of the host system itself as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a flow chart of a method for adjusting the capacity of a shared cache area according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Figure 1 is a schematic diagram of a storage system according to an embodiment of the present invention. Figure 1, the storage system (also called data storage system) 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0014] The host system 11 includes a processor 111 and a memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices.

[0015] The memory 112 is connected to the processor 111 and used to cache data. For example, the memory 112 may include a random access memory (RAM) or a similar volatile storage device. It should be noted that the memory 112 is disposed in the host system 11 (for example, disposed on the motherboard of the host system 11 or directly disposed in the processor 111), rather than disposed in the storage device 12.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0017] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0020] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0022] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0024] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0025] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0026] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0028] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0029] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0033] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the processor 111 may configure a shared cache area 101 in the memory 112. By utilizing the memory resources of the host system 11 (e.g., the shared cache area 101), the processor 111 provides an efficient temporary data exchange space for the storage device 12, which not only reduces the delay caused by frequent access to the flash memory, but also significantly improves the performance of random read and write operations.

[0036] Specifically, based on the data in the shared cache area 101, the storage device 12 can perform preset operations related to the memory module 122, such as at least one of the following operations: ① Command scheduling optimization: Allow the memory control circuit 23 to temporarily store multiple I / O requests from the host system 11 in the shared cache area 101 in advance, thereby optimizing the execution order of these requests, reducing unnecessary addressing time and page switching, and improving the overall response speed. ② Address mapping management: The shared cache area 101 can be used to store and update the logical to physical address mapping table (L2P Mapping Table) to speed up the search process for data locations, especially for random read operations, greatly improving efficiency. And perform sorting operations on multiple mapping table entries cached in the shared cache area 101 according to the sorting algorithm to obtain sorting queues and other operations. ③ Data cache: When reading data from the memory module 122, if the data has been loaded into the shared cache area 101, it can be directly obtained from it to avoid accessing the slower memory module 122 again, thereby speeding up the data reading speed. Similarly, when writing new data, the data can be temporarily saved in the shared cache area 101, and then the background optimization strategy determines when and how to persist it in the memory module 122. ④ Metadata processing: In addition to user data, it can also be used to cache key metadata such as file allocation table (FAT) and wear leveling information to ensure efficient data management and access mode even under high load conditions.

[0037] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the memory device 12. For example, the memory control circuit 23 may perform a handshake operation with the host system 11. The handshake operation is used to exchange information related to the establishment of the connection between the host system 11 and the memory device 12, such as clock information and / or voltage information.

[0038] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12 according to the result of the handshake operation. Thereafter, the memory control circuit 23 may access (also referred to as access) the shared cache area 101 through the connection.

[0039] In one embodiment, the memory control circuit 23 may store the management data in the shared cache area 101. During access to the memory module 122, the memory control circuit 23 may query or update (i.e., modify) the management data in the shared cache area 101. For example, the management data may include part of the data in the logic-to-physical mapping table (also referred to as a mapping table entry). The mapping table entry may carry mapping information (e.g., logic-to-physical mapping information). The mapping information may reflect the mapping relationship between at least one logical unit and at least one physical unit.

[0040] In one embodiment, when the host system 11 wants to read data belonging to a certain logical unit (also referred to as a first logical unit) from the storage device 12, the processor 111 may store read information corresponding to the first logical unit in the shared cache area 101. For example, the read information may include a read instruction indicating to read data belonging to the first logical unit. For example, the read instruction may include a random read instruction and / or a continuous read instruction. The random read instruction is used to indicate to read data from a single logical unit or multiple non-continuous logical units. The continuous read instruction is used to indicate to read data from multiple continuous logical units. The memory control circuit 23 may access the shared cache area 101 to obtain the read information.

[0041] After obtaining the read information, the memory control circuit 23 may confirm whether the mapping table entry associated with the first logical unit has been cached in the shared cache area 101. If the mapping table entry associated with the first logical unit is not cached in the shared cache area 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 into the shared cache area 101.

[0042] If the mapping table entry related to the first logical unit has been cached in the shared cache area 101 (or after the mapping table entry is loaded from the memory module 122 to the shared cache area 101), the memory control circuit 23 can query the mapping table entry in the shared cache area 101 to obtain the mapping relationship between the first logical unit and the physical unit (also referred to as the first physical unit) in the memory module 122. Then, the memory control circuit 23 can read data (also referred to as the first data) from the first physical unit in the memory module 122 according to the mapping relationship. Then, the memory control circuit 23 can return the read first data to the host system 11 in response to the read information.

[0043] In one embodiment, when the host system 11 wants to store data (also referred to as second data) belonging to a certain logical unit (also referred to as the second logical unit) into the storage device 12, the processor 111 may store write information corresponding to the second logical unit in the shared cache area 101. For example, the write information may include a write instruction indicating to update the data belonging to the second logical unit. For example, the write instruction may include a random write instruction and / or a continuous write instruction. The random write instruction is used to indicate to update the data belonging to a single logical unit or a plurality of discontinuous logical units. The continuous write instruction is used to indicate to update the data belonging to a plurality of continuous logical units. The memory control circuit 23 may access the shared cache area 101 to obtain the write information.

[0044] After obtaining the write information, the memory control circuit 23 may store the second data into a physical unit (also referred to as a second physical unit) in the memory module 122 according to the write information. On the other hand, the memory control circuit 23 may confirm whether the mapping table entry related to the second logical unit has been cached in the shared cache area 101. If the mapping table entry related to the second logical unit is not cached in the shared cache area 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 to the shared cache area 101.

[0045] If the mapping table entry related to the second logical unit has been cached in the shared cache area 101 (or after the mapping table entry is loaded from the memory module 122 to the shared cache area 101), the memory control circuit 23 may update the mapping table entry in the shared cache area 101 to establish a mapping relationship between the second logical unit and the second physical unit. Then, the memory control circuit 23 may notify the host system 11 to complete the write operation in response to the write information.

[0046] In one embodiment, the memory control circuit 23 may also store other types of management data in the shared cache area 101 (for example, load it from the memory module 122 into the shared cache area 101). For example, the management data may include valid count management data, wear leveling management data, or bad block management data, etc., which are not limited by the present invention. The valid count management data is used to manage the valid data storage status of at least some physical units in the memory module 122. For example, the valid count management data may include a valid count corresponding to at least one physical unit in the memory module 122. The wear leveling management data is used to manage the wear status of at least some physical units in the memory module 122. For example, the wear leveling management data may include a read count, a write count, and / or an erase count corresponding to at least one physical unit in the memory module 122. The bad block management data is used to manage damaged physical units (also called bad blocks) in the memory module 122. For example, the bad block management data may be used to mark at least one physical unit in the memory module 122 as a bad block. Thereafter, the memory control circuit 23 may access or manage the memory module 122 according to the management data in the shared cache area 101.

[0047] It should be noted that the shared cache area 101 set in the memory 112 will occupy a part of the storage space of the memory 112, thereby reducing the capacity of the memory 112 that can be used by the host system 11 itself. For example, after setting the shared cache area 101, the remaining capacity of the memory 112 after deducting the shared cache area 101 is the memory space that can be used by the host system 11 itself. Therefore, if the capacity of the shared cache area 101 is larger, it may cause the operating performance of the host system 11 itself to decrease (due to the reduction of the memory space that can be used by the host system 11 itself). However, if the capacity of the shared cache area 101 is too small, it may reduce the performance of the storage device 12 (due to the reduction of the memory space that can be used by the storage device 12).

[0048] However, through the technical solution proposed in the embodiment of the present invention, the capacity of the shared cache area 101 can be dynamically adjusted according to the current data storage status of the shared cache area 101. Therefore, the performance of the storage device 12 or the entire storage system 10 can be effectively improved without affecting the operating performance of the host system 11 itself as much as possible.

[0049] Specifically, the technical solution provided by the embodiment of the present invention can achieve fine management of the mapping table entries residing in the shared cache area 101, including but not limited to sorting, adding and removing operations, while maintaining a relatively small capacity configuration (including but not limited to reducing its capacity requirements) in the shared cache area 101. In this way, on the basis of ensuring that the operating efficiency of the host system 11 is not disturbed, the performance of the storage device 12 and even the entire storage system 10 is further enhanced, and the optimal balance between the processing capacity of the host system 11 and the response speed of the storage device 12 is achieved, ensuring that both can operate in an ideal state without affecting each other.

[0050] This solution is particularly suitable for scenarios that improve random read and write performance. Traditionally, in order to maximize the performance of random reads and writes, all mapping table entries should theoretically be loaded into the buffer memory 24. However, under the limitations of current product design - for example, the buffer memory 24 usually has a fixed capacity of 256KB, while the amount of data in the mapping table entries may reach 1GB or more (taking 1TB capacity as an example), which makes it impossible to load all mapping table entries at once, resulting in the need to frequently load mapping table entries in batches, thereby increasing latency and affecting the reading speed of the storage device 12. By using a shared cache area 101 to efficiently manage these mapping table entries, not only this challenge is solved, but also independent and undisturbed optimization of the performance of the host system 11 and the storage device 12 is achieved.

[0051] Specifically, this solution allows the storage system 10 to maintain high data access speed and low latency characteristics when processing a large number of mapping table entries, thereby ensuring the performance indicators of random read and write. At the same time, it also avoids the cost increase caused by adding additional hardware resources, as well as the possible increase in system complexity and decrease in stability. In short, this innovative technical solution provides a feasible and efficient way to solve the challenges of high-performance storage systems.

[0052] In one embodiment, one or more mapping table entries may be cached in the shared cache area 101. After the memory control circuit 23 caches at least one mapping table entry in the shared cache area 101, the processor 111 may detect whether there is a mapping table entry corresponding to a specific application (also referred to as a specific mapping table entry) in at least one mapping table entry currently cached in the shared cache area 101. If the specific mapping table entry exists in the at least one mapping table entry currently cached in the shared cache area 101, the processor 111 may determine a capacity (also referred to as a target capacity) from a plurality of candidate capacities. Then, the processor 111 may automatically adjust (e.g., increase or decrease) the capacity of the shared cache area 101 according to the target capacity. Thus, the performance of the host system 11 and the storage device 12 when executing the specific application can be effectively improved. However, if there is no specific mapping table entry corresponding to the specific application in at least one mapping table entry currently cached in the shared cache area 101, the processor 111 may not adjust the capacity of the shared cache area 101.

[0053] In one embodiment, after the memory control circuit 23 caches at least one mapping table entry in the shared cache area 101, the processor 111 may track the type of at least one mapping table entry cached in the shared cache area 101 to obtain a tracking result. In other words, the tracking result may reflect the type of the at least one mapping table entry currently cached in the shared cache area 101. Then, the processor 111 may determine whether the specific mapping table entry exists in the at least one mapping table entry currently cached in the shared cache area 101 according to the tracking result.

[0054] In one embodiment, the processor 111 may obtain identification information corresponding to a mapping table entry (also referred to as a target mapping table entry) in the shared cache area 101. The identification information may reflect the type of the target mapping table entry. Then, the processor 111 may determine whether the target mapping table entry belongs to the specific mapping table entry based on the identification information.

[0055] In one embodiment, when the target mapping table entry is cached to the shared cache area 101, an identification information may be associated with the target mapping table entry according to the application corresponding to the target mapping table entry. For example, assuming that the application corresponding to the target mapping table entry is application A, the identification information A corresponding to application A may be associated with the target mapping table entry. Alternatively, assuming that the application corresponding to the target mapping table entry is application B, the identification information B corresponding to application B may be associated with the target mapping table entry.

[0056] In one embodiment, the processor 111 may query the management table according to the identification information corresponding to the target mapping table item to obtain the query result. The management table may record multiple types (also referred to as candidate types) corresponding to multiple identification information (also referred to as candidate identification information). Then, the processor 111 may determine whether the target mapping table item belongs to the specific mapping table item based on the query result. For example, if the query result reflects that the type of the target mapping table item is consistent with the type of the specific mapping table item (e.g., the same), the processor 111 may determine that the target mapping table item belongs to the specific mapping table item. However, if the query result reflects that the type of the target mapping table item is inconsistent with the type of the specific mapping table item (e.g., different), the processor 111 may determine that the target mapping table item does not belong to the specific mapping table item.

[0057] In one embodiment, after determining that the target mapping table entry currently cached in the shared cache area 101 belongs to the specific mapping table entry, the processor 111 may determine the type of application (i.e., the specific application) corresponding to the target mapping table entry belonging to the specific mapping table entry. Then, the processor 111 may determine one of the multiple candidate capacities as the target capacity according to the type of the specific application.

[0058] In one embodiment, if the application (i.e., the specific application) corresponding to the target mapping table entry is a certain application (also referred to as the first application), the processor 111 may determine a certain capacity (also referred to as the first capacity) among the multiple candidate capacities as the target capacity. In one embodiment, if the application (i.e., the specific application) corresponding to the target mapping table entry is another application (also referred to as the second application), the processor 111 may determine another capacity (also referred to as the second capacity) among the multiple candidate capacities as the target capacity. The first application is different from the second application. The first capacity is different from the second capacity.

[0059] In one embodiment, after determining the target capacity, the processor 111 may dynamically adjust the capacity of the shared cache area 101 to be consistent with (e.g., the same as) the target capacity. In one embodiment, after determining the target capacity, the processor 111 may add or subtract the target capacity from the current capacity of the shared cache area 101.

[0060] In one embodiment, after determining the target capacity, the processor 111 may obtain a capacity adjustment parameter according to the target capacity. Then, the processor 111 may adjust (e.g., increase or decrease) the capacity of the shared cache area 101 according to the capacity adjustment parameter. For example, the processor 111 may input the target capacity into a calculation formula or a lookup table, and obtain the capacity adjustment parameter according to the output of the calculation formula or the lookup table.

[0061] For example, when running a map program (belonging to the specific application), the processor 111 can dynamically increase the capacity of the shared cache area 101 according to the mapping table entries currently cached in the shared cache area 101 and belonging to the map program. The enlarged shared cache area 101 can be more suitable for caching a large amount of map information that needs to be loaded during the operation of the map program. It should be noted that how much capacity needs to be increased (or reduced) depends on practical needs. However, the specific application may also include other types of applications.

[0062] Thus, when the host system 11 executes a specific application, the processor 111 can dynamically adjust the capacity of the shared cache 101 to an appropriate size corresponding to the specific application, thereby improving the performance of the host system 11 and the storage device 12 when executing the specific application.

[0063] In one embodiment, the type of a mapping table entry may reflect that the mapping table entry belongs to at least one of an active foreground application, an inactive foreground application, and a background application. In one embodiment, it is assumed that the current processor 111 runs applications A and B. Among them, application A runs in the foreground of the operating system (OS), and application B runs in the background of the operating system. At this time, the processor 111 may classify application A as an active foreground application and application B as a background application. It should be noted that those skilled in the art should know how the processor runs different applications in the foreground and background of the operating system, and will not be elaborated here.

[0064] In one embodiment, assume that another application C is switched to the foreground of the operating system. In response to application C being switched to the foreground of the operating system, the processor 111 may classify application C as an active foreground application. At the same time, the processor 111 may reclassify (e.g., downgrade) application A, which was originally an active foreground application, as an inactive foreground application, and maintain application B as a background application.

[0065] In one embodiment, the identification information corresponding to the target mapping table item may reflect that the target mapping table item belongs to an active foreground application, an inactive foreground application, or a background application. In addition, when the type of the target mapping table item changes, the processor 111 may update the identification information of the target mapping table item accordingly. The updated identification information may reflect the current type of the target mapping table item. For example, when the target mapping table item is switched from originally belonging to an inactive foreground application to belonging to an active foreground application, the processor 111 may update the identification information of the target mapping table item accordingly, so that the updated identification information reflects that the target mapping table item currently belongs to an active foreground application.

[0066] In one embodiment, the specific mapping table entry must belong to an active foreground application or an inactive foreground application. That is, if the target mapping table entry in the at least one mapping table entry belongs to an active foreground application or an inactive foreground application, when the type of the target mapping table entry is consistent with (e.g., the same as) the type of the specific mapping table, the processor 111 may allow the target mapping table entry to be determined as a specific mapping table entry. However, if the target mapping table entry does not belong to an active foreground application or an inactive foreground application, the processor 111 may not allow (or prohibit) the target mapping table entry to be determined as a specific mapping table entry.

[0067] In one embodiment, if the target mapping table entry in the at least one mapping table entry belongs to a background application, the processor 111 may determine that the target mapping table entry does not belong to a specific mapping table entry. In other words, when the target mapping table entry belongs to a background application, even if the type of the target mapping table entry is consistent with (e.g., the same as) the type of the specific mapping table, the processor 111 may determine that the target mapping table entry does not belong to a specific mapping table entry.

[0068] In one embodiment, when data is to be removed from the shared cache area 101, the processor 111 may preferentially remove the remaining mapping table entries in the shared cache area 101 that do not belong to the specific mapping table entry from the shared cache area 101. In one embodiment, when data is to be removed from the shared cache area 101, the processor 111 may preferentially or forcibly retain the specific mapping table entry in the shared cache area 101 (i.e., the specific mapping table entry in the shared cache area 101 is not removed).

[0069] In one embodiment, by retaining the specific mapping table entry in the shared cache 101 as much as possible, the performance of the host system 11 and the storage device 12 when executing the specific application can be improved. On the other hand, by removing the remaining mapping table entries that do not belong to the specific mapping table entry from the shared cache 101, even if the capacity of the shared cache 101 is reduced, the performance of the host system 11 and the storage device 12 when executing the specific application can still be effectively maintained (or even improved).

[0070] In one embodiment, in an extreme case, after dynamically adjusting the capacity of the shared cache area 101, the shared cache area 101 may only be large enough to store the specific mapping table entry, and the remaining mapping table entries may be removed. Thus, the operating performance of the host system 11 and the storage device 12 can be maintained (or even improved) while reducing the capacity of the shared cache area 101 as much as possible.

[0071] In one embodiment, the processor 111 may further configure multiple areas in the shared cache area 101 to classify and store different types of mapping table entries, thereby effectively improving the performance of the host system 11 and the storage device 12 .

[0072] In one embodiment, the processor 111 may detect the data storage capacity of at least one of the memory 112 and the shared cache area 101. For example, this data storage capacity may reflect how much data is currently stored in at least one of the memory 112 and the shared cache area 101. In one embodiment, the processor 111 may detect whether the data storage capacity has reached a critical value. When the data storage capacity reaches the critical value, the processor 111 may perform the aforementioned operation of removing the mapping table entry from the shared cache area 101. However, if the data storage capacity does not reach the critical value, the processor 111 may temporarily not perform the aforementioned operation of removing the mapping table entry from the shared cache area 101.

[0073] In one embodiment, when the data storage capacity of at least one of the memory 112 and the shared cache area 101 is relatively large (e.g., reaches the critical value), data that has little impact on the operating performance of the host system 11 (and the storage device 12) (e.g., other mapping table entries that do not belong to the specific mapping table entry) is removed first, and additional memory space can be released for use by the host system 11 (and the storage device 12). In this way, the performance of the host system 11 (and the storage device 12) can be improved.

[0074] It should be noted that, in one embodiment, the type of at least one mapping table entry cached in the shared cache area 101 can also be configured or adjusted according to practical needs, and is not limited to the above. In addition, in one embodiment, the specific application may include a video player, a music player, or other suitable applications, which are not described one by one here.

[0075] In one embodiment, if there are multiple types of specific mapping table entries in the shared cache area 101 at the same time, the processor 111 may determine another target capacity (also referred to as the second target capacity) according to the target capacities (also referred to as the first target capacity) respectively corresponding to the multiple types of specific mapping table entries. For example, the processor 111 may average the multiple first target capacities determined to obtain the second target capacity. Thus, even if there are multiple types of specific mapping table entries in the shared cache area 101 at the same time, the capacity of the shared cache area 101 may be maintained at an appropriate size (e.g., near the average value of the multiple first target capacities) as much as possible, so as to achieve a better balance between controlling (e.g., reducing) the capacity of the shared cache area 101 and maintaining system performance as much as possible.

[0076] In one embodiment, when multiple mapping table entries of the same type and / or having the same priority in the shared cache area 101 are to be removed, the processor 111 may randomly remove at least one of the multiple mapping table entries from the shared cache area 101. In one embodiment, by preferentially removing mapping table entries of a specific type and / or having a specific priority, even if the occupied capacity of the shared cache area 101 in the memory 111 is reduced, the performance of the host system 11 and the storage device 12 can be maintained or even improved.

[0077] In one embodiment, when multiple mapping table entries of the same type and / or having the same priority are to be removed from the shared cache 101, the processor 111 may also determine which mapping table entry of the multiple mapping table entries is to be removed from the shared cache 101 first according to the frequency, number of times or time points at which the multiple mapping table entries are accessed (e.g., accessed, queried or used) respectively. For example, the processor 111 may compare the frequency, number of times or time points at which the multiple mapping table entries are accessed (e.g., accessed, queried or used) respectively to obtain a comparison result. Then, the processor 111 may determine which mapping table entry of the multiple mapping table entries is to be removed from the shared cache 101 first according to the comparison result. For example, the processor 111 may preferentially remove from the shared cache 101 the mapping table entry that has a relatively high access frequency, a relatively large number of access times and / or a time point at which the access is relatively close to the current system time as shown in the comparison result. These evaluation factors may be selected one or more of them to be considered in selecting the mapping table entry to be removed first. Thus, it is possible to ensure that the performance of the host system 11 and the storage device 12 can be maintained or even improved after some mapping table entries are removed from the shared cache area 101. In one embodiment, the processor 111 may also select one or more mapping table entries that need to be removed first from multiple mapping table entries of the same type and / or with the same priority through other sorting algorithms, depending on practical needs.

[0078] Figure 4is a flow chart of a method for adjusting the capacity of a shared cache area according to an embodiment of the present invention. Figure 4 In step S401, a shared cache area is configured in the memory of the host system, wherein a storage device is used to perform a preset operation based on the data cached in the shared cache area. In step S402, it is detected whether there is a specific mapping table item corresponding to a specific application in at least one mapping table item currently cached in the shared cache area. In step S403, it is determined whether there is the specific mapping table item in at least one mapping table item currently cached in the shared cache area. If the specific mapping table item exists in at least one mapping table item currently cached in the shared cache area, in step S404, a target capacity is determined from a plurality of candidate capacities. In step S405, the capacity of the shared cache area is adjusted according to the target capacity. However, if the specific mapping table item does not exist in at least one mapping table item currently cached in the shared cache area, in step S406, the capacity of the shared cache area is not adjusted.

[0079] However, Figure 4 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 4 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 4 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0080] In summary, the shared cache capacity adjustment method and storage system proposed in the embodiment of the present invention can dynamically adjust the capacity of the shared cache according to the current data storage status of the shared cache, thereby effectively improving the performance of the storage device or the entire storage system without affecting the operating performance of the host system itself as much as possible.

[0081] In one embodiment, the aforementioned management and / or sorting mechanism for mapping table entries may also be used to manage and / or sort other types of data. For example, in one embodiment, the aforementioned mapping table entries may be replaced by various instructions, valid count management data, wear leveling management data, bad block management data, or other types of custom data, which will not be repeated here.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for adjusting the capacity of a shared cache area, characterized in that: Used in a storage system, the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache capacity adjustment method includes: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Detecting whether there is a specific mapping table entry corresponding to a specific application in at least one mapping table entry currently cached in the shared cache area, wherein the specific mapping table entry belongs to an active foreground application or an inactive foreground application, wherein if the specific application is running in the foreground of the operating system, the specific mapping table entry is determined to belong to the active foreground application, and if another application replaces the specific application to run in the foreground of the operating system, the specific mapping table entry is determined to belong to the inactive foreground application; If the specific mapping table entry corresponding to the specific application exists in the at least one mapping table entry currently cached in the shared cache area, determining a target capacity from a plurality of candidate capacities; and According to the target capacity, adjusting the capacity of the shared cache area, Wherein determining the target capacity from the multiple candidate capacities comprises: If the specific application is the first application, determining a first capacity among the plurality of candidate capacities as the target capacity; and If the specific application is a second application, a second capacity among the plurality of candidate capacities is determined as the target capacity, wherein the first capacity is different from the second capacity.

2. The method for adjusting the capacity of a shared cache area according to claim 1, wherein the at least one mapping table entry includes a target mapping table entry, and the step of determining whether the specific mapping table entry corresponding to the specific application exists in the at least one mapping table entry currently cached in the shared cache area comprises: Obtaining identification information corresponding to the target mapping table entry; as well as According to the identification information, it is determined whether the target mapping table entry belongs to the specific mapping table entry.

3. The method for adjusting the capacity of a shared cache area according to claim 2, wherein the step of determining whether the target mapping table entry belongs to the specific mapping table entry according to the identification information comprises: According to the identification information, query the management table to obtain a query result, wherein the query result reflects the type of the target mapping table entry; as well as According to the query result, it is determined whether the target mapping table entry belongs to the specific mapping table entry.

4. The method for adjusting the capacity of a shared cache area according to claim 1, wherein the step of determining the target capacity from the plurality of candidate capacities comprises: Determining the type of the specific application corresponding to the specific mapping table entry; as well as According to the type of the specific application, one of the plurality of candidate capacities is determined as the target capacity.

5. The method for adjusting the capacity of a shared cache area according to claim 1, further comprising: When data is to be removed from the shared cache area, the remaining mapping table entries in the at least one mapping table entry that do not belong to the specific mapping table entry are preferentially removed from the shared cache area.

6. A storage system, characterized in that: include: Host system; as well as a storage device, connected to the host system, The host system is used to: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Detecting whether there is a specific mapping table entry corresponding to a specific application in at least one mapping table entry currently cached in the shared cache area, wherein the specific mapping table entry belongs to an active foreground application or an inactive foreground application, wherein if the specific application is running in the foreground of the operating system, the specific mapping table entry is determined to belong to the active foreground application, and if another application replaces the specific application to run in the foreground of the operating system, the specific mapping table entry is determined to belong to the inactive foreground application; If the specific mapping table entry corresponding to the specific application exists in the at least one mapping table entry currently cached in the shared cache area, determining a target capacity from a plurality of candidate capacities; as well as According to the target capacity, adjusting the capacity of the shared cache area, Wherein determining the target capacity from the multiple candidate capacities comprises: If the specific application is the first application, determining a first capacity among the multiple candidate capacities as the target capacity; as well as If the specific application is a second application, a second capacity among the plurality of candidate capacities is determined as the target capacity, wherein the first capacity is different from the second capacity.

7. The storage system according to claim 6, wherein the at least one mapping table entry comprises a target mapping table entry, and the operation of determining whether the at least one mapping table entry currently cached in the shared cache area has the specific mapping table entry corresponding to the specific application comprises: Obtaining identification information corresponding to the target mapping table entry; as well as According to the identification information, it is determined whether the target mapping table entry belongs to the specific mapping table entry.

8. The storage system according to claim 7, wherein the operation of determining whether the target mapping table entry belongs to the specific mapping table entry according to the identification information comprises: According to the identification information, query the management table to obtain a query result, wherein the query result reflects the type of the target mapping table entry; as well as According to the query result, it is determined whether the target mapping table entry belongs to the specific mapping table entry.

9. The storage system according to claim 6, wherein the operation of determining the target capacity from the plurality of candidate capacities comprises: Determining the type of the specific application corresponding to the specific mapping table entry; as well as According to the type of the specific application, one of the plurality of candidate capacities is determined as the target capacity.

10. The storage system according to claim 6, wherein the host system is further configured to: When data is to be removed from the shared cache area, the remaining mapping table entries in the at least one mapping table entry that do not belong to the specific mapping table entry are preferentially removed from the shared cache area.

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