Branch prediction method, branch predictor and related devices

Abstract

Embodiments of the present application provide a branch prediction method, a branch predictor and related devices, wherein the method comprises: obtaining address information and first identification information of a to-be-predicted instruction; based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, which are stored in advance, the redundancy information comprising second identification information and permission information; if the to-be-predicted instruction is a user state instruction, determining whether the first identification information and the second identification information are consistent; if the first identification information and the second identification information are consistent, allowing access of the target address to be executed; if the to-be-predicted instruction is a kernel state instruction, determining whether the permission information is a privilege level identification; if yes, and the first identification information and the second identification information are consistent or inconsistent, allowing access of the target address to be executed. Embodiments of the present application can improve the instruction processing efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of processor, in particular to a branch prediction method, a branch predictor and related devices. BACKGROUND

[0002] In a modern processor, instructions need to go through a fetch, decode, execute and writeback process; among them, the fetch is used to obtain the instructions to be executed, the decode is used to analyze and translate the fetched instructions to obtain the micro-instructions (Uop) corresponding to the instructions, the execution is used to execute the corresponding instruction operation based on the micro-instructions obtained by the decode, and the writeback is used to write the results of the instruction operation back to a preset address.

[0003] However, the existing instruction processing flow needs to be improved in terms of instruction processing efficiency. SUMMARY

[0004] Therefore, embodiments of the present application provide a branch prediction method, a branch predictor and related devices to improve the instruction processing efficiency.

[0005] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, the embodiments of the present application provide a branch prediction method, comprising:

[0007] obtaining address information and first identification information of a to-be-predicted instruction, the first identification information being used to indicate the source of the to-be-predicted instruction;

[0008] based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, which are stored in advance, the redundancy information including second identification information and permission information, the second identification information being used to indicate the source of a history instruction from which the target instruction is obtained, and the permission information being used to indicate whether the history instruction from which the target instruction is obtained is a privileged instruction;

[0009] if the to-be-predicted instruction is a user-mode instruction, judging whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allowing access to the target address to be executed;

[0010] if the to-be-predicted instruction is a kernel-mode instruction, judging whether the permission information is a privileged identification; if yes, and the first identification information and the second identification information are consistent or inconsistent, allowing access to the target address to be executed.

[0011] Optionally, if the to-be-predicted instruction is a kernel-mode instruction, it is judged whether the permission information is a privilege level identifier; if yes, and the first identifier information and the second identifier information are consistent or inconsistent, the access of the target address is executed, specifically as follows:

[0012] If the to-be-predicted instruction is a kernel-mode instruction, it is judged whether the permission information is a privilege level identifier; if yes, the step of judging whether the first identifier information and the second identifier information are consistent is skipped, and the access of the target address is executed.

[0013] Or,

[0014] If the to-be-predicted instruction is a kernel-mode instruction, it is judged whether the permission information is a privilege level identifier, and whether the first identifier information and the second identifier information are consistent; if the permission information is a privilege level identifier, and the first identifier information and the second identifier information are consistent or inconsistent, the access of the target address is executed.

[0015] Optionally, the redundant information further includes a valid identifier for marking whether the target address is valid, and the method further includes:

[0016] receiving a valid identifier refreshing instruction;

[0017] based on the valid identifier refreshing instruction, executing an updating process of the valid identifier of the target address stored in the branch target buffer;

[0018] The updating process includes: judging whether the permission information of the target address is a privilege level identifier; if no, updating the valid identifier of the target address to a first value, the first value being used for marking that the target address is invalid; if yes, skipping the item where the target address is located.

[0019] Optionally, after the target address and the redundant information of the target instruction corresponding to the to-be-predicted instruction are acquired based on the address information, and before the access of the target address is executed, the method further includes:

[0020] based on the valid identifier, judging whether the target address is valid;

[0021] if no, prohibiting the access of the target address.

[0022] Optionally, the first identifier information is a processor core identifier or a logical core identifier of a processor core initiating the to-be-predicted instruction, and the second identifier information is a processor core identifier or a logical core identifier of a processor core initiating a historical instruction.

[0023] Optionally, in a virtualization scenario, the kernel-mode instruction is a kernel-mode instruction of a host.

[0024] In a second aspect, the embodiments of the present application provide a branch predictor, comprising:

[0025] instruction information obtaining logic, configured to obtain address information of a to-be-predicted instruction and first identification information, wherein the first identification information is used to indicate a source of the to-be-predicted instruction;

[0026] prediction information obtaining logic, configured to obtain, based on the address information, a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, wherein the redundancy information comprises second identification information and permission information, the second identification information is used to indicate a source of a history instruction from which the target instruction is obtained, and the permission information is used to indicate whether the history instruction from which the target instruction is obtained is a privileged instruction;

[0027] access determining logic, configured to, if the to-be-predicted instruction is a user-mode instruction, determine whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allow access to the target address to be performed; and if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification, and if yes, and the first identification information and the second identification information are consistent or inconsistent, allow access to the target address to be performed.

[0028] Optionally, the access determining logic is configured to, if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification, and if yes, and the first identification information and the second identification information are consistent or inconsistent, perform access to the target address, specifically:

[0029] if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification, and if yes, skipping the step of determining whether the first identification information and the second identification information are consistent, and performing access to the target address;

[0030] or,

[0031] if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification, and determining whether the first identification information and the second identification information are consistent, and if the permission information is a privileged identification, and the first identification information and the second identification information are consistent or inconsistent, performing access to the target address.

[0032] Optionally, the redundancy information further comprises a valid identification used to mark whether the target address is valid, and the branch predictor further comprises:

[0033] redundancy information refreshing logic, configured to receive a valid identification refreshing instruction, and perform, based on the valid identification refreshing instruction, an updating process on the valid identification of the target address stored in the branch target buffer;

[0034] The update process includes: determining whether the permission information of the target address is a privileged identifier; if not, updating the valid identifier of the target address to a first value, the first value being used to mark the target address as invalid; if yes, skipping the item containing the target address.

[0035] Optionally, the access determination logic is further configured to determine whether the target address is valid based on the valid identifier; if not, to prohibit access to the target address.

[0036] Optionally, the first identification information is the processor core identifier or logical core identifier that initiated the instruction to be predicted, and the second identification information is the processor core identifier or logical core identifier that initiated the historical instruction.

[0037] Optionally, in a virtualization scenario, the kernel-mode instructions are the host's kernel-mode instructions.

[0038] Thirdly, embodiments of this application also provide a processor, the processor including the branch predictor described in the second aspect.

[0039] Fourthly, embodiments of this application also provide a chip, including the processor provided in the third aspect of embodiments of this application.

[0040] Fifthly, embodiments of this application also provide an electronic device, including the chip provided in the fourth aspect of embodiments of this application.

[0041] In a sixth aspect, embodiments of this application also provide a storage medium storing one or more computer-executable instructions for performing the branch prediction method as described in the first aspect.

[0042] In a seventh aspect, embodiments of this application also provide a computer program product, including one or more computer-executable instructions, which, when executed, implement the branch prediction method as described in the first aspect.

[0043] The branch prediction method, the branch predictor and the related device provided by the embodiments of the present application, the method comprises: obtaining address information and first identification information of a to-be-predicted instruction, the first identification information is used to indicate the source of the to-be-predicted instruction; based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address which is stored in advance, the redundancy information comprises second identification information and permission information, the second identification information is used to indicate the source of a historical instruction of the target instruction, and the permission information is used to indicate whether the historical instruction of the target instruction is a privileged instruction; if the to-be-predicted instruction is a user state instruction, it is judged whether the first identification information and the second identification information are consistent, if the first identification information and the second identification information are consistent, the access of the target address is allowed to be executed; if the to-be-predicted instruction is a kernel state instruction, it is judged whether the permission information is a privileged identification; if yes, and the first identification information and the second identification information are consistent or inconsistent, the access of the target address is allowed to be executed.

[0044] It can be seen that, in the branch prediction process, when the to-be-predicted instruction is a user state instruction, the identification information is judged based on the normal process, that is, whether the first identification information and the second identification information are consistent is judged, and when the first identification information and the second identification information are consistent, the access of the target address is allowed to be executed; and when the to-be-predicted instruction is a kernel state instruction, whether the permission information is a privileged identification is judged, and when the permission information is a privileged identification, the access of the target address can be executed regardless of whether the corresponding identification information is consistent, so that the kernel state instruction can access across sources, thereby improving the instruction processing efficiency on the premise of guaranteeing the original safety effect. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0046] Figure 1 It is an optional schematic diagram of an instruction processing flow.

[0047] Figure 2 It is an instruction processing timing schematic diagram in an instruction pipeline.

[0048] Figure 3 It is an optional flow schematic diagram of branch instruction prediction.

[0049] Figure 4 It is a prediction controlled flow schematic diagram.

[0050] Figure 5 An optional structure diagram of a BTB entry.

[0051] Figure 6 An optional diagram of a branch prediction process.

[0052] Figure 7 An optional structure diagram of a BTB entry.

[0053] Figure 8 An optional diagram of a BTB entry access under an IBRS mechanism.

[0054] Figure 9 An optional diagram of a BTB entry access.

[0055] Figure 10 An optional diagram of a branch prediction method provided by an embodiment of the present application.

[0056] Figure 11 An optional structure diagram of a BTB entry provided by an embodiment of the present application.

[0057] Figure 12 An optional diagram of a prediction information refreshing process in a branch prediction method provided by an embodiment of the present application.

[0058] Figure 13 An optional diagram of a branch prediction method provided by an embodiment of the present application.

[0059] Figure 14 An optional structure diagram of a branch predictor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0061] In a general instruction processing process, reference is made to Figure 1The optional schematic diagram of the instruction processing flow is shown. The instructions usually need to go through the processes of instruction fetch, instruction decode, execution and write back in sequence. Instruction fetch is to fetch the instructions corresponding to the program running from the cache or main memory of the processor; instruction decode is to decode the fetched instructions to determine the operation code and / or address code, etc. of the instructions; execution is to execute the instruction operation according to the obtained operation code and / or address code, etc. to realize the program running; and write back is to write the results obtained after executing the program into the register at the preset address.

[0062] In the instruction processing, the processor generally uses the instruction pipeline technology to improve the processing efficiency of the instructions. In this technology, different hardware modules are configured for different processing processes. In the pipeline operation of the processor, multiple instructions in different processing processes can be processed and transferred in the corresponding hardware modules in sequence.

[0063] Reference is made to Figure 2 The schematic diagram of the instruction processing timing in an instruction pipeline is shown. As shown in Figure 2 When instruction 1 enters the decode stage, the processor can perform instruction 2 fetch in advance. When instruction 1 enters the execution stage, the processor can perform instruction 2 decode and instruction 3 fetch in parallel. When instruction 1 enters the write back stage, the processor can perform instruction 2 execution, instruction 3 decode and instruction 4 fetch. When instruction 1 is submitted, the processor can perform instruction 2 write back, instruction 3 execution, instruction 4 decode and instruction 5 fetch. And so on, so as to realize the parallel execution of multiple instructions. It can be seen that in the two clock cycles t1 and t2, the instruction pipeline technology can complete five instructions. Compared with the serial instruction flow which can only complete one instruction in one clock cycle, the processing efficiency of the instructions is greatly improved.

[0064] However, when processing branch instructions (one of the instructions), it is necessary to use a branch prediction mechanism to reduce the instruction delay. It can be understood that the branch instruction is an instruction whose program flow direction can be changed. In a specific program flow, the branch instruction can execute different instruction sequences (i.e. enter different branch flows) based on different instruction results. Reference is made to Figure 3An optional flow diagram of branch instruction prediction is shown. Branch instruction N needs to enter different branch flows, i.e. branch N1 and branch N2, based on the result of instruction M. If the instruction is executed according to normal logic, branch instruction N needs to wait for the result of instruction M, such as result M1 or result M2. However, in the pipeline operation of the processor, multiple instructions in different processing stages are processed in different hardware logics at the same time. The delay of one instruction will block the processing of multiple other instructions in the subsequent pipeline, thereby causing pipeline delay.

[0065] To reduce the pipeline delay caused by the processor waiting for the instruction result of the branch instruction to determine the next instruction fetch, a branch prediction mechanism can be used to predict which instruction to execute next (such as Figure 3 The branch Ni is shown, where i can be 1 or 2. The waiting time of the processor when executing the branch instruction is reduced.

[0066] In an optional prediction mechanism, the target address of the branch instruction can be used for corresponding prediction. Specifically, the address information of the historical branch instruction and the target address corresponding to the historical branch instruction are stored in an entry of a BTB (Branch Target Buffer). When a branch instruction with the same address information appears subsequently, the target address corresponding to the historical branch instruction is used as the address of the predicted target instruction, thereby realizing prediction of the branch instruction. The information stored in the entry can be referred to as prediction information of the BTB.

[0067] However, this prediction mechanism has a security risk. In a specific scenario, such as Spectre Variant 2, an attacker can control the prediction target of the branch predictor through training, guide the victim to speculatively execute some malicious code, and access confidential data. Referring to Figure 4 A controlled flow diagram of prediction is shown. The attacker can use the branch instruction at PC1 address in the attacker address space to train a BTB entry. For example, the attacker can control the branch instruction at PC1 to jump to a target address PC4, so that the target address of the branch instruction corresponding to the BTB entry is the victim address PC4 as intended by the attacker. The attacker can control the branch instruction at PC1 to record that the address information (such as the HASH value of the address) of the branch instruction is equal to the address information (such as the HASH value of the address) of the branch instruction at the victim PC2.

[0068] When the victim executes the branch instruction at PC2, the branch predictor will index the branch instruction at PC2 to the BTB entry trained by the attacker due to the collision of the address information (e.g., the HASH value of the address) of the branch instruction at PC2 and the address information (e.g., the HASH value of the address) of the branch instruction at PC1 of the attacker. At this time, the branch instruction at PC2 of the victim is actually supposed to jump to the instruction at PC3, but the prediction information recorded in the BTB entry predicts that the target address is PC4, so the instruction at PC4 will be taken as the target instruction, and thus the instruction at PC4 trained by the attacker will be executed. Then, the instruction at PC4 executed based on the prediction will access the confidential information and leave a trace in the Cache, which can be recovered by the side-channel technology, resulting in the leakage of the confidential information.

[0069] Correspondingly, in some implementations, hardware defense mechanisms such as STIBP (Single Thread Indirect Branch Prediction) and IBRS (Indirect Branch Restricted Speculation) can eliminate this risk.

[0070] Specifically, under the STIBP mechanism, in the entry of the BTB, in addition to recording the target address of the target instruction, the identification information of the historical branch instruction that leads to the target instruction can also be recorded, for reference Figure 5 An optional structure diagram of a BTB entry is shown, the identification information can be recorded as redundant information (also referred to as a tag) in the entry corresponding to the target address, used to indicate the source of the instruction, the identification information may, for example, be a logical core identification, and correspondingly, the identification information of the historical branch instruction may be the logical core identification that issues the historical branch instruction, and the identification information of the current branch instruction may be the logical core identification that issues the current branch instruction.

[0071] Correspondingly, for reference Figure 6An optional schematic diagram of a branch prediction process is shown, and the branch prediction process is under the STIBP mechanism. The identification information (such as a logical core identification) of an attacker may be TID1, for example, and the identification information (such as a logical core identification) of a victim may be TID2, for example. When the attacker trains the prediction target of the branch prediction controller, the identification information TID1 of the branch instruction of PC1 used for training is recorded in the BTB. In the branch prediction process of the branch instruction of the victim PC2, since the identification information TID2 of the branch instruction of PC2 is different from the identification information TID1 recorded in the corresponding item, that is, the identification information TID2 of the branch instruction is different from the identification information of the historical branch instruction TID1 of the target instruction, the branch instruction of PC2 cannot access the target instruction corresponding to the item address PC4, and thus it is necessary to execute the instruction at PC3 based on an architectural jump.

[0072] However, under the IBRS mechanism, reference is made to Figure 7 An optional structure schematic diagram of a BTB item is shown. In the entry of the BTB, in addition to recording the target address of the target instruction and the identification information of the historical branch instruction obtaining the target instruction (hereinafter referred to as a historical instruction), the permission information of the historical branch instruction obtaining the target instruction is also recorded in the item corresponding to the target address. The permission information may be recorded as redundant information (also referred to as a tag) for indicating whether the instruction is a privileged instruction, so as to distinguish whether the instruction is a kernel mode instruction (in a virtualization scenario, it may be understood as a kernel mode instruction of a host, that is, a HOST instruction) or a user mode instruction.

[0073] It can be understood that the kernel mode instruction is a privileged instruction, and the user mode instruction is a non-privileged instruction. The kernel mode instruction may be understood as an instruction running in a kernel mode, and the user mode instruction may be understood as an instruction running in a user mode. In the branch prediction process under the IBRS mechanism, the branch instruction cannot access the target instruction with identification information different from that of the branch instruction. Under this premise, the branch instruction also cannot access the target instruction that does not conform to the permission access rule.

[0074] Specifically, the permission access rule may be, for example: the user mode branch instruction is allowed to access the target address with the permission information marked as a privileged level identification, which indicates that the historical instruction obtaining the target instruction is a privileged instruction; the kernel mode branch instruction is prohibited from accessing the target address with the permission information marked as a non-privileged level identification, which indicates that the historical instruction obtaining the target instruction is a non-privileged instruction; that is, the user mode branch instruction is allowed to access the target address with the permission information as a privileged level identification and a non-privileged level identification, and the kernel mode branch instruction only accesses the target address with the permission information as a privileged level identification.

[0075] Correspondingly, under the IBRS mechanism, firstly, it is judged whether the identification information of the branch instruction is same as the identification information corresponding to the target address, if same, it is further judged whether the permission of the branch instruction and the permission information of the target address corresponding to the BTB record conform to the permission access rule, and it is determined whether to perform the access to the target address based on the result of the permission access rule.

[0076] Reference Figure 8 A BTB item access schematic diagram under the IBRS mechanism is shown, the identification information is TID0, and the permission information of the branch instruction is privilege level CPL0, and only the target address indicated in the item with the identification information of TID0 and the permission information of CPL0 in the BTB can be accessed; the identification information is TID1, and the branch instruction with the permission information of non-privilege level CPL3 is allowed to access the target address indicated in the item with the identification information of TID1 and the permission information of CPL3 and CPL0 in the BTB.

[0077] The inventors believe that under the above hardware defense mechanism, the instruction processing efficiency needs to be improved. After analysis, the main reason is that some instructions have cross-source sharing (such as cross-core sharing) needs, and both STIBP and IBRS prohibit cross-source access for all instructions, resulting in that instructions with cross-source sharing needs cannot achieve cross-core access. That is, the prediction mechanism with the hardware defense mechanism sacrifices the instruction processing efficiency under the premise of ensuring security.

[0078] The inventors consider that it can be tried to distinguish instructions with cross-source sharing needs and allow part of instructions with cross-source sharing needs to perform cross-source sharing, and under this premise, the original security effect should also be ensured. After research, the inventors believe that the instructions can be divided from the perspective of the kernel mode and the user mode (that is, the perspective of instruction permission judgment) under the premise of combining permission judgment, so as to distinguish instructions that need to be cross-source shared, and allow part of the instructions to cross-source share corresponding prediction data (that is, data in the BTB) under the premise of conforming to the permission access rule. That is, Figure 9 A BTB item access schematic diagram is shown, the identification information is TID0, and the permission information of the branch instruction is CPL0, which can not only access the target address indicated in the item with the identification information of TID0 and the permission information of CPL0 in the BTB, but also access the target address indicated in the item with the identification information of TID1 and the permission information of CPL0 in the BTB.

[0079] This is because, among the instructions with cross-source sharing needs, the kernel mode instruction has a greater cross-source sharing demand as a system-level management control instruction, and based on the permission access rule, the permission of the kernel mode instruction is high, the corresponding security risk is low, and the cross-source access has little effect on the original security protection effect.

[0080] Specifically, if an attacker attacks a high-privilege kernel-mode instruction in a low-privilege mode, a high-privilege target address needs to be trained under the premise of complying with the privilege access rule. At this time, the attacker can only train through a system call and use a branch instruction in the system call to train. In this scenario, the training process of the attacker is greatly limited. First, the branch instruction address used by the attacker for training is limited by the address of the system call in the kernel, and it is difficult to construct a training address that collides with the victim's HASH. Second, the target address used by the attacker for training is determined by the target address of the branch instruction in the system call, which is not controlled by the attacker, so it is difficult to construct a target address that meets the attacker's intention. Therefore, the risk of implementing an attack in this attack scenario is almost impossible.

[0081] If an attacker wants to attack a high-privilege kernel-mode instruction in a high-privilege mode, the attacker first needs to break through the privilege level boundary under the premise of complying with the privilege access rule. However, if the attacker has broken through the privilege level boundary, the corresponding security risk will be more direct confidential data leakage, and information leakage based on the speculative execution mechanism is unnecessary. That is, this scenario is meaningless.

[0082] Obviously, under the premise of combining the privilege judgment, the instructions are divided from the perspective of the kernel mode and the user mode (that is, the perspective of the instruction priority), so as to distinguish the instructions that have cross-source sharing needs and allow the part of the instructions to cross-source share under the premise of complying with the privilege access rule, which can improve the instruction processing efficiency under the premise of guaranteeing the original security effect.

[0083] Therefore, an embodiment of the present application provides a branch prediction method, a branch predictor and related equipment. The method comprises: obtaining address information and first identification information of a to-be-predicted instruction, the first identification information being used to indicate the source of the to-be-predicted instruction; based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, which are stored in advance, the redundancy information comprising second identification information and privilege information, the second identification information being used to indicate the source of a historical instruction from which the target instruction is obtained, and the privilege information being used to indicate whether the historical instruction from which the target instruction is obtained is a privilege-level instruction; if the to-be-predicted instruction is a user-mode instruction, judging whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allowing access of the target address to be executed; if the to-be-predicted instruction is a kernel-mode instruction, judging whether the privilege information is a privilege-level identification; if yes, and the first identification information and the second identification information are consistent or inconsistent, allowing access of the target address to be executed.

[0084] It can be seen that, in the branch prediction process, when the to-be-predicted instruction is a user-mode instruction, the identification information is judged based on the normal process, that is, whether the first identification information and the second identification information are consistent is judged, and when the first identification information and the second identification information are consistent, the access to the target address is allowed to be executed; and when the to-be-predicted instruction is a kernel-mode instruction, whether the permission information is a privilege level identification is judged, and when the permission information is a privilege level identification, the access to the target address can be executed regardless of whether the corresponding identification information is consistent, so that the kernel-mode instruction can access across sources, thereby improving the instruction processing efficiency on the premise of guaranteeing the original security effect.

[0085] Next, the branch prediction scheme provided by the embodiment of the application is described in detail.

[0086] Figure 10 An optional flowchart of a branch prediction method provided by the embodiment of the application is shown in Figure 10 , and the branch prediction flowchart comprises the following steps.

[0087] In step S100, address information and first identification information of a to-be-predicted instruction are acquired, and the first identification information is used to indicate the source of the to-be-predicted instruction.

[0088] The to-be-predicted instruction is a branch instruction of a to-be-predicted branch, and the address information is used to indicate the address of the to-be-predicted instruction, which can be, for example, a HASH value of the address. The identification information is used to indicate the source of the instruction, which is used to indicate the initiator of the instruction, which can be, for example, a processor core that initiates the instruction, and when there is a logical core, the source can also be the logical core, and correspondingly, the identification information can be a processor core identification or a logical core identification that initiates the instruction, and the like. The first identification information is used to indicate the source of the to-be-predicted instruction in the embodiment, for example, the first identification information is a processor core identification or a logical core identification that initiates the to-be-predicted instruction, so as to control the access to the target address indicated in the branch target buffer (BTB) based on the source. When the identification information is a logical core identification that initiates the instruction, the method can be applied in a processor core, and is used to realize the access to the predicted data across logical cores in the processor core.

[0089] It can be understood that the instruction information of the instruction recorded in the processor generally includes the source information (i.e., the identification information) of the instruction, and correspondingly, the first identification information can be acquired from the instruction information recorded in the processor.

[0090] In step S110, based on the address information, the target address of the target instruction corresponding to the to-be-predicted instruction and the redundancy information of the target address are acquired.

[0091] It can be understood that the prediction information pre-stored in the BTB is obtained based on the processing flow of the historical instruction, and the prediction information can include the address of the target instruction predicted for the historical instruction, that is, the target address, wherein the target instruction can be understood as the result of the prediction of the BTB, that is, the next instruction predicted for the to-be-predicted instruction. Based on the address information of the historical instruction and the address information of the to-be-predicted instruction, the target address of the corresponding target instruction can be determined.

[0092] The redundant information includes second identification information and permission information, the second identification information is used to indicate the source of the historical instruction from which the target instruction is obtained, and the permission information is used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction;

[0093] In the stored prediction information, the second identification information in the redundant information is used to indicate the source of the historical instruction from which the target instruction is obtained, for example, the second identification information can be a processor core identifier or a logical core identifier that initiates the historical instruction, so that based on the second identification information, it is confirmed whether the source of the to-be-predicted instruction is consistent with the source of the historical instruction from which the target instruction is obtained, if consistent, it indicates that the source of the to-be-predicted instruction is the same as that of the historical instruction, and the access to the corresponding target address can be understood as a safe access; if not consistent, the source of the to-be-predicted instruction is not the same as that of the historical instruction, and the access to the corresponding target address can have a security risk.

[0094] The permission information in the redundant information is used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction; wherein the privileged instruction can be understood as a kernel mode instruction, that is, an instruction running in a kernel mode, and the non-privileged instruction can be understood as a user mode instruction, that is, an instruction running in a user mode. Based on the marking of the permission information, the access to the target address can be controlled, and the access to the target address can be realized only on the premise of meeting the permission access rule, that is, the privileged instruction accesses the target address obtained by the historical instruction being a privileged instruction, and the non-privileged instruction accesses the target address obtained by the historical instruction being a privileged instruction or a non-privileged instruction.

[0095] It can be understood that the instruction information of the to-be-predicted instruction usually records the attribute and source of the instruction, and therefore, based on the instruction information of the to-be-predicted instruction, it can be determined whether the to-be-predicted instruction is a kernel mode instruction, wherein if yes, step S120 is executed, and it is determined whether to allow the access to the target address based on the judgment of the permission information, and if no, it indicates that the to-be-predicted instruction is a user mode instruction, and step S130 is executed, and based on the result of step S130, it is determined whether to allow the access to the target address.

[0096] Specifically, steps S120 and S130 are described as follows:

[0097] Step S120: judging whether the permission information is a privilege level identifier;

[0098] By judging whether the permission information is a privilege level identifier, it is determined whether the historical instruction is a privilege level instruction, thereby allowing the corresponding access to be executed based on the permission access rule.

[0099] In the present application, when the to-be-predicted instruction is a user state instruction, the access to the target address can be executed regardless of whether the permission information is a privilege level identifier or a non-privilege level identifier. Accordingly, when the to-be-predicted instruction is a user state instruction, the judgment of the permission information in the present step is not needed, i.e., the present step can be skipped, or the present step can be executed, but regardless of the result (e.g., yes or no), it is determined whether to allow the access to the target address to be executed based on the result of step S130.

[0100] In the optional example, when there are two kinds of judgments of the permission condition and the source condition, when the result of the present step is yes, step S130 can be skipped, or step S130 can be executed, but regardless of the result (e.g., yes or no), step S200 is allowed to be executed to implement the access to the target address, thereby enabling the to-be-predicted instruction to share the prediction information in the BTB across sources.

[0101] It should be noted that when the to-be-predicted instruction is a user state instruction, the access to the target address can be executed regardless of whether the permission information is a privilege level identifier or a non-privilege level identifier. Accordingly, when the to-be-predicted instruction is a user state instruction, the judgment of the permission information in the present step is not needed, i.e., the present step can be skipped, or the present step can be executed, but regardless of the result (e.g., yes or no), it is determined whether to allow the access to the target address to be executed based on the result of step S130.

[0102] Step S130: judging whether the first identifier information and the second identifier information are consistent;

[0103] By judging whether the identifier information (i.e., the first identifier information of the to-be-predicted instruction and the second identifier information of the historical instruction) is consistent, it is determined whether the to-be-predicted instruction and the historical instruction are of the same source, thereby determining whether to execute the access to the corresponding target address based on the result.

[0104] In the present application, when the to-be-predicted instruction is a user state instruction, the access to the target address can be executed regardless of whether the permission information is a privilege level identifier or a non-privilege level identifier. Accordingly, when the to-be-predicted instruction is a user state instruction, the judgment of the permission information in the present step is not needed, i.e., the present step can be skipped, or the present step can be executed, but regardless of the result (e.g., yes or no), it is determined whether to allow the access to the target address to be executed based on the result of step S130.

[0105] When the to-be-predicted instruction is a kernel-mode instruction, in order to realize sharing of prediction information from different sources, step S130 can be skipped, or, when the result of step S120 is yes, step S130 is executed again, and no matter what the result of step S130 is (i.e. when the result of the judgment is yes or no), the access to the target address in step S200 is allowed.

[0106] It should be noted that when both step S120 and step S130 need to be executed, step S120 and step S130 can be executed simultaneously or sequentially, and then corresponding processing procedures can be executed based on the corresponding results.

[0107] Step S200: performing the access to the target address;

[0108] Based on the foregoing result, the access to the target address can be performed to realize branch prediction of the to-be-predicted instruction.

[0109] It can be seen that, in the embodiment of the present application, when the to-be-predicted instruction is a user-mode instruction, the judgment of the identification information is based on the normal procedure, and when the to-be-predicted instruction is a kernel-mode instruction, the judgment of whether the permission information is a privilege-level identification is used as a criterion, and the judgment of the identification information indicating the source of the prediction data is no longer performed, so that the kernel-mode instruction can access across sources, thereby improving the instruction processing efficiency on the premise of guaranteeing the original security effect.

[0110] In a further example, referring to Figure 11 An optional structure diagram of a BTB item is shown, and the redundant information further includes a valid identification for marking whether the target address is valid, which can invalidate the historical prediction information (i.e. existing prediction information) in the BTB at a preset occasion, thereby avoiding the influence of the historical prediction information on subsequent instructions and excluding possible security risks. The preset occasion can be, for example, device switching mode or switching user.

[0111] As can be seen from the foregoing analysis, sharing of prediction information of historical instructions of a privilege level does not increase security risks, but can improve the instruction processing efficiency on the premise of guaranteeing the original security effect, and therefore, in order to further improve the instruction processing efficiency, the embodiment of the present application further adjusts the refreshing procedure of the valid identification, keeps the valid identification of the prediction information meeting the permission condition unchanged (i.e. does not perform the invalidation procedure of the prediction information meeting the permission condition), so that the kernel-mode instruction can share the historical prediction information.

[0112] Referring to Figure 12 A prediction information refreshing procedure in a branch prediction method is shown, and the refreshing procedure includes:

[0113] Step S300: receiving a valid identification refreshing command;

[0114] The valid identification refreshing command is used to invalidate the historical prediction information in the BTB, so as to avoid the influence of the historical prediction information on the subsequent instructions. It can be understood that at a preset occasion (for example, when the device switches the mode or switches the user), the device will issue a valid identification refreshing command, so that the existing prediction information is invalidated based on the valid identification refreshing command, thereby avoiding the influence of the historical prediction information on the subsequent instructions.

[0115] It should be noted that in the embodiment of the application, the refreshing of the historical prediction information can skip the item (i.e. the prediction information) of the prediction information that meets the permission condition, so that the kernel instruction can access the target address obtained based on the historical instruction for the privileged instruction, thereby improving the instruction processing efficiency.

[0116] Step S310: based on the valid identification refreshing command, performing an updating process of the valid identification of the target address stored in the branch target buffer;

[0117] The updating process includes: judging whether the permission information of the target address is a privileged identification; if not, updating the valid identification of the target address to a first value, the first value being used to mark that the target address is invalid; if yes, skipping the item where the target address is located, so that the valid identification of the target address remains the original value.

[0118] The first value may be, for example, "0", to mark that the corresponding target address is invalid. In an optional example, the valid identification may also be a second value, which may be, for example, "1", to mark that the corresponding target address is valid. In the embodiment of the application, if the valid identification of the target address is not invalidated, i.e. the valid identification of the target address is the second value, by skipping the item where the target address is located, the valid identification of the target address can always remain the original value (i.e. the second value), so that the kernel instruction can access the target address obtained based on the historical instruction for the privileged instruction, thereby improving the instruction processing efficiency.

[0119] Correspondingly, in an optional implementation of the embodiment of the application, the embodiment of the application also provides a branch prediction process performed based on the valid identification. Specifically, referring to Figure 13 An optional flowchart of a branch prediction method is shown, after step S110 is performed, before step S200 is performed, the branch prediction method further includes:

[0120] S140: judging whether the target address is valid based on the valid identification;

[0121] It can be understood that the history prediction information in the BTB can be invalidated at the preset time based on the valid identifier, and the prediction information corresponding to the non-privileged instructions in the BTB before and after the preset time is avoided from being confused and shared by judging whether the target address is valid.

[0122] Specifically, if yes, it indicates that the target address (which can also be understood as the prediction information where the target address is located) is valid, and the execution step S200 is allowed to implement the access to the target address. If no, it indicates that the target address (which can also be understood as the prediction information where the target address is located) is invalid, and the execution step S200 is prohibited.

[0123] It should be noted that in the example in which the valid identifier exists, whether the to-be-predicted instruction is a kernel-mode instruction or a user-mode instruction, the step S140 needs to be executed to judge the validity of the prediction information.

[0124] It should be noted that the execution order of the above steps S120, S130 and S140 is not limited, and the steps can be executed simultaneously or sequentially, and the present application does not make a specific limitation here, Figure 13 For example, the step S140 is executed later. However, when the result of any step indicates that the execution step S200 is prohibited, the step S200 is not executed. In optional examples, different steps can be selected for instructions of different privilege levels, for example, when the to-be-predicted instruction is a kernel-mode instruction, the steps S120 and S140 are selected to be executed, the step S130 is skipped, and the step S200 is executed when both steps indicate that the execution step S200 is allowed. When the to-be-predicted instruction is a user-mode instruction, the steps S130 and S140 are selected to be executed, and the step S200 is executed when both steps indicate that the execution step S200 is allowed.

[0125] It can be seen that in the embodiments of the present application, the further configured valid identifier is used for corresponding access control, the influence of the prediction information obtained by the non-privileged history instructions on the subsequent instructions is avoided, and possible security risks are excluded.

[0126] In an optional implementation, with reference to Figure 14 An optional structure diagram of a branch predictor provided by an embodiment of the present application is shown in the figure, the branch predictor can be an optional hardware structure for implementing the branch prediction method, and the branch predictor comprises:

[0127] The instruction information acquisition logic 400 is configured to acquire address information and first identifier information of a to-be-predicted instruction, and the first identifier information is used to indicate the source of the to-be-predicted instruction.

[0128] The prediction information obtaining logic 410 is configured to obtain, based on the address information, pre-stored target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, the redundancy information including second identification information and permission information, the second identification information being used to indicate a source of a history instruction of the target instruction, and the permission information being used to indicate whether the history instruction of the target instruction is a privileged instruction.

[0129] The access determination logic 420 is configured to, if the to-be-predicted instruction is a user-mode instruction, determine whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allow access to the target address; or if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification, and if yes, and the first identification information and the second identification information are consistent or inconsistent, allow access to the target address.

[0130] Optionally, the access determination logic 420 is configured to, if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification, and if yes, and the first identification information and the second identification information are consistent or inconsistent, perform access to the target address, specifically:

[0131] if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification, and if yes, skipping the step of determining whether the first identification information and the second identification information are consistent, and performing access to the target address;

[0132] or,

[0133] if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification, and determining whether the first identification information and the second identification information are consistent, and if the permission information is a privileged identification, and the first identification information and the second identification information are consistent or inconsistent, performing access to the target address.

[0134] Optionally, the redundancy information further includes a valid identification used to mark whether the target address is valid, and the branch predictor further includes:

[0135] The redundancy information refreshing logic 430 is configured to receive a valid identification refreshing instruction, and perform, based on the valid identification refreshing instruction, an updating process on the valid identification of the target address stored in the branch target buffer.

[0136] The updating process includes: determining whether the permission information of the target address is a privileged identification, and if not, updating the valid identification of the target address to a first value, the first value being used to mark that the target address is invalid, and if yes, skipping the item where the target address is located.

[0137] Optionally, the access determination logic 420 is further configured to determine whether the target address is valid based on the valid identification; and if not, prohibit the access of the target address.

[0138] Optionally, the first identification information is a processor core identification or a logical core identification of a processor core that initiates the instruction to be predicted, and the second identification information is a processor core identification or a logical core identification of a processor core that initiates the historical instruction.

[0139] Optionally, in a virtualization scenario, the kernel-mode instruction is a kernel-mode instruction of a host.

[0140] It can be understood that the scheme provided by the embodiments of the present application is based on a normal flow to determine the permission information and the identification information when the instruction to be predicted is a user-mode instruction, that is, to determine whether the permission information is a privilege level identification; if not, to determine whether to perform the access of the target address based on the first identification information and the second identification information; and when the instruction to be predicted is a kernel-mode instruction, to determine whether the permission information is a privilege level identification, and when the permission information is a privilege level identification, to perform the access of the target address regardless of whether the corresponding identification information is consistent, so that the kernel-mode instruction can be accessed across sources, thereby improving the instruction processing efficiency on the premise of guaranteeing the original security effect.

[0141] The embodiments of the present application also provide a processor, which can include the branch predictor described above.

[0142] The embodiments of the present application also provide a chip, which can include the processor described above.

[0143] The embodiments of the present application also provide an electronic device, which can include the chip described above.

[0144] The embodiments of the present application also provide a storage medium, which stores one or more computer executable instructions, and the one or more computer executable instructions are used to perform the branch prediction method described above.

[0145] The embodiments of the present application also provide a computer program product, which includes one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the branch prediction method described above.

[0146] The above describes the multiple embodiment schemes provided by the embodiments of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiment schemes disclosed and disclosed by the embodiments of the present application.

[0147] Although the present application discloses the above-mentioned embodiments, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A branch prediction method characterized by, The method comprises: obtaining address information and first identification information of a to-be-predicted instruction, the first identification information being used to indicate a source of the to-be-predicted instruction; based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, which are stored in advance, the redundancy information comprising second identification information and permission information, the second identification information being used to indicate a source of a historical instruction from which the target instruction is obtained, and the permission information being used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction; if the to-be-predicted instruction is a user-mode instruction, determining whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allowing access to the target address to be executed; if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification; if yes, and regardless of whether the first identification information and the second identification information are consistent or inconsistent, allowing access to the target address to be executed.

2. The branch prediction method of claim 1, wherein, if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification; if yes, skipping the step of determining whether the first identification information and the second identification information are consistent, and executing access to the target address; or, if the to-be-predicted instruction is a kernel-mode instruction, determining whether the permission information is a privileged identification, and determining whether the first identification information and the second identification information are consistent; if the permission information is a privileged identification, and regardless of whether the first identification information and the second identification information are consistent or inconsistent, executing access to the target address. The redundancy information further comprises a valid identification used to mark whether the target address is valid, and the method further comprises:

3. The branch prediction method according to claim 1 or 2, characterized by, receiving a valid identification refreshing instruction; based on the valid identification refreshing instruction, executing an updating process of the valid identification of the target address stored in the branch target buffer; wherein, the updating process comprises: determining whether the permission information of the target address is a privileged identification; if no, updating the valid identification of the target address to a first value, the first value being used to mark that the target address is invalid; if yes, skipping the item in which the target address is located. After the target address of the target instruction corresponding to the to-be-predicted instruction and the redundancy information of the target address are obtained based on the address information, and before the access to the target address is executed, the method further comprises:

4. The branch prediction method of claim 3, wherein, based on the valid identification, determining whether the target address is valid; if no, prohibiting the access to the target address to be executed. The first identification information is a processor core identification or a logical core identification of an initiator of the to-be-predicted instruction, and the second identification information is a processor core identification or a logical core identification of an initiator of a historical instruction.

5. The branch prediction method of claim 1, wherein, In a virtualization scenario, the kernel-mode instruction is a kernel-mode instruction of a host.

6. The branch prediction method of claim 1, wherein, The method comprises:

7. A branch predictor characterized by, ​ instruction information obtaining logic configured to obtain address information of a to-be-predicted instruction and first identification information, the first identification information being used to indicate a source of the to-be-predicted instruction; prediction information obtaining logic configured to obtain, based on the address information, a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, the redundancy information including second identification information and permission information, the second identification information being used to indicate a source of a history instruction from which the target instruction is obtained, and the permission information being used to indicate whether the history instruction from which the target instruction is obtained is a privileged instruction; access determination logic configured to, if the to-be-predicted instruction is a user-mode instruction, determine whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allow access to the target address to be performed. if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification; if yes, and regardless of whether the first identification information and the second identification information are consistent or inconsistent, allow access to the target address to be performed.

8. The branch predictor of claim 7, wherein, The access determination logic is configured to, if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification; if yes, skip the step of determining whether the first identification information and the second identification information are consistent, and perform access to the target address. Or, if the to-be-predicted instruction is a kernel-mode instruction, determine whether the permission information is a privileged identification, and determine whether the first identification information and the second identification information are consistent; if the permission information is a privileged identification, and regardless of whether the first identification information and the second identification information are consistent or inconsistent, perform access to the target address. The redundancy information further includes a valid identification used to mark whether the target address is valid, and the branch predictor further includes:

9. The branch predictor according to claim 7 or 8, characterized in that, redundancy information refreshing logic configured to receive a valid identification refreshing instruction, and perform, based on the valid identification refreshing instruction, an updating process on the valid identification of the target address stored in the branch target buffer. The updating process includes: determining whether the permission information of the target address is a privileged identification; if no, updating the valid identification of the target address to a first value, the first value being used to mark that the target address is invalid; and if yes, skipping the item in which the target address is located. The access determination logic is further configured to determine, based on the valid identification, whether the target address is valid; if no, prohibit access to the target address to be performed.

10. The branch predictor of claim 9, wherein, The first identification information is a processor core identification or a logical core identification of a processor core that initiates the to-be-predicted instruction, and the second identification information is a processor core identification or a logical core identification of a processor core that initiates a history instruction.

11. The branch predictor of claim 7, wherein, In a virtualization scenario, the kernel-mode instruction is a kernel-mode instruction of a host.

12. The branch predictor of claim 7, wherein, The processor includes the branch predictor of any one of claims 7-12.

13. A processor, comprising: The processor includes the processor of claim 13.

14. A chip, characterized by ​ 15. An electronic device, comprising: A chip comprising the chip as claimed in claim 14.

16. A storage medium, characterized by The storage medium stores one or more computer-executable instructions for performing the branch prediction method as claimed in any one of claims 1-6.

17. A computer program product, characterised in that, The storage medium stores one or more computer-executable instructions for performing the branch prediction method as claimed in any one of claims 1-6.

Images