Resource scheduling method, resource access method and electronic equipment

Abstract

The invention discloses a resource scheduling method, a resource access method and electronic equipment, and belongs to the technical field of resource access and management.The disclosed method comprises the steps that in response to a detected cache resource scheduling instruction, matched target cache resource scheduling information is determined from multiple sets of cache resource scheduling information, and the target cache resource scheduling information is sent to a server; the cache resource scheduling information in the multiple groups of cache resource scheduling information at least comprises a cache mode corresponding to a cache resource; and executing cache resource scheduling processing matched with the target cache resource scheduling information on a target cache resource.

Description

Technical Field

[0001] The present application belongs to the technical field of resource access and management, and in particular, relates to a resource scheduling method, a resource access method and an electronic device. Background Art

[0002] System Level Cache (SLC) is a storage device integrated inside the SoC (System on Chip) chip. It is used to provide cache services for multiple master devices of the SoC. It reduces the access to DDR SDRAM (Double Data Rate SDRAM) by retaining the data that the master devices need to access frequently inside the chip, thereby reducing latency and saving power.

[0003] SLC generally supports two working modes, namely Cache mode and OCM (On Chip Memory) mode. In Cache mode, the data in SLC may be replaced, and the data access of SoC master device is prone to delay jitter; in OCM mode, SLC works as a normal memory without replacement algorithm, so it can ensure that the data is always stored in the chip, which helps to provide a certain access delay for SoC master device. Existing SLC designs generally support the coexistence of Cache mode and OCM mode, that is, by dividing the SLC capacity, one part of the SLC cache area works in Cache mode and the other part of the SLC cache area works in OCM mode, but this division is static, that is, once the division is completed in the power-on initialization phase, it cannot be dynamically adjusted. However, the static division mechanism of target cache resources such as SLC lacks flexibility. With the increasing diversity of chip usage scenarios such as SoC, the static division mechanism is gradually unable to adapt to the ever-changing usage requirements of target cache resources. Summary of the invention

[0004] To this end, this application discloses the following technical solutions:

[0005] A resource scheduling method, comprising:

[0006] In response to detecting the cache resource scheduling instruction, determining matching target cache resource scheduling information from multiple sets of cache resource scheduling information, wherein the cache resource scheduling information in the multiple sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource;

[0007] For the target cache resource, a cache resource scheduling process matching the target cache resource scheduling information is executed.

[0008] Optionally, in response to detecting the cache resource scheduling instruction, determining matching target cache resource scheduling information from multiple sets of cache resource scheduling information includes:

[0009] In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

[0010] Optionally, the target cache resource scheduling information includes: cache mode information and operation information;

[0011] The cache mode information is used to indicate whether to set the first cache area in the target cache resource to the first cache mode or to cancel the first cache mode for the corresponding second cache area; the operation information is used to indicate the transmission operation mode between the data in the target cache resource and the storage component;

[0012] The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction.

[0013] Optionally, when the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, the target cache resource scheduling information further includes configuration address information.

[0014] Optionally, the performing cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information includes:

[0015] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a target address space of the first cache area is determined according to the configuration address information; data in the first cache area is written into a corresponding storage area of ​​a storage component according to the target address space; and a corresponding first operation is performed on the first cache area according to the operation information;

[0016] In response to the target cache resource scheduling information indicating that the first cache mode will be revoked for the corresponding second cache area, a corresponding second operation is performed on the second cache area according to the operation information; the configuration address information of the second cache area stored in the second configuration component of the target group and the second way identifier used to indicate the way corresponding to the second cache area are cleared.

[0017] Optionally, the resource scheduling method further includes:

[0018] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction mark for a path corresponding to the first cache area is set;

[0019] In response to the target cache resource scheduling information indicating that the first cache mode is canceled for the corresponding second cache area, the use restriction mark for the path corresponding to the second cache area is canceled;

[0020] The use restriction mark is used to restrict the reallocation and use of the corresponding way in the first cache mode; the target cache resource is divided into multiple ways, each way corresponding to a cache area of ​​a corresponding size.

[0021] A resource access method, comprising:

[0022] Obtain access request to target cache resource;

[0023] Matching the first access address included in the access request with the address range of the target cache resource to obtain a matching result;

[0024] Determine the request type of the access request to the target cache resource according to the matching result; the request type is used to indicate the cache mode of the cache area requested to access the target cache resource, and the cache area in the target cache resource can be scheduled to be in different cache modes;

[0025] According to the request type, an access operation matching the access request is performed on a corresponding cache area in the target cache resource.

[0026] Optionally, before performing an access operation matching the access request on a corresponding cache area in the target cache resource according to the request type, the method further includes:

[0027] Based on the determined request type, performing a target adding operation on the access request; the target adding operation is used to add a corresponding request type to the access request;

[0028] The performing, according to the request type, an access operation matching the access request on a corresponding cache area in the target cache resource comprises:

[0029] If a request type indicating access to a cache area of ​​a first cache mode is added to the access request, the first access address is mapped to a second access address of the target cache resource based on a first mapping method, and the cache area of ​​the first mode in the target cache resource is accessed based on the second access address;

[0030] If the access request is not added with a request type for indicating access to the cache area of ​​the first cache mode or is added with a request type for indicating access to the cache area of ​​the second cache mode, mapping the first access address to a third access address of the target cache resource based on a second mapping manner, and accessing the cache area of ​​the second cache mode in the target cache resource based on the third access address;

[0031] The permission for using the target cache resource in the first cache mode is higher than the permission for using the target cache resource in the second cache mode.

[0032] Optionally, matching the first access address included in the access request with the address range of the target cache resource includes:

[0033] Matching the first access address included in the access request with the target address range in the address range of the target cache resource to obtain a matching result;

[0034] The target address range is an address range corresponding to a cache area in the target cache resource that is in a first cache mode.

[0035] An electronic device, comprising:

[0036] A determination module, configured to determine, in response to detecting a cache resource scheduling instruction, matching target cache resource scheduling information from a plurality of sets of cache resource scheduling information, wherein the cache resource scheduling information in the plurality of sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource;

[0037] The resource scheduling processing module is used to perform cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource.

[0038] Optionally, the electronic device further comprises a configuration module, wherein the configuration module comprises a first configuration component for configuring command data and a plurality of groups of second configuration components for configuring cache resource configuration information;

[0039] The determination module is specifically used for:

[0040] In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from the multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

[0041] Optionally, the electronic device further includes a management module for performing configuration management on the configuration module;

[0042] The management module is used to:

[0043] Before the determination module responds to the cache resource scheduling instruction, a target group second configuration component that can be used to allocate cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the first configuration information for allocating cache resources in the first cache mode is written to the determined target group second configuration component; and / or, a target group second configuration component that can be used to revoke cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the second configuration information for revoking cache resources in the first cache mode is written to the determined target group second configuration component;

[0044] Writing instruction data for instructing cache resource scheduling into the first configuration component;

[0045] The target cache resource scheduling information includes the first configuration information and / or the second configuration information.

[0046] Optionally, the electronic device further includes a data transmission module, configured to perform at least one of the following:

[0047] In the case where the cache resource scheduling process is used to allocate a cache area of ​​the first cache mode, writing the data in the cache area of ​​the target cache resource that needs to be scheduled as the first cache mode back to the corresponding first storage area in the storage component;

[0048] In the case where the cache resource scheduling process is used to allocate cache resources of the first cache mode, the storage data of the second storage area in the storage component is loaded into the cache area in the target cache resource that needs to be scheduled as the first cache mode.

[0049] Optionally, the electronic device further includes a replacement strategy module, configured to:

[0050] In a case where the obtained access request to the target cache resource is used to indicate access to the target cache area of ​​the second cache mode and the target cache area is missing from the target cache resource, determining a target way that is not in the first cache mode from the target cache resource according to usage restriction tags corresponding to different ways in the target cache resource, and allocating the cache area corresponding to the target way as the target cache area of ​​the second cache mode;

[0051] Among them, the cache area within the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple ways, each way corresponds to a cache area of ​​corresponding size; the usage restriction mark is used to limit the reallocation and use of the corresponding way in the first cache mode.

[0052] A storage medium carries one or more computer instruction sets, which, when executed by an electronic device, can enable the electronic device to implement any of the resource scheduling methods or resource access methods provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0054] Figure 1 It is a flow chart of the resource scheduling method provided by this application;

[0055] Figure 2 It is a schematic diagram of register configuration provided by this application;

[0056] Figure 3 It is a schematic diagram of the working mechanism of the DMA engine provided by this application;

[0057] Figure 4 This is a schematic diagram of the working mechanism of the flush cache module provided by this application;

[0058] Figure 5 It is a schematic diagram of the working mechanism of the replacement strategy module provided by this application;

[0059] Figure 6 is a flow chart of the resource access method provided by this application;

[0060] Figure 7 It is a schematic diagram of the working mechanism of the OCM request judgment module provided by this application;

[0061] Figure 8 It is a structural diagram of the electronic device provided in this application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] The embodiments of the present application provide a resource scheduling method, a resource access method and an electronic device for dynamically scheduling different cache areas of a target cache resource according to a required cache mode, so as to improve the management flexibility of the target cache resource and adapt to the ever-changing usage requirements of the target cache resource.

[0064] The resource scheduling method or resource access method provided in the embodiments of the present application can be applied to electronic devices in many general or special computing device environments or configurations, such as personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor devices, etc.

[0065] See also Figure 1 As shown in the method flow chart, the resource scheduling method provided in the embodiment of the present application may include the following steps 101 to 102, and these steps are described in detail below.

[0066] Step 101: In response to detecting a cache resource scheduling instruction, determining matching target cache resource scheduling information from multiple sets of cache resource scheduling information; the cache resource scheduling information in the multiple sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource.

[0067] The cache resource scheduling instruction is a scheduling instruction for a target cache resource. The target cache resource may be, but is not limited to, a system-level cache SLC in a chip such as a SoC.

[0068] The cache area in the target cache resource can be scheduled to be in different cache modes. The different cache modes include a first cache mode and a second cache mode. The first cache mode has a higher right to use the target cache resource than the second cache mode.

[0069] Taking the target cache resource as SLC as an example, the first cache mode can be OCM mode, that is, on-chip memory mode, and the second cache mode can be Cache mode. Among them, the OCM mode has higher access rights to SLC than the Cache mode. In Cache mode, the data in SLC may be replaced, and data access of the SoC master device is prone to delay jitter; in OCM mode, SLC works as a normal memory without replacement algorithm, so it can ensure that data is always stored on the chip, which helps to provide a certain access delay for the SoC master device.

[0070] The cache resource scheduling information includes at least the cache mode of the corresponding cache resource, for example, at least mode information used to indicate whether the corresponding cache resource is in the first cache mode or the second cache mode, etc. In addition, it may also include but is not limited to the address information of the corresponding cache resource, the path information of the corresponding cache resource and / or the operation information required when the corresponding cache resource is scheduled, etc.

[0071] The target cache resource is divided into multiple paths, each path corresponding to a cache area of ​​a corresponding size.

[0072] In implementation, the cache resource scheduling instruction for the target cache resource may be pre-configured before step 101 according to actual application requirements.

[0073] Optionally, in the embodiment of the present application, a first configuration component and a plurality of groups of second configuration components are pre-set in the electronic device, wherein the first configuration component can be used to configure instruction data, and the instruction data may include but is not limited to instruction data for indicating cache resource scheduling. Each group of second configuration components can be used to configure cache resource scheduling information.

[0074] Exemplarily, taking the target cache resource as SLC, the first cache mode as OCM mode, and the second cache mode as Cache mode as an example, the embodiment of the present application designs a software-configurable ocm_cmd register as the first configuration component to configure cache resource scheduling instructions. Optionally, the ocm_cmd register has only 1 bit, that is, a single-bit register, which is specifically used as the OCM setting master switch, wherein, optionally, if the value of the single bit in ocm_cmd is set to 1, it indicates that resources need to be scheduled for the SLC, which is specifically used to indicate the allocation of the OCM mode cache area in the SLC or the cancellation of the OCM mode cache area. At the same time, multiple groups of software-configurable ocm_cfg registers are also designed as the multiple groups of second configuration components to configure cache resource scheduling information.

[0075] Assuming that the SLC has an xMB address space and consists of y ways, each way occupies x / yMB, and x / y groups of ocm_cfg registers can be designed, each group of registers corresponding to one way. For example, assuming that the SLC has a 16MB address space and consists of 16 ways, each way occupies 1MB, and a total of 16 groups of software-configurable ocm_cfg registers can be designed. Each group of registers may include, but is not limited to, various cache resource scheduling information as shown in Table 1 below.

[0076] Table 1

[0077]

[0078] Among them, base represents the base address, for example, the base address of the OCM interval. way represents the way, valid represents the valid bit flag, and opcode represents the operation information or operation code. For more detailed information about each field, please refer to Table 1.

[0079] When the target cache resource needs to be scheduled, for example, when the cache area of ​​the first cache mode needs to be allocated in the target cache resource or the cache area of ​​the first cache mode needs to be revoked (such as allocating or revoking the OCM cache area), the way information that has been allocated to the first cache mode and the corresponding second configuration component can be first determined from the multi-way cache area. On this basis, the target way that can be used to allocate the cache area of ​​the first cache mode and the corresponding target group second configuration component can be determined from the way information that has not been allocated to the first cache mode and the corresponding second configuration component, or the target way that needs to revoke the cache area of ​​the first cache mode and the corresponding target group second configuration component can be determined from the way information that has been allocated to the first cache mode and the corresponding second configuration component, and the target cache resource scheduling information for realizing the required resource scheduling of the target cache resource (such as allocating or revoking the cache area of ​​the first cache mode such as OCM) is written to the determined target group second configuration component. For example, see Figure 2 The register configuration diagram shown in the figure can specifically write target cache resource scheduling information for allocating OCM cache areas or for canceling OCM cache areas into the determined target group ocm_cfg register. The configured target cache resource scheduling information may include part or all of the base, way, valid and opcode information shown in Table 1.

[0080] In addition to writing the target cache resource scheduling information to the second configuration component of the target group, instruction data for indicating cache resource scheduling may also be written to the first configuration component, for example, Figure 2 The ocm_cmd register shown in FIG. 1 is written with instruction data "1" for instructing resource scheduling.

[0081] On this basis, in step 101, in response to detecting that the first configuration component is configured with instruction data for indicating cache resource scheduling, the target group second configuration component configured with target cache resource scheduling information can be determined from multiple groups of second configuration components, and the target cache resource scheduling information configured in the target group second configuration component can be obtained. For example, in response to detecting that the ocm_cmd register is configured with instruction data "1" for indicating cache resource scheduling, the target group ocm_cfg register configured with target cache resource scheduling information can be determined from multiple groups of ocm_cfg registers, and the target cache resource scheduling information can be read therefrom.

[0082] The target cache resource scheduling information includes: cache mode information and operation information.

[0083] The cache mode information is used to indicate that the first cache area in the target cache resource is set to the first cache mode or that the corresponding second cache area is deactivated from the first cache mode; for example, it is used to indicate that the first cache area in the SLC is set to the OCM mode or that the corresponding second cache area in the SLC is deactivated from the OCM mode. The cache mode information can be specifically a valid bit identifier valid in Table 1, and when its value is 1, it indicates that the indicated first cache area is allocated to the OCM mode, and when it is 0, it indicates that the indicated second cache area is deactivated from the OCM mode.

[0084] The operation information is used to indicate the data transmission operation mode between the target cache resource and the storage component, for example, to indicate the data transmission operation mode between the SLC and the DDR when performing resource scheduling on the SLC, etc. The operation information can specifically be the operation code opcode shown in Table 1.

[0085] Among them, when the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, the target cache resource scheduling information also includes configuration address information for indicating the address of the first cache area, for example, indicating the base address of the first cache area, which may specifically be the base shown in Table 1.

[0086] Specifically, if the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, for example, indicates that the first cache area in the SLC is set to the OCM mode, exemplarily, the target cache resource scheduling information may specifically include at least part of the following information:

[0087] 11) a first valid bit flag for indicating that the corresponding first cache area is set to the first cache mode such as the OCM mode, such as valid in Table 1, and valid is assigned a value of 1 to indicate that the corresponding first cache area is set to the first cache mode such as the OCM mode;

[0088] 12) A first base address of the first cache area, such as base in Table 1.

[0089] 13) A first way identifier for indicating the way corresponding to the first cache area, such as way in Table 1.

[0090] 14) A first operation code for indicating an operation to be performed on the first cache area when the first cache area is set to the first cache mode, such as the opcode in Table 1, and opcode=01 or opcode=10 may be set.

[0091] The meanings of different opcode values ​​are shown in Table 1, where, when allocating the OCM mode cache area for the SLC, if it is necessary to first map the data in the corresponding address space of the DDR to the first cache area to be allocated to the OCM mode, the opcode is set to 10, otherwise the opcode is set to 01.

[0092] The target address space of the first cache area may be determined according to the first base address and the size of the cache area corresponding to each way (eg, each way corresponds to a 1MB cache address space).

[0093] If the cache mode information indicates that the second cache area in the target cache resource is deactivated from the first cache mode, for example, indicates that the second cache area in the SLC is deactivated from the OCM mode, exemplarily, the target cache resource scheduling information may specifically include at least part of the following information:

[0094] 21) A second valid bit flag for indicating that the first mode is to be canceled for the corresponding second cache area; such as valid in Table 1, and valid is assigned a value of 0 to indicate that the first cache mode such as the OCM mode is to be canceled for the corresponding second cache area.

[0095] 22) A second operation code for indicating an operation to be performed on the second cache area when the first mode is canceled from the second cache area, such as the opcode in Table 1, and opcode=01 or opcode=11 may be set.

[0096] The meanings of different opcode values ​​are shown in Table 1, where when canceling the first cache mode such as the OCM mode of the second cache area, if the data in the second cache area needs to be written back to the DDR, the opcode is set to 11, otherwise the opcode is set to 01.

[0097] The second cache area is specifically a cache area corresponding to the way occupied by the second configuration component of the target group of the first cache mode such as the current OCM to be revoked.

[0098] 23) The second base address of the second cache area corresponds to the base in Table 1.

[0099] 24) A second way identifier used to indicate the way corresponding to the second cache area, corresponding to the way in Table 1.

[0100] Among them, the target group second configuration component can be determined from the multiple groups of second configuration components based on the cache mode information and the operation information, for example, the corresponding group of second configuration components configured with the first valid bit identifier and the first operation code (that is, valid=1, and opcode=01 or opcode=10) in the multiple groups of second configuration components is determined as the target group second configuration component, or the corresponding group of second configuration components configured with the second valid bit identifier and the second operation code (that is, valid=0, and opcode=01 or opcode=11) in the multiple groups of second configuration components is determined as the target group second configuration component.

[0101] The target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction, for example, pre-written into the target group second configuration component.

[0102] Step 102: Execute cache resource scheduling processing that matches the target cache resource scheduling information on the target cache resource.

[0103] The step 102 may be further implemented as including at least one of the following 31)-32):

[0104] 31) In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a target address space of the first cache area is determined according to the configuration address information; according to the target address space, data in the first cache area is written into a corresponding storage area of ​​a storage component; and a corresponding first operation is performed on the first cache area according to the operation information.

[0105] Optionally, the configuration address information may be a first base address written into the second configuration component of the target group. When determining the target address space of the first cache area based on the configuration address information, the target address space of the first cache area may be determined specifically based on the first base address and the size of the cache area corresponding to each way (for example, each way corresponds to 1MB of cache address space).

[0106] Taking the storage component as DDR and the target cache resource as SLC in Soc as an example, when writing the data in the first cache area to the corresponding storage area of ​​the storage component according to the target address space, the existing flush cache mechanism of SLC can be used to write the data corresponding to the way indicated by the way in the second configuration component of the target group, that is, the data in the first cache area, back to DDR one by one. Among them, for the cacheline in the first cache area that has been written back to DDR, its tag is set to an invalid state. For the cacheline that has not been written back to DDR, if other requests hit its access, it will not hinder the normal operation of the request.

[0107] When the corresponding first operation is performed on the first cache area according to the operation information, the corresponding first operation may be performed on the first cache area according to the first operation code.

[0108] For example, if the first operation code opcode=01, set it to 00 to reset the first operation code, and then jump directly to the next step; if the first operation code opcode=10, first set the first operation code to 00 to reset it, and then load the data in the DDR corresponding to the base~base+size(way) cache address space into the base~base+size(way) cache address space.

[0109] Among them, base represents the first base address, size(way) represents the size of the cache area corresponding to each way, and base~base+size(way) correspondingly represents the target address space of the first cache area.

[0110] Optionally, the embodiment of the present application is pre-designed with a DMA (Direct Memory Access) engine, see Figure 3 The working mechanism of the DMA engine shown in the figure can load the DDR data of the specified address into the cache area corresponding to the specified way in the SLC by issuing a DMA Read request. Therefore, when the data in the DDR corresponding to the base~base+size(way) cache address space is loaded into the base~base+size(way) cache address space, the DMA engine can be activated and the DMA engine can be used to load the data in the DDR into the cache address space corresponding to the SLC.

[0111] In addition, in response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode such as the OCM mode, in addition to performing the above-mentioned processing, some other auxiliary processing may also be included, for example, resetting the command data in the first configuration component (ocm_cmd register), resetting the first operation code, and issuing an interrupt to the software to notify the software that the mode scheduling is successful (i.e., completing the setting of the first cache area to the first cache mode such as OCM), etc.

[0112] 32) In response to the target cache resource scheduling information indicating that the first cache mode will be canceled for the corresponding second cache area, a corresponding second operation is performed on the second cache area according to the operation information; and the configuration address information of the second cache area stored in the second configuration component of the target group and the second way identifier used to indicate the way corresponding to the second cache area are cleared.

[0113] When performing the corresponding second operation on the second cache area according to the operation information, the corresponding second operation can be performed on the first cache area according to the second operation code (such as opcode). For example, in the case of valid=0 and opcode=01, the opcode is set to 00 to reset the opcode, and then jump directly to the next step; in the case of valid=0 and opcode=11, the opcode is set to 00 to reset the opcode, and then based on the cache refresh module, such as Figure 4 The flush cache module shown performs a cache refresh operation, that is, writes the data in the second cache area back to its corresponding address interval in the DDR.

[0114] In response to the target cache resource scheduling information indicating that the first cache mode, such as the OCM mode, will be canceled in the corresponding second cache area, and after completing the processing of step 32), some auxiliary processing can also be performed, such as issuing an interrupt to the software to notify it that the mode scheduling is successful (that is, completing the cancellation of the first cache mode such as OCM in the second cache area), etc.

[0115] In actual applications, scheduling of target cache resources is not limited to allocating cache areas of the first cache mode and canceling cache areas of the first cache mode in the target cache resources, but may also include adjusting cache areas of the first cache mode, such as adjusting cache areas of the OCM mode.

[0116] Among them, adjusting the cache area of ​​the first cache mode, such as the OCM mode, mainly refers to adjusting the address space or the corresponding way of a cache area that has been allocated to the first cache mode, such as the OCM mode. The adjustment operation can be decomposed into first executing the operation of revoking the second cache area of ​​the first cache mode, and then executing the operation of allocating the first cache area of ​​the first cache mode. For details, please refer to the allocation and revocation process of the cache area of ​​the first cache mode above, which will not be described in detail here.

[0117] To summarize, the resource scheduling method provided in this embodiment, by responding to the detection of a cache resource scheduling instruction, determines the matching target cache resource scheduling information from multiple groups of cache resource scheduling information (the cache resource scheduling information at least includes the cache mode of the corresponding cache resource), and performs cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information. This can realize dynamic scheduling of different cache areas of the target cache resource according to the required cache mode, thereby improving the management flexibility of the target cache resource and adapting to the ever-changing usage requirements of the target cache resource.

[0118] In an optional embodiment, the resource scheduling method provided by the present application may further include the following processing:

[0119] 41) In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction flag is set for a way corresponding to the first cache area.

[0120] The usage restriction mark is used to restrict the reallocation and usage of the corresponding way in the first cache mode.

[0121] This embodiment sets the first cache area to the first cache mode in response to the target cache resource scheduling information indication, and sets a usage restriction mark for the road corresponding to the first cache area, so that when other requests need to allocate a new road in the future, the first cache area and its corresponding road cannot be used, so as to ensure the high priority of the first cache area in the first cache mode, such as ensuring the high priority of the first cache area in the OCM mode, until the first cache mode of the first cache area, such as the OCM mode, is revoked, the first cache area supports reallocation and use for other requests.

[0122] 42) In response to the target cache resource scheduling information indicating that the first cache mode is canceled for the corresponding second cache area, the usage restriction mark for the way corresponding to the second cache area is canceled.

[0123] Contrary to the situation in step 41), in this step 42), by responding to the target cache resource scheduling information indicating that the first cache mode will be revoked for the corresponding second cache area, the usage restriction mark for the road corresponding to the second cache area is revoked, which can be used to enable the second cache area with the revoked first cache mode such as OCM mode to be reallocated and used when there are other requests that need to allocate a new road.

[0124] In actual applications, for each way corresponding to a target cache resource such as SLC, it is possible to record whether the cache area corresponding to each way is scheduled as a first cache mode such as OCM and / or whether there is a corresponding usage restriction mark, and save the resulting record information to facilitate subsequent direct use of the record information as a basis for convenient and efficient cache scheduling processing such as OCM allocation, cancellation, and adjustment of target cache resources such as SLC.

[0125] This embodiment sets a usage restriction mark for the cache area in the first cache mode such as the OCM mode or its corresponding way, thereby ensuring that the corresponding cache area in the target cache resource will not be reallocated and used by other resource requests during the period when the corresponding cache area in the target cache resource is scheduled as the first cache mode such as OCM, thereby ensuring the high usage authority of the target cache resource by the first cache mode such as OCM; at the same time, by recording whether the cache area corresponding to each way is scheduled as the first cache mode such as OCM and / or whether there is a corresponding usage restriction mark, it is convenient to directly use the formed record information as a basis for the subsequent required OCM allocation, cancellation, adjustment and other cache scheduling processing of the target cache resources such as SLC.

[0126] An application example of the resource scheduling method disclosed in the embodiment of the present application is provided below.

[0127] In this example, the target cache resource is the SLC in the SoC, the storage component is DDR, the first cache mode is the OCM mode, and the second cache mode is the Cache mode. The OCM mode has higher permissions to use the SLC than the Cache mode. In addition, this example designs an ocm_cmd register, which has only 1 bit and is used as the main switch for OCM settings. At the same time, a DMA engine is designed, which can load the DDR data of the specified address into the specified way / cache area in the SLC by issuing a DMA Read request.

[0128] In addition, this example assumes that the SLC has a 16MB address space, consisting of 16 ways, each of which occupies 1MB. At the same time, 16 groups of software-configurable ocm_cfg registers are designed: ocm_cfg_0~15. The information included in each group of registers is shown in Table 1 above.

[0129] On this basis, the dynamic scheduling of the SLC OCM mode cache area allocation, cancellation or adjustment can be realized through the collaboration between software and hardware. Among them, for the need to allocate or cancel the OCM cache mode, the software is responsible for configuring instructions and related scheduling information, and the hardware is responsible for responding to the software configuration, so as to realize the required OCM allocation, cancellation or adjustment and other resource scheduling through the collaboration of software and hardware.

[0130] The following first describes the software and hardware process of allocating an OCM address range on the SLC, and the software and hardware process is specifically as follows.

[0131] 1. Software Process:

[0132] a. The software first queries the ocm_cfg_0~15 registers to determine the address and path information of the SLC that has been allocated to OCM mode;

[0133] b. The software selects a group of registers that are not allocated to OCM mode from the ocm_cfg_0~15 registers, writes the base address to be allocated to OCM mode into the base in the selected ocm_cfg, and writes the way to be allocated to OCM mode into the way in the selected ocm_cfg (note that the way that has been allocated to OCM mode cannot be used), and writes valid in the selected ocm_cfg to 1. If it is necessary to map the DDR corresponding space data to the cache address space to be allocated to OCM mode in advance, write 10 to the opcode, otherwise write 01 to the opcode;

[0134] c. The software writes 1 to ocm_cmd;

[0135] d. Wait for the interrupt signal from the subsequent hardware indicating that the OCM allocation is successful. After receiving the interrupt signal from the hardware, the cache area scheduled to the OCM mode can receive and respond normally to the OCM access request.

[0136] The OCM access request refers to an access request for instructing a read / write operation to an OCM cache area.

[0137] 2. Hardware Process:

[0138] a. When ocm_cmd is detected to be 1, it is first set to 0 to achieve reset, and 16 groups of ocm_cfg registers are checked at the same time. For registers with valid=1 and (opcode=01 or opcode=10), the existing flush cache mechanism of SLC is first used to write the data in the cache area corresponding to the way specified in way back to the corresponding storage area of ​​DDR one by one, and for the cacheline in the cache area that has been written back to DDR, the tag information used to indicate that its status is invalid is set. For the cacheline in the cache area that has not been written back to DDR, if other requests hit their access, it will not hinder the normal operation of the request;

[0139] b. Combined with reference Figure 5 The working mechanism of the replacement strategy module shown in the figure, the replacement strategy module (replacement) inside the SLC reads the data in the way. When there are other requests that need to allocate a new way, the way specified in the way cannot be used;

[0140] c. After the flush cache mechanism is executed on the way specified in way, check the opcode. If its value is 10, set it to 00 to reset it, then activate the DMA engine, and load the data in the DDR corresponding to the base~base+size(way) cache area into the way specified by way. If its value is 01, set it to 00 to reset it, and then jump directly to the next step.

[0141] d. Set a restriction mark for the use of the way;

[0142] e. Send an interrupt to the software to notify the software that the OCM allocation is successful.

[0143] Next, the software and hardware process of deleting an OCM address range on the SLC is described. The software and hardware process is as follows.

[0144] 1. Software Process:

[0145] a. The software queries the ocm_cfg_0~15 registers to first determine the address of the cache area allocated to OCM mode and the corresponding path information;

[0146] b. The software selects the register corresponding to the cache area where the OCM mode needs to be canceled from the ocm_cfg_0~15 registers, and writes 0 to the valid bit. If the data in the cache area where the OCM mode needs to be canceled needs to be written back to DDR, write 11 to the opcode in the selected register, otherwise write 01;

[0147] c. The software writes 1 to ocm_cmd;

[0148] d. Wait for the interrupt signal from the subsequent hardware indicating that the OCM interval has been successfully cancelled. After receiving the interrupt signal from the hardware, it can be confirmed that the OCM interval has been cancelled.

[0149] 2. Hardware Process:

[0150] a. When ocm_cmd is detected to be 1, first set it to 0 to achieve reset, and check 16 groups of ocm_cfg registers at the same time. For registers with valid=0 and opcode=01, set opcode to 00 to achieve reset, and then jump directly to the next step; for registers with valid=0 and opcode==11, set opcode to 00 to achieve reset, and then execute the flush cache operation, that is, write the data in the cache area corresponding to the way in the way back to the DDR address interval corresponding to the base in the DDR.

[0151] b. Notify the replacement strategy module inside the SLC to cancel the usage restriction mark for the road corresponding to way;

[0152] c. Clear base and way to 0;

[0153] d. Send an interrupt to the software to notify the software that the OCM revocation is successful.

[0154] Adjusting the cache area of ​​the OCM mode mainly refers to adjusting the base or way of a cache area that has been allocated the OCM mode. The corresponding software and hardware processes can be decomposed into a process of first executing the above-mentioned OCM cancellation operation, and then re-executing the above-mentioned OCM allocation operation process.

[0155] This example uses the resource scheduling method provided in the embodiment of the present application, and utilizes the collaborative work of software and hardware to dynamically schedule OCM at runtime, such as dynamically allocating, revoking or adjusting OCM, etc., thereby realizing dynamic division and management of different cache modes of SLC, thereby improving the management flexibility of SLC and adapting to the ever-changing usage requirements of SLC.

[0156] In addition, this example dynamically schedules the SLC in OCM mode during runtime, which can give the software the ability to flexibly adapt to different application scenarios (such as video playback, photo taking, smart traffic management, etc.), helping to improve system energy efficiency; and the dynamic cache resource scheduling of the SLC does not affect the normal working performance of the system. At the same time, the automatic mapping mechanism between the SLC on the SoC chip and off-chip storage such as DDR provided by this application can also reduce software intervention, thereby being able to further adapt to the different usage requirements of SLC for different devices.

[0157] The present application also provides a resource access method. Figure 6As shown in the method flow chart, the resource access method provided in the embodiment of the present application may include the following steps 601 to 604, and these steps are described in detail below.

[0158] Step 601: Obtain an access request to a target cache resource.

[0159] Exemplarily, an access request to an SLC in the SoC may be obtained, and specifically may be an access request for requesting a data read / write operation to a cache area in the SLC.

[0160] The access request includes a first access address, which is actually the address of the corresponding storage area of ​​a storage component outside the SoC, such as a DDR. That is to say, for the resource request subject, what is visible is the storage area of ​​a storage component outside the SoC, such as a DDR, and the first access address carried in the initiated access request to the resource corresponds to the address of the storage area in the storage component such as the DDR.

[0161] Since the storage area in the storage component such as DDR corresponds to the corresponding cache area on the SLC in the chip such as SoC, or the storage area in the storage component can correspond to the corresponding cache area on the SLC in the chip such as SoC through a temporary allocation operation, the system will map the first access address in the access request to the address of the corresponding cache area of ​​the SLC in the chip such as SoC.

[0162] Step 602: Match the first access address included in the access request with the address range of the target cache resource to obtain a matching result.

[0163] Optionally, the first access address included in the access request may be matched with a target address range in the address range of the target cache resource to obtain a matching result.

[0164] The target address range is an address range corresponding to a cache area in the target cache resource that is in a first cache mode.

[0165] In an optional implementation, the first access address included in the access request can be directly matched with the target address range of the way / cache area corresponding to each corresponding second configuration component configured in the first cache mode in each group of second configuration components. However, it is not limited to this. In other optional implementations, the target address space corresponding to the cache area / way of each first cache mode can also be summarized and recorded in advance to form an address record table of the target address range, and the first access address included in the access request can be matched with each target address range in the address record table.

[0166] Take the target cache resource as SLC and the first cache mode as OCM as an example. Figure 7 The working mechanism of the OCM request judgment module shown can specifically utilize a pre-designed OCM request judgment module to match the first access address included in the access request with the address range of valid=1 in ocm_cfg_0~15; alternatively, the first access address included in the access request can be matched with the target address range corresponding to each OCM mode cache area that is pre-aggregated and recorded.

[0167] Step 603: determine the request type of the access request to the target cache resource based on the matching result; the request type is used to indicate the cache mode of the cache area requested to access the target cache resource, and the cache area within the target cache resource can be scheduled to be in different cache modes.

[0168] If the first access address in the access request matches the cache area address space of a certain cache area in each cache area of ​​the first cache mode, then the access request is characterized as a request type for indicating access to the cache area of ​​the first cache mode; otherwise, the access request is characterized as a request type for indicating access to the cache area of ​​the second cache mode.

[0169] For example, if the first access address included in the access request matches the spatial address range corresponding to the path used by a group of registers in each group of registers with valid=1 in ocm_cfg_0~15, then it is characterized that the access request is a request type for indicating access to the OCM mode cache area in the SLC; otherwise, it is characterized that the access request is a request type for indicating access to a non-OCM mode cache area in the SLC, such as a Cache mode cache area.

[0170] Optionally, after determining the request type of the access request for the target cache resource, a target adding operation may be performed on the access request based on the determined request type.

[0171] The target adding operation is used to add a corresponding request type to the access request.

[0172] For example, if it is determined that the access request is a request type indicating access to an OCM mode cache area within an SLC, OCM tag information may be added to the access request to characterize the access request as an OCM request. In addition, matched way information may also be added to the access request.

[0173] On the contrary, if it is determined that the access request is a request type for indicating access to a cache area in a cache mode in an SLC, no tag may be added to the access request, or cache tag information may be added to indicate that the access request is a cache request.

[0174] Step 604: According to the request type, perform an access operation matching the access request on a corresponding cache area in the target cache resource.

[0175] Specifically, if the access request is added with a request type for indicating access to a cache area of ​​a first cache mode, the first access address is mapped to a second access address of the target cache resource based on a first mapping method, and the cache area of ​​the first mode within the target cache resource is accessed based on the second access address.

[0176] For example, if OCM tag information is added to the access request, the first access address is mapped to a second access address for an OCM mode cache area in the SLC based on a first mapping method, and the corresponding OCM mode cache area in the SLC is accessed based on the second access address.

[0177] On the contrary, if the access request is not added with a request type for indicating access to the cache area of ​​the first cache mode or is added with a request type for indicating access to the cache area of ​​the second cache mode, the first access address is mapped to a third access address to the target cache resource based on the second mapping method, and the cache area of ​​the second cache mode within the target cache resource is accessed based on the third access address.

[0178] For example, if OCM tag information is not added to the access request or Cache tag information is added, the first access address is mapped to a third access address for the Cache mode cache area in the SLC based on the second mapping method, and the corresponding Cache mode cache area in the SLC is accessed based on the third access address.

[0179] The first mapping method is different from the second mapping method. For example, the Cache mode adopts a hash mapping method (the second mapping method), and the OCM mode adopts a non-hash mapping method (the first mapping method), etc. The specific requirements may depend on the actual requirements of different cache modes for address mapping methods.

[0180] In implementation, optionally, for the OCM request after adding the way information and the OCM mark information, it can be sent to the command queue Command Queue of the SLC controller in the SLC to wait for the SLC controller to process it. After receiving the access request based on the Command Queue, the SLC controller first identifies it as an OCM request based on the added OCM mark information, and then converts the first access address into the second access address of the OCM mode cache area according to the first mapping method corresponding to the OCM mode and the way information, and performs normal read / write operations on the corresponding OCM mode cache area based on the second access address.

[0181] On the contrary, if the access request is not an OCM request, it will be sent to the Command Queue of the SLC controller in normal Cache mode. When the SLC controller receives an access request in normal Cache mode through the Command Queue, it first identifies it as a Cache request based on its characteristics of not adding OCM tag information or adding Cache tag information, and then performs address mapping according to the second mapping method corresponding to the Cache mode, maps the first access address in the access request to the third access address, and checks whether the third access address hits in the SLC. If it hits, the required read / write operation can be performed directly. If a miss occurs, a new way needs to be allocated for it. At this time, the replacement strategy module can be used to select a non-OCM way for allocation based on the recorded way mark, that is, the selected non-OCM way is specifically used to allocate a non-OCM cache area as the Cache mode cache area to be accessed by the access request.

[0182] The resource access method of the present embodiment determines the request type of the access request for the target cache resource by matching the first access address contained in the access request with the address range of the target cache resource, and then performs a matching access operation on the corresponding cache area in the target cache resource according to the determined request type; and in the case where the access request fails to hit the target cache resource, selects a non-OCM way (a cache area not in the first cache mode) to allocate the requested cache area according to the recorded way mark, thereby realizing a resource access scheme that matches the resource scheduling method for dynamic resource scheduling provided in the embodiment of the present application, thereby improving the flexibility of management and access to the target cache resources and being able to adapt to the ever-changing usage requirements of the target cache resources.

[0183] The present application also provides an electronic device, the structure of which is as follows: Figure 8 As shown, including at least:

[0184] A determination module 10, configured to determine, in response to detecting a cache resource scheduling instruction, matching target cache resource scheduling information from a plurality of sets of cache resource scheduling information, wherein the cache resource scheduling information in the plurality of sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource;

[0185] The resource scheduling processing module 20 is used to perform cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource.

[0186] In an optional implementation, the electronic device further comprises a configuration module, the configuration module comprising a first configuration component for configuring command data and a plurality of groups of second configuration components for configuring cache resource configuration information;

[0187] The determination module is specifically used to: in response to detecting that the first configuration component is configured with instruction data for indicating cache resource scheduling, determine the target group second configuration component configured with target cache resource scheduling information from the multiple groups of second configuration components, and obtain the target cache resource scheduling information in the target group second configuration component.

[0188] In an optional implementation manner, the target cache resource scheduling information includes: cache mode information and operation information;

[0189] The cache mode information is used to indicate whether to set the first cache area in the target cache resource to the first cache mode or to cancel the first cache mode for the corresponding second cache area; the operation information is used to indicate the transmission operation mode between the data in the target cache resource and the storage component;

[0190] The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction.

[0191] In an optional implementation, when the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, the target cache resource scheduling information further includes configuration address information.

[0192] In an optional implementation manner, the resource scheduling processing module 20 is specifically configured to:

[0193] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a target address space of the first cache area is determined according to the configuration address information; data in the first cache area is written into a corresponding storage area of ​​a storage component according to the target address space; and a corresponding first operation is performed on the first cache area according to the operation information;

[0194] In response to the target cache resource scheduling information indicating that the first cache mode will be revoked for the corresponding second cache area, a corresponding second operation is performed on the second cache area according to the operation information; the configuration address information of the second cache area stored in the second configuration component of the target group and the second way identifier used to indicate the way corresponding to the second cache area are cleared.

[0195] In an optional implementation manner, the resource scheduling processing module 20 is further configured to:

[0196] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction mark for a path corresponding to the first cache area is set;

[0197] In response to the target cache resource scheduling information indicating that the first cache mode is canceled for the corresponding second cache area, the use restriction mark for the path corresponding to the second cache area is canceled;

[0198] The use restriction mark is used to restrict the reallocation and use of the corresponding way in the first cache mode; the target cache resource is divided into multiple ways, each way corresponding to a cache area of ​​a corresponding size.

[0199] In an optional implementation, the electronic device further includes a management module for performing configuration management on the configuration module;

[0200] The management module is specifically used for:

[0201] Before the determination module responds to the cache resource scheduling instruction, a target group second configuration component that can be used to allocate cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the first configuration information for allocating cache resources in the first cache mode is written to the determined target group second configuration component; and / or, a target group second configuration component that can be used to revoke cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the second configuration information for revoking cache resources in the first cache mode is written to the determined target group second configuration component;

[0202] Writing instruction data for instructing cache resource scheduling into the first configuration component;

[0203] The target cache resource scheduling information includes the first configuration information and / or the second configuration information.

[0204] In an optional implementation, the electronic device further includes a data transmission module, configured to perform at least one of the following:

[0205] In the case where the cache resource scheduling process is used to allocate a cache area of ​​the first cache mode, writing the data in the cache area of ​​the target cache resource that needs to be scheduled as the first cache mode back to the corresponding first storage area in the storage component; optionally, the cache flush module described above can be used to implement the process;

[0206] In the case where the cache resource scheduling process is used to allocate cache resources of the first cache mode, the storage data of the second storage area in the storage component is loaded into the cache area in the target cache resource that needs to be scheduled as the first cache mode; optionally, the DMA engine described above can be used to implement this process.

[0207] In an optional implementation, the electronic device further includes a replacement strategy module, configured to:

[0208] In a case where the obtained access request to the target cache resource is used to indicate access to the target cache area of ​​the second cache mode and the target cache area is missing from the target cache resource, determining a target way that is not in the first cache mode from the target cache resource according to usage restriction tags corresponding to different ways in the target cache resource, and allocating the cache area corresponding to the target way as the target cache area of ​​the second cache mode;

[0209] Among them, the cache area within the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple ways, each way corresponds to a cache area of ​​corresponding size; the usage restriction mark is used to limit the reallocation and use of the corresponding way in the first cache mode.

[0210] An embodiment of the present application also provides a storage medium, which carries one or more computer instruction sets. When the one or more computer instruction sets are executed by an electronic device, the electronic device can implement a resource scheduling method and / or a resource access method as provided in any of the method embodiments above.

[0211] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0212] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0213] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0214] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0215] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A resource scheduling method, comprising: In response to detecting the cache resource scheduling instruction, determining matching target cache resource scheduling information from multiple sets of cache resource scheduling information, wherein the cache resource scheduling information in the multiple sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource; For the target cache resource, a cache resource scheduling process matching the target cache resource scheduling information is executed.

2. The resource scheduling method according to claim 1, wherein in response to detecting the cache resource scheduling instruction, determining the matching target cache resource scheduling information from multiple sets of cache resource scheduling information comprises: In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

3. The resource scheduling method according to claim 2, wherein the target cache resource scheduling information comprises: Cache mode information and operation information; The cache mode information is used to indicate whether to set the first cache area in the target cache resource to the first cache mode or to cancel the first cache mode of the corresponding second cache area; the operation information is used to indicate the transmission operation mode between the data in the target cache resource and the storage component; The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction. 4 . The resource scheduling method according to claim 3 , wherein when the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, the target cache resource scheduling information further includes configuration address information.

5. The resource scheduling method according to claim 4, wherein the step of executing cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource comprises: In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a target address space of the first cache area is determined according to the configuration address information; According to the target address space, write the data in the first cache area into a corresponding storage area of ​​the storage component; and perform a corresponding first operation on the first cache area according to the operation information; In response to the target cache resource scheduling information indicating that the first cache mode is to be cancelled for the corresponding second cache area, a corresponding second operation is performed on the second cache area according to the operation information; The configuration address information of the second cache area and the second way identifier for indicating the way corresponding to the second cache area stored in the second configuration component of the target group are cleared.

6. The resource scheduling method according to claim 5, further comprising: In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction mark for a path corresponding to the first cache area is set; In response to the target cache resource scheduling information indicating that the first cache mode is canceled for the corresponding second cache area, the use restriction mark for the path corresponding to the second cache area is canceled; The use restriction mark is used to restrict the reallocation and use of the corresponding way in the first cache mode; the target cache resource is divided into multiple ways, each way corresponding to a cache area of ​​a corresponding size.

7. A resource access method, comprising: Obtain access request to target cache resource; Matching the first access address included in the access request with the address range of the target cache resource to obtain a matching result; Determine the request type of the access request to the target cache resource according to the matching result; the request type is used to indicate the cache mode of the cache area requested to access the target cache resource, and the cache area in the target cache resource can be scheduled to be in different cache modes; According to the request type, an access operation matching the access request is performed on a corresponding cache area in the target cache resource.

8. The resource access method according to claim 7, before performing an access operation matching the access request on a corresponding cache area in the target cache resource according to the request type, further comprising: Based on the determined request type, performing a target adding operation on the access request; The target adding operation is used to add a corresponding request type to the access request; The performing, according to the request type, an access operation matching the access request on a corresponding cache area in the target cache resource comprises: If a request type indicating access to a cache area of ​​a first cache mode is added to the access request, the first access address is mapped to a second access address of the target cache resource based on a first mapping method, and the cache area of ​​the first mode in the target cache resource is accessed based on the second access address; If the access request is not added with a request type for indicating access to the cache area of ​​the first cache mode or is added with a request type for indicating access to the cache area of ​​the second cache mode, mapping the first access address to a third access address of the target cache resource based on a second mapping manner, and accessing the cache area of ​​the second cache mode in the target cache resource based on the third access address; The permission for using the target cache resource in the first cache mode is higher than the permission for using the target cache resource in the second cache mode.

9. The resource access method according to claim 7, wherein matching the first access address included in the access request with the address range of the target cache resource comprises: Matching the first access address included in the access request with the target address range in the address range of the target cache resource to obtain a matching result; The target address range is an address range corresponding to a cache area in the target cache resource that is in a first cache mode.

10. An electronic device comprising: A determination module, configured to determine, in response to detecting a cache resource scheduling instruction, matching target cache resource scheduling information from a plurality of sets of cache resource scheduling information, wherein the cache resource scheduling information in the plurality of sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource; The resource scheduling processing module is used to perform cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource.

11. The electronic device according to claim 10, further comprising a configuration module, the configuration module comprising a first configuration component for configuring command data and a plurality of groups of second configuration components for configuring cache resource configuration information; The determination module is specifically used for: In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from the multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

12. The electronic device according to claim 11, further comprising a management module for performing configuration management on the configuration module; The management module is used to: Before the determination module responds to the cache resource scheduling instruction, a target group second configuration component that can be used to allocate cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the first configuration information for allocating cache resources in the first cache mode is written to the determined target group second configuration component; and / or, a target group second configuration component that can be used to revoke cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the second configuration information for revoking cache resources in the first cache mode is written to the determined target group second configuration component; Writing instruction data for instructing cache resource scheduling into the first configuration component; in, The target cache resource scheduling information includes the first configuration information and / or the second configuration information.

13. The electronic device according to claim 10, further comprising a data transmission module, configured to perform at least one of the following: In the case where the cache resource scheduling process is used to allocate a cache area of ​​the first cache mode, writing the data in the cache area of ​​the target cache resource that needs to be scheduled as the first cache mode back to the corresponding first storage area in the storage component; In the case where the cache resource scheduling process is used to allocate cache resources of the first cache mode, the storage data of the second storage area in the storage component is loaded into the cache area in the target cache resource that needs to be scheduled as the first cache mode.

14. The electronic device according to claim 10, further comprising a replacement strategy module, configured to: In a case where the obtained access request to the target cache resource is used to indicate access to the target cache area of ​​the second cache mode and the target cache area is missing from the target cache resource, determining a target way that is not in the first cache mode from the target cache resource according to usage restriction tags corresponding to different ways in the target cache resource, and allocating the cache area corresponding to the target way as the target cache area of ​​the second cache mode; in, The cache area in the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple paths, each path corresponding to a cache area of ​​a corresponding size; The use restriction tag is used to restrict the reallocation and use of the corresponding way in the first cache mode.

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