Resource scheduling method, resource access method and electronic device

Abstract

The present application discloses a resource scheduling method, a resource access method, and an electronic device, belonging to the technical field of resource access and management. The disclosed method includes: in response to detecting a cache resource scheduling instruction, determining, from multiple groups of cache resource scheduling information, the matching target cache resource scheduling information, where the cache resource scheduling information in the multiple groups of cache resource scheduling information at least includes the cache mode of the corresponding cache resource; and performing a cache resource scheduling process matching the target cache resource scheduling information on the target cache resource.

Description

Technical Field

[0001] This application belongs to the technical field of resource access and management, and particularly relates to a resource scheduling method, a resource access method, and an electronic device. Background Art

[0002] System Level Cache (SLC) is a storage device integrated inside a System on Chip (SoC) chip, which is used to provide cache services for multiple master devices of the SoC. By retaining the data that the master devices need to access frequently inside the chip, the access to Double Data Rate SDRAM (DDR SDRAM) is reduced, thereby achieving the purpose of reducing latency and saving power consumption.

[0003] SLC generally supports two working modes, namely the Cache mode and the On Chip Memory (OCM) mode. In the Cache mode, the data in the SLC may be replaced, and the data access of the SoC master device is likely to cause latency jitter; in the OCM mode, the SLC works as a normal memory without a replacement algorithm, so it can ensure that the data is always stored inside the chip, which helps to provide a definite access latency for the SoC master device. The existing SLC designs generally support the coexistence of the Cache mode and the OCM mode, that is, by dividing the SLC capacity, a part of the SLC cache area works in the Cache mode, and another part of the SLC cache area works in the OCM mode. However, this division is static, that is, once the division is completed during the power-on initialization phase, it cannot be dynamically adjusted. However, the static division mechanism of target cache resources such as SLC lacks flexibility. With the increasing diversity of chip usage scenarios such as SoC, the static division mechanism gradually cannot meet the increasingly changing usage requirements of target cache resources. Summary of the Invention

[0004] Therefore, the present application discloses the following technical solutions:

[0005] A resource scheduling method, comprising:

[0006] In response to detecting a cache resource scheduling instruction, determine the matching target cache resource scheduling information from multiple groups of cache resource scheduling information, where the cache resource scheduling information in the multiple groups of cache resource scheduling information at least includes the cache mode of the corresponding cache resource;

[0007] Perform cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information.

[0008] Optionally, determining the matching target cache resource scheduling information from multiple groups of cache resource scheduling information in response to detecting a cache resource scheduling instruction includes:

[0009] In response to detecting that the first configuration component is configured with instruction data for indicating cache resource scheduling, determining a target group of second configuration components configured with the target cache resource scheduling information from multiple groups of second configuration components, and obtaining the target cache resource scheduling information in the target group of second configuration components.

[0010] Optionally, the target cache resource scheduling information includes: cache mode information and operation information;

[0011] The cache mode information is used to indicate setting the first cache area in the target cache resource to the first cache mode or canceling the first cache mode for the corresponding second cache area; the operation information is used to indicate the data transfer operation mode between the data in the target cache resource and the storage component.

[0012] The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction.

[0013] Optionally, when the cache mode information indicates setting the first cache area in the target cache resource to the first cache mode, the target cache resource scheduling information further includes configuration address information.

[0014] Optionally, performing cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource includes:

[0015] In response to the target cache resource scheduling information indicating setting the first cache area to the first cache mode, determining the target address space of the first cache area according to the configuration address information; writing the data in the first cache area into the corresponding storage area of the storage component according to the target address space; performing a corresponding first operation on the first cache area according to the operation information.

[0016] In response to the target cache resource scheduling information indicating canceling the first cache mode for the corresponding second cache area, performing a corresponding second operation on the second cache area according to the operation information; clearing the configuration address information of the second cache area stored in the target group of second configuration components and the second path identifier for indicating the path corresponding to the second cache area.

[0017] Optionally, the resource scheduling method further includes:

[0018] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, set a usage restriction flag for the path corresponding to the first cache area;

[0019] In response to the target cache resource scheduling information indicating that the corresponding second cache area cancels the first cache mode, cancel the usage restriction flag for the path corresponding to the second cache area;

[0020] Wherein, the usage restriction flag is used to restrict the reallocation and use of the corresponding path in the first cache mode; the target cache resource is divided into multiple paths, and each path corresponds to a cache area of a corresponding size.

[0021] A resource access method includes:

[0022] Obtain an access request for a target cache resource;

[0023] Match the first access address included in the access request with the address range of the target cache resource to obtain a matching result;

[0024] Determine the request type of the access request for the target cache resource according to the matching result; the request type is used to indicate the cache mode of the cache area requested to be accessed in the target cache resource, and the cache areas in the target cache resource can be scheduled to be in different cache modes;

[0025] Execute an access operation matching the access request on the corresponding cache area in the target cache resource according to the request type.

[0026] Optionally, before executing an access operation matching the access request on the corresponding cache area in the target cache resource according to the request type, it further includes:

[0027] Based on the determined request type, perform a target addition operation on the access request; the target addition operation is used to add a corresponding request type to the access request;

[0028] The executing an access operation matching the access request on the corresponding cache area in the target cache resource according to the request type includes:

[0029] If the access request is added with a request type for indicating the cache area of the first cache mode, map the first access address to the second access address of the target cache resource based on the first mapping method, and access the cache area of the first mode in the target cache resource based on the second access address;

[0030] If the request type for indicating the cache area for accessing the first cache mode is not added to the access request or the request type for indicating the cache area for accessing the second cache mode is added, map the first access address to the third access address of the target cache resource based on the second mapping method, and access the cache area of the second cache mode in the target cache resource based on the third access address;

[0031] Among them, the usage permission of the first cache mode for the target cache resource is higher than that of the second cache mode for the target cache resource.

[0032] Optionally, the matching of the first access address included in the access request with the address range of the target cache resource includes:

[0033] Match the first access address included in the access request with the target address range in the address range of the target cache resource to obtain a matching result;

[0034] Among them, the target address range is the address range corresponding to the cache area in the first cache mode in the target cache resource.

[0035] An electronic device includes:

[0036] A determination module, configured to, in response to detecting a cache resource scheduling instruction, determine matching target cache resource scheduling information from multiple groups of cache resource scheduling information, where the cache resource scheduling information in the multiple groups of cache resource scheduling information at least includes the cache mode of the corresponding cache resource;

[0037] A resource scheduling processing module, configured to perform cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information.

[0038] Optionally, the electronic device further includes a configuration module, and the configuration module includes a first configuration component for configuring command data and multiple groups of second configuration components for configuring cache resource configuration information;

[0039] The determination module is specifically configured to:

[0040] In response to detecting that the instruction data for indicating cache resource scheduling is configured in the first configuration component, determine the target group of second configuration components configured with the target cache resource scheduling information from the multiple groups of second configuration components, and obtain the target cache resource scheduling information in the target group of second configuration components.

[0041] Optionally, the electronic device further includes a management module for performing configuration management on the configuration module;

[0042] The management module is configured to:

[0043] Before the determining module responds to the cache resource scheduling instruction, determine, from the multiple groups of second configuration components, the target group of second configuration components that can be used to allocate cache resources in the first cache mode, and write the first configuration information for allocating cache resources in the first cache mode to the determined target group of second configuration components; and / or, determine, from the multiple groups of second configuration components, the target group of second configuration components that can be used to revoke the cache resources in the first cache mode, and write the second configuration information for revoking the cache resources in the first cache mode to the determined target group of second configuration components;

[0044] Write instruction data for indicating cache resource scheduling to the first configuration component;

[0045] Wherein, the target cache resource scheduling information includes the first configuration information and / or the second configuration information.

[0046] Optionally, the electronic device further includes a data transmission module, configured to perform at least one of the following:

[0047] When the cache resource scheduling process is for allocating a cache area in the first cache mode, write back the data in the cache area that needs to be scheduled to the first cache mode in the target cache resource to the corresponding first storage area in the storage component;

[0048] When the cache resource scheduling process is for allocating cache resources in the first cache mode, load the stored data in the second storage area of the storage component into the cache area that needs to be scheduled to the first cache mode in the target cache resource.

[0049] Optionally, the electronic device further includes a replacement policy module, configured to:

[0050] When the obtained access request for the target cache resource is used to indicate accessing the target cache area in the second cache mode and the target cache area is missing in the target cache resource, determine, according to the usage restriction marks corresponding to different ways in the target cache resource, the target way in the target cache resource that is not in the first cache mode, and allocate the cache area corresponding to the target way as the target cache area in the second cache mode;

[0051] Wherein, the cache areas in the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple ways, and each way corresponds to a cache area of a corresponding size; the usage restriction marks are used to restrict the reallocation and use of the corresponding ways in the first cache mode.

[0052] A storage medium carries one or more computer instruction sets. When the one or more computer instruction sets are executed by an electronic device, the electronic device can implement the resource scheduling method or resource access method provided in any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0054] Figure 1 is the flowchart of the resource scheduling method provided by the present application;

[0055] Figure 2 is the schematic diagram of register configuration provided by the present application;

[0056] Figure 3 is the schematic diagram of the working mechanism of the dma engine provided by the present application;

[0057] Figure 4 is the schematic diagram of the working mechanism of the flush cache module provided by the present application;

[0058] Figure 5 is the schematic diagram of the working mechanism of the replacement policy module provided by the present application;

[0059] Figure 6 is the flowchart of the resource access method provided by the present application;

[0060] Figure 7 is the schematic diagram of the working mechanism of the OCM request judgment module provided by the present application;

[0061] Figure 8 is the composition structure diagram of the electronic device provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0062] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0063] Embodiments of the present application provide a resource scheduling method, a resource access method, and an electronic device, which are used to dynamically schedule different cache regions of a target cache resource according to the required cache mode, so as to improve the management flexibility of the target cache resource and adapt to the increasingly changing usage requirements of the target cache resource.

[0064] The resource scheduling method or resource access method provided by the embodiments of the present application can be applied to electronic devices in many general or special computing device environments or configurations, such as: personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor devices, and so on.

[0065] See Figure 1 Referring to the schematic diagram of the method flow shown, the resource scheduling method provided by the embodiments of the present application may include the following steps 101 to 102, and these steps will be described in detail below.

[0066] Step 101, in response to detecting a cache resource scheduling instruction, determine the matching target cache resource scheduling information from multiple groups of cache resource scheduling information; the cache resource scheduling information in the multiple groups of cache resource scheduling information at least includes the cache mode of the corresponding cache resource.

[0067] The cache resource scheduling instruction is a scheduling instruction for the target cache resource. The target cache resource may, but is not limited to, be a system-level cache SLC in a chip such as an SoC.

[0068] The cache regions in the target cache resource can be scheduled to be in different cache modes. The different cache modes include a first cache mode and a second cache mode. Among them, the first cache mode has a higher usage right to the target cache resource than the second cache mode.

[0069] Taking the target cache resource as the SLC as an example, the first cache mode can be the OCM mode, that is, the on-chip memory mode, and the second cache mode can be the Cache mode. Among them, the OCM mode has a higher usage right to the SLC than the Cache mode. In the Cache mode, the data in the SLC may be replaced, and the data access of the SoC master device is likely to cause latency jitter; in the OCM mode, the SLC works as a normal memory without a replacement algorithm, so it can ensure that the data is always stored in the chip, which helps to provide a definite access latency for the SoC master device.

[0070] The cache resource scheduling information at least includes the cache mode corresponding to the cache resource, for example, at least includes mode information for characterizing that the corresponding cache resource is in the first cache mode or the second cache mode, etc. In addition, it may also include, but is not limited to, the address information of the corresponding cache resource, the way information of the corresponding cache resource, and / or the operation information required when the corresponding cache resource is scheduled, etc.

[0071] Among them, the target cache resource is divided into multiple ways, and each way corresponds to a cache area of a corresponding size.

[0072] In implementation, according to actual application requirements, cache resource scheduling instructions for the target cache resource can be pre-configured before step 101.

[0073] Optionally, in the embodiments of the present application, a first configuration component and multiple groups of second configuration components are pre-set in the electronic device. The first configuration component can be used to configure instruction data, and the instruction data may include, but is not limited to, instruction data for indicating cache resource scheduling. Each group of second configuration components can be used to configure cache resource scheduling information.

[0074] Exemplarily, taking the target cache resource as SLC, the first cache mode as the OCM mode, and the second cache mode as the Cache mode as an example, the embodiments of the present application design a software-configurable ocm_cmd register as the first configuration component to be used for configuring cache resource scheduling instructions. Optionally, the ocm_cmd register has only 1 bit, that is, a single-bit register, and is specifically used as the OCM setting total switch. Among them, optionally, if the value of the single bit in ocm_cmd is set to 1, it indicates that resource scheduling needs to be performed on the SLC, and is specifically used to indicate allocating a cache area in the OCM mode or canceling the cache area in the OCM mode in the SLC. At the same time, multiple groups of software-configurable ocm_cfg registers are also designed as the multiple groups of second configuration components to be used for configuring cache resource scheduling information.

[0075] Assume that the SLC has an xMB address space and is composed of y ways, then each way occupies x / y MB, and x / y groups of ocm_cfg registers can be designed, and each group of registers corresponds to one way. For example, assume that the SLC has a 16MB address space and is composed of 16 ways, then each way occupies 1MB, and a total of 16 groups of software-configurable ocm_cfg registers can be designed accordingly. Each group of registers may include, but is not limited to, the following cache resource scheduling information shown in Table 1.

[0076] Table 1

[0077]

[0078] Among them, base represents the base address, for example, it represents the base address of the OCM interval. way represents the way, valid represents the valid bit flag, and opcode represents the operation information or operation code. For more detailed information about each field, please refer to Table 1.

[0079] When it is necessary to schedule the target cache resource, for example, when it is necessary to allocate a cache area of the first cache mode or revoke a cache area of the first cache mode (such as allocating or revoking an OCM cache area) in the target cache resource, the way information that has been allocated as the first cache mode and the corresponding second configuration component can be determined from the multiple cache areas first. On this basis, the target way and the corresponding target group second configuration component that can be used to allocate the cache area of the first cache mode can be determined from the way information that has not been allocated as the first cache mode and the corresponding second configuration component, or the target way and the corresponding target group second configuration component that need to revoke the cache area of the first cache mode can be determined from the way information that has been allocated as the first cache mode and the corresponding second configuration component, and the target cache resource scheduling information for implementing the required resource scheduling (such as allocating or revoking a cache area of the first cache mode such as OCM) for the target cache resource is written to the determined target group second configuration component. For example, referring to Figure 2 the schematic diagram of register configuration shown, specifically, the target cache resource scheduling information for allocating or revoking the OCM cache area can be written to the determined target group ocm_cfg register, and the configured target cache resource scheduling information may include some or all of the information such as base, way, valid, and opcode shown in Table 1.

[0080] In addition to writing the target cache resource scheduling information to the target group second configuration component, instruction data for indicating cache resource scheduling can also be written to the first configuration component. For example, writing Figure 2 the instruction data "1" for indicating resource scheduling to the ocm_cmd register shown in.

[0081] On this basis, in this step 101, specifically, in response to detecting that the first configuration component is configured with instruction data for indicating cache resource scheduling, the target group second configuration component configured with the target cache resource scheduling information is determined from multiple groups of second configuration components, and the target cache resource scheduling information configured in the target group second configuration component is obtained. For example, in response to detecting that the ocm_cmd register is configured with the instruction data "1" for indicating cache resource scheduling, the target group ocm_cfg register configured with the target cache resource scheduling information is determined from multiple groups of ocm_cfg registers, and the target cache resource scheduling information is read from it.

[0082] Among them, the target cache resource scheduling information includes: cache mode information and operation information.

[0083] The cache mode information is used to indicate setting the first cache area in the target cache resource to the first cache mode or canceling the first cache mode for the corresponding second cache area; for example, it is used to indicate setting the first cache area in the SLC to the OCM mode or canceling the OCM mode for the corresponding second cache area in the SLC. The cache mode information can specifically be the valid bit flag valid in Table 1. When its value is 1, it indicates that the indicated first cache area is allocated to the OCM mode, and when it is 0, it indicates canceling the OCM mode for the indicated second cache area.

[0084] The operation information is used to indicate the data transfer operation mode between the target cache resource and the storage component. For example, when performing resource scheduling on the SLC, it is used to indicate the data transfer operation mode between the SLC and the DDR, etc. The operation information can specifically be the opcode shown in Table 1.

[0085] Among them, when the cache mode information indicates setting the first cache area in the target cache resource to the first cache mode, the target cache resource scheduling information further includes configuration address information, which is used to indicate the address of the first cache area, such as indicating the base address of the first cache area, and can specifically be the base shown in Table 1.

[0086] Specifically, if the cache mode information indicates setting the first cache area in the target cache resource to the first cache mode, for example, indicating setting the first cache area in the SLC to the OCM mode, exemplarily, the target cache resource scheduling information can specifically include at least some of the following information:

[0087] 11) The first valid bit flag for indicating setting the corresponding first cache area to the first cache mode such as the OCM mode, such as valid in Table 1, and assigning valid the value of 1 to indicate setting the corresponding first cache area to the first cache mode such as the OCM mode;

[0088] 12) The first base address of the first cache area, such as base in Table 1.

[0089] 13) The first way identifier for indicating the way corresponding to the first cache area, such as way in Table 1.

[0090] 14) The first opcode for indicating the operation to be performed on the first cache area when setting the first cache area to the first cache mode, such as opcode in Table 1, and opcode can be set to 01 or opcode = 10.

[0091] The meanings represented by different values of the opcode are shown in Table 1. Among them, when allocating the cache area in the OCM mode for the SLC, if it is necessary to first map the data in the corresponding address space of the DDR to the first cache area to be allocated as the OCM mode, the opcode is set to 10; otherwise, the opcode is set to 01.

[0092] The target address space of the first cache area can be determined according to the first base address and the cache area size corresponding to each way (for example, each way corresponds to a 1MB cache address space).

[0093] If the cache mode information indicates to cancel the first cache mode for the second cache area in the target cache resource, for example, indicates to cancel the OCM mode for the second cache area in the SLC. Exemplarily, the target cache resource scheduling information may specifically include at least some of the following information:

[0094] 21) The second valid bit identifier used to indicate canceling the first mode for the corresponding second cache area; such as valid in Table 1, and valid is assigned 0 to indicate canceling the first cache mode such as the OCM mode for the corresponding second cache area.

[0095] 22) The second opcode used to indicate the operation to be performed on the second cache area when canceling the first mode for the second cache area, such as opcode in Table 1, and opcode can be set to 01 or opcode = 11.

[0096] The meanings represented by different values of the opcode are shown in Table 1. Among them, when canceling the first cache mode such as the OCM mode for the second cache area, if it is necessary to write the data in the second cache area back to the DDR, the opcode is set to 11; otherwise, the opcode is set to 01.

[0097] The second cache area is specifically the cache area corresponding to the way occupied by the target group second configuration component currently to cancel the first cache mode such as the OCM.

[0098] 23) The second base address of the second cache area, corresponding to base in Table 1.

[0099] 24) The second way identifier used to indicate the way corresponding to the second cache area, corresponding to way in Table 1.

[0100] Among them, the target group second configuration component can be determined from the multiple groups of second configuration components based on the cache mode information and the operation information. For example, the corresponding group of second configuration components in the multiple groups of second configuration components that are configured with a first valid bit flag and a first opcode (i.e., valid = 1, and opcode = 01 or opcode = 10) is determined as the target group second configuration component, or the corresponding group of second configuration components in the multiple groups of second configuration components that are configured with a second valid bit flag and a second opcode (i.e., valid = 0, and opcode = 01 or opcode = 11) is determined as the target group second configuration component.

[0101] The target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction, for example, pre-written into the target group second configuration component.

[0102] Step 102: Perform cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information.

[0103] This step 102 can be further implemented as including at least one of the following 31)-32):

[0104] 31) In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, determine the target address space of the first cache area according to the configuration address information; according to the target address space, write the data in the first cache area into the corresponding storage area of the storage component; perform a corresponding first operation on the first cache area according to the operation information.

[0105] Optionally, the configuration address information can be the first base address written into the target group second configuration component. When determining the target address space of the first cache area according to the configuration address information, the target address space of the first cache area can be specifically determined according to the first base address and the cache area size corresponding to each way (for example, each way corresponds to a 1MB cache address space).

[0106] Taking the storage component as DDR and the target cache resource as the SLC in the Soc as an example, when writing the data in the first cache area to the corresponding storage area of the storage component according to the target address space, the existing flush cache mechanism (cache flush mechanism) of the SLC can be specifically used to write back the data corresponding to the way indicated by the way in the target group second configuration component, that is, the data in the first cache area, to the DDR one by one. Among them, for the cacheline (cache line) in the first cache area that has been written back to the DDR, set its tag to the invalid state. For the cacheline that has not been written back to the DDR, if other requests access it and hit, it does not prevent the normal operation of the request.

[0107] When performing the corresponding first operation on the first cache area according to the operation information, the corresponding first operation can be specifically performed on the first cache area according to the first operation code.

[0108] For example, if the first operation code opcode = 01, set it to 00 to reset the first operation code, and then directly jump to the next step; if the first operation code opcode = 10, first set the first operation code to 00 to reset it, and then load the data in the DDR corresponding to the base~base+size(way) cache address space into the base~base+size(way) cache address space.

[0109] Among them, base represents the first base address, size(way) represents the cache area size corresponding to each way, and base~base+size(way) correspondingly represents the target address space of the first cache area.

[0110] Optionally, the embodiment of the present application is pre-designed with a dma (Direct Memory Access) engine. Refer to Figure 3 the working mechanism of the dma engine shown. The engine can load the DDR data at the specified address into the cache area corresponding to the specified way in the SLC by issuing a dma Read request (dma read request). Thus, when loading the data in the DDR corresponding to the base~base+size(way) cache address space into the base~base+size(way) cache address space, the dma engine can be activated, and the dma engine can be used to load the DDR data into its corresponding cache address space in the SLC.

[0111] In addition, in response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode such as the OCM mode, in addition to performing the above processing, some other auxiliary processing may also be included. For example, resetting the command data in the first configuration component (ocm_cmd register), resetting the first opcode, and issuing an interrupt to the software to notify the software that the mode scheduling is successful (i.e., completing the setting of the first cache area to the first cache mode such as OCM), etc.

[0112] 32) In response to the target cache resource scheduling information indicating that the corresponding second cache area cancels the first cache mode, perform a corresponding second operation on the second cache area according to the operation information; clear the configuration address information of the second cache area stored in the target group second configuration component and the second way identifier indicating the way corresponding to the second cache area.

[0113] When performing a corresponding second operation on the second cache area according to the operation information, specifically, a corresponding second operation may be performed on the first cache area according to the second opcode (such as opcode). For example, for the case where valid = 0 and opcode = 01, set the opcode to 00 to reset the opcode, and then directly jump to the next step; for the case where valid = 0 and opcode = 11, set the opcode to 00 to reset the opcode, and then based on the cache flush module, such as Figure 4 the flush cache module shown, perform a cache flush operation, that is, write the data in the second cache area back to the corresponding address range in the DDR.

[0114] After responding to the target cache resource scheduling information indicating that the corresponding second cache area cancels the first cache mode such as canceling the OCM mode and completing the processing in step 32), some auxiliary processing may also be performed. For example, issuing an interrupt to the software to notify it that the mode scheduling is successful (i.e., completing the cancellation of the first cache mode such as OCM for the second cache area), etc.

[0115] In practical applications, the scheduling of the target cache resources is not limited to allocating a cache area with the first cache mode and canceling the cache area with the first cache mode in the target cache resources, and may also include adjusting the cache area with the first cache mode, such as adjusting the cache area with the OCM mode.

[0116] Among them, adjusting the cache area of the first cache mode such as the OCM mode mainly refers to adjusting the address space or the corresponding way of a cache area that has been allocated to the first cache mode such as the OCM mode. This adjustment operation can be decomposed into first performing an operation to revoke the second cache area of the first cache mode, and then performing an operation to allocate the first cache area of the first cache mode. For the specific process of allocating and revoking the cache area of the first cache mode, please refer to the above text and will not be elaborated here.

[0117] In summary, the resource scheduling method provided in this embodiment, by responding to the detection of a cache resource scheduling instruction, determines the matching target cache resource scheduling information from multiple groups of cache resource scheduling information (the cache resource scheduling information at least includes the cache mode of the corresponding cache resource), and performs cache resource scheduling processing on the target cache resource that matches the target cache resource scheduling information, can realize dynamic scheduling of different cache areas of the target cache resource according to the required cache mode, thereby improving the management flexibility of the target cache resource and adapting to the increasingly changing usage requirements of the target cache resource.

[0118] In an optional embodiment, the resource scheduling method provided in this application may further include the following processing:

[0119] 41) In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, set a usage restriction flag for the way corresponding to the first cache area.

[0120] Among them, the usage restriction flag is used to restrict the reallocation and use of the corresponding way in the first cache mode.

[0121] In this embodiment, in response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction flag for the way corresponding to the first cache area is set, so that when there are other requests that need to allocate a new way later, the first cache area and its corresponding way cannot be used, so as to ensure the high priority of the first cache area in the first cache mode, such as ensuring the high priority of the first cache area in the OCM mode, until the first cache mode of the first cache area such as the OCM mode is revoked, the first cache area supports reallocation and use for other requests.

[0122] 42) In response to the target cache resource scheduling information indicating that the corresponding second cache area revokes the first cache mode, revoke the usage restriction flag for the way corresponding to the second cache area.

[0123] Contrary to the situation in 41), in this step 42), by responding to the target cache resource scheduling information indicating to revoke the first cache mode for the corresponding second cache area, the usage restriction flag for the path corresponding to the second cache area is revoked, which can be used to enable subsequent reallocation and use of the second cache area with the first cache mode such as the OCM mode revoked when other requests need to allocate a new path.

[0124] In practical applications, for each path corresponding to a target cache resource such as the SLC, it is possible to record whether the cache area corresponding to each path is scheduled as a first cache mode such as the OCM mode and / or whether there is a usage restriction flag, etc., and save the formed record information, so as to facilitate subsequent directly based on this record information to conveniently and efficiently perform cache scheduling processes such as OCM allocation, revocation, and adjustment on target cache resources such as the SLC.

[0125] In this embodiment, by setting a usage restriction flag for the cache area in the first cache mode such as the OCM mode or the path corresponding to it, it can be ensured that during the period when the corresponding cache area in the target cache resource is scheduled as a first cache mode such as the OCM mode, it will not be reallocated and used by other resource requests, thus ensuring the high usage authority of the first cache mode such as the OCM mode for the target cache resource; at the same time, by recording whether the cache area corresponding to each path is scheduled as a first cache mode such as the OCM mode and / or whether there is a usage restriction flag, etc., it can be convenient to directly perform cache scheduling processes such as OCM allocation, revocation, and adjustment on target cache resources such as the SLC based on the formed record information conveniently and efficiently.

[0126] The following provides an application example of the resource scheduling method disclosed in the embodiments of the present application.

[0127] In this example, the target cache resource is the SLC in the SoC, the storage component is the DDR, the first cache mode is the OCM mode, and the second cache mode is the Cache mode. The usage authority of the OCM mode for the SLC is higher than that of the Cache mode for the SLC. And this example designs an ocm_cmd register, which has only 1 bit and is used as the OCM setting total switch. At the same time, a dma engine is designed, and this dma engine can load the DDR data at a specified address into the specified path / cache area in the SLC by issuing a dma Read request.

[0128] In addition, this example assumes that the SLC has a 16MB address space, consists of 16 paths, and each path occupies 1MB. At the same time, 16 groups of software-configurable ocm_cfg registers: ocm_cfg_0~15 are designed. The information included in each group of registers is shown in Table 1 above.

[0129] On this basis, through the cooperation between software and hardware, dynamic scheduling such as the allocation, revocation, or adjustment of the OCM mode cache area for the SLC can be achieved. Among them, for the requirements of allocating or revoking the OCM cache mode, the software is responsible for configuring instructions and related scheduling information, and the hardware is responsible for responding to the software configuration to achieve the required resource scheduling such as OCM allocation, revocation, or adjustment through the cooperation between software and hardware.

[0130] The following first describes the software and hardware processes for allocating an OCM address range on the SLC, and the specific software and hardware processes are as follows.

[0131] I. Software process:

[0132] a. The software first queries the ocm_cfg_0~15 registers to determine the address and way information already allocated as the OCM mode in the SLC;

[0133] b. The software selects a group of registers in the ocm_cfg_0~15 registers that are not allocated as the OCM mode, writes the base address to be allocated as the OCM mode to the base in the selected ocm_cfg, writes the way to be allocated as the OCM mode to the way in the selected ocm_cfg (note that the way already allocated as the OCM mode cannot be used), and writes 1 to the valid in the selected ocm_cfg. If it is necessary to map the corresponding DDR space data to the cache address space to be allocated as the OCM mode in advance, write 10 to the opcode, otherwise write 01 to the opcode;

[0134] c. The software writes 1 to the ocm_cmd;

[0135] d. Wait for the interrupt signal indicating the successful OCM allocation sent by the subsequent hardware. After receiving the hardware interrupt signal, the cache area scheduled as the OCM mode can receive and normally respond to the OCM access request.

[0136] The OCM access request refers to an access request used to indicate a read / write operation on the OCM cache area.

[0137] II. Hardware process:

[0138] a. When ocm_cmd is detected as 1, first set it to 0 to achieve reset. At the same time, check the 16 groups of ocm_cfg registers. For the registers with valid = 1 and (opcode = 01 or opcode = 10), first use the existing flush cache mechanism in SLC to write the data in the cache area corresponding to the specified way in the way back to the corresponding storage area in DDR one by one, and set the tag information for the cacheline that has been written back to DDR in this cache area to indicate its state as invalid. For the cacheline in this cache area that has not been written back to DDR, if other requests access it and hit, it does not prevent the normal operation of the request;

[0139] b. Referring to the working mechanism of the replacement policy module shown in Figure 5 When there is a need to allocate a new way for other requests, the replacement policy module (replacement) inside SLC will read the data in the way and cannot use the specified way in the way;

[0140] c. After the operation of the flush cache mechanism on the specified way in the way is completed, check the opcode. If its value is 10, first set it to 00 to achieve reset, then activate the dma engine, and load the data in DDR corresponding to the cache area from base to base + size(way) into the specified way in the way; if its value is 01, first set it to 00 to achieve reset, and then directly jump to the next step;

[0141] d. Set the usage limit mark for the way;

[0142] e. Send an interrupt to the software to notify the software that the OCM allocation is successful.

[0143] Next, continue to describe the software and hardware processes for revoking an OCM address range on SLC. The specific software and hardware processes are as follows.

[0144] I. Software process:

[0145] a. The software queries the ocm_cfg_0~15 registers to first determine the addresses of the cache areas that have been allocated in OCM mode and the corresponding way information;

[0146] b. The software selects the register corresponding to the cache area for which the OCM mode needs to be revoked from the ocm_cfg_0~15 registers and writes 0 to the valid in it. If it is necessary to write the data in this cache area to be revoked from the OCM mode back to DDR, write 11 to the opcode in the selected register, otherwise write 01;

[0147] c. The software writes 1 to ocm_cmd;

[0148] d. Wait for the interrupt signal indicating the successful revocation of OCM sent by the subsequent hardware. After receiving this interrupt signal from the hardware, it can be confirmed that the OCM interval has been revoked.

[0149] II. Hardware process:

[0150] a. When detecting that ocm_cmd is 1, first set it to 0 for reset. At the same time, check the 16 groups of ocm_cfg registers. For the registers with valid = 0 and opcode = 01, set the opcode to 00 for reset, and then directly jump to the next step; for the registers with valid = 0 and opcode == 11, set the opcode to 00 for reset, and then perform the flush cache operation, that is, write the data in the cache area corresponding to the way in the way back to the DDR address interval corresponding to base in DDR.

[0151] b. Notify the replacement policy module inside the SLC to cancel the usage restriction flag for the way corresponding to the way.

[0152] c. Clear both base and way to 0.

[0153] d. Send an interrupt to the software to notify the software that the OCM revocation is successful.

[0154] Adjusting the cache area of the OCM mode mainly refers to adjusting the base or way of a cache area already allocated in the OCM mode. The corresponding software and hardware processes can be decomposed into first executing the process of the above OCM revocation operation, and then re - executing the process of the above OCM allocation operation.

[0155] In this example, based on the resource scheduling method provided in the embodiments of the present application, by using the cooperation of software and hardware to perform dynamic scheduling of the OCM at runtime, such as dynamic allocation, revocation, or adjustment of the OCM, etc., the dynamic partitioning and management of different cache modes of the SLC are realized, thereby improving the management flexibility of the SLC and adapting to the increasingly changing usage requirements of the SLC.

[0156] In addition, by performing dynamic scheduling of the OCM mode on the SLC at runtime in this example, the software can be given the ability to flexibly adapt to different application scenarios (such as video playback, photo taking, intelligent transportation management, etc.), which helps to improve the system energy efficiency; and the dynamic cache resource scheduling of the SLC does not affect the normal working performance of the system. At the same time, the automatic mapping mechanism between the SLC on the SoC chip provided in the present application and the off - chip storage such as DDR can also reduce software intervention, thereby further adapting to the different usage requirements of different devices for the SLC.

[0157] The embodiments of the present application also provide a resource access method. See Figure 6The schematic diagram of the method flow shown. The resource access method provided by the embodiments of the present application may include the following steps 601 to 604, and the following will describe these steps in detail respectively.

[0158] Step 601: Obtain an access request for the target cache resource.

[0159] Exemplarily, an access request for the SLC in the SoC can be obtained, specifically an access request for data read / write operations on the cache area within the SLC.

[0160] The access request contains a first access address, and the first access address actually is the address of the corresponding storage area of the storage component outside the SoC, such as DDR. That is to say, for the resource request subject, what is visible is the storage area of the storage component outside the SoC, such as DDR, and the first access address carried in the access request for the resource is correspondingly the address of the storage area in storage components such as DDR.

[0161] Since the storage area in storage components such as DDR corresponds to a corresponding cache area on the SLC in the chip such as SoC, or the storage area in the storage component can be made to correspond to a corresponding cache area on the SLC in the chip such as SoC through a temporary allocation operation. Therefore, for the first access address in the access request, the system will map it to the address of the corresponding cache area of the SLC in the chip such as SoC.

[0162] Step 602: Match the first access address included in the access request with the address range of the target cache resource to obtain a matching result.

[0163] Optionally, specifically, the first access address included in the access request can be matched with the target address range in the address range of the target cache resource to obtain a matching result.

[0164] Wherein, the target address range is the address range corresponding to the cache area in the first cache mode within the target cache resource.

[0165] In an optional implementation manner, the first access address included in the access request can be directly matched with the target address range corresponding to each corresponding second configuration component configured to be in the first cache mode among each group of second configuration components. However, it is not limited to this. In other optional implementation manners, the target address spaces corresponding to the cache areas / ways in the first cache mode can also be summarized and recorded in advance to form an address record table of the target address range, and the first access address included in the access request can be matched with each target address range in the address record table.

[0166] Taking the target cache resource as SLC and the first cache mode as OCM mode as an example, refer to Figure 7 the working mechanism of the OCM request judgment module shown in the figure. Specifically, the first access address included in the access request can be matched with the address range where valid = 1 in ocm_cfg_0~15 by using a pre-designed ocm request judgment module; alternatively, the first access address included in the access request can also be matched with the target address range corresponding to the cache area of each OCM mode recorded in advance.

[0167] Step 603: Determine the request type of the access request for the target cache resource according to the matching result; the request type is used to indicate the cache mode of the cache area requested to be accessed in the target cache resource, and the cache areas in the target cache resource can be scheduled to be in different cache modes.

[0168] If the first access address in the access request matches the address space of a certain cache area among the cache areas of each way in the first cache mode, it indicates that the access request is a request type for indicating access to the cache area of the first cache mode; otherwise, it indicates that the access request is a request type for indicating access to the cache area of the second cache mode.

[0169] For example, if the first access address included in the access request matches the spatial address range corresponding to the way used by a certain group of registers where valid = 1 in ocm_cfg_0~15, it indicates that the access request is a request type for indicating access to the OCM mode cache area in the SLC; otherwise, it indicates that the access request is a request type for indicating access to the non-OCM mode cache area in the SLC, such as the Cache mode cache area.

[0170] Optionally, after determining the request type of the access request for the target cache resource, an operation of adding a target can be performed on the access request based on the determined request type.

[0171] The operation of adding a target is used to add a corresponding request type to the access request.

[0172] For example, if it is determined that the access request is a request type for indicating access to the OCM mode cache area in the SLC, OCM mark information can be added to the access request to indicate that the access request is an OCM request. In addition, the way information that is matched can also be added to the access request.

[0173] Conversely, if it is determined that the access request is a request type for indicating access to the cache area in the SLC in Cache mode, no tag may be added to the access request, or Cache tag information may also be added to characterize the access request as a Cache request.

[0174] Step 604: According to the request type, perform an access operation matching the access request on the corresponding cache area in the target cache resource.

[0175] Specifically, if the access request is added with a request type for indicating access to the cache area in the first cache mode, map the first access address to the second access address of the target cache resource based on the first mapping method, and access the cache area in the first mode in the target cache resource based on the second access address.

[0176] For example, if the access request is added with OCM tag information, map the first access address to the second access address of the OCM mode cache area in the SLC based on the first mapping method, and access the corresponding OCM mode cache area in the SLC based on the second access address.

[0177] Conversely, if the access request is not added with a request type for indicating access to the cache area in the first cache mode or is added with a request type for indicating access to the cache area in the second cache mode, map the first access address to the third access address of the target cache resource based on the second mapping method, and access the cache area in the second cache mode in the target cache resource based on the third access address.

[0178] For example, if the access request is not added with OCM tag information or is added with Cache tag information, map the first access address to the third access address of the Cache mode cache area in the SLC based on the second mapping method, and access the corresponding Cache mode cache area in the SLC based on the third access address.

[0179] The first mapping method is different from the second mapping method. For example, the Cache mode adopts the hash mapping method (the second mapping method), and the OCM mode adopts the non-hash mapping method (the first mapping method), etc. Specifically, it can be determined according to the actual requirements of different cache modes for the address mapping method.

[0180] During implementation, optionally, for an OCM request after adding way information and OCM tag information, it can be sent to the command queue (Command Queue) of the SLC controller within the SLC to wait for processing by the SLC controller. After receiving the access request based on the Command Queue, the SLC controller first identifies it as an OCM request based on the added OCM tag information, and then converts the first access address into a second access address for the OCM mode cache area according to the first mapping method corresponding to the OCM mode and the way information, and performs normal read / write operations on the corresponding OCM mode cache area based on the second access address.

[0181] Conversely, if the access request is not an OCM request, it is sent to the Command Queue of the SLC controller in the normal Cache mode. When the SLC controller receives an access request in the normal Cache mode through the Command Queue, it first identifies it as a Cache request based on the characteristics that it does not have OCM tag information added or has Cache tag information added, and then performs address mapping according to the second mapping method corresponding to the Cache mode, mapping the first access address in the access request to a third access address, and checking whether the third access address hits in the SLC. If it hits, the required read / write operation can be directly performed. If a miss occurs, a new way needs to be allocated for it. At this time, the replacement policy module can select a non-OCM way for allocation according to the recorded way tags, that is, specifically use the selected non-OCM way to allocate a non-OCM cache area as the cache area to be accessed by the access request in the Cache mode.

[0182] The resource access method of this embodiment determines the request type of the access request for the target cache resource by matching the first access address included in the access request with the address range of the target cache resource, and then performs a matching access operation on the corresponding cache area within the target cache resource according to the determined request type; and when the access request fails to hit in the target cache resource, according to the recorded way tags, a non-OCM way (cache area of a non-first cache mode) is selected for the allocation of the requested cache area, implementing a resource access scheme that matches the resource scheduling method for dynamic resource scheduling provided by this application embodiment, thereby improving the flexibility of management and access to the target cache resource and being able to adapt to the increasingly changing usage requirements of the target cache resource.

[0183] This application embodiment also provides an electronic device, the composition structure of which is as Figure 8 shown, including at least:

[0184] Determination module 10, configured to determine, in response to detecting a cache resource scheduling instruction, target cache resource scheduling information that matches from multiple groups of cache resource scheduling information, where the cache resource scheduling information in the multiple groups of cache resource scheduling information at least includes the cache mode of the corresponding cache resource;

[0185] Resource scheduling processing module 20, configured to perform cache resource scheduling processing that matches the target cache resource scheduling information on the target cache resource.

[0186] In an optional implementation manner, the electronic device further includes a configuration module, and the configuration module includes a first configuration component for configuring command data and multiple second configuration components for configuring cache resource configuration information;

[0187] The determination module is specifically configured to: in response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, determine a target group of second configuration components that are configured with the target cache resource scheduling information from the multiple groups of second configuration components, and obtain the target cache resource scheduling information in the target group of second configuration components.

[0188] In an optional implementation manner, the target cache resource scheduling information includes: cache mode information and operation information;

[0189] The cache mode information is used to indicate setting a first cache area in the target cache resource to the first cache mode or canceling the first cache mode for a corresponding second cache area; the operation information is used to indicate the transmission operation mode between the data in the target cache resource and the storage component;

[0190] The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction.

[0191] In an optional implementation manner, when the cache mode information indicates setting a first cache area in the target cache resource to the first cache mode, the target cache resource scheduling information further includes configuration address information.

[0192] In an optional implementation manner, the resource scheduling processing module 20 is specifically configured to:

[0193] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, determine the target address space of the first cache area according to the configuration address information; according to the target address space, write the data in the first cache area into the corresponding storage area of the storage component; perform a corresponding first operation on the first cache area according to the operation information;

[0194] In response to the target cache resource scheduling information indicating that the corresponding second cache area cancels the first cache mode, perform a corresponding second operation on the second cache area according to the operation information; clear the configuration address information of the second cache area stored in the target group second configuration component and the second path identifier indicating the path corresponding to the second cache area.

[0195] In an alternative embodiment, the resource scheduling processing module 20 is further configured to:

[0196] In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, set a usage limit flag for the path corresponding to the first cache area;

[0197] In response to the target cache resource scheduling information indicating that the corresponding second cache area cancels the first cache mode, cancel the usage limit flag for the path corresponding to the second cache area;

[0198] Wherein, the usage limit flag is used to limit the reallocation and use of the corresponding path in the first cache mode; the target cache resources are divided into multiple paths, and each path corresponds to a cache area of a corresponding size.

[0199] In an alternative embodiment, the electronic device further includes a management module for performing configuration management on the configuration module;

[0200] The management module is specifically configured to:

[0201] Before the determination module responds to the cache resource scheduling instruction, determine the target group second configuration component that can be used to allocate the cache resources in the first cache mode from the multiple groups of second configuration components, and write the first configuration information for allocating the cache resources in the first cache mode to the determined target group second configuration component; and / or, determine the target group second configuration component that can be used to cancel the cache resources in the first cache mode from the multiple groups of second configuration components, and write the second configuration information for canceling the cache resources in the first cache mode to the determined target group second configuration component;

[0202] Write the instruction data for indicating cache resource scheduling into the first configuration component;

[0203] Among them, the target cache resource scheduling information includes the first configuration information and / or the second configuration information.

[0204] In an alternative embodiment, the electronic device further includes a data transmission module configured to perform at least one of the following:

[0205] When the cache resource scheduling process is used to allocate a cache area in the first cache mode, write the data in the cache area that needs to be scheduled to the first cache mode in the target cache resource back to the corresponding first storage area in the storage component; optionally, this process can be specifically implemented by the cache flush module described above.

[0206] When the cache resource scheduling process is used to allocate cache resources in the first cache mode, load the stored data in the second storage area of the storage component into the cache area that needs to be scheduled to the first cache mode in the target cache resource; optionally, this process can be specifically implemented by the dma engine described above.

[0207] In an alternative embodiment, the electronic device further includes a replacement policy module configured to:

[0208] When the access request for the target cache resource obtained is used to indicate accessing the target cache area in the second cache mode and the target cache area is missing in the target cache resource, determine the target way in the non-first cache mode from the target cache resource according to the usage restriction marks corresponding to different ways in the target cache resource, and allocate the cache area corresponding to the target way as the target cache area in the second cache mode;

[0209] Among them, the cache area in the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple ways, and each way corresponds to a cache area of a corresponding size; the usage restriction mark is used to restrict the reallocation and use of the corresponding way in the first cache mode.

[0210] The embodiments of the present application further provide a storage medium carrying one or more computer instruction sets, which, when executed by an electronic device, can enable the electronic device to implement the resource scheduling method and / or resource access method provided in any of the above method embodiments.

[0211] It should be noted that the various embodiments in this specification are described in a progressive manner, and the key points of each embodiment are the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0212] For the convenience of description, when describing the above system or device, various modules or units are described separately according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0213] From the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

[0214] Finally, it should also be noted that in this article, relational terms such as first, second, third, and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0215] The above are only the preferred embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A resource scheduling method, comprising: In response to detecting a cache resource scheduling instruction, determining matching target cache resource scheduling information from multiple sets of cache resource scheduling information, wherein the cache resource scheduling information in the multiple sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource; the cache resource scheduling instruction represents allocating a cache area of ​​a first cache mode in the target cache resource or canceling a cache area of ​​the first cache mode; For the target cache resource, a cache resource scheduling process matching the target cache resource scheduling information is executed.

2. The resource scheduling method according to claim 1, wherein in response to detecting the cache resource scheduling instruction, determining the matching target cache resource scheduling information from multiple sets of cache resource scheduling information comprises: In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

3. The resource scheduling method according to claim 2, wherein the target cache resource scheduling information comprises: Cache mode information and operation information; The cache mode information is used to indicate whether to set the first cache area in the target cache resource to the first cache mode or to cancel the first cache mode of the corresponding second cache area; the operation information is used to indicate the transmission operation mode between the data in the target cache resource and the storage component; The target group of second configuration components is determined from the multiple groups of second configuration components based on the cache mode information and the operation information; the target cache resource scheduling information is pre-written into the corresponding second configuration component based on the cache resource scheduling instruction. 4 . The resource scheduling method according to claim 3 , wherein when the cache mode information indicates that the first cache area in the target cache resource is set to the first cache mode, the target cache resource scheduling information further includes configuration address information.

5. The resource scheduling method according to claim 4, wherein the step of executing cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource comprises: In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a target address space of the first cache area is determined according to the configuration address information; According to the target address space, write the data in the first cache area into a corresponding storage area of ​​the storage component; and perform a corresponding first operation on the first cache area according to the operation information; In response to the target cache resource scheduling information indicating that the first cache mode is to be cancelled for the corresponding second cache area, a corresponding second operation is performed on the second cache area according to the operation information; The configuration address information of the second cache area and the second way identifier for indicating the way corresponding to the second cache area stored in the second configuration component of the target group are cleared.

6. The resource scheduling method according to claim 5, further comprising: In response to the target cache resource scheduling information indicating that the first cache area is set to the first cache mode, a usage restriction mark for a path corresponding to the first cache area is set; In response to the target cache resource scheduling information indicating that the first cache mode is canceled for the corresponding second cache area, the use restriction mark for the path corresponding to the second cache area is canceled; The use restriction mark is used to restrict the reallocation and use of the corresponding way in the first cache mode; the target cache resource is divided into multiple ways, each way corresponding to a cache area of ​​a corresponding size.

7. A resource access method, comprising: Obtain access request to target cache resource; Matching the first access address included in the access request with the address range of the target cache resource to obtain a matching result; Determine the request type of the access request to the target cache resource according to the matching result; the request type is used to indicate the cache mode of the cache area requested to access the target cache resource, and the cache area in the target cache resource can be dynamically scheduled to be in different cache modes through a cache resource scheduling instruction; According to the request type, an access operation matching the access request is performed on a corresponding cache area in the target cache resource.

8. The resource access method according to claim 7, before performing an access operation matching the access request on a corresponding cache area in the target cache resource according to the request type, further comprising: Based on the determined request type, performing a target adding operation on the access request; The target adding operation is used to add a corresponding request type to the access request; The performing, according to the request type, an access operation matching the access request on a corresponding cache area in the target cache resource comprises: If a request type indicating access to a cache area of ​​a first cache mode is added to the access request, the first access address is mapped to a second access address of the target cache resource based on a first mapping method, and the cache area of ​​the first mode in the target cache resource is accessed based on the second access address; If the access request is not added with a request type for indicating access to the cache area of ​​the first cache mode or is added with a request type for indicating access to the cache area of ​​the second cache mode, mapping the first access address to a third access address of the target cache resource based on a second mapping manner, and accessing the cache area of ​​the second cache mode in the target cache resource based on the third access address; The permission for using the target cache resource in the first cache mode is higher than the permission for using the target cache resource in the second cache mode.

9. The resource access method according to claim 7, wherein matching the first access address included in the access request with the address range of the target cache resource comprises: Matching the first access address included in the access request with the target address range in the address range of the target cache resource to obtain a matching result; The target address range is an address range corresponding to a cache area in the target cache resource that is in a first cache mode.

10. An electronic device, comprising: A determination module, configured to determine, in response to detecting a cache resource scheduling instruction, matching target cache resource scheduling information from a plurality of sets of cache resource scheduling information, wherein the cache resource scheduling information in the plurality of sets of cache resource scheduling information at least includes a cache mode of a corresponding cache resource; the cache resource scheduling instruction represents allocating a cache area of ​​a first cache mode in the target cache resource or canceling a cache area of ​​the first cache mode; The resource scheduling processing module is used to perform cache resource scheduling processing matching the target cache resource scheduling information on the target cache resource.

11. The electronic device according to claim 10, further comprising a configuration module, the configuration module comprising a first configuration component for configuring command data and a plurality of groups of second configuration components for configuring cache resource configuration information; The determining module is specifically used for: In response to detecting that instruction data for indicating cache resource scheduling is configured in the first configuration component, a target group second configuration component configured with target cache resource scheduling information is determined from the multiple groups of second configuration components, and the target cache resource scheduling information in the target group second configuration component is obtained.

12. The electronic device according to claim 11, further comprising a management module for performing configuration management on the configuration module; The management module is used to: Before the determination module responds to the cache resource scheduling instruction, a target group second configuration component that can be used to allocate cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the first configuration information for allocating cache resources in the first cache mode is written to the determined target group second configuration component; and / or, a target group second configuration component that can be used to revoke cache resources in the first cache mode is determined from the multiple groups of second configuration components, and the second configuration information for revoking cache resources in the first cache mode is written to the determined target group second configuration component; Writing instruction data for instructing cache resource scheduling into the first configuration component; in, The target cache resource scheduling information includes the first configuration information and / or the second configuration information.

13. The electronic device according to claim 10, further comprising a data transmission module, configured to perform at least one of the following: In the case where the cache resource scheduling process is used to allocate a cache area of ​​the first cache mode, writing the data in the cache area of ​​the target cache resource that needs to be scheduled as the first cache mode back to the corresponding first storage area in the storage component; In the case where the cache resource scheduling process is used to allocate cache resources of the first cache mode, the storage data of the second storage area in the storage component is loaded into the cache area in the target cache resource that needs to be scheduled as the first cache mode.

14. The electronic device according to claim 10, further comprising a replacement strategy module, configured to: In a case where the obtained access request to the target cache resource is used to indicate access to the target cache area of ​​the second cache mode and the target cache area is missing from the target cache resource, determining a target way that is not in the first cache mode from the target cache resource according to usage restriction tags corresponding to different ways in the target cache resource, and allocating the cache area corresponding to the target way as the target cache area of ​​the second cache mode; in, The cache area in the target cache resource can be scheduled to be in the first cache mode or the second cache mode; the target cache resource is divided into multiple paths, each path corresponding to a cache area of ​​a corresponding size; The use restriction tag is used to restrict the reallocation and use of the corresponding way in the first cache mode.

Images