Read operation processing method for storage device and storage device

Abstract

A read operation processing method for a storage device and the storage device are disclosed. The method is completed by a read processing program and a re-read processing program. The read processing program writes read error information of each storage page of a first flash memory particle into a first linked list. The re-read processing program includes: sequentially reading a plurality of read error information from the first linked list; for each read error information, determining an adaptive re-read voltage table; for each read error information, sequentially reading a plurality of read voltages from the adaptive re-read voltage table, and performing multiple rounds of re-reading on the corresponding storage page based on the plurality of read voltages until the data can be successfully corrected, wherein each round of re-reading includes a first stage and a second stage, and in the multiple rounds of re-reading of the plurality of storage pages, the first stage of one round of re-reading of a next storage page is performed in the second stage of one round of re-reading of a previous storage page, and the first stage is different from the second stage. The method can improve the re-reading efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of memory, and more particularly, to a read operation processing method for a storage device and the storage device. BACKGROUND

[0002] Currently, many storage devices, such as USB flash memory, SD card, CF card, SSD, eMMC embedded storage card, UFS device, etc., all use flash memory medium, especially NAND type flash memory medium, as the main storage medium, and gradually become the mainstream form. Compared with traditional magnetic medium memory, the performance has a qualitative leap. The flash memory medium is composed of a large number of storage units, each of which is composed of a floating gate transistor. The charge stored in the floating gate level of the floating gate transistor will change over time.

[0003] In order to ensure data security, such storage devices are generally provided with an ECC (Error Check Correction) circuit for data recovery and error correction. The ECC circuit is arranged in the controller. In the data writing stage, the encoded data is stored in the flash memory medium based on the original data coding. In the data reading stage, the data is read from the flash memory medium, and the original data is obtained by correcting a certain number of error data bits using the error correction code (ECC). The ECC circuit can reduce the error rate and improve the product yield.

[0004] In the data reading stage, before correcting the error data using the error correction code, a set of appropriate read voltages need to be applied to the bit lines connected to the corresponding storage units. If the level of the flash memory medium is good, or in a good use environment (for example, the number of charges in the floating gate level of the floating gate transistor does not change much), the data reading is completed by using a default voltage once. However, when the flash memory level is poor or at the end of life, or the use environment is not good, a retry table needs to be called for re-reading. However, the prior art performs re-reading in a first-in-first-out manner, which results in a slow error correction speed for the later read commands. The error correction of the later read commands cannot start until the final error correction result of the read command with an error is obtained, which is relatively low in efficiency. SUMMARY

[0005] In view of the above problems, the purpose of the embodiments of the present disclosure is to provide a read operation processing method for a storage device and the storage device to solve the problems in the prior art.

[0006] According to a first aspect of the embodiments of the present disclosure, a read operation processing method for a storage device is provided, the storage device comprising a controller and a flash storage medium, the flash storage medium comprising a plurality of flash memory particles, each flash memory particle being configured with at least one read voltage table, the read operation processing method being completed by a read processing program and a read retry processing program, the read processing program writing read error information of each storage page of a first flash memory particle in the plurality of flash memory particles into a first linked list,

[0007] The read retry processing program then performs the following steps:

[0008] Reading a plurality of read error information from the first linked list in sequence;

[0009] For each read error information, determining an adapted read voltage table according to the storage page to which the read error information pertains;

[0010] For each read error information, reading a plurality of read voltage groups from the adapted read voltage table in sequence, and performing a plurality of read retries on the storage page to which the read error information pertains based on the plurality of read voltage groups until the read-retrieved data can be successfully error-corrected,

[0011] Wherein each read retry comprises a first phase and a second phase, and in the plurality of read retries on the plurality of storage pages, the first phase of a read retry on a next storage page is performed in the second phase of a read retry on a previous storage page, the first phase being different from the second phase.

[0012] In some embodiments, the determining of the adapted read voltage table according to the storage page to which the read error information pertains comprises:

[0013] Determining the adapted read voltage table according to one or more of a write / erase count, a proportion of error data, and an error occurrence position of a storage block in which the storage page to which the read error information pertains is located.

[0014] In some embodiments, the determining of the adapted read voltage table according to one or more of a write / erase count, a proportion of error data, and an error occurrence position of a storage block in which the storage page to which the read error information pertains is located comprises:

[0015] Obtaining a first index number according to the write / erase count of the storage block in which the storage page to which the read error information pertains is located;

[0016] Determining an error type according to the proportion of error data and the error occurrence position, and obtaining a second index number according to the error type;

[0017] Determining the adapted read voltage table from at least one read voltage table configured for the flash memory particle in which the storage page to which the read error information pertains is located according to the first index number and the second index number.

[0018] In some embodiments, the read retry processing program further comprises:

[0019] loading the adapted re-read voltage table from the flash storage medium into the controller.

[0020] In some embodiments, the re-read voltage table adapted for each of the plurality of memory pages of the same memory block is the same re-read voltage table.

[0021] In some embodiments, wherein the first stage reads data from the flash storage medium to a register, the second stage reads data from the register to system memory.

[0022] In some embodiments, each node unit of the first linked list contains, in addition to the read error information, a bitmap, each element of the bitmap indicating whether the corresponding re-read voltage table has been used.

[0023] In some embodiments, the read processing program and the re-read processing program are implemented as firmware in the controller; the read processing program writes read error information of memory pages in the same flash die into the same linked list, the number of linked lists being equal to the number of flash dies, the read processing program writing read error information to one or more linked lists in parallel or serially; the re-read processing program reads the read error information from one or more linked lists and processes it, the re-read processing program processing each linked list in series or in parallel.

[0024] According to a second aspect of embodiments of the present disclosure, a controller of a storage device is provided, configured to perform the read operation processing method described above.

[0025] According to a third aspect of embodiments of the present disclosure, a storage device is provided, comprising a controller and a flash storage medium coupled thereto, the controller being configured to implement the read operation processing method described above.

[0026] The read operation processing method provided by embodiments of the present disclosure hides part of the time overhead of re-reading the next memory page in the first stage of a round of re-reading of the next memory page in the second stage of a round of re-reading of the previous memory page, thereby improving the re-reading efficiency. Further, the use of re-read voltage tables is indicated by a bitmap, avoiding omission of re-read voltage tables. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other objects, features and advantages of embodiments of the present disclosure will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 a schematic block diagram of an exemplary host system is shown;

[0029] Figure 2 is a flowchart of a read operation processing method for a storage device according to an embodiment of the present disclosure;

[0030] Figure 3 a timing relationship of three rounds of re-reading of three storage pages Page0 to Page2 is shown according to an embodiment of the present disclosure;

[0031] Figure 4 is a schematic diagram of a cache read of a Nand type flash memory;

[0032] Figure 5 is a flowchart of a read operation processing method for a storage device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The embodiments of the present disclosure are described below based on the embodiments, but the embodiments of the present disclosure are not limited to only these embodiments. In the following detailed description of the embodiments of the present disclosure, some specific details are described in detail. The present disclosure can also be understood without the description of these specific details by those skilled in the art. In order to avoid confusion of the essence of the present disclosure, the well-known methods, processes, flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0034] The flowcharts and block diagrams in the drawings illustrate the possible system, method, device, framework, function and operation of the embodiments of the present disclosure. The blocks on the flowcharts and block diagrams can represent a module, a program segment or only a piece of code, which are executable instructions for implementing the specified logic function. It should also be noted that the executable instructions for implementing the specified logic function can be recombined to generate new modules and program segments. Therefore, the blocks of the drawings and the block sequence are only used to better illustrate the processes and steps of the embodiments, and should not be regarded as a limitation on the invention itself.

[0035] Figure 1 a schematic block diagram of an exemplary host system 100 is shown. The host system 100 is, for example, a personal computer, a notebook computer, a server.

[0036] The host system 100 includes a host device 110 (e.g., a computer system including a host processor and memory) and a storage device. The host device 110 can issue host commands to the storage device so that the storage device manages host data stored in the storage device according to the commands. For example, the host device 110 can be communicatively connected to the storage device (e.g., through a host interface 121) and issue various commands (e.g., READ, WRITE, UNMAP, REASSIGN BLOCK, TRIM, etc.) to the storage device. The storage device can store, update, read, and / or otherwise manage host data according to address ranges prompted by the commands. Once the commands are executed, the storage device can transmit a response to the host device 110 indicating that the commands have been successfully completed.

[0037] The storage device is composed of a controller 120 and a flash memory medium 130. The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a storage medium interface 128. The host interface 121 of the controller 120 is connected to the host device 110 for buffering and transmitting host commands and host data. The processor 123 is connected to the host interface 121, the cache unit 124, and the storage medium interface 128, and the processor 123 parses the host commands and performs corresponding operations. The cache unit 124, for example, is a static random-access memory (SRAM) and / or a dynamic random-access memory (DRAM), and can be used to store mapping relationships between logical addresses and physical addresses and some configuration data. The storage medium interface 128 includes an interface circuit for realizing data transmission between the controller 120 and the storage medium 130. The flash memory medium 130 includes a plurality of flash memory dies, each of which is divided into a plurality of storage blocks, and each of the storage blocks is divided into a plurality of storage pages.

[0038] The controller 120 may also include an ECC (Error Check Correction) circuit for data recovery and error correction. In addition, the controller 120 should also include various software programs, which, together with the above-mentioned hardware components, implement various management functions and data reading and writing. These software programs include a data writing program and a data reading program. The data writing program uses the ECC circuit to perform LDPC (Low Density Parity Check Code) encoding on the original data to generate storage data, and writes the storage data to the flash storage medium 130. The data reading program reads the storage data from the flash storage medium 130, and then performs LDPC decoding through the ECC circuit to obtain the original data. However, if the number (or proportion) of erroneous data is too large and the ECC circuit fails to correct the error, then as described in the background technology, it is necessary to call a retry table for rereading.

[0039] In order to improve the rereading efficiency, the present disclosure provides a method as follows Figure 2 As shown for Figure 1 The read operation processing method of the storage device shown. The read operation processing method can be implemented as a read processing program and a reread processing program presented as a software program. Among them, the read processing program is responsible for processing the read commands for each storage page, which may specifically include: for the read command, reading the corresponding storage page data based on the default read voltage, and then recovering and correcting the data through the ECC circuit to obtain the original data. For the storage page data that cannot be corrected by ECC, the read error information is recorded in a linked list. For the linked list, the read processing program writes the read error information of the storage page in the same flash memory particle into the same linked list. The number of linked lists is equal to the number of flash memory particles. The read processing program can write the read error information to one or more linked lists in parallel or serially; the reread processing program reads the read error information from one or more linked lists and processes it. The reread processing program can process each linked list serially or in parallel. After configuring the table, issuing all read error information commands in parallel can reduce the average delay of the read command after the read error. The flowchart of the reread processing program is as follows Figure 2 As shown below. Figure 1 Detailed description Figure 2 Flowchart of the process.

[0040] In step S201, multiple read error messages are sequentially read from a first linked list. The first linked list corresponds to a first flash memory cell, which is any one of the multiple flash memory cells in the flash storage medium 130. The first linked list is generated by the read processing program to store read error information for each storage page in the first flash memory cell. The read error information may include the error location (corresponding to the storage block and storage page), the number (or percentage) of erroneous data, an error description, an error type, and so on.

[0041] In step S202, for each read error information, determine the adapted read voltage table according to the storage page it is for. Each flash memory grain in the flash memory medium 130 is configured with at least one read voltage table, which is stored in the flash memory medium 130 and / or the cache unit 124. After determining the adapted read voltage table, determine whether the table is in the cache unit 124, if not, upload the table from the flash memory medium 130 to the cache unit 124. How to retrieve the adapted read voltage table depends on the organization and indexing method of the read voltage table, for example, determine the adapted read voltage table according to one or more of the write / erase times of the storage block, the error type (error data ratio and error occurrence position). Each read error information can be adapted to one or more read voltage tables, and multiple read error information can correspond to the same read voltage table. In addition, each read voltage table generally stores multiple sets of read voltages.

[0042] In step S203, for each read error information, sequentially read multiple sets of read voltages from the adapted read voltage table, and perform read on the storage page it is for according to the multiple sets of read voltages, until the read data is successfully corrected, then stop the read.

[0043] Based on the present embodiment, sequentially read multiple read error information from the first linked list, for each read error information, determine and obtain the read voltage table adapted to the storage page it is for, then sequentially read multiple sets of read voltages from the read voltage table, and perform data read according to the multiple sets of read voltages, if the read data can be successfully corrected by the ECC circuit, stop the data read.

[0044] Further, each round of read includes two stages: the first stage and the second stage, and the first stage is different from the second stage. Generally, the first stage reads data from the flash memory medium to the register, and the second stage reads data from the register to the system memory. Then, in multiple rounds of read of multiple storage pages, the first stage of one round of read of the next storage page is performed in the second stage of one round of read of the previous storage page. Figure 3 Take this as an example to illustrate this. Figure 3 The timing relationship of three rounds of read of three storage pages Page0 to Page2 according to one embodiment of the present disclosure is shown. As shown in the figure, each round of read of each of Page0 to Page2 includes a first stage and a second stage, then the second stage of read of Page1 is performed in the second stage of read of Page0, and the first stage of read of Page2 is performed in the second stage of read of Page1. In this way, part of the overhead of read of the next storage page can be hidden in the time overhead of read of the previous storage page, thereby improving the read processing efficiency.

[0045] according to Figure 3 For example, assuming that Page 2 is successfully corrected after 4 rereads, Page 1 is successfully corrected after 8 rereads, and Page 0 is successfully corrected after 10 rereads, and further assuming that the system frequency is 667 Hz, the second phase of each memory page takes 94 us, the first phase takes 68 us, and the remaining operations (such as setting the read voltage) are considered to have no time overhead. According to this embodiment, the time required for a reread is: 68 + 94 * 3 = 486 us. Therefore, the time required for a reread of Page 0 to Page 2 is: 486 * 4 + 4 * (68 + 94 * 2) + 2 * (68 + 94) = 3292 us. If the original method of rereading one memory page before rereading the next memory page is used, the time consumed is: 10 * (68 + 94) + 8 * (68 + 94) + 4 * (68 + 94) = 3564 us. It can be seen that the time consumed by rereading in the manner of this embodiment is less than the time consumed by rereading one storage page and then rereading the next storage page.

[0046] Figure 4 This is a schematic diagram illustrating the principle of a cache read operation for a Nand-type flash memory. In the first step, the data from Page N of the Nand-type flash memory is retrieved and stored in the data register. In the second step, the data from Page N is retrieved from the data register and stored in the cache register. In the third step, while the data from Page N is retrieved from the cache register and stored in the system register, the data from Page N+1 is retrieved from the Nand-type flash memory and stored in the data register. Furthermore, the cache read operation completes (ready) earlier than a normal read operation. Therefore, for Nand-type flash memory, the cache read mechanism can be used to perform multiple rereads in this embodiment.

[0047] Figure 5 This is a flowchart of a method for processing a read operation of a storage device provided by another embodiment of the present disclosure. Figure 2 The Examples provide more details.

[0048] In step S501 , the bitmap is cleared to zero, indicating that all re-read voltage meters are not used.

[0049] In step S502, the number of programming / erasing times of the corresponding memory block is obtained according to the read error information, and a first index number is determined according to the number of programming / erasing times.

[0050] In step S503, the error type is determined according to the error data ratio and the error occurrence position, and the second index number is obtained according to the error type. The error data ratio and the error occurrence position can be contained in the read error information. Moreover, the error type of the current re-reading can also be determined in combination with the past state (for example, the past error type) of the storage block where the error occurs.

[0051] In step S504, the adapted re-reading voltage table is loaded into the cache unit of the controller from the flash storage medium, and the re-reading is performed using the re-reading voltage table. The first index number and the second index number determine the name of the adapted re-reading voltage table.

[0052] In step S505, the corresponding bit in the bit map is set, indicating that the corresponding re-reading voltage table has been used.

[0053] In step S506, the next read error information to be processed in the linked list is read.

[0054] In step S507, it is judged whether there is a next read error information in the linked list, if yes, it is jumped to step S502 for execution, and if no, the process is ended.

[0055] In the embodiment, the re-reading voltage table is organized and indexed according to the write / erase times and the error type. Referring to Table 1, the first index number is determined according to the program / erase times, that is, when the program / erase times of a certain storage block is in the interval [0~1 / 5] of the total program / erase times, the first index code is 1, when the program / erase times of a certain storage block is in the interval [1 / 5~2 / 5] of the total program / erase times, the first index code is 2, and so on.

[0056] Table 1

[0057] Program / Erase Count 0~1 / 5 1 / 5~2 / 5 2 / 5~3 / 5 3 / 5~4 / 5 4 / 5~1 First Index Code 1 2 3 4 5

[0058] Referring to Table 2, the second index number is determined according to the error type, that is, when the error type is read disturb related, the second index number is *.1, when the error type is data retention related, the second index number is *.2, and so on.

[0059] When the program / erase times of a certain storage block is in the interval [0~1 / 5] of the total program / erase times, the first index code is *.1, when the program / erase times of a certain storage block is in the interval [1 / 5~2 / 5] of the total program / erase times, the first index code is 2, and so on.

[0060] Table 2

[0061] Second Index Code Error Type *.1 read disturb-related table dominant *.2 Data retention-related table dominant *.3 Open block-related table dominant *.4 Cross-temperature-related table dominant

[0062] Then, the adapted re-read voltage table is organized according to the first index number and the second index number. For example, if the first index number is 1 and the second index number is 1, the adapted re-read voltage table is Table 1.1. Of course, the organization and indexing of the re-read voltage table is only exemplary, and the re-read voltage table can be organized and indexed in other ways, which are not limited in the embodiments of the present disclosure.

[0063] In the embodiments, the bit map is used to indicate whether the adapted re-read voltage table is used for each read error information. The bit map can be a one-dimensional or two-dimensional table or more. Referring to Table 3, the bit map is in the form of a two-dimensional table, and each data in the table is a bit of '0' or '1'. The bit of '0' indicates that the corresponding re-read voltage table is not used, and the bit of '1' indicates that the corresponding re-read voltage table is used. For example, the bit of '1' in the third row and the fourth column indicates that table 2.3 is used. Thus, the current use of the re-read voltage table can be determined by maintaining the bit map. Further, the bit map can be used to determine whether the adapted re-read voltage table is loaded from the flash storage medium to the cache unit.

[0064] Table 3

[0065] table 1 2 3 4 5 *.1 0 0 0 0 0 *.2 0 0 1 0 0 *.3 0 0 0 0 0 *.4 0 0 0 0 0

[0066] In some embodiments, if the adapted re-read voltage table obtained according to the read error information cannot make the data error correction successful, other re-read voltage tables can be selected.

[0067] Accordingly, the embodiments of the present disclosure also provide a computer readable storage medium for storing software program codes formed according to the read data operation method.

[0068] Those skilled in the art can understand that the various modules or units of the data processing system according to the embodiments of the present disclosure can be implemented by hardware, firmware or software. The software includes, for example, coded programs formed by various programming languages such as JAVA, C / C++ / C#, SQL, etc. Although the steps and the order of the steps of the embodiments of the present disclosure are given in the method and the method legend, the executable instructions implementing the logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method legend, and the order can be adjusted at any time according to the function. For example, some of the steps can be performed in parallel or in reverse order.

[0069] The above merely describes preferred embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

[0070] In light of the above description of the embodiments according to the present disclosure, these embodiments do not describe all the details of the application, nor limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. The description is chosen and described in order to provide the best and most clear implementation of the principles and their practical application, so that others skilled in the art can best understand the present disclosure and use it in the best way. The present disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A read operation processing method for a storage device, the storage device comprising a controller and a flash memory storage medium, the flash memory storage medium comprising a plurality of flash memory particles, each flash memory particle being configured with at least one reread voltage table, the read operation processing method being performed by a read processing program and a reread processing program, the read processing program writing read error information of each storage page of a first flash memory particle among the plurality of flash memory particles into a first linked list, The reread processing procedure then performs the following steps: Reading a plurality of pieces of read error information sequentially from the first linked list; For each read error message, determining an adapted reread voltage table according to the targeted memory page; For each read error message, multiple sets of read voltages are sequentially read from the adapted reread voltage table, and the targeted storage page is reread multiple times based on the multiple sets of read voltages until the reread data can be successfully corrected. Among them, each round of rereading includes a first stage and a second stage. In multiple rounds of rereading of multiple storage pages, the first stage of a rereading round of the next storage page is performed in the second stage of a rereading round of the previous storage page. The first stage is different from the second stage. The first stage reads data from the flash memory storage medium to the register, and the second stage reads data from the register to the system memory.

2. The read operation processing method according to claim 1, wherein: The step of determining an adapted reread voltage table according to the targeted storage page includes: An adapted reread voltage table is determined according to one or more of the number of write / erase times, the error data ratio, and the error occurrence location of the memory block where the targeted memory page is located.

3. The read operation processing method according to claim 2, wherein: The method of determining an adapted reread voltage table according to one or more of the number of write / erase times, the proportion of error data, and the location of error occurrence of the memory block where the target memory page is located comprises: Obtain a first index number according to the number of write / erase operations of the memory block where the target memory page is located; Determine the error type based on the error data ratio and the error location, and obtain a second index number based on the error type; The adapted reread voltage table is determined from at least one reread voltage table configured for the flash memory particle where the targeted storage page is located according to the first index number and the second index number.

4. The read operation processing method according to claim 1 or 2, wherein: The reread processing program also includes: The adapted reread voltage table is loaded from the flash memory storage medium into the controller.

5. The read operation processing method according to claim 1, wherein: The reread voltage tables adapted to the multiple storage pages of the same storage block are the same reread voltage tables.

6. The read operation processing method according to claim 1 or 2, wherein each node unit of the first linked list includes, in addition to the read error information, a bit map, and each element of the bit map is used to indicate whether the corresponding retry voltage table has been used.

7. The read operation processing method according to claim 1, wherein: The read processing program and the reread processing program are implemented as firmware in the controller; the read processing program writes read error information of storage pages in the same flash memory particle into the same linked list, where the number of linked lists is equal to the number of flash memory particles, and the read processing program writes read error information to one or more linked lists in parallel or serially; The reread processing program reads the read error information from one or more linked lists and processes the information. The reread processing program processes each linked list in series or in parallel.

8. A controller of a storage device, configured to execute the read operation processing method according to any one of claims 1 to 7.

9. A storage device comprising a coupled controller and a flash memory storage medium, wherein the controller is configured to implement the read operation processing method according to any one of claims 1 to 7.

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