Link testing method, electronic device, storage medium, product and computing device

Abstract

The present invention discloses a link testing method, an electronic device, a storage medium, a product and a computing device, which are applied to the technical field of data transmission. The method includes determining a device to be tested according to a link to be tested and a link training trigger condition; after the link to be tested finishes the link training operation and the link is restored, determining a target register in the device to be tested that stores the operation state parameter information of the link to be tested based on the link training trigger condition, and reading the operation state parameter information; when it is diagnosed according to the operation state parameter information that the link to be tested has no fault, performing the corresponding link training operation again based on the link training trigger condition. The present invention can solve the problems in the related art that rely on special tools, have a long startup time and a long recurrence period for low-probability hardware faults, has strong applicability, and can effectively improve the link testing efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and particularly to a link test method, an electronic device, a storage medium, a product and a computing device. Background Art

[0002] PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) is the largest-sized interface on a computer motherboard, which is used to connect various components inside a computer, such as network cards, sound cards, independent graphics cards, video capture cards, etc., so that efficient data transmission can be carried out between these components and a processor.

[0003] To ensure server performance, in the related art, during the server development process, in the laboratory stage, a hardware debugging interface and professional software are used to design and verify the signal integrity of the PCIe link. By performing power-on and power-off cycle tests and restart tests on the whole machine, the stability of the link is detected. However, this test method not only depends on special tools and has limited usage scenarios, but also has problems such as long startup time and long recurrence periods for low-probability hardware failures.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The present invention provides a link test method, an electronic device, a non-volatile storage medium, a computer program product and a computing device, which do not depend on special tools, have strong applicability, and can effectively improve the link test efficiency.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] On the one hand, the present invention provides a link test method, including:

[0008] Determining a device under test according to a link to be tested and a link training trigger condition; when the link training operation is completed on the link to be tested and the link is restored, based on the link training trigger condition, determining a target register in the device under test that stores the operation state parameter information of the link to be tested, and reading the operation state parameter information; when it is diagnosed according to the operation state parameter information that the link to be tested has no fault, performing the corresponding link training operation again based on the link training trigger condition.

[0009] In a first exemplary implementation, determining the device under test according to the link under test and the link training trigger condition includes: obtaining service modules connected to the link under test and participating in the execution of user tasks; when the link training trigger condition is a cold reset or a warm reset, the device under test is each service module; when the link training trigger condition is a hot reset, the device under test is a service module that does not operate at the physical layer.

[0010] In a second exemplary implementation, determining the target register storing the operation status parameter information of the link under test in the device under test based on the link training trigger condition, and reading the operation status parameter information includes: when the link training trigger condition is a hot reset, controlling the baseboard management controller to obtain the register of the target service module operating at the physical layer through a preset access command, so as to obtain the operation status parameter information of the link under test stored in the target service module.

[0011] In a third exemplary implementation, determining the target register storing the operation status parameter information of the link under test in the device under test based on the link training trigger condition, and reading the operation status parameter information includes: when the link training trigger condition is a cold reset or a warm reset, reading the operation data information of the link under test stored in the register of the device under test through a sideband signal; obtaining the recovery times and link parameter values from the private register of the device under test; using the operation data information, the recovery times and the link parameter values as the operation status parameter information of the link under test.

[0012] In a fourth exemplary implementation, the link under test is a PCIe link under test. Determining the target register storing the operation status parameter information of the link under test in the device under test based on the link training trigger condition, and reading the operation status parameter information includes: when the link training trigger condition is a hot reset, reading the operation data information of the link under test from the PCIe configuration space register of the device under test; sending a hardware information acquisition instruction to the baseboard management controller to control the baseboard management controller to access the private register of the device under test; using the operation data information, the recovery times and the link parameter values stored in the private register as the operation status parameter information of the link under test.

[0013] In a fifth exemplary implementation, it further includes: by comparing the operation status parameter information with the predicted normal operation status parameters, if it is determined that the link under test has a fault, an error message is generated, and the log data corresponding to the current link training operation process is stored as test log data.

[0014] In the sixth exemplary embodiment, re - executing the corresponding link training operation based on the link training trigger condition includes: when the link training trigger condition is a cold reset, sending a power control signal to the device under test to control the device under test to perform an operation of first powering off and then powering on; after the link under test is restored, reading again from the target register the operation state parameter information of the link under test under the current link training operation, and diagnosing again whether there is a fault in the link under test according to the operation state parameter information, and continuously repeating until a preset fault diagnosis stop condition is reached.

[0015] In the sixth exemplary embodiment, re - executing the corresponding link training operation based on the link training trigger condition includes: when the link training trigger condition is a warm reset, sending a reset operation signal to the device under test to control the device under test to perform an operation of first resetting and then de - resetting; after the link under test is restored, reading again from the target register the operation state parameter information of the link under test under the current link training operation, and diagnosing again whether there is a fault in the link under test according to the operation state parameter information, and continuously repeating until a preset fault diagnosis stop condition is reached.

[0016] In the seventh exemplary embodiment, re - executing the corresponding link training operation based on the link training trigger condition includes: when the link training trigger condition is a hot reset, the target application program running under the operating system triggers a hot reset operation by setting the bridge control register of the device under test; after the link under test is restored, reading again from the target register the operation state parameter information of the link under test under the current link training operation, and diagnosing again whether there is a fault in the link under test according to the operation state parameter information, and continuously repeating until a preset fault diagnosis stop condition is reached.

[0017] The present invention also provides an electronic device, including a processor, and the processor is used to implement the steps of the link test method as described in any one of the previous ones when executing a computer program stored in a memory.

[0018] The present invention also provides a non - volatile storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the link test method as described in any one of the previous ones.

[0019] The present invention also provides a computer program product, including a computer program / instructions, and the computer program / instructions, when executed by a processor, implement the steps of the link test method as described in any one of the previous ones.

[0020] The present invention finally also provides a computing device, which at least includes a server. The server includes a baseboard management controller, a central processing unit, a link training control processor, and a first PCIe device. The first PCIe device is connected to the central processing unit through a PCIe bus and serves as a service module for executing user tasks. The central processing unit and the baseboard management controller are in the same network segment. Among them, the baseboard management controller is connected to the first PCIe device and the central processing unit through sideband signals, and is used to determine a to-be-tested PCIe device according to a to-be-tested PCIe link and a first type of link training trigger condition. When the to-be-tested PCIe link finishes the link training operation and the link is restored, based on the first type of link training trigger condition, determine a target register in the to-be-tested PCIe device that stores the operation status parameter information of the to-be-tested PCIe link, and read the operation status parameter information. When it is diagnosed according to the operation status parameter information that the to-be-tested PCIe link has no fault, then execute the corresponding link training operation again based on the first type of link training trigger condition. The first type of link training trigger condition includes a cold reset or a warm reset. The central processing unit is used to determine a to-be-tested PCIe device according to a to-be-tested PCIe link and a second type of link training trigger condition. When the to-be-tested PCIe link finishes the link training operation and the link is restored, based on the second type of link training trigger condition, determine a target register in the to-be-tested PCIe device that stores the operation status parameter information of the to-be-tested PCIe link, and read the operation status parameter information. When it is diagnosed according to the operation status parameter information that the to-be-tested PCIe link has no fault, then execute the corresponding link training operation again based on the second type of link training trigger condition. The second type of link training trigger condition includes a hot reset. The link training control processor is connected to the baseboard management controller and is used to control the power supply and reset of the server and meet the timing requirements of the first PCIe device and the central processing unit.

[0021] In a first exemplary embodiment, it further includes a network switch and a monitoring end. The network switch is connected to the baseboard management controller through a network port to enable the monitoring end to remotely access the baseboard management controller. The monitoring end is used to obtain error data and test log data during the link training operation of the to-be-tested link from the baseboard management controller.

[0022] In a second exemplary embodiment, the baseboard management controller is further configured to: when the link training trigger condition is a cold reset, perform a power-off operation and a power-on operation on the PCIe device to be tested by controlling the registers of the link training control processor; correspondingly, the central processing unit is further configured to: when the link training trigger condition is a warm reset, perform a reset operation and a de-reset operation on the PCIe device to be tested by controlling the registers of the link training control processor.

[0023] The advantages of the technical solution provided by the present invention are as follows: by performing corresponding link training through different trigger scenarios for link establishment, and performing link fault diagnosis based on the operating state parameter information read from the registers after link recovery, the stability and signal integrity of the link are tested. The total link establishment time is in the millisecond level. When the related art performs link stability tests through power-on / off cycling tests and restart tests, the basic input / output system startup time and operating system loading time are both in the minute level. Therefore, it is possible to avoid the redundant waiting time in the PCIe link test process of the related art, especially for test scenarios with low-probability hardware failure problems and problems that rely on long-cycle reproduction, significantly reducing the test time, improving the link stability verification efficiency, and effectively enhancing the link test efficiency. In addition, by performing link fault diagnosis based on the operating state parameter information read from the registers after link recovery, the problem that the link training state machine test depends on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is applicable not only to the laboratory stage but also to product testing and operation and maintenance scenarios, with better applicability.

[0024] In addition, the present invention also provides corresponding implementation electronic devices, non-volatile storage media, computer program products, and computing devices for the link test method, further making the method more practical, and the electronic devices, non-volatile storage media, computer program products, and computing devices have corresponding advantages.

[0025] The technical features mentioned above, the technical features to be mentioned below, and the technical features shown separately in the drawings can be combined with each other arbitrarily, as long as the combined technical features are not contradictory to each other. All feasible feature combinations are clearly recorded technical content in this article. Any one of the sub-features included in the same statement can be independently applied without necessarily being applied together with other sub-features. It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions of the present invention or related technologies, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or related technologies. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0027] Figure 1 Flow schematic diagram of a link test method provided by the present invention;

[0028] Figure 2 Schematic diagram of a service module in an exemplary scenario provided by the present invention;

[0029] Figure 3 Flow schematic diagram of the hot reset and de - reset processes provided by the present invention;

[0030] Figure 4 Structural diagram of an exemplary implementation manner of a link test device provided by the present invention;

[0031] Figure 5 Structural diagram of an exemplary implementation manner of an electronic device provided by the present invention;

[0032] Figure 6 Structural diagram of an exemplary implementation manner of a computing device provided by the present invention;

[0033] Figure 7 Frame schematic diagram of the link test method provided by the present invention in an exemplary application scenario;

[0034] Figure 8 Flow schematic diagram of the link test method triggered by cold reset and warm reset provided by the present invention;

[0035] Figure 9 Frame schematic diagram of the link test method provided by the present invention in another exemplary application scenario;

[0036] Figure 10 Flow schematic diagram of the link test method triggered by hot reset provided by the present invention. Detailed implementation manners

[0037] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Among them, the term "first" in the specification and the above-mentioned drawings is used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0038] With the progress of high-performance graphics processors and neural network algorithms, artificial intelligence technology has developed rapidly and been widely applied in various fields. The implementation of artificial intelligence technology depends on a high-performance software and hardware environment, and requires the ability to quickly respond to, analyze, converge, and close the loop for software and hardware failures. As an interface connecting the graphics processing unit (GPU) to other components on the motherboard, PCIe is used to transfer data between the GPU and the server system. With the continuous improvement of the data transfer rate, in order to ensure the reliability of the PCIe link, link training is performed during the initialization of the PCIe link to determine the optimal data transfer parameters. If the link training fails, it may cause the server to malfunction. In addition, errors such as parity errors and cyclic redundancy check errors may occur in PCIe communication, which affect the stability and reliability of the server. For example, large models require ultra-large-scale distributed training clusters. If a single graphics processor drops during the model training process, the previously trained model will become invalid, which will undoubtedly prolong the execution time of the task.

[0039] In order to ensure the reliability of the PCIe link, in the related art, during the server development process, the PCIe link is tested in the laboratory stage, including signal integrity verification, link training state machine transition verification, and stability verification. Among them, the signal integrity verification and link training state machine transition verification of the PCIe link are verified using the manufacturer's special tools for the PCIe link. This method not only depends on the hardware debugging interface and professional software, but also takes a long time, is highly professional, requires a high professional quality of the operator, and is only applicable to the design verification in the laboratory stage and cannot be used in the whole machine scenarios such as production testing and computer room operation and maintenance. The stability verification of the PCIe link is achieved through power-on and power-off cycle testing and restart testing. This method requires waiting for the BIOS (Basic Input Output System) and OS (Operating System) to start during the testing process, and the startup of the BIOS and OS takes a long time. Especially for low-probability hardware failure problems, the reproduction cycle is long, and the corresponding problem-solving and regression cycles are even longer.

[0040] In order to solve the problems that the traditional power-on / off cycle test and restart test in related technologies take a long time, and the link training state machine test relies on special tools and cannot be popularized in production test and operation and maintenance scenarios, the present invention realizes the test of link stability and signal integrity by performing corresponding link training through different trigger scenarios of link establishment, and diagnosing link faults according to the operation state parameter information read from the register after the link is restored. It does not rely on special tools, has strong applicability, and can effectively improve the link test efficiency. After introducing the technical solution of the present invention, various non-limiting embodiments of the present invention will be described in detail below. In order to better illustrate the present invention, numerous specific details are given in the following specific embodiments. Those skilled in the art should understand that the present invention can also be implemented without these specific details. In other instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail in order to highlight the gist of the present invention.

[0041] First, please refer to Figure 1 , Figure 1 which is a schematic flowchart of a link test method provided in this embodiment. This embodiment may include the following content:

[0042] S101: Determine the device under test according to the link to be tested and the link training trigger condition.

[0043] Among them, a link is a communication path during data transmission. The link to be tested is a link for detecting whether there are problems in the data communication path between communication nodes. This link can be based on any bus protocol, including but not limited to the PCIe bus protocol, CAN (Controller Area Network), and I2C (Inter-Integrated Circuit) protocol. Correspondingly, the link to be tested is a PCIe link to be tested, a CAN link to be tested, or an I2C link to be tested. Link training can ensure the stability and efficiency of high-speed data transmission. Through training, the link can determine the best signal quality and transmission rate, thereby optimizing data transmission performance. To verify the link performance, some operating status data during the link training process need to be obtained in this embodiment. Link training is a hardware process controlled by the physical layer. After the computer system or server system is reset, the hardware will automatically start the link training process, and the process is managed by the LTSSM (Link Training and Status Machine). This process configures and initializes the ports and links of the device, so as to support subsequent data transfer. Currently, there are multiple system reset methods. According to the different manifestations of link problems under different reset methods, the variables or pointers followed by the problems can be obtained. Based on this, the present invention tests the link according to the link training trigger conditions of different devices connected to the link to be tested. According to different link training trigger conditions, it can be divided into hot reset, warm reset, and cold reset. Among them, the hot reset is triggered by an in-band TS (Training Sequence) sequence without the need for other hardware signal changes. The warm reset triggers the bus port reset through an external PERST_N (global reset signal) signal and rebuilds the link. The cold reset powers off the bus device and then powers it on again, completely resetting the device and reloading the firmware.

[0044] In this embodiment, the link to be tested refers to the PCIe link that needs to be tested. The link to be tested is connected to multiple service modules that participate in executing services through corresponding buses. The service modules include but are not limited to a central processing unit, a bus switch such as a PCIe switch, a retimer, a graphics processing unit, a network card, and a hard disk. These service modules are connected to this link through corresponding buses. The link to be tested includes at least two devices to be tested, that is, the devices located at both ends of the link to be tested. Since the registers of the devices to be tested connected to the link to be tested store data related to the link status, and the ways of reading the registers of the devices are different under different reset methods, this step needs to determine the devices to be read under different link training trigger conditions and define them as the devices to be tested. That is, the device to be tested refers to the service module connected to the link to be tested and participating in executing services, and this service module can directly read the corresponding register data under the corresponding reset method.

[0045] S102: After the link to be tested finishes the link training operation and the link is restored, based on the link training trigger condition, determine the target register in the device to be tested that stores the operation status parameter information of the link to be tested, and read the operation status parameter information.

[0046] In order to identify whether there is a fault in the link to be tested, relevant data reflecting the status of the link to be tested needs to be obtained. The present invention obtains this data by performing a link training operation on the link to be tested. Correspondingly, whenever it is detected that the link training operation is completed and the link to be tested is restored, or when it is detected that the link to be tested finishes the link training operation and the link is restored according to a fixed frequency or a preset trigger method, determine the register that stores the operation status parameter information of the link to be tested. For the convenience of description, it is defined as the target register, and read the operation status parameter information of the link to be tested at the current moment, that is, during this link training process. The operation status parameter information includes but is not limited to the bandwidth, rate, recoverable errors, unrecoverable errors, the lane where the error code is located, the number of recovery times, and the link parameter values of the link to be tested.

[0047] S103: When it is diagnosed that there is no fault in the link to be tested according to the operation status parameter information, perform the corresponding link training operation again based on the link training trigger condition.

[0048] When the operation status parameter information is obtained in the previous step, it is compared with the corresponding data when the link to be tested has no fault, so as to identify that the link to be tested has no fault at the current moment, that is, during the current link training process. Exemplarily, standard values or standard ranges corresponding to various types of data included in the operation status parameter information can be preset in advance. The operation status parameter information under the standard values or standard ranges indicates that the current link is operating normally. For the convenience of description, it can be defined as the predicted normal operation status parameter without faults. By comparing the two, it is possible to quickly identify whether there is a fault in the link to be tested. When it is determined that the operation status parameter information diagnoses that the link to be tested has no fault, the link to be tested is triggered again according to the link training trigger condition to perform link training, and then jump to execute S102. Exemplarily, when it is determined that there is a fault in the link to be tested by comparing the operation status parameter information and the predicted normal operation status parameter, an error message is generated, and the log data corresponding to the current link training operation process is stored as test log data. That is to say, when it is determined that the operation status parameter information diagnoses that there is a fault in the link to be tested, an error can be reported and the log data can be exported for subsequent use. For example, if the link to be tested is a PCIe link to be tested, it can be used for subsequent PCIe link fault analysis and PCIe link operation and maintenance recovery.

[0049] In the technical solution provided in this embodiment, corresponding link training is performed through different trigger scenarios of link establishment, and link fault diagnosis is performed according to the operation status parameter information read from the register after link recovery, so as to realize the test of the stability and signal integrity of the link. The total link establishment time of the link is in milliseconds. When the related technology performs link stability testing through power-on / off cycle testing and restart testing, the basic input / output system startup and operating system loading times are both in minutes. Therefore, it is possible to avoid the extra waiting time in the PCIe link testing process of the related technology, especially for the test scenarios of low-probability hardware fault problems and problems that rely on long-cycle reproduction, greatly reducing the test time, improving the link stability verification efficiency, and effectively enhancing the link testing efficiency. In addition, by performing link fault diagnosis according to the operation status parameter information read from the register after link recovery, the problem that the link training state machine test depends on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is not only applicable to the laboratory stage, but also can be used in product testing and operation and maintenance scenarios, with better applicability.

[0050] In the above embodiment, there is no limitation on how to determine the device to be tested. The present invention also gives an exemplary implementation method, which may include the following content:

[0051] Obtain the service modules connected to the link to be tested and participating in the execution of user tasks; when the link training trigger condition is a cold reset or a warm reset, the device to be tested is each service module; when the link training trigger condition is a hot reset, the device to be tested is the service module that does not work at the physical layer.

[0052] In this embodiment, the device to be tested is determined according to different link training trigger conditions, so as to Figure 2 Take, for example, the central processing unit, PCIe switch, retimer, and graphics processing unit as service modules, which are interconnected through the PCIe bus with each other and are PCIe devices of a server or a computer system. When the link to be tested is the PCIe link between the central processing unit and the PCIe switch, the service modules are the central processing unit and the PCIe switch. In the case of a cold reset, warm reset, or hot reset, the device to be tested is the central processing unit and the PCIe switch. When the link to be tested is the PCIe link between the PCIe switch and the graphics retimer processor, the service modules are the PCIe switch, retimer, and graphics processing unit. Since they work at the physical layer, there is no configuration space and they are invisible to the OS. For a cold reset or a warm reset, the device to be tested is the PCIe switch, retimer, and graphics processing unit. For a hot reset, the device to be tested is the PCIe switch and the graphics processing unit.

[0053] As can be seen from the above, this embodiment determines the device to be tested for reading the running state parameter information according to different resets, which is beneficial to improving the diagnostic accuracy and efficiency of the link.

[0054] In the above embodiment, there is no limitation on how to determine the device to be tested for reading the running state parameter information. The present invention also provides an exemplary implementation manner, which may include the following content:

[0055] Based on the above embodiments, when the link training trigger condition is a cold reset or a warm reset, the operation data information of the link to be tested stored in the register of the device to be tested is read through the sideband signal; the recovery times and link parameter values are obtained from the private register of the device to be tested; the operation data information, recovery times and link parameter values are used as the operation status parameter information of the link to be tested. When the link training trigger condition is a hot reset, the operation data information of the link to be tested is read from the PCIe configuration space register of the device to be tested; a hardware information acquisition instruction is sent to the baseboard management controller to access the private register of the device to be tested by controlling the baseboard management controller; the operation data information, the recovery times stored in the private register and the link parameter values are used as the operation status parameter information of the link to be tested. To ensure the accurate diagnosis of the status of the test PCIe link, for a service module operating at the physical layer under a hot reset, such as a retimer, the baseboard management controller can be controlled by a preset access command to obtain the register of the target service module operating at the physical layer, so as to obtain the operation status parameter information of the link to be tested stored in the target service module. The preset access command can be a command that can access and control the BMC pre-set, and the in-band access out-of-band method is adopted to obtain the operation status parameter information of the service module.

[0056] In this embodiment, the link to be tested is a PCIe link. For a cold reset or a warm reset, an out-of-band method is adopted for data reading. A PCIe device register out-of-band acquisition tool can be pre-integrated to read the register of the device to be tested through the sideband signal, and basic information such as the current link bandwidth, rate, recoverable error, unrecoverable error, and the lane where the error code is located of the link to be tested is read from the register. If the device to be tested also includes a private register, correspondingly, the recovery times and link parameter values are also read from the private register, and the read basic information and private information are compared with the preset standard values or standard ranges to determine whether an error occurs. For a hot reset, an in-band method is adopted for data reading. An application program running on the operating system obtains the PCIe configuration space register of the device to be tested and reads basic information such as the current link bandwidth, rate, recoverable error, unrecoverable error, and the lane where the error code is located. If the device to be tested has a private register, the application program under the OS can access the BMC through the IP (Internet Protocol), and the hardware information acquisition instruction can be an IPMI command for example. Correspondingly, an IPMI command can be sent to the BMC through the IP to control the BMC to access the private register of the device to be tested and read the private information such as the recovery times and link parameters from it, and the read configuration space information and private information are compared with the preset values to determine whether an error occurs.

[0057] As can be seen from the above, in this embodiment, for each device connected to the link to be tested, data stored in multiple registers is read in a matching manner based on different reset methods, which is beneficial to improving the diagnostic accuracy and efficiency of the link.

[0058] The above embodiment does not make any limitation on how to perform the corresponding link training operation again based on the link training trigger condition. Based on the above embodiment, the present invention also provides an implementation method of the link training operation under different resets, which may include the following contents:

[0059] When the link training trigger condition is a cold reset, a power control signal is sent to the device to be tested to control the device to be tested to perform an operation of powering off first and then powering on; after the link to be tested is restored, the operation state parameter information of the link to be tested under the current link training operation is read again from the target register, and it is determined again whether there is a fault in the link to be tested according to the operation state parameter information, and the process is repeated continuously until a preset fault diagnosis stop condition is reached.

[0060] When the link training trigger condition is a warm reset, a reset operation signal is sent to the device to be tested to control the device to be tested to perform an operation of resetting first and then de - resetting; after the link to be tested is restored, the operation state parameter information of the link to be tested under the current link training operation is read again from the target register, and it is determined again whether there is a fault in the link to be tested according to the operation state parameter information, and the process is repeated continuously until a preset fault diagnosis stop condition is reached.

[0061] When the link training trigger condition is a hot reset, the target application program running under the operating system triggers the hot reset operation by setting the bridge control register of the link to be tested; after the link to be tested is restored, the operation state parameter information of the link to be tested under the current link training operation is read again from the target register, and it is determined again whether there is a fault in the link to be tested according to the operation state parameter information, and the process is repeated continuously until a preset fault diagnosis stop condition is reached.

[0062] In this embodiment, for cold reset, if the current diagnosis is normal and there is no error, the device under test is controlled to power off and then power on. After waiting for the link to recover, the operation status parameter information stored in the register of the device under test is obtained again, that is, steps S102 - S103 are repeatedly executed until a preset fault diagnosis stop condition is reached. The preset fault diagnosis stop condition can be, for example, that the number of test cycles reaches a preset number of cycles. For warm reset, if the current diagnosis is normal and there is no error, the device under test can be controlled to reset first and then de - reset. After waiting for the link to recover, the operation status parameter information stored in the register of the device under test is obtained again, that is, steps S102 - S103 are repeatedly executed until a preset fault diagnosis stop condition is reached. For hot reset, if the current diagnosis is normal and there is no error, the application program triggers the hot reset by setting the bridge control register of the device under test. After waiting for the PCIe link to recover, the operation status parameter information stored in the register of the device under test is obtained again, that is, steps S102 - S103 are repeatedly executed until a preset fault diagnosis stop condition is reached.

[0063] Exemplarily, the Bridge Control Register is a register used to control and manage the behavior of the PCI (Peripheral Component Interconnect) bridge. The hot reset can be achieved by first triggering the Bridge Control Register {Bit 6 of Bridge Control Register (Offset 0x3E)}. The hot reset can be triggered by the application program writing 1 to the Secondary Bus Reset bit in the bridge control register. Use the command setpci - s 00:01.1 3E.B = 40 to set the Secondary Bus Reset bit to 1, and then use the lspci command to check whether the modification in the bridge control register is successful. The hot reset is triggered by sending the TS1 ordered set, which is sent simultaneously on all valid lanes and lasts for at least 2 ms. The device under test performs a hot reset after receiving two consecutive TS1 ordered sets. After triggering the hot reset, as Figure 3 Steps ① and ②: The link state first enters the recovery state, then enters the hot reset state, and finally returns to the detection state and starts the link initialization training again. The de - reset is as Figure 3Steps ③④⑤⑥⑦⑧: Set the Secondary Bus Reset bit back to 0 through the application to exit the thermal reset state. Use the command setpci - s00:01.13E.B = 00 to clear the Secondary Bus Reset bit, thus ending the thermal reset. After the thermal reset is completed, the link state machine will return from the thermal reset state to the detection state, and the link will start initializing the training again. Use diagnostic tools such as the lspci command to poll and check the status of the device under test to ensure that the device has resumed normal operation and the link has been successfully re - initialized. If all the state machines, hardware logics, port states, and configuration registers of the device under test had specific configurations before the reset, it is necessary to ensure that these configurations are restored after the reset release so that the device under test can work as expected, ensuring the diagnostic accuracy and efficiency of the link, and thus improving the link test efficiency.

[0064] As can be seen from the above, in this embodiment, out - of - band diagnosis avoids the invalid time of BIOS startup and OS startup, saves link test time, and improves link verification efficiency. The in - band thermal reset diagnosis method avoids the dependence on dedicated tools for link training state machine testing and can be used in product testing and operation and maintenance scenarios. The whole process can be tested in multiple scenarios and multiple rounds, increasing the sample size, and ensuring the stability and consistency of the production of a large number of servers and computer systems.

[0065] The present invention also provides a corresponding device for the link test method, further making the method more practical. Among them, the device can be described from the perspective of functional modules and hardware respectively. The link test device provided by the present invention is introduced below. This device is used to implement the link test method provided by the present invention. In this embodiment, the link test device can include or be divided into one or more program modules. These one or more program modules are stored in a storage medium and executed by one or more processors to complete the link test method disclosed in Embodiment 1. The program modules referred to in this embodiment refer to a series of computer program instruction segments that can complete specific functions, and are more suitable for describing the execution process of the link test device in the storage medium than the program itself. The following description will specifically introduce the functions of each program module in this embodiment. The link test device described below can be correspondingly referred to the link test method described above.

[0066] From the perspective of functional modules, see Figure 4 , Figure 4 is the structural diagram of the link test device provided by this embodiment in a specific implementation manner. The device can include:

[0067] The device determination module 401 is used to determine the device under test according to the link under test and the link training trigger condition.

[0068] A status data reading module 402, configured to, after the link to be tested finishes the link training operation and the link is restored, determine a target register storing the operation status parameter information of the link to be tested in the device to be tested based on the link training trigger condition, and read the operation status parameter information.

[0069] A link testing module 403, configured to, when it is diagnosed according to the operation status parameter information that the link to be tested has no fault, execute the corresponding link training operation again based on the link training trigger condition.

[0070] Exemplarily, in some implementation manners of this embodiment, the above device determination module 401 may further be configured to: obtain a service module connected to the link to be tested and participating in the execution of user tasks; when the link training trigger condition is a cold reset or a warm reset, the device to be tested is each service module; when the link training trigger condition is a hot reset, the device to be tested is a service module that does not work at the physical layer.

[0071] As a schematic implementation manner of the above embodiment, the above status data reading module 402 may further be configured to: when the link training trigger condition is a hot reset, control the baseboard management controller through a preset access command to obtain the register of the target service module working at the physical layer, so as to obtain the operation status parameter information of the link to be tested stored in the target service module.

[0072] Exemplarily, in some other implementation manners of this embodiment, the above status data reading module 402 may further be configured to: when the link training trigger condition is a cold reset or a warm reset, read the operation data information of the link to be tested stored in the register of the device to be tested through a sideband signal; obtain the recovery times and the link parameter values from the private register of the device to be tested; use the operation data information, the recovery times and the link parameter values as the operation status parameter information of the link to be tested.

[0073] Exemplarily, in some other implementation manners of this embodiment, the above status data reading module 402 may further be configured to: when the link training trigger condition is a hot reset, read the operation data information of the link to be tested from the PCIe configuration space register of the device to be tested; send a hardware information acquisition instruction to the baseboard management controller to control the baseboard management controller to access the private register of the device to be tested; use the operation data information, the recovery times and the link parameter values stored in the private register as the operation status parameter information of the link to be tested.

[0074] Exemplarily, in some other implementation manners of this embodiment, the above device may further include a fault diagnosis module, configured to determine that the link to be tested has a fault by comparing the operation status parameter information with the predicted normal operation status parameters, then generate an error message, and store the log data corresponding to the current link training operation process as test log data.

[0075] Exemplarily, in some other embodiments of this embodiment, the above link test module 403 can also be used to: when the link training trigger condition is a cold reset, send a power control signal to the device under test to control the device under test to perform an operation of powering off first and then powering on; after the link under test is restored, read again the running state parameter information of the link under test under the current link training operation from the target register, and diagnose again whether the link under test has a fault according to the running state parameter information, and repeat continuously until a preset fault diagnosis stop condition is reached.

[0076] Exemplarily, in some other embodiments of this embodiment, the above link test module 403 can also be used to: when the link training trigger condition is a warm reset, send a reset operation signal to the device under test to control the device under test to perform an operation of resetting first and then de - resetting; after the link under test is restored, read again the running state parameter information of the link under test under the current link training operation from the target register, and diagnose again whether the link under test has a fault according to the running state parameter information, and repeat continuously until a preset fault diagnosis stop condition is reached.

[0077] Exemplarily, in some other embodiments of this embodiment, the above link test module 403 can also be used to: when the link training trigger condition is a hot reset, the target application program running under the operating system triggers the hot reset operation by setting the bridge control register of the device under test; after the link under test is restored, read again the running state parameter information of the link under test under the current link training operation from the target register, and diagnose again whether the link under test has a fault according to the running state parameter information, and repeat continuously until a preset fault diagnosis stop condition is reached.

[0078] The link test device mentioned above is described from the perspective of functional modules. Further, the present invention also provides an electronic device, which is described from the perspective of hardware. Figure 5 It is a schematic structural diagram of the electronic device provided in an embodiment of the present invention. As Figure 5 shown, the electronic device includes a memory 50 for storing a computer program; a processor 51 for implementing the steps of the link test method mentioned in any of the above embodiments when executing the computer program.

[0079] Among them, the processor 51 may include one or more processing cores, such as a 4-core processor or an 8-core processor. The processor 51 may also be a controller, a microcontroller, a microprocessor, or other data processing chips, etc. The processor 51 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 51 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 51 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 51 may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0080] The memory 50 may include one or more computer non-volatile storage media, which may be non-transitory. The memory 50 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. The memory 50 may be an internal storage unit of an electronic device in some embodiments, such as the hard disk of a server. The memory 50 may also be an external storage device of an electronic device in other embodiments, such as a plug-in hard disk equipped on a server, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory 50 may also include both an internal storage unit and an external storage device of an electronic device. The memory 50 can be used not only to store application software installed in the electronic device and various types of data, such as the code of the program during the execution of the link test method, etc., but also to temporarily store the data that has been output or will be output. In this embodiment, the memory 50 is at least used to store the following computer program 501, wherein, after the computer program is loaded and executed by the processor 51, it can implement the relevant steps of the link test method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 50 may also include an operating system 502 and data 503, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 502 may include Windows, Unix, Linux, etc. The data 503 may include, but is not limited to, data corresponding to the link test results, etc.

[0081] In some embodiments, the electronic device may further include a display screen 52, an input / output interface 53, a communication interface 54 or a network interface, a power supply 55 and a communication bus 56. The display screen 52 and the input / output interface 53, such as a keyboard, are user interfaces. Exemplary user interfaces may also include standard wired interfaces, wireless interfaces, and the like. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch screen, and the like. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visual user interface. The communication interface 54 may exemplarily include a wired interface and / or a wireless interface, such as a WI-FI interface, a Bluetooth interface, and the like, which are generally used to establish a communication connection between the electronic device and other electronic devices. The communication bus 56 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, and the like. The bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0082] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, for example, it may also include a sensor 57 to realize various functions.

[0083] It can be understood that if the link test method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the related technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes, but is not limited to: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, removable disk, CD-ROM, magnetic disk or optical disk, etc., various media that can store program codes. Based on this, the present invention also provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, it performs the steps of the link test method described in any one of the above embodiments.

[0084] It can be understood that if the link test method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, this computer software product may not need to be stored in a physical storage medium. For example, it can be directly transmitted to a computer or other devices with information processing capabilities through a wired network or a wireless network to execute all or part of the steps of the methods in the various embodiments of the present invention. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the related technology, or all or part of the technical solution, can be embodied in the form of a software product. Based on this, the present invention also provides a computer program product, which stores a computer program. When the computer program is executed by a processor, it performs the steps of the link test method described in any one of the above embodiments.

[0085] Finally, considering that the PCIe link establishment process of the server is relatively easy to reproduce PCIe hardware fault problems, in this embodiment, for three trigger scenarios of PCIe link establishment, cold reset, warm reset, and hot reset, the PCIe link test is completed through the out-of-band diagnosis method of the server's BMC and the in-band diagnosis method of the CPU, solving the problems of long time occupied by BIOS startup and OS startup in the whole system power-on and off cycle test and the whole system restart test, and the problem that the link training state machine test relies on special tools and cannot be popularized in production test and operation and maintenance scenarios. The present invention also provides a computing device, which at least includes a server, as Figure 6 shown, may include the following contents:

[0086] The server of the present invention at least includes a baseboard management controller 601, i.e., BMC 601, a central processing unit 602, i.e., CPU 602, a link training control processor 603, and a first PCIe device 604. The first PCIe device 604 is connected to the central processing unit 602 through a PCIe bus. As a service module for executing user tasks, the first PCIe device 604 is a PCIe device, such as a hard disk, a network card, a PCIe switch, a retimer, and a graphics processor. The server may include multiple PCIe devices. In this embodiment, the two PCIe devices, i.e., the first PCIe device 604 and the CPU, are taken as examples for introduction; the central processing unit 602 and the baseboard management controller 601 are in the same network segment so that application programs under the OS can remotely access the BMC through IP. The total link establishment time of the PCIe link is in the millisecond level, the BIOS startup and the OS loading are in the minute level, and redundant waiting time is avoided in out-of-band diagnosis. For the devices connected to the downstream ports of the PCIe switch, the firmware loading and link establishment are both very fast, and the waiting time is in the millisecond level, and the waiting time can be set according to the actual verification value; for the PCIe devices hung under the central processing unit, restricted by the BIOS startup and the PCIe initialization time points, the waiting time is in the second level, and it can be set according to the actual verification value.

[0087] In this embodiment, for cold reset and warm reset, the baseboard management controller 601 is used as the execution and control unit. The BMC 601 can be pre-integrated with a PCIe device register out-of-band acquisition tool. The baseboard management controller is connected to the first PCIe device and the central processing unit through sideband signals, and is used to determine the device under test according to the link to be tested and the first type of link training trigger condition. When the link to be tested completes the link training operation and the link is restored, the target register storing the running state parameter information of the link to be tested in the device under test is determined based on the first type of link training trigger condition, and the running state parameter information is read. When it is diagnosed that the link to be tested has no fault according to the running state parameter information, the corresponding link training operation is executed again based on the first type of link training trigger condition. The first type of link training trigger condition includes cold reset or warm reset. Correspondingly, the baseboard management controller is further used for: when the link training trigger condition is cold reset, the device under test is powered off and powered on by controlling the register of the link training control processor. For hot reset, the CPU 602 is used as the execution and control unit. When the first PCIe device 604 and the CPU 602 are normally started and the CPU 602 has completed the OS loading, the central processing unit is used to determine the device under test according to the link to be tested and the second type of link training trigger condition. When the link to be tested completes the link training operation and the link is restored, the target register storing the running state parameter information of the link to be tested in the device under test is determined based on the second type of link training trigger condition, and the running state parameter information is read. When it is diagnosed that the link to be tested has no fault according to the running state parameter information, the corresponding link training operation is executed again based on the second type of link training trigger condition. The second type of link training trigger condition includes hot reset. Correspondingly, the central processing unit is further used for when the link training trigger condition is warm reset, the device under test is reset and de-reset by controlling the register of the link training control processor.

[0088] Among them, the link training control processor 603 is connected to the baseboard management controller 601, and is used to control the power supply and reset of the server, and meet the timing requirements of the first PCIe device 604 and the central processing unit 602. The link training control processor 603 can be any device supporting programming control, such as CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array), which does not affect the implementation of the present invention.

[0089] As can be seen from the above, in this embodiment, corresponding link training is performed according to different trigger scenarios of PCIe link establishment of the server, and after the link is restored, PCIe link fault diagnosis of the server is performed based on the operation status parameter information read from the register, so as to implement the test of the stability and signal integrity of the PCIe link of the server. The total link establishment time of the PCIe link of the server is in the millisecond level. When the related technology performs link stability testing through power-on and power-off cycle testing and restart testing, the basic input / output system startup and operating system loading times are both in the minute level. Therefore, the redundant waiting time during the PCIe link testing process can be avoided, especially for test scenarios of low-probability hardware fault problems and problems that rely on long-cycle reproduction, greatly reducing the testing time, improving the efficiency of PCIe link stability verification, and effectively improving the efficiency of PCIe link testing. In addition, by performing PCIe link fault diagnosis based on the operation status parameter information read from the register after the link is restored, the problem that the link training state machine test depends on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is not only applicable to the laboratory stage, but also can be used in product testing and operation and maintenance scenarios, with better applicability.

[0090] In order to facilitate improving the link testing efficiency, based on the above embodiment, the computing device may further include a network switch and a monitoring end; the network switch is connected to the baseboard management controller through a network port to enable the monitoring end to remotely access the baseboard management controller; the monitoring end is used to obtain the error data and test log data of the link to be tested during the link training operation from the baseboard management controller.

[0091] To make it clearer for those skilled in the art about the technical solution of the present invention, the present invention takes the link to be tested as a PCIe link, the service module includes a central processing unit, a PCIe switch, a retimer, and a graphics processing unit, each service module is connected through a PCIe bus, the link training control processor 603 is a CPLD, and the monitoring end is a monitoring computer as an example to elaborate the link testing method, which may include the following content:

[0092] As Figure 7As shown, for scenarios where the link training trigger condition includes a cold reset or a warm reset, the baseboard management controller is connected to the central processing unit, PCIe switch, retimer, graphics processing unit, and CPLD through I2C (Inter-Integrated Circuit, integrated bus). The baseboard management controller integrates each PCIe device, that is, an out-of-band access tool for the registers of the central processing unit, PCIe switch, retimer, and graphics processing unit. Through this tool, the registers defined in the PCIe specifications of different PCIe devices and the private registers defined by different chip manufacturers can be obtained through preset commands. The BMC includes an RGMII (Reduced Gigabit Media Independent Interface) interface, through which it is connected to a network chip. The network chip is connected to a network switch through DMI (Direct Media Interface) and is connected to a monitoring computer through the network switch, so that it can be accessed by the monitoring computer through an IP connection. The CPLD is connected to the power supply line through a sideband signal for controlling the power supply of the whole machine and each PCIe device. The CPLD controls the platform reset signals of each service module through independent GPIO (General-PurpOSe Input / Output). For the sake of distinction, the reset signals of the central processing unit, PCIe switch, retimer, and graphics processing unit can be defined as PERST_N, PERST_SW_N, PERST_RT_N, and PERST_GPU_N in sequence. The baseboard management controller flexibly controls the platform reset signal and power supply of the PCIe device by accessing the programmable logic device register through I2C. As Figure 8As shown, the out-of-band diagnostic script can be pre-stored in the BMC. When the out-of-band diagnostic script is started, the PCIe device to be tested is determined according to the PCIe link to be tested. If diagnosing the link between the central processing unit and the PCIe switch, the PCIe devices to be tested are the central processing unit and the PCIe switch. If diagnosing the PCIe link between the PCIe switch and the graphics processing unit, the PCIe devices to be tested are the PCIe switch, the retimer, and the graphics processing unit. The BMC reads the registers of the PCIe device to be tested through the sideband signal, and reads basic information such as the bandwidth, rate, recoverable errors, unrecoverable errors, and the lane where the error code is located of the current link. It can also read the number of recovery times and link parameter values from the private registers of the PCIe device to be tested. The basic information and private information are compared with the preset predicted normal operating state parameters to determine whether the PCIe link to be tested has an error. For a cold reset, if the current PCIe link to be tested is normal and there is no error reported, the BMC controls the power-off and then power-on of the PCIe device to be tested by controlling the CPLD register through I2C, waits for the PCIe link to recover, and then obtains the registers of the PCIe device to be tested again, repeating the process until the preset number of cycles is reached. For a warm reset, if the PCIe link to be tested is normal and there is no error reported, the BMC controls the reset and then de-reset of the PCIe device to be tested by controlling the CPLD register through I2C, waits for the link to recover, and then obtains the registers of the PCIe device to be tested again, repeating the above process until the preset number of cycles is reached. If it is diagnosed that the current PCIe link to be tested has an error, the diagnosis is ended, the test log is saved, and the out-of-band diagnostic script is exited. The BMC can be remotely accessed through the monitoring computer to view the error message and export the test log.

[0093] As Figure 9 shown, for the scenario where the link training trigger condition includes a warm reset, the baseboard management controller is connected to the central processing unit, the PCIe switch, the retimer, and the graphics processing unit through I2C. The central processing unit is connected to the PCIe switch through the root complex and the PCIe bus. The downstream port of the PCIe switch is connected to the retimer through the PCIe bus. The retimer is connected to the graphics processing unit through the PCIe bus. The BMC is connected to the DMI interface of the physical layer and the communication lead RJ45 through the RGMII interface and is connected to the network switch, and is connected to the monitoring computer through the network switch, so that it can be accessed by the monitoring computer through an IP connection. The central processing unit is connected to the DMI interface of the network card through USB (Universal Serial Bus) and is connected to the network switch through the communication lead RJ45, so that the BMC and the CPU are in the same network segment. When each PCIe device, that is, the central processing unit, the PCIe switch, the retimer, and the graphics processing unit are normally started, after the BIOS starts the system and completes the OS loading, asFigure 10 As shown, the in-band diagnostic script can be pre-stored in the OS storage tape. Start the in-band diagnostic script, and determine the PCIe device to be tested according to the PCIe link to be tested. If diagnosing the link between the diagnostic central processing unit and the PCIe switch, the PCIe devices to be tested are the central processing unit and the PCIe switch. If diagnosing the PCIe link between the PCIe switch and the graphics processing unit, since the retimer works at the physical layer and has no configuration space and is invisible to the OS, the PCIe devices to be tested are the PCIe switch and the graphics processing unit. The application running on the operating system obtains the PCIe configuration space registers of the PCIe device to be tested, and reads basic information such as the bandwidth, rate, recoverable errors, unrecoverable errors, and the lane where the error code is located of the current link; it can also send IPMI commands to the BMC through the IP to control the BMC to access the private registers of the PCIe device to read the number of recovery times and the link parameter values. Compare the basic information and private information with the preset predicted normal operating state parameters to determine whether the PCIe link to be tested is in error. If the current PCIe link to be tested is normal and there is no error reporting, the application triggers a warm reset through the set bridge control register, waits for the PCIe link to recover, and then obtains the PCIe device configuration space registers again, repeating the execution until the preset number of cycles is reached. If it is diagnosed that the current PCIe link to be tested is in error, the diagnosis is ended, the test log is saved, and the in-band diagnostic script is exited; remotely access the BMC through the monitoring computer, view the error information, and export the test log.

[0094] As can be seen from the above, in this embodiment, the PCIe link diagnosis is completed through the out-of-band diagnostic script and the in-band diagnostic script, effectively avoiding the invalid time of BIOS startup and OS startup, and also avoiding the problem that the link training state machine test depends on special tools and cannot be popularized in product testing and operation and maintenance scenarios, effectively improving the link test efficiency.

[0095] The above has introduced in detail a link test method, an electronic device, a non-volatile storage medium, a computer program product, and a computing device provided by the present invention. Each embodiment in this specification is described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. Whether the units and algorithm steps of each example described in the disclosed embodiments are executed in the form of electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, and such implementation should not be considered to exceed the scope of the present invention. Without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A computing device, at least including a server, characterized in that, The server includes a baseboard management controller, a central processing unit, a link training control processor, and a first PCIe device; The first PCIe device is connected to the central processing unit through a PCIe bus and serves as a service module for executing user tasks; the central processing unit and the baseboard management controller are in the same network segment; Among them, the baseboard management controller is connected to the first PCIe device and the central processing unit through sideband signals, and is used to determine a to-be-tested PCIe device according to a to-be-tested PCIe link and a first type of link training trigger condition; when the to-be-tested PCIe link finishes the link training operation and the link is restored, determine a target register in the to-be-tested PCIe device that stores the operation status parameter information of the to-be-tested PCIe link based on the first type of link training trigger condition, and read the operation status parameter information; when it is diagnosed that the to-be-tested PCIe link has no fault according to the operation status parameter information, execute the corresponding link training operation again based on the first type of link training trigger condition; the first type of link training trigger condition includes a cold reset or a warm reset, and the baseboard management controller determines the to-be-tested PCIe device as each service module; The central processing unit is used to determine a to-be-tested PCIe device according to a to-be-tested PCIe link and a second type of link training trigger condition; when the to-be-tested PCIe link finishes the link training operation and the link is restored, determine a target register in the to-be-tested PCIe device that stores the operation status parameter information of the to-be-tested PCIe link based on the second type of link training trigger condition, and read the operation status parameter information; when it is diagnosed that the to-be-tested PCIe link has no fault according to the operation status parameter information, execute the corresponding link training operation again based on the second type of link training trigger condition; the second type of link training trigger condition includes a hot reset, and the central processing unit determines the to-be-tested PCIe device as a service module that does not work at the physical layer; The link training control processor is connected to the baseboard management controller and is used to control the power supply and reset of the server and meet the timing requirements of the first PCIe device and the central processing unit.

2. The computing device according to claim 1, wherein It further includes a network switch and a monitoring end; The network switch is connected to the baseboard management controller through a network port to enable the monitoring end to remotely access the baseboard management controller; The monitoring end is used to obtain error reporting data and test log data of the to-be-tested PCIe link during the link training operation from the baseboard management controller.

3. The computing device according to claim 1, wherein The baseboard management controller is further used to: when the first type of link training trigger condition is a cold reset, perform a power-off operation and a power-on operation on the to-be-tested PCIe device by controlling the register of the link training control processor; correspondingly, the central processing unit is further used to: when the first type of link training trigger condition is a warm reset, perform a reset operation and a de-reset operation on the to-be-tested PCIe device by controlling the register of the link training control processor.

4. A link testing method, characterized in that, Applied to a server including a baseboard management controller, a central processing unit, a link training control processor, and a first PCIe device, where the first PCIe device is connected to the central processing unit through a PCIe bus and serves as a service module for executing user tasks; the central processing unit and the baseboard management controller are in the same network segment, the baseboard management controller is connected to the first PCIe device and the central processing unit through sideband signals, and the link training control processor is connected to the baseboard management controller, including: Determine the PCIe device to be tested according to the PCIe link to be tested and the first type of link training trigger condition; when the PCIe link to be tested finishes the link training operation and the link resumes, determine the target register storing the operation status parameter information of the PCIe link to be tested in the PCIe device to be tested based on the first type of link training trigger condition, and read the operation status parameter information; when it is diagnosed that the PCIe link to be tested has no fault according to the operation status parameter information, execute the corresponding link training operation again based on the first type of link training trigger condition; the first type of link training trigger condition includes a cold reset or a warm reset, and the PCIe device to be tested is each service module; Determine the PCIe device to be tested according to the PCIe link to be tested and the second type of link training trigger condition; when the PCIe link to be tested finishes the link training operation and the link resumes, determine the target register storing the operation status parameter information of the PCIe link to be tested in the PCIe device to be tested based on the second type of link training trigger condition, and read the operation status parameter information; when it is diagnosed that the PCIe link to be tested has no fault according to the operation status parameter information, execute the corresponding link training operation again based on the second type of link training trigger condition; the second type of link training trigger condition includes a hot reset, and the PCIe device to be tested is a service module that does not work at the physical layer; Control the power supply and reset of the server and meet the timing requirements of the first PCIe device and the central processing unit.

5. The link test method according to claim 4, wherein Determine the target register storing the operation status parameter information of the PCIe link to be tested in the PCIe device to be tested based on the second type of link training trigger condition, and read the operation status parameter information, including: When the second type of link training trigger condition is a hot reset, control the baseboard management controller to obtain the register of the target service module working at the physical layer through a preset access command to obtain the operation status parameter information of the PCIe link to be tested stored in the target service module.

6. The link test method according to claim 4, characterized in that Determine the target register storing the operation status parameter information of the PCIe link to be tested in the PCIe device to be tested based on the first type of link training trigger condition, and read the operation status parameter information, including: When the first type of link training trigger condition is a cold reset or a warm reset, read the operation data information of the PCIe link to be tested stored in the register of the PCIe device to be tested through sideband signals; Obtain the number of recoveries and link parameter values from the private registers of the PCIe device to be tested; Use the operation data information, the number of recoveries, and the link parameter values as the operation status parameter information of the PCIe link to be tested.

7. The link test method according to claim 4, characterized in that Based on the second type of link training trigger condition, determine the target register in the PCIe device to be tested that stores the operation status parameter information of the PCIe link to be tested, and read the operation status parameter information, including: When the second type of link training trigger condition is a warm reset, read the operation data information of the PCIe link to be tested from the PCIe configuration space register of the PCIe device to be tested; Send a hardware information acquisition instruction to the baseboard management controller to control the baseboard management controller to access the private registers of the PCIe device to be tested; Use the operation data information, the number of recoveries stored in the private register, and the link parameter values as the operation status parameter information of the PCIe link to be tested.

8. The link test method according to claim 4, wherein It further includes: If it is determined that the PCIe link to be tested has a fault by comparing the operation status parameter information with the predicted normal operation status parameters, generate an error message and store the log data corresponding to the current link training operation process as test log data.

9. The link test method according to any one of claims 4 to 8, characterized in that Based on the first type of link training trigger condition, perform the corresponding link training operation again, including: When the first type of link training trigger condition is a cold reset, send a power control signal to the PCIe device to be tested to control the PCIe device to be tested to perform an operation of powering off and then powering on; After the PCIe link to be tested recovers, read the operation status parameter information of the PCIe link to be tested under the current link training operation from the target register again, and diagnose whether the PCIe link to be tested has a fault again according to the operation status parameter information, and repeat continuously until a preset fault diagnosis stop condition is reached.

10. The link test method according to any one of claims 4 to 8, characterized in that, Based on the first type of link training trigger condition, perform the corresponding link training operation again, including: When the first type of link training trigger condition is a warm reset, send a reset operation signal to the PCIe device to be tested to control the PCIe device to be tested to perform an operation of resetting and then de - resetting; After the PCIe link to be tested recovers, read the operation status parameter information of the PCIe link to be tested under the current link training operation from the target register again, and diagnose whether the PCIe link to be tested has a fault again according to the operation status parameter information, and repeat continuously until a preset fault diagnosis stop condition is reached.

11. The link test method according to any one of claims 4 to 8, characterized in that Based on the second type of link training trigger condition, perform the corresponding link training operation again, including: When the second type of link training trigger condition is a warm reset, the target application running under the operating system triggers a warm reset operation by setting the bridge control register of the PCIe device to be tested; After the PCIe link to be tested is restored, the operating state parameter information of the PCIe link to be tested under the current link training operation is read again from the target register, and the PCIe link to be tested is diagnosed for faults again according to the operating state parameter information, and the process is continuously repeated until a preset fault diagnosis stop condition is reached.

12. An electronic device, characterized in that, It includes a processor and a memory. When the processor executes the computer program stored in the memory, it implements the steps of the link test method according to any one of claims 4 to 11.

13. A non-volatile storage medium, characterized in that, A computer program is stored on the non-volatile storage medium. When the computer program is executed by a processor, it implements the steps of the link test method according to any one of claims 4 to 11.

14. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, it implements the steps of the link test method according to any one of claims 4 to 11.

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