Interrupt control device and method, storage medium, and electronic device

Abstract

The invention discloses an interrupt control device and method, a computer readable storage medium and an electronic device. The interrupt control device includes a first circuit, at least one routing register, a data conversion circuit, and a second circuit. The first circuit is configured to receive interrupt information, and the interrupt information comprises an interrupt target; the at least one routing register is configured to record and configure interrupt routing information corresponding to an interrupt target; the data conversion circuit is configured to convert the interrupt information into interrupt data, and the interrupt data carries interrupt routing information corresponding to an interrupt target; the second circuit is configured to provide interrupt data over the bus to at least one target device. The interrupt control device can improve the reliability, flexibility and efficiency of interrupt processing.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an interrupt control device and interrupt control method, a computer-readable storage medium, and an electronic device. Background Art

[0002] Ordinary interrupt handling architectures are usually used in processors, and there is a lack of advanced interrupt architecture design solutions that can better meet multi-core requirements. In addition, ordinary interrupt handling architectures may not be conducive to the physical layout and wiring of multi-core chips. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an interrupt control device, which includes: a first circuit configured to receive interrupt information, wherein the interrupt information includes an interrupt target; at least one routing register configured to record and configure interrupt routing information corresponding to the interrupt target; a data conversion circuit configured to convert the interrupt information into interrupt data, wherein the interrupt data carries the interrupt routing information corresponding to the interrupt target; and a second circuit configured to provide the interrupt data to at least one target device via a bus.

[0004] For example, in an interrupt control device provided in an embodiment of the present disclosure, it also includes: a cache circuit configured to store the interrupt information.

[0005] For example, in an interrupt control device provided in an embodiment of the present disclosure, the cache circuit includes: a cache threshold register and a cache sub-circuit; wherein the cache threshold register is configured to set a capacity upper limit for the interrupt information in the cache circuit, and in response to the interrupt information stored in the cache circuit reaching the capacity upper limit, back pressure the interrupt information; the cache sub-circuit is configured to store the interrupt information.

[0006] For example, in the interrupt control device provided in an embodiment of the present disclosure, the data conversion circuit is further configured to search for interrupt routing information corresponding to the interrupt target through the at least one routing register, and convert the interrupt information into the interrupt data.

[0007] For example, in the interrupt control device provided in an embodiment of the present disclosure, the interrupt routing information includes routing information within the chip where the interrupt control device is located or includes routing information across chips.

[0008] For example, in the interrupt control device provided in an embodiment of the present disclosure, the at least one routing register includes a first routing register and a second routing register; wherein the first routing register is configured to configure first routing information, wherein the first routing information includes routing information within the chip where the interrupt control device is located; and the second routing register is configured to configure second routing information, wherein the second routing information includes the cross-chip routing information.

[0009] For example, in an interrupt control device provided in an embodiment of the present disclosure, the interrupt information includes data information carried by multiple interrupt requests respectively issued by multiple target interrupt sources; the first routing register is further configured to search for the first routing information according to the interrupt information, and provide the first routing information to the data conversion circuit; the data conversion circuit is further configured to determine the interrupt data according to the first routing information and the data information.

[0010] For example, in the interrupt control device provided in one embodiment of the present disclosure, the interrupt information includes data information carried by multiple interrupt requests respectively issued by multiple target interrupt sources; the second routing register is further configured to search for the second routing information according to the interrupt information, and provide the second routing information to the data conversion circuit; the data conversion circuit is further configured to determine the interrupt data according to the second routing information and the data information.

[0011] For example, in the interrupt control device provided in one embodiment of the present disclosure, the interrupt information includes data information and interrupt target address information carried by multiple interrupt requests respectively issued by multiple target interrupt sources, wherein the interrupt target address information includes identification information of the chip where the interrupt control device is located, cross-chip chip identification information or processor identification information, and the data information includes identification information of the chip where the interrupt control device is located, the cross-chip chip or the interrupt processing module in the processor.

[0012] At least one embodiment of the present disclosure provides an interrupt control method, which includes: receiving interrupt information, wherein the interrupt information includes an interrupt target; recording and configuring interrupt routing information corresponding to the interrupt target; converting the interrupt information into interrupt data, wherein the interrupt data carries the interrupt routing information corresponding to the interrupt target; and providing the interrupt data to at least one target device via a bus.

[0013] At least one embodiment of the present disclosure provides an interrupt control device, which includes: a processing unit and a storage medium, wherein the storage medium stores at least one computer program, and when the at least one computer program is executed by the processing unit, the interrupt control method provided by any embodiment of the present disclosure is implemented.

[0014] At least one embodiment of the present disclosure provides an electronic device, wherein the electronic device includes the interrupt control device provided by any embodiment of the present disclosure.

[0015] For example, in an electronic device provided in an embodiment of the present disclosure, an interrupt controller and the bus are also included, wherein the interrupt controller is configured to send the interrupt information.

[0016] At least one embodiment of the present disclosure provides a non-volatile computer-readable storage medium for non-temporarily storing computer-readable instructions, and when the computer-readable instructions are executed by a computer, the interrupt control method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0018] Figure 1 A schematic block diagram of an interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 2 A schematic block diagram of another interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0020] Figure 3 An example diagram of an application of an interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0021] Figure 4 A flowchart of an interrupt control method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 5 A schematic block diagram of another interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 6 A schematic block diagram showing an electronic device provided by at least one embodiment of the present disclosure; and

[0024] Figure 7 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0027] With the continuous development and improvement of the RISC-V (Reduced Instruction Set Computer-V) ecosystem, processor cores, SoC (System on Chip) and other chip products designed and produced using the RISC-V architecture have gradually been put into use in various fields, promoting the innovation and development of the entire industry. In particular, in recent years, with the rapid development of artificial intelligence technology, the computing power requirements for chips have become increasingly higher. Therefore, the demand for multi-core SoC chips based on RISC-V is also gradually increasing.

[0028] Multi-core SoC chips can better meet the computing needs of increasingly complex application scenarios, thereby achieving higher performance, lower power consumption, and better processor core collaboration capabilities. Interrupts enable the processor to promptly process requests from a variety of external devices or electronic devices, effectively manage the allocation and access of resources such as memory and buses, so that electronic equipment systems can quickly respond to important events and abnormal situations.

[0029] On the other hand, in a multi-core SoC chip, different cores need to communicate and collaborate with each other, and there are many peripherals and devices that need to communicate with the processor core. This requires an effective interrupt control device to manage and distribute interrupt signals from various external devices or other cores, so that the interrupt signals can be correctly transmitted to the corresponding processor core, and the processing system can respond to external events in a timely manner, thereby improving the stability and reliability of the processing system.

[0030] The inventors of the present disclosure have noticed that in large-scale system-level SoC chips, with the continuous increase of multimedia, communication, storage and other functions, the number of modules on the SOC chip has increased dramatically, and the monolithic and huge SoC is gradually shifting towards deconstruction or modularization. This shift has put forward higher requirements on the interrupt control device. For example, it is necessary not only to process the interrupt signals within the SoC chip itself, but also to process the interrupt request signals sent from multiple chips outside the device.

[0031] However, most of the current interrupt control devices can only realize the interrupt transmission of the SoC chip itself through hard wiring. In a multi-core SoC chip system, due to the large number and variety of peripherals, the method of directly connecting the interrupt source to each processor has been difficult to meet the interrupt processing needs of the system. This method requires a large number of hard wiring, which not only increases the complexity of layout and wiring, but also occupies a large amount of chip area. In addition, the hard-wired interrupt solution cannot realize interrupt transmission between chips, which limits the flexibility and scalability of the system.

[0032] In addition, the interrupt control device can adopt a separate control and routing method when processing message interrupts generated by peripherals or software interrupts generated within the system. For example, the message interrupt generated by the peripheral needs to be configured by the interrupt conversion service module, and then written into the register corresponding to the corresponding redistributor module (for example, a module that further processes and distributes the interrupt), and sent to the processor interface module after being processed by the redistributor module; and the software interrupt generated by the processor needs to be sent by each processor to the corresponding processor interface module, and then enter the redistribution processor module after processing, and then sent to the distributor module, and sent to the corresponding redistributor module after processing, and finally sent to the corresponding processor interface module for processing. The entire routing process needs to distinguish between message interrupts generated by peripherals and software interrupts generated by processors, and the routing method of software interrupts is relatively cumbersome, which increases the processing time of interrupts and reduces routing efficiency.

[0033] The inventors of the present disclosure also noticed that when there are a large number of processors and peripherals in the system, the transmission and layout of a large number of linear interrupts will occupy a large chip area; and when interrupt transmission is required between multiple chips, most existing interrupt controllers cannot complete the distribution and routing of interrupts between chips; in addition, the interrupt control device controls and routes peripheral interrupts and software interrupts separately, and the routing method of software interrupts is cumbersome. Therefore, for the interrupt control device, it is necessary to pay more attention to the improvement of flexibility, scalability, efficiency and standardization to meet the interrupt processing needs under the trend of large multi-core SoC chips and modular design.

[0034] At least one embodiment of the present disclosure provides an interrupt control device and an interrupt control method, a computer-readable storage medium, and an electronic device. The interrupt control device includes: a first circuit, at least one routing register, a data conversion circuit, and a second circuit. The first circuit is configured to receive interrupt information, wherein the interrupt information includes an interrupt target; at least one routing register is configured to record and configure interrupt routing information corresponding to the interrupt target; the data conversion circuit is configured to convert the interrupt information into interrupt data, wherein the interrupt data carries the interrupt routing information corresponding to the interrupt target; the second circuit is configured to provide the interrupt data to at least one target device through a bus. The interrupt control device can improve the reliability, flexibility, and efficiency of interrupt processing.

[0035] Figure 1 A schematic block diagram of an interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0036] like Figure 1 As shown, the interrupt control device 100 includes a first circuit 110 , at least one routing register 120 , a data conversion circuit 130 and a second circuit 140 .

[0037] The first circuit 110 is configured to receive interrupt information.

[0038] At least one routing register 120 is configured to record and configure interrupt routing information corresponding to an interrupt target.

[0039] The data conversion circuit 130 is configured to convert the interrupt information into interrupt data.

[0040] The second circuit 140 is configured to provide the interrupt data to at least one target device through the bus.

[0041] For example, the first circuit 110 may include a front-end interface module of the interrupt control device 100 , and the front-end interface module may be configured to receive interrupt information.

[0042] For example, the interrupt information may include an interrupt target, bus write address channel information, bus write data channel information, or bus write response channel information, etc., which is not limited in the embodiments of the present disclosure. Here, "interrupt target" may refer to, for example, identification information of a target processor carried by the interrupt information that should respond to the interrupt request and execute the corresponding interrupt handler.

[0043] For example, the interrupt information may further include data information and interrupt target address information carried by multiple interrupt requests respectively issued by multiple target interrupt sources.

[0044] For example, the interrupt target address information may include identification information of the chip where the interrupt control device is located (also referred to as "this chip") (for example, the ID of this chip), chip identification information across chips (for example, chip ID across chips), or identification information of the processor (ie, the interrupt target) (for example, the processor ID).

[0045] For example, each chip or processor may include multiple CPUs, and the chip ID, cross-chip chip ID, and processor ID included in the interrupt target address information may further indicate the CPU ID in each chip or processor.

[0046] For example, the data information may include identification information of an interrupt processing module in a chip where the interrupt control device is located, a chip across chips, or a processor.

[0047] For example, the interrupt processing module in each chip or processor included in the data information may include the module for processing interrupts in the CPU inside each chip or processor. For example, the data information may include identification information (i.e., interrupt number) of the interrupt processing module in each chip or processor.

[0048] It should be noted that in the embodiments of the present disclosure, "cross-chip" refers to different chips within a multi-chip system (e.g., a module or device comprising multiple chips). For example, interrupt requests or interrupt information can be transmitted and processed between different chips in the system according to actual needs.

[0049] Here, "processor" may include a processor in the chip itself, or a processor across chips. For example, a multi-chip system includes multiple independent chips, each of which may include at least one processor and a corresponding interrupt source. For example, when an interrupt source on a chip generates an interrupt, if the interrupt needs to be processed by a processor on another chip in the system, then the interrupt request needs to be passed to the target chip through a cross-chip interrupt routing.

[0050] For example, the interrupt information may include interrupt information sent by an interrupt controller in the form of a message interrupt, and may also include a software interrupt sent by a processor, etc., which is not limited in the embodiments of the present disclosure.

[0051] In a possible implementation, for example, the first circuit 110 may be configured to receive interrupt information generated from an interrupt controller, and the interrupt controller may be coupled to the interrupt control device 100 via a bus, for example.

[0052] For example, the interrupt controller may receive multiple interrupt requests from multiple target interrupt sources, determine a target interrupt request from the multiple interrupt requests, and output interrupt information according to the target interrupt request.

[0053] For example, the interrupt controller may convert the parameter information of the interrupt source corresponding to the target interrupt request into the interrupt information. Here, the parameter information may include, for example, address encoding information, interrupt priority information, interrupt source encoding information or processor quantity information, etc., which is not limited in the embodiments of the present disclosure.

[0054] In another possible implementation, for example, the first circuit 110 may be configured to receive interrupt information issued by a processor, where the interrupt information may include a software interrupt issued by the processor.

[0055] For example, the routing register 120 may be programmed, and the corresponding interrupt routing information may be configured according to actual needs. For example, the configuration of the routing register 120 may include the configuration of interrupt routing information such as the address of the interrupt target and the entry address of the interrupt processing program.

[0056] For example, when the first circuit 110 receives interrupt information, the interrupt control device 100 can search for corresponding interrupt routing information in the routing register 120 based on the interrupt information (for example, the interrupt source identification information carried by the interrupt information or the identification information of the target processor corresponding to the interrupt target, etc.).

[0057] For example, the method of searching for the interrupt routing information may include a hash table search, a linear search, or a corresponding mapping algorithm search, etc., which is not limited in the embodiments of the present disclosure.

[0058] For example, the data conversion circuit 130 may be configured to convert the interrupt information received by the first circuit 110 into interrupt data suitable for transmission through the bus. The conversion process of the interrupt information may include, for example, a data format conversion operation, a data encapsulation operation, or a corresponding encoding operation, etc., which is not limited in the embodiments of the present disclosure.

[0059] For example, for data encapsulation operations, the data conversion circuit 130 can be configured to encapsulate the information carried in the interrupt information (such as interrupt target information, interrupt type information, interrupt routing information corresponding to the interrupt target, or interrupt priority information, etc.) into an interrupt data packet according to a predetermined format.

[0060] For example, for the format conversion operation, the data conversion circuit 130 may be configured to convert the interrupt information into a data format suitable for bus transmission according to the transmission requirements of the bus. The embodiments of the present disclosure do not limit the specific form of the data format conversion.

[0061] For example, in a system with high security requirements, the data conversion circuit 130 may be further configured to encode or encrypt the interrupt data to improve the security of data transmission.

[0062] For example, the second circuit 140 may include an output interface module, which may be configured to transmit the interrupt data to at least one target device via a bus. Here, the target device may include, for example, a processor or a processing unit as a target, and the embodiments of the present disclosure are not limited thereto.

[0063] For example, the output interface module included in the second circuit 140 may be further configured to couple with a bus (such as PCI, PCIe, AXI, etc.) The second circuit 140 may support specific bus protocols and timing requirements so that the interrupt data can be correctly transmitted to the target device.

[0064] In at least one embodiment of the present disclosure, various circuits and components in the interrupt control device 100 work together to realize the reception, routing, conversion and transmission functions of interrupt information. The design and optimization of these circuits and components help to improve the performance, reliability and flexibility of the interrupt processing device 100.

[0065] Figure 2 A schematic block diagram of another interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0066] like Figure 2 As shown, in some embodiments of the present disclosure, the interrupt control device 100 further includes a cache circuit 150. The cache circuit 150 may be configured to store received interrupt information. For example, the cache circuit 150 may further include a cache threshold register 151 and at least one cache sub-circuit 152.

[0067] For example, the cache threshold register 151 may be configured to set an upper capacity limit of the cache circuit or certain specific operation trigger points.

[0068] For example, when the amount of data stored in the cache circuit reaches or exceeds the set cache threshold, a corresponding signal can be triggered to notify the interrupt control device 100 or the target device to take corresponding measures, such as speeding up the processing of interrupts, discarding low-priority interrupt requests, or issuing warnings, etc. By adjusting the cache threshold, the interrupt processing performance can be optimized and the response speed and resource usage can be balanced.

[0069] For example, in response to the amount of data stored in the cache circuit reaching or exceeding a set cache threshold (e.g., 10 interrupt control information), the cache threshold register 151 can be configured to back-pressure the interrupt information, that is, the cache threshold register 151 can be configured to stop receiving new interrupt information, or take other measures to slow down the speed of receiving interrupt information to prevent cache overflow.

[0070] For example, the cache subcircuit 152 may be configured to store interrupt information received from the first circuit 110. For example, when the first circuit 110 receives interrupt information, the received interrupt information may be sent to the cache circuit 150 for storage, and the cache circuit 110 may determine whether to accept and store new interrupt information according to the current storage situation and the cache threshold, or take other measures (such as discarding old information, issuing a warning, etc.), etc., and the embodiments of the present disclosure are not limited to this.

[0071] For example, the data conversion circuit 130 may read the interrupt information from the cache circuit 150 , convert the interrupt information into interrupt data, and then send it to the second circuit 140 for further processing.

[0072] In at least one embodiment of the present disclosure, interrupt information is stored in the cache circuit 150, so that interrupt loss or system instability caused by processing delays can be reduced, and the cache threshold is set by the cache threshold register 151, so that flexible adjustment and optimization of interrupt processing performance can be achieved, so that interrupt information can be effectively stored and managed, and the stability and performance of the interrupt control device 100 can be further improved.

[0073] In some embodiments of the present disclosure, the data conversion circuit 130 is further configured to search for interrupt routing information corresponding to the interrupt target through at least one routing register 120 and convert the interrupt information into interrupt data.

[0074] For example, the data conversion circuit 130 may be configured to access at least one routing register 120 after receiving the interrupt information to obtain interrupt routing information corresponding to the interrupt target.

[0075] For example, the mapping relationship between the corresponding interrupt target and the interrupt routing information, i.e., the interrupt routing path, may be stored in the routing register 120. For example, these interrupt routing paths may be routing paths inside the chip where the interrupt control device 100 is located, or routing paths across multiple chips (for example, multiple chips inside and outside the interrupt control device 100 may be connected via inter-chip communication links).

[0076] For example, the data conversion circuit 130 may be configured to search for corresponding interrupt routing information in the routing register 120 according to the interrupt target in the interrupt information.

[0077] For example, the interrupt routing information includes routing information within the chip where the interrupt control device 100 is located or includes routing information across chips.

[0078] Here, the routing information within the chip may include the interrupt routing path within the chip where the interrupt control device 100 is located. For example, on a single chip, multiple processing units, peripheral modules or functional blocks may be integrated, and they need to communicate and coordinate through interrupts; thus, the routing information within the chip can be used to describe the interrupt transmission path between the internal units and components of these single chips. For example, the routing information within the chip may include the source address, the destination address, the interrupt vector number, the priority, etc., and the embodiments of the present disclosure are not limited to this. Here, the cross-chip routing information may, for example, refer to the transmission path required for the interrupt request to be transmitted from one chip to another chip in a multi-chip environment.

[0079] For example, after the data conversion circuit 130 finds the interrupt routing information corresponding to the interrupt target, the data conversion circuit 130 can convert the interrupt information into the interrupt data and integrate the interrupt routing information into the interrupt data. For the method of converting the interrupt information into the interrupt data by the data conversion circuit 130, for example, reference can be made to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0080] Here, the data conversion circuit 130 converts the interrupt information into interrupt data containing the corresponding interrupt routing information by searching the interrupt routing information in at least one routing register 120, so that the interrupt request can be correctly transmitted and processed within the chip or in a cross-chip environment.

[0081] like Figure 2 As shown, in some embodiments of the present disclosure, the at least one routing register 120 includes at least one first routing register 121 and at least one second routing register 122 .

[0082] For example, the first routing register 121 may be configured to configure first routing information. The first routing information may include routing information within a chip where the interrupt control device 100 is located.

[0083] For example, the first routing information may be used to indicate routing paths between components and processing units inside the chip where the interrupt control device 100 is located.

[0084] For example, by configuring the first routing register 121, the interrupt control device 100 can transmit the interrupt request along the corresponding path (i.e., the first routing information) inside the chip where the interrupt control device 100 is located, thereby achieving effective collaboration between the various units and components inside the chip where the interrupt control device 100 is located.

[0085] For example, the second routing register 122 may be configured to configure second routing information. The second routing information may include cross-chip routing information. For example, the second routing information may be used to indicate a routing path required for an interrupt request to be transmitted from one chip to another chip.

[0086] For example, by configuring the second routing register 122, the interrupt control device 100 can implement cross-chip interrupt transmission, so that the interrupt request can span multiple chips and be transmitted between the multiple chips according to the corresponding path (ie, the second routing information).

[0087] In some embodiments of the present disclosure, the interrupt information may further include data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0088] The first routing register 121 may be further configured to search for first routing information according to the interrupt information, and provide the first routing information to the data conversion circuit 130 .

[0089] The data conversion circuit 130 may be further configured to determine the interrupt data according to the first routing information and the data information.

[0090] For example, multiple target interrupt sources may include various units and functional modules inside the chip where the interrupt control device 100 is located, such as a processor, a peripheral interface, a timer, etc. For example, multiple target interrupt sources can generate corresponding interrupt requests according to their own operating status and needs.

[0091] For example, the interrupt information may come from an interrupt controller or a software interrupt issued by a processor, and the embodiments of the present disclosure are not limited to this. The interrupt information includes data information carried by the target interrupt request.

[0092] For example, the first routing register 121 stores first routing information related to the internal routing of the chip where the interrupt control device 100 is located; after the first circuit 110 receives the interrupt information, the first circuit 110 can pass the received interrupt information to the first routing register 121; the first routing register 121 can retrieve the corresponding first routing information from the lookup table or data structure in the first routing register 121 according to the relevant identifier (such as the interrupt target, etc.) carried in the interrupt information; thereafter, the first routing register 121 can provide the first routing information to the data conversion circuit 130 to generate corresponding interrupt data, which carries the interrupt routing information corresponding to the interrupt target (i.e., the first routing information).

[0093] For example, the data conversion circuit 130 may be configured to determine interrupt data according to the first routing information and the data information corresponding to the target interrupt request included in the interrupt information, where the interrupt data carries the first routing information and the data information corresponding to the target interrupt request.

[0094] For example, the specific method by which the data conversion circuit 130 determines the interrupt data according to the first routing information and the data information may also refer to the related description of the data conversion circuit 130 converting the interrupt information into interrupt data in the aforementioned embodiment, which will not be repeated here.

[0095] In at least one embodiment of the present disclosure, through the first routing register 121 and the data conversion circuit 130, the interrupt information can be converted into interrupt data carrying the first routing information and the data information corresponding to the target interrupt request. This process enables the interrupt request to be efficiently and accurately transmitted inside the chip where the interrupt control device 100 is located, thereby improving the response speed and reliability of the interrupt control device to the interrupt request.

[0096] In some embodiments of the present disclosure, the interrupt information may further include data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0097] The second routing register 122 may be further configured to search for second routing information according to the interrupt information, and provide the second routing information to the data conversion circuit.

[0098] The data conversion circuit may be further configured to determine the interrupt data according to the second routing information and the data information.

[0099] For example, the multiple target interrupt sources may also include multiple cross-chip interrupt sources. For example, the multiple target interrupt sources (ie, multiple different chips or modules) may generate corresponding interrupt requests according to their own operating states and requirements.

[0100] For example, the interrupt information may come from an interrupt controller or a software interrupt issued by a processor, and the embodiments of the present disclosure are not limited to this. The interrupt information includes data information carried by the target interrupt request.

[0101] For example, the second routing register 122 may be configured to store and configure second routing information, where the second routing information may be used to represent cross-chip routing information.

[0102] For example, after the first circuit 110 receives the interrupt information, if the interrupt target is located in a different chip, the data conversion circuit 130 may search for the interrupt routing information (ie, the second routing information) corresponding to the interrupt target through the second routing register 122 .

[0103] For example, the specific method for the second routing register 122 to search for the second routing information corresponding to the interrupt target can also refer to the relevant description of the routing register 120 or the first routing register 121 recording and configuring the interrupt routing information corresponding to the interrupt target in the aforementioned embodiment, which will not be repeated here.

[0104] For example, the specific method for the data conversion circuit 130 to determine the interrupt data according to the second routing information and the data information may also refer to the description of the data conversion circuit 130 converting the interrupt information into the interrupt data in the foregoing embodiment, which will not be repeated here.

[0105] In at least one embodiment of the present disclosure, when the interrupt control device 100 processes a cross-chip interrupt request, interrupt information is generated by multiple cross-chip interrupt sources, and then through the second routing register 122 and the data conversion circuit, the interrupt information can be converted into interrupt data carrying the second routing information and data information corresponding to the target interrupt request, so that the interrupt request can be efficiently and accurately transmitted between different chips, thereby improving the response speed and reliability of the interrupt control device to cross-chip interrupt requests.

[0106] For example, the first circuit 110, routing register 120, first routing register 121, second routing register 122, data conversion circuit 130, second circuit 140, cache circuit 150, cache threshold register 151 and cache sub-circuit 152 involved in the above embodiments can be hardware, software, firmware and any feasible combination thereof. For example, the first circuit 110, routing register 120, first routing register 121, second routing register 122, data conversion circuit 130, second circuit 140, cache circuit 150, cache threshold register 151 and cache sub-circuit 152 can be dedicated or general circuits, chips or devices, etc., or can be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation form of each of the above units.

[0107] It should be noted that, in the embodiment of the present disclosure, each module of the interrupt control device 100 may correspond to each step of the interrupt control method (described below). Figure 1 to Figure 2 The components and structures of the interrupt control device 100 shown are merely exemplary and non-limiting. The interrupt control device 100 may further include other components and structures as required.

[0108] Figure 3 A diagram showing an application example of an interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0109] The interrupt control device 200 is taken as an example below to exemplarily describe the interrupt control device involved in the embodiment of the present disclosure.

[0110] In some embodiments of the present disclosure, Figure 3 As shown, the interrupt control device 200 may include a data conversion circuit 230, a routing register 220, and a cache circuit 250. The interrupt control device 200 may be coupled to one or more processors 270 via a bus 260.

[0111] For example, the interrupt control device 200 may receive interrupt information and store the received interrupt information in the cache circuit 150 .

[0112] For example, the interrupt information may include interrupt information generated by an interrupt controller (not shown in the figure), and the interrupt controller provides the interrupt information to the interrupt control device 200 through a bus. The method for the interrupt controller to generate interrupt information, for example, can refer to the relevant description of the aforementioned embodiment, which will not be repeated here. For another example, the interrupt information may also include a software interrupt generated by a processor, and the embodiments of the present disclosure do not limit the source of the interrupt information.

[0113] For example, the interrupt control device 200 may include one or more routing registers 220 .

[0114] For example, the routing register 220 may be configured to record and configure interrupt routing information corresponding to an interrupt target.

[0115] For example, the routing register 220 may be further configured to configure interrupt routing information corresponding to the interrupt target according to the received routing register configuration information.

[0116] For example, the data conversion circuit 230 may be configured to convert the interrupt information into interrupt data.

[0117] For example, the data conversion circuit 230 may be further configured to search for interrupt routing information corresponding to the interrupt target through one or more routing registers 220 , and convert the interrupt information into interrupt data.

[0118] For example, the routing register 220 records and configures the interrupt routing information corresponding to the interrupt target, and the specific operation of the data conversion circuit 230 converting the interrupt information into interrupt data can also refer to the relevant description of the routing register 120 and the data conversion circuit 130 in the aforementioned embodiment, which will not be repeated here.

[0119] For example, the programmable interrupt routing controller is responsible for receiving interrupt information and routing the interrupt information to the correct target device based on the system address convention and the information in the routing register.

[0120] In some embodiments of the present disclosure, for example, the interrupt information may include at least one of interrupt address information, data information, chip (eg, current chip or cross-chip) identification information, and processor identification information.

[0121] For example, the data conversion circuit 230 may be configured to identify the interrupt address information and the target processor identification (eg, processor ID) carried in the interrupt information according to a preset address mapping relationship (ie, a preset address convention).

[0122] For example, in response to identifying that the interrupt information includes identification information of a processor (such as processor 1) in the present chip (such as die1), the data conversion circuit 230 can be configured to search the routing register of the present chip (i.e., the first routing register) in the routing register 220 to obtain the interrupt routing information of the processor (such as processor 1) on the bus 260.

[0123] For example, in response to identifying that the interrupt information includes a processor (such as processor 3) in another chip (for example, a chip other than the interrupt control device, across chips, such as die2), the data conversion circuit 230 can be configured to search the cross-chip routing register (i.e., the second routing register) in the routing register 220 to obtain the interrupt routing information of the chip (die2) on the bus 260.

[0124] For example, the interrupt target address information may be represented as 0x2300_1000, the data information may be represented as 35, and the processor identification information (processor ID) may be represented as processor 1.

[0125] For example, the data conversion circuit 230 may be configured to integrate the interrupt address information, data and corresponding interrupt routing information carried in the interrupt information into interrupt data, and provide the interrupt data to the corresponding target device through the bus according to the interrupt routing information.

[0126] For example, after the routing register 220 generates interrupt data, the interrupt control device 200 may provide the interrupt data to the processor 270 corresponding to the interrupt target through the bus 260 according to the interrupt routing information carried in the interrupt data.

[0127] For example, the data conversion circuit 230, routing register 220, cache circuit 250, bus 260 and processor 270 involved in the above embodiments can be hardware, software, firmware and any feasible combination thereof. For example, the data conversion circuit 230, routing register 220, cache circuit 250, bus 260 and processor 270 can be dedicated or general circuits, chips or devices, etc., or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0128] It should be noted that in the embodiments of the present disclosure, the related operations, functions or beneficial effects performed by the various circuits and modules of the interrupt control device 200 can also refer to the related descriptions of the various circuits and modules of the interrupt control device 100 in the aforementioned embodiments. Figure 3 The components and structures of the interrupt control device 200 shown are merely exemplary and non-limiting. The interrupt control device 200 may further include other components and structures as required.

[0129] Figure 4 A flowchart of an interrupt control method provided by at least one embodiment of the present disclosure is shown.

[0130] like Figure 4 As shown, the interrupt control method may include steps S300 to S330. The interrupt control method may also be applied to the interrupt control device (eg, the interrupt control device 100 or the interrupt control device 200) provided in any embodiment of the present disclosure.

[0131] Step S300: receiving interruption information, where the interruption information includes an interruption target.

[0132] Step S310: Record and configure the interrupt routing information corresponding to the interrupt target.

[0133] Step S320: converting the interrupt information into interrupt data, wherein the interrupt data carries interrupt routing information corresponding to the interrupt target.

[0134] Step S330: providing the interrupt data to at least one target device via the bus.

[0135] In some embodiments of the present disclosure, the interrupt control method further includes step S340.

[0136] Step S340: store the interruption information.

[0137] In some embodiments of the present disclosure, step S340 may further include steps S341 - S342 .

[0138] Step S341: Control the cache threshold register to set the upper limit of the capacity of the cache circuit; and

[0139] Step S342: Control the cache sub-circuit to store the interrupt information.

[0140] In some embodiments of the present disclosure, step S320 may further include: searching for interrupt routing information corresponding to the interrupt target through at least one routing register, and converting the interrupt information into interrupt data.

[0141] In some embodiments of the present disclosure, the interrupt routing information includes routing information within a chip where the interrupt control device is located or includes routing information across chips.

[0142] In some embodiments of the present disclosure, the at least one routing register includes a first routing register and a second routing register. Step S310 may further include steps S311-S312.

[0143] Step S311: Control the first routing register to configure the first routing information, wherein the first routing information includes routing information in the chip where the interrupt control device is located;

[0144] Step S312: Control the second routing register to configure second routing information, wherein the second routing information includes cross-chip routing information.

[0145] In some embodiments of the present disclosure, the interrupt information includes data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0146] Step S311 may further include: searching for first routing information according to the interrupt information, and providing the first routing information to the data conversion circuit.

[0147] Step S320 may further include: determining interrupt data according to the first routing information and the data information.

[0148] In some embodiments of the present disclosure, the interrupt information includes data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0149] Step S312 may further include: searching for second routing information according to the interrupt information, and providing the second routing information to the data conversion circuit;

[0150] Step S320 may further include: determining interrupt data according to the second routing information and the data information.

[0151] In some embodiments of the present disclosure, the interrupt information may further include data information and interrupt target address information carried by multiple interrupt requests respectively issued by multiple target interrupt sources; the interrupt target address information includes identification information of the chip where the interrupt control device is located, cross-chip chip identification information or processor identification information.

[0152] It should be noted that, for the functions or beneficial effects of each step in the above interrupt control method, for example, reference may be made to the description of the interrupt control device 100 in the above embodiment, which will not be repeated here.

[0153] Figure 5 A schematic block diagram of an interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0154] At least one embodiment of the present disclosure further provides an interrupt control device, such as Figure 5 As shown, the interrupt control device 400 includes a processing unit 410 and a storage medium 420 .

[0155] For example, the interrupt control device 400 may include the interrupt control device provided by any of the above embodiments. The interrupt control device 400 may improve the reliability, flexibility and efficiency of interrupt processing.

[0156] For example, the storage medium 420 may be used to store a computer program (e.g., computer-readable instructions, one or more computer program modules) in a non-temporary manner. The processing unit 410 may be used to run the computer program, and when the computer program is run by the processing unit 410, one or more steps in the interrupt control method described above may be executed. The storage medium 420 and the processing unit 410 may be interconnected via a bus system and / or other forms of connection mechanisms, which are not limited in the embodiments of the present disclosure.

[0157] For example, the processing unit 410 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. The processing unit 410 may be a general-purpose processor or a dedicated processor, and may control other components in the interrupt control device 400 to perform desired functions.

[0158] For example, the storage medium 420 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processing unit 410 may run one or more computer program modules to implement various functions of the interrupt control device 400. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0159] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the interrupt control device 400 can refer to the above description of the interrupt control method, which will not be repeated here.

[0160] Figure 6 A schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure is shown.

[0161] At least some embodiments of the present disclosure also provide an electronic device, such as Figure 6 As shown, the electronic device 500 includes an interrupt control device 508. For example, the interrupt control device 508 may include an interrupt control device provided by any embodiment of the present disclosure.

[0162] For example, the electronic device 500 may further include an interrupt controller (not shown in the figure), which may be configured to provide interrupt information to the interrupt control device 508 .

[0163] For example, the electronic devices in the embodiments of the present disclosure may include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device 500 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0164] For example, Figure 6As shown, in some examples, the electronic device 500 includes one or more processors 501 (e.g., a central processing unit, a graphics processing unit, etc.), the processor 501 may be, for example, a RISC architecture (e.g., RISC-V), the processor 501 may include a processor involved in any embodiment of the present disclosure, and the processor 501 may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device (not shown) to a random access memory (RAM) 503. Various programs and data required for the operation of the computer system are also stored in the RAM 503. The processor 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0165] For example, the following components may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 510 as needed, so that the computer program read therefrom can be installed into the storage device as needed. Although Figure 6 The electronic device 500 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0166] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 509 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0167] For example, the electronic device 500 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0168] At least one embodiment of the present disclosure also provides a non-volatile computer-readable storage medium, which is used to non-temporarily store computer-readable instructions, and when the computer-readable instructions are executed by a computer, the above-mentioned interrupt control method can be implemented. Using this computer-readable storage medium, the reliability, flexibility and efficiency of interrupt processing can be improved.

[0169] Figure 7 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Figure 7 As shown, the non-volatile computer-readable storage medium 600 is used to store computer-readable instructions 610. For example, when the computer-readable instructions 610 are executed by a computer, one or more steps in the interrupt control method described above can be executed.

[0170] For example, the non-volatile computer-readable storage medium 600 can be applied to an interrupt control device or an electronic device provided in any embodiment of the present disclosure. Figure 6 The corresponding description of the storage device in the electronic device 500 is not repeated here.

[0171] There are a few points to note:

[0172] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0173] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0174] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An interruption control device, comprising: A first circuit is configured to receive interrupt information, wherein the interrupt information includes an interrupt target; at least one routing register configured to record and configure interrupt routing information corresponding to the interrupt target; a data conversion circuit configured to convert the interrupt information into interrupt data, wherein the interrupt data carries interrupt routing information corresponding to the interrupt target; and The second circuit is configured to provide the interrupt data to at least one target device via a bus.

2. The interrupt control device according to claim 1, further comprising: The cache circuit is configured to store the interrupt information.

3. The interruption control device according to claim 2, wherein: The cache circuit includes a cache threshold register and a cache subcircuit; The cache threshold register is configured to set an upper capacity limit of the interrupt information in the cache circuit, and in response to the interrupt information stored in the cache circuit reaching the upper capacity limit, back pressure the interrupt information; The buffer subcircuit is configured to store the interrupt information.

4. The interruption control device according to claim 1, wherein: The data conversion circuit is further configured to search for interrupt routing information corresponding to the interrupt target through the at least one routing register, and convert the interrupt information into the interrupt data.

5. The interruption control device according to claim 1, wherein: The interrupt routing information includes routing information within the chip where the interrupt control device is located or includes routing information across chips.

6. The interruption control device according to claim 5, wherein: The at least one routing register includes a first routing register and a second routing register; Wherein, the first routing register is configured to configure first routing information, wherein the first routing information includes routing information within the chip where the interrupt control device is located; The second routing register is configured to configure second routing information, wherein the second routing information includes the cross-chip routing information.

7. The interruption control device according to claim 6, wherein: The interrupt information includes data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources; The first routing register is further configured to search for the first routing information and provide the first routing information to the data conversion circuit according to the interrupt information; The data conversion circuit is further configured to determine the interrupt data according to the first routing information and the data information.

8. The interruption control device according to claim 6, wherein: The interrupt information includes data information carried by a plurality of interrupt requests respectively issued by a plurality of target interrupt sources; The second routing register is further configured to search for the second routing information according to the interrupt information and provide the second routing information to the data conversion circuit; The data conversion circuit is further configured to determine the interrupt data according to the second routing information and the data information.

9. The interruption control device according to any one of claims 1 to 8, wherein: The interrupt information includes data information and interrupt target address information carried by multiple interrupt requests respectively issued by multiple target interrupt sources. The interrupt target address information includes the identification information of the chip where the interrupt control device is located, the chip identification information across chips, or the identification information of the processor. The data information includes identification information of the chip where the interrupt control device is located, the cross-chip chip or the interrupt processing module in the processor.

10. An interrupt control method, comprising: receiving interruption information, wherein the interruption information includes an interruption target; Recording and configuring interrupt routing information corresponding to the interrupt target; Converting the interrupt information into interrupt data, wherein the interrupt data carries interrupt routing information corresponding to the interrupt target; and The interrupt data is provided to at least one target device via a bus.

11. An interruption control device, comprising: Processing unit; as well as A storage medium, wherein the storage medium stores at least one computer program, and when the at least one computer program is executed by the processing unit, the interrupt control method according to claim 10 is implemented.

12. An electronic device, comprising the interruption control device according to any one of claims 1 to 9 or the interruption control device according to claim 11.

13. The electronic device as claimed in claim 12, further comprising an interrupt controller and the bus, wherein: The interrupt controller is configured to send the interrupt information.

14. A non-volatile computer-readable storage medium, used for non-temporarily storing computer-readable instructions, which implement the interrupt control method according to claim 10 when the computer-readable instructions are executed by a computer.

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