AXI bus low-bandwidth to high-bandwidth low-latency conversion method, device, terminal and data transmission system

Abstract

This invention provides a method, apparatus, terminal, and data transmission system for low-width to high-width low-latency conversion of an AXI bus. The system receives an AXI transmission command sent from a low-width data terminal to a high-width data terminal, and transmits the received data to be transmitted after width conversion via the AXI bus according to a preset transmission mode. The operation of the current command ends upon receiving a data channel response signal. This invention reduces data read / write latency during width conversion, further improving the efficiency of the AXI bus.

Description

Technical Field

[0001] This invention relates to the field of data transmission, and in particular to a method, apparatus, terminal, and data transmission system for converting low-bandwidth to high-bandwidth low-latency AXI bus. Background Technology

[0002] The AXI protocol is an on-chip bus designed for high performance, high bandwidth, and low latency. The AXI bus is a multi-channel transmission bus that transmits write addresses, write data, write responses, read addresses, read data, and responses in different channels. Master and slave devices can be flexibly connected based on the AXI bus, but when the data widths of the master and slave devices are inconsistent, a bus width conversion device is required for data width matching. Handling data transfer from a low-width data port to a high-width data port is a common requirement in the AXI protocol, especially when data from different sources (such as peripherals, smaller processor cores, etc.) needs to be integrated into a wider data bus or processing unit. While the AXI protocol itself supports flexible data widths, automatic conversion from a fixed low-width to a high-width data port is not a feature directly provided by the AXI protocol. This typically requires additional logic design at the source or destination of the data transfer.

[0003] In existing AXI bus data low-width to high-width conversion device designs, data is typically written into FIFO (First In First Out) or RAM (Random Access Memory) storage spaces in each channel first, and then the data is read from the FIFO or RAM storage spaces. This inevitably increases the delay of AXI bus data conversion and reduces the efficiency of AXI bus. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method, apparatus, terminal and data transmission system for low-width to high-width low-latency conversion of AXI bus, to solve the technical problem that in the prior art, data is first written into storage space such as FIFO or RAM in each channel and then the data is read from the storage space such as FIFO or RAM, which inevitably increases the latency of AXI bus data conversion and reduces the efficiency of AXI bus.

[0005] To achieve the above and other related objectives, the present invention provides a method for low-width to high-width low-latency conversion of an AXI bus. The method includes: receiving a data transmission command sent from a low-width data terminal to a high-width data terminal; transmitting data converted from the received data to be transmitted via the AXI bus according to a preset transmission mode; and ending the operation of the current data transmission command when a data channel response signal is received.

[0006] In one embodiment of the present invention, the data transmission command corresponds to a transmission type, which includes: data address, data bit width, and data transmission length.

[0007] In one embodiment of the present invention, the method includes: receiving a write address transmission signal transmitted by a low-width data terminal through a write address channel; using a preset write transmission mode, transmitting high-width data (after bit-width conversion) of the low-width data transmitted by the low-width data terminal through the write data channel to a high-width data terminal via an AXI bus; and ending the current write data transmission operation when receiving a write response channel signal fed back by the high-width data terminal through a write response channel after the data writing is completed.

[0008] In one embodiment of the present invention, the preset write-send mode includes: a first preset write-send mode, including: matching the data bit width of the high-bit-width data end based on the data bit width size and data transmission length in the write address transmission signal, and adjusting the data transmission length accordingly; whenever the received low-bit-width data reaches the data bit width size of the high-bit-width data end through the shift register, the data is sent to the high-bit-width data end until all the data is sent; a second preset write-send mode includes: mapping the sequentially received low-bit-width data to the high-bit-width data bits adapted to the high-bit-width data end according to the write address in the write address transmission signal, and using a valid byte signal to identify the valid low-bit-width data in the current high-bit-width data, and sending it to the high-bit-width data end until all the data is sent.

[0009] In one embodiment of the present invention, the method includes: receiving a read address transmission signal transmitted by a low-width data terminal through a read address channel; transmitting low-width data converted from high-width data transmitted by the high-width data terminal through a read data channel to the low-width data terminal via an AXI bus using a preset read transmission mode; and ending the current read data transmission operation when receiving a read response channel signal fed back by the high-width data terminal through a read data response channel after the data reading is completed.

[0010] In one embodiment of the present invention, the preset read-send mode includes: a first preset read-send mode, comprising: matching the data bit width of the high-bit-width data end based on the data bit width size and data transmission length in the read address transmission signal, and adjusting the data transmission length accordingly; shifting the sequentially received high-bit-width data into low-bit-width data according to the data bit width size in the read address transmission command, and sequentially sending it to the low-bit-width data end until all data is sent; and a second preset read-send mode, comprising: extracting corresponding low-bit-width data from the received high-bit-width data according to the read address in the read channel transmission signal, and sequentially sending it to the low-bit-width data end until all data is sent.

[0011] In one embodiment of the present invention, the high-width data received in the second preset read-send mode is obtained by mapping each read data required by the low-width data terminal to an appropriate high-width data bit according to the read address through the high-width data terminal.

[0012] To achieve the above and other related objectives, the present invention provides an AXI bus low-width to high-width low-latency conversion device, disposed between the low-width data terminal and the high-width data terminal, the device being used in the aforementioned AXI bus low-width to high-width low-latency conversion method.

[0013] To achieve the above and other related objectives, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store a computer program; the one or more processors are connected to the memories and are used to run the computer program to execute the AXI bus low-width to high-width low-latency conversion method.

[0014] To achieve the above and other related objectives, the present invention provides a data transmission system based on low-width to high-width low-latency conversion of an AXI bus. The system includes: a low-width data terminal, a high-width data terminal, and an AXI bus low-width to high-width low-latency conversion device capable of executing the AXI bus low-width to high-width low-latency conversion method; wherein the AXI bus low-width to high-width low-latency conversion device is disposed between the low-width data terminal and the high-width data terminal.

[0015] As described above, this invention provides a method, apparatus, terminal, and data transmission system for low-width to high-width low-latency conversion of an AXI bus, offering the following advantages: This invention receives AXI transmission commands sent from a low-width data terminal to a high-width data terminal, and transmits the received data to be transmitted after width conversion via the AXI bus according to a preset transmission mode. Upon receiving a data channel response signal, the operation of the current command is terminated. This invention reduces data read / write latency during width conversion, further improving the efficiency of the AXI bus. Attached Figure Description

[0016] Figure 1 The diagram shown is a flowchart illustrating a method for converting low-width to high-width low-latency AXI bus according to an embodiment of the present invention.

[0017] Figure 2 The diagram shown is a flowchart illustrating a write data transmission operation according to an embodiment of the present invention.

[0018] Figure 3 The diagram shown is a flowchart illustrating a read data transmission operation according to an embodiment of the present invention.

[0019] Figure 4 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of the present invention.

[0020] Figure 5 The diagram shown is a schematic representation of a data transmission system based on low-bit-width to high-bit-width low-latency conversion of an AXI bus according to an embodiment of the present invention.

[0021] Figure 6 The diagram shown is a schematic representation of a data transmission system based on low-width to high-width conversion between the master and slave ends, according to an embodiment of the present invention.

[0022] Figure 7 The diagram shown is a schematic representation of a data transmission system based on low-bit-width to high-bit-width low-latency conversion of an AXI bus according to an embodiment of the present invention. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0024] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0025] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0026] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0027] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0028] This invention provides a low-latency conversion method for low-width to high-width AXI bus data. It receives an AXI transmission command sent from a low-width data terminal to a high-width data terminal, and transmits the received data to be transmitted after bit-width conversion via the AXI bus according to a preset transmission mode. The operation of the current command ends upon receiving a data channel response signal. This invention reduces data read / write latency during bit-width conversion, further improving the efficiency of the AXI bus.

[0029] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0030] like Figure 1 This is a flowchart illustrating a method for converting low-width to high-width low-latency AXI bus according to an embodiment of the present invention.

[0031] The method includes:

[0032] Step S1: Receive the data transmission command sent from the low-width data terminal to the high-width data terminal.

[0033] Step S2: Transmit the received data to be transmitted after bit width conversion via the AXI bus according to the preset transmission mode.

[0034] Step S3: When a data channel response signal is received, the operation of the current data transmission command is terminated.

[0035] In one embodiment, when the low-width data terminal needs to send data to the high-width data terminal, a data transmission command corresponding to a transmission type (such as read / write) is first issued. In this scenario, the command specifically indicates that the data will be transmitted from the low-width data terminal to the high-width data terminal.

[0036] Data transfer commands must include at least the following:

[0037] The data address provides the address of the first data in a burst transmission; if the transmission type is write transmission, it is the write address, and if the transmission type is read transmission, it is the read address.

[0038] Data transmission length gives the exact number of transmissions in a single burst.

[0039] The data bit width indicates the size of the data transmitted in a single transmission.

[0040] The transmission types involved in this invention are write data transmission and read data transmission. The following specific embodiments will be used to describe the method for converting low-width to high-width low-latency AXI bus transmission under the two transmission modes.

[0041] In one embodiment, if the low-width data terminal needs to write data to the high-width data terminal, a write command needs to be sent first. In the AXI protocol, write operations typically involve multiple channels, including the write address channel (AW), the write data channel (W), and the write response channel (B). Figure 2 Specific conversion methods include:

[0042] Receive the write address channel signal sent by the low-width data terminal through the write address channel. This signal will contain key information such as write address, data bit width, and data transmission length.

[0043] The low-width data is received by the low-width data terminal through the write data channel; wherein the low-width data is implemented by the write data channel signal, including at least: write data (WDATA) and write byte valid signal (WSTRB).

[0044] Using a preset write-send mode, the high-width data after bit-width conversion is sent to the high-width data terminal via the AXI bus;

[0045] Upon receiving the write response channel signal fed back by the high-width data terminal after the data writing is completed through the write response channel, the current write data transmission operation ends; wherein, the write response channel signal (BRESP) indicates the status of the write operation, such as whether the write operation was successful or failed.

[0046] In one embodiment, the preset write-to-send mode includes the following two, which can be set according to requirements:

[0047] The first preset write-and-send mode primarily adjusts and matches the data width (AWSIZE) and data transmission length (AWLEN) to the requirements of the high-width data end based on the bit width and data transmission length of the low-width data, and then combines and sends the data. Specific modes include:

[0048] Because the bit widths of the low-width and high-width data ends are inconsistent, it is necessary to match and convert the data bit width size (AWSIZE) and data transmission length (AWLEN). The data bit width size (AWSIZE) and data transmission length (AWLEN) in the write address transmission signal sent from the low-width data end are matched to the data bit width size of the high-width data end, and the data transmission length is adjusted accordingly. This typically involves increasing AWSIZE and decreasing AWLEN, because the total data length is fixed at the byte level, but the number of transmission units required is reduced when sending according to the high-width data.

[0049] Whenever the received low-width data reaches the data width of the high-width data end through the shift register, the data is sent to the high-width data end until all the data has been sent.

[0050] The advantage of this mode is that it sends fewer data packets, can adapt to data transmission needs with different bit widths, and ensures smooth data transmission by dynamically adjusting the transmission length and packetization method. By adjusting data packetization and transmission length, the risk of data loss and corruption during transmission is reduced, thus guaranteeing data integrity.

[0051] The second preset write-to-send mode primarily maps low-width data to the corresponding positions of high-width data according to the write address, and uses a valid byte signal to identify the valid data portion. Specific modes include:

[0052] The received low-width data are mapped to the high-width data bits of the high-width data end according to the write address in the write address transmission command. The valid byte signal is used to identify the valid low-width data in the current high-width data and then sent to the high-width data end until all the data of the data transmission length in the write address transmission command has been sent.

[0053] Specifically, data is received sequentially from the low-width data end, and mapped to high-width data bits according to the write address in the write address transmission command. For data bits that do not contain valid low-width data, the bit is left unchanged or set to an invalid value. A valid byte signal is used to identify which bytes in the high-width data are valid low-width data, and this signal is sent to the high-width data end until all data has been transmitted. The valid byte signal is similar to the WSTRB signal in the AXI protocol. The WSTRB signal is a binary vector with the same bit width as the slave data, but contains only two values: 0 (indicating invalid data) and 1 (indicating valid data).

[0054] This mode reduces the overhead of data packing and unpacking during transmission and avoids unnecessary bit-width conversion, thus significantly improving data transmission efficiency. It eliminates the need for matching and conversion between AWSIZE and AWLEN, making data transmission more direct and simpler, reducing processing steps and potential error sources, and improving system stability and reliability.

[0055] The two preset write-send modes each have their own characteristics and advantages. The first preset write-send mode is more suitable for scenarios that require handling data transmission with different bit widths, ensuring data integrity and efficient transmission through flexible data packetization and transmission length adjustment. The second preset write-send mode, on the other hand, is more suitable for scenarios with higher requirements for data transmission efficiency, improving data transmission efficiency and overall system performance by simplifying the processing flow and reducing overhead. In practical applications, the appropriate mode should be selected based on specific needs and system environment.

[0056] For example, if the master end is a low-width data end with a data width of 8 bits, and the slave end is a high-width data end with a data width of 16 bits, and data needs to be written from the master end to the slave end, the write address transmission signal sent by the master end specifies that the write address is 0, the bit width is 8 bits, and the write length is 8 (D0, D1, D2, D3, D4, D5, D6, D7).

[0057] The method of using the first preset write-send mode specifically includes: first, matching the data bit width and length sent from the master end to the specifications required by the slave end, the data bit width becomes 16 bits and the length becomes 4 bits; first, shifting and registering the master end data to obtain the first complete data to be sent from the slave end, D00{D1, D0}, and then sending the data D00 to the slave end. Then, the slave end receives the next data to be sent, D01{D3, D2} and continues to send until the data to be sent, D02{D5, D4} and D03{D7, D6}, have all been sent.

[0058] The method using the second preset write-and-send mode specifically includes: mapping each piece of data sent from the master end to the high-width data bits of the slave end according to the address, based on the bit width and length transmitted from the master end. Since the slave end is 16 bits wide, each piece of master end data will occupy one byte (8 bits) of slave end data, while the other byte (8 bits) will be considered invalid data (usually represented by xx). Simultaneously, a corresponding WSTRB signal is generated for each piece of slave end data. For each piece of slave end data, the WSTRB signal will have two bits, one corresponding to the lower 8 bits of the slave end data, and the other corresponding to the higher 8 bits. For the master data D0, its corresponding data on the slave is D00{xx, D0} (xx represents invalid data), and wstrb00 is 2'b01 (0 represents invalid data, 1 represents valid data); for the master data D1, its corresponding data on the slave is D01{D1, xx}, and wstrb01 is 2'b10; for the master data D2, its corresponding data on the slave is D02{xx, D2}, and wstrb02 is 2'b01; for the master data D3, its corresponding data on the slave is D03{D3, xx}, and wstrb01 is 2'b10; and so on until the last master data D7, whose corresponding data on the slave is D07{D7, xx} and wstrb07 is 2'b10, marking the end of the write process.

[0059] In one embodiment, if the low-width data terminal needs to read data from the high-width data terminal, a read command needs to be sent first. In the AXI protocol, read operations typically involve multiple channels, including the read address channel (AR) and the read data response channel (R), where the read data response channel includes the read data channel. Figure 3 Specific conversion methods include:

[0060] Receive the read address transmission signal transmitted from the low-width data terminal through the read address channel. This signal will contain key information such as read address, data bit width, and data transmission length.

[0061] Receive high-bit-width data transmitted by the high-bit-width data terminal through the read data channel; wherein, the high-bit-width data is implemented by read data channel signals, including at least: read data (RDATA), read response (RRESP), and read byte valid signal (RVALID).

[0062] The converted low-width data is sent to the low-width data terminal via the AXI bus using a preset read-send mode.

[0063] The current read data transmission operation ends upon receiving a read response channel signal from the high-width data terminal after data reading is complete. This read response channel signal indicates the status of the read operation, such as whether the read operation was successful or failed.

[0064] In one embodiment, the preset read-send mode includes the following two, which can be set according to requirements:

[0065] The first preset read transmission mode includes: because the bit widths of the low-width data terminal and the high-width data terminal are inconsistent, it is necessary to match and convert the data bit width size (ARSIZE) and the data transmission length (ARLEN). The data bit width size (ARSIZE) and the data transmission length (ARLEN) in the read address transmission signal are used to match the data bit width size for the high-width data terminal, and the data transmission length is adjusted accordingly.

[0066] The high-width data received in sequence are shifted and converted into low-width data according to the data bit width size in the read address transmission command, and then sent to the low-width data end in sequence until all data has been sent.

[0067] This mode enables the handling of data read requests with different bit widths and lengths, thereby meeting diverse data interaction needs. By performing bit width matching and conversion before data transmission, it ensures that the data sent to the low-bit-width data end meets the requirements in terms of bit width and length, thus avoiding data truncation or misalignment and guaranteeing data integrity.

[0068] The second preset read-to-send mode includes:

[0069] In this mode, the read address transmission command of the low-width data end is sent directly without the need to match and convert ARSIZE and ARLEN. The high-width data end maps each read data required in the read address transmission command of the low-width data end to the appropriate high-width data bit to obtain high-width data.

[0070] Based on the read address in the read channel transmission signal, the corresponding low-width data is extracted from the received high-width data and sent sequentially to the low-width data end until all data has been sent.

[0071] This mode eliminates the need for additional matching or conversion of ARSIZE and ARLEN, simplifying the data reading and sending process. This allows the system to process data read requests more efficiently, reducing processing complexity and latency. By directly retrieving and extracting the required data from the high-bit-width data end, intermediate data conversion and processing steps are reduced, significantly improving data transmission efficiency.

[0072] Both preset read / send modes have their advantages, and the choice depends on the specific application scenario and requirements. If the system needs to handle data read requests with varying bit widths and lengths, and has high requirements for data integrity and performance, then the first preset read / send mode may be more suitable. Conversely, if the system primarily handles data read requests with fixed bit widths and lengths, and has high requirements for data transmission efficiency and resource consumption, then the second preset read / send mode may be more appropriate.

[0073] For example, if the master end is a low-width data end with a data width of 8 bits, and the slave end is a high-width data end with a data width of 16 bits, and the master end needs to read data from the slave end, the read address transmission signal sent by the master end specifies that the read address is 0, the bit width is 8 bits, and the read length is 8 (D0, D1, D2, D3, D4, D5, D6, D7).

[0074] The method using the first preset read-send mode specifically includes: first, matching the data bit width and data transmission length sent from the master end to the specifications required by the slave end, so that the data bit width of the slave end becomes 16 bits and the length becomes 4 bits; first, obtaining the first slave end data D00{D1, D0} and shifting it to obtain the first complete data D0 to be read from the master end, and then sending this data D0 to the master end; then, the slave end data continues to be shifted to obtain the next data D1 to be read and then sent to the master end; then, obtaining the next slave end data D01 and shifting it to obtain the data D2, D3 required by the master end; then, continuing to read the data from the slave end until all the slave end data D7 to be sent has been sent.

[0075] The method using the second preset read-send mode specifically includes: for the first data D00 read from the slave end, remap it to the first data D0 from the master end according to the address, and take the lower 8 bits of D00 and send it to the master end; then the second data D1 from the master end is mapped to the higher 8 bits of the second data D01 from the slave end; then the third data D2 from the master end is mapped to the lower 8 bits of the third data D02 from the slave end; then the fourth data D3 from the master end is mapped to the higher 8 bits of the fourth data D03 from the slave end; and so on until the last data D7 from the master end is mapped to the higher 8 bits of the eighth data D07 from the slave end, and the reading is completed.

[0076] It should be noted that the bus system used in this invention can be, in addition to the AXI bus, such as AHB (Advanced High-performance Bus) or a custom bus that requires data width conversion.

[0077] Similar to the above embodiments, the present invention provides an AXI bus low-width to high-width low-latency conversion device, disposed between the low-width data terminal and the high-width data terminal; the device is used to receive data transmission commands sent from the low-width data terminal to the high-width data terminal; to send data converted from the received data to be transmitted via the AXI bus according to a preset transmission mode; and to terminate the operation of the current data transmission command when a data channel response signal is received.

[0078] Since the implementation principle of the AXI bus low-width to high-width low-latency conversion device has been described in the previous embodiments, it will not be repeated here.

[0079] The AXI bus low-width to high-width low-latency conversion method provided in this embodiment of the invention can be implemented on the terminal side or the server side. For the hardware structure of the electronic terminal, please refer to [link to relevant documentation]. Figure 4 This is a schematic diagram of an optional hardware structure of an AXI bus low-width to high-width low-latency conversion terminal 1000 provided in an embodiment of the present invention. The terminal 1000 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It is understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 4 The general will label all buses as bus systems.

[0080] The user interface 1009 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0081] It is understood that memory 1002 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0082] In this embodiment of the invention, the memory 1002 is used to store various types of data to support the operation of the terminal 1000. Examples of this data include: any executable program for operation on the terminal 1000, such as the operating system 10021 and application program 10022; the operating system 10021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 10022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The method for converting low-width to high-width low-latency AXI bus provided in this embodiment of the invention can be included in the application program 10022.

[0083] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The processor 1001 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0084] In an exemplary embodiment, the terminal 1000 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0085] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0086] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0087] like Figure 5 This diagram illustrates the structure of a data transmission system based on low-bit-width to high-bit-width low-latency conversion using an AXI bus, according to an embodiment of the present invention.

[0088] The data transmission system includes: a low-width data terminal 1, a high-width data terminal 2, and an AXI bus low-width to high-width low-latency conversion device 3; the AXI bus low-width to high-width low-latency conversion device 3 is disposed between the low-width data terminal 1 and the high-width data terminal 2. The AXI bus low-width to high-width low-latency conversion device 3 can implement the AXI bus low-width to high-width low-latency conversion method in the above embodiments;

[0089] The AXI bus low-width to high-width low-latency conversion device 3 receives the data transmission command sent by the low-width data terminal 1; receives the data to be transmitted and transmits the data to be transmitted after width conversion through the AXI bus according to the preset transmission mode; when the data channel response signal is received, the operation of the current data transmission command ends.

[0090] It should be noted that if the AXI bus low-width to high-width low-latency conversion device 3 is set within the AXI bus system, it is equivalent to being directly connected between the low-width data terminal 1 and the high-width data terminal 2. Figure 5 The attached diagram is for this situation. For example, as shown... Figure 6The low-width data terminal 1 is usually the master terminal, and the high-width data terminal 2 is usually the slave terminal. The bit width conversion module is located between the master terminal and the slave terminal, and communicates with the slave terminal and the master terminal through the master port M and the slave port S respectively.

[0091] If the AXI bus low-width to high-width low-latency conversion device 3 is set up independently of the AXI bus system, then the AXI bus low-width to high-width low-latency conversion device 3 is connected between the low-width data terminal 1 and the AXI bus system 4, and the AXI bus system is connected to the high-width data terminal 2, such as... Figure 7 As shown.

[0092] In summary, the AXI bus low-width to high-width low-latency conversion method, apparatus, terminal, and data transmission system of the present invention receive AXI transmission commands sent from the low-width data terminal to the high-width data terminal, transmit data (after width conversion of the received data to be transmitted) through the AXI bus according to a preset transmission mode, and terminate the operation of the current command upon receiving a data channel response signal. The present invention reduces data read / write latency during width conversion, thereby further improving the efficiency of the AXI bus. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An AXI bus low-bit-width to high-bit-width low-latency conversion method, characterized in that, The method comprises: receiving a data transmission command sent from a low bit width data end to a high bit width data end; sending data converted in bit width from the received data to be sent through an AXI bus according to a preset sending mode; ending the operation of the current data transmission command when a data channel response signal is received; wherein a write address transmission signal transmitted by the low bit width data end through a write address channel is received, high bit width data converted in bit width from low bit width data transmitted by the low bit width data end through a write data channel is sent to the high bit width data end through the AXI bus using a preset write sending mode, and the current write data transmission operation is ended when a write response channel signal fed back by the high bit width data end through a write response channel after data writing is completed is received; the preset write sending mode is selected according to specific requirements and system environment, including: a first preset write sending mode, comprising: matching the data bit width size of the high bit width data end based on the data bit width size and the data transmission length in the write address transmission signal, and adjusting the data transmission length accordingly; whenever the received low bit width data reaches the data bit width size of the high bit width data end through a shift register, the data is sent to the high bit width data end until all the data is sent; and a second preset write sending mode, comprising: mapping the low bit width data received in sequence to the high bit width data bits suitable for the high bit width data end according to the write addresses in the write address transmission signal, respectively, while using an effective byte signal to identify the effective low bit width data in the current high bit width data, and sending to the high bit width data end until all the data is sent.

2. The AXI bus low-width-to-high-width low-latency conversion method according to claim 1, characterized by, The data transmission command corresponds to a transmission type, which includes: data address, data bit width size and data transmission length.

3. The AXI bus low-width-to-high-width low-latency conversion method according to claim 1, characterized by, The method comprises: receiving a read address transmission signal transmitted by a low bit width data end through a read address channel, sending low bit width data converted from high bit width data transmitted by the high bit width data end through a read data channel to the low bit width data end through an AXI bus using a preset read sending mode, and ending the current read data transmission operation when a read response channel signal fed back by the high bit width data end through a read data response channel after data reading is completed is received.

4. The AXI bus low-bit-width to high-bit-width low-latency conversion method according to claim 3, characterized in that, The preset read sending mode comprises: a first preset read sending mode, comprising: matching the data bit width size of the high bit width data end based on the data bit width size and the data transmission length in the read address transmission signal, and adjusting the data transmission length accordingly; converting the high bit width data received in sequence into low bit width data according to the data bit width size in the read address transmission command, respectively, and sending to the low bit width data end in sequence until all the data is sent; a second preset read sending mode, comprising: according to the read addresses in the read address transmission signal, intercepting corresponding low bit width data from the received high bit width data, respectively, and sending to the low bit width data end in sequence until all the data is sent.

5. The AXI bus low-width-to-high-width low-latency conversion method according to claim 1, characterized by, The high-width data received in the second preset read transmission mode is mapped to the high-width data bit according to the read address, and each read data required by the low-width data end is obtained through the high-width data end.

6. An AXI bus low bit width to high bit width low latency conversion apparatus, characterized by, The device is arranged between the low-width data end and the high-width data end, and is configured to perform the AXI bus low-width to high-width low-delay conversion method according to any one of claims 1 to 5.

7. An electronic terminal, characterized in that The system comprises: one or more memories and one or more processors; the one or more memories are configured to store a computer program; the one or more processors are connected to the memories and are configured to run the computer program to perform the method according to any one of claims 1 to 5.

8. A data transfer system based on AXI bus low bit width to high bit width low latency conversion, characterized in that, The system comprises: a low-width data end, a high-width data end, and an AXI bus low-width to high-width low-delay conversion device according to claim 6; wherein the AXI bus low-width to high-width low-delay conversion device is arranged between the low-width data end and the high-width data end.

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