A PCIe forking method and device

Abstract

The application provides a PCIe bifurcation method and device. The method comprises: for a to-be-processed signal of a conversion type of channel to port, performing channel flipping or channel degradation in a port after bifurcation mapping convergence, and then outputting; for a to-be-processed signal of a separation type of port to channel, performing channel flipping or channel degradation in the port, and then outputting to a corresponding channel after bifurcation mapping splitting; and for a to-be-processed signal of a replication type of port to channel, replicating according to the number of channels supported by the port, and then outputting to a corresponding channel after bifurcation mapping splitting. The technical scheme can maximize the reuse of Lane logic resources, support flexible customization of interactive signals between multiple ports and multiple lanes, support classification and batch processing of interactive signals between multiple ports and multiple lanes, and automatically generate codes.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a PCIe bifurcation method and device. BACKGROUND

[0002] PCI Express (peripheral component interconnect express), abbreviated as PCIe, is a high-speed, serial, full-duplex, computer expansion bus standard, which uses a high-speed differential bus and adopts a point-to-point connection mode for communication between two devices. A plurality of PCI Express devices are interconnected by using a Switch, so that a large number of devices can be connected together in a system. PCIe bifurcation is a function of dividing data channels in a PCIe slot. SUMMARY

[0003] The application aims to provide a PCIe bifurcation method and device, and aims to solve the problems of long chip development period and great verification convergence difficulty caused by the need for customized special development and design of the existing PCIe bifurcation technology.

[0004] According to a first aspect of the application, a PCIe bifurcation method is provided, comprising:

[0005] For a to-be-processed signal of a conversion type of channel to port, after bifurcation mapping convergence, channel flipping or channel degradation is performed inside the corresponding port, and then the signal is output;

[0006] For a to-be-processed signal of a separation type of a conversion type of port to channel, after channel flipping or channel degradation is performed inside the corresponding port, the signal is output to the corresponding channel after bifurcation mapping splitting;

[0007] For a to-be-processed signal of a copy type of a conversion type of port to channel, the signal is copied according to the number of channels supported by the corresponding port, and then the signal is output to the corresponding channel after bifurcation mapping splitting.

[0008] In an optional implementation, the method further comprises:

[0009] A convergence module for bifurcation mapping convergence is designed in advance, and a degradation flipping module for channel flipping or channel degradation is designed in advance;

[0010] The bifurcation mapping convergence module comprises a plurality of bifurcation mapping modules, and the degradation flipping module comprises a plurality of degradation flipping modules.

[0011] instantiating the converging module, connecting internal signals of the instantiated converging module according to a bifurcation mode corresponding to the to-be-processed signal, so as to realize bifurcation mapping convergence of the received to-be-processed signal;

[0012] instantiating the downgrade flip module according to the maximum supported number of ports, and connecting internal signals of the instantiated downgrade flip module, so as to realize channel flipping or channel downgrading of the bifurcation mapping converged to-be-processed signal in a port.

[0013] In an optional embodiment, the method further comprises:

[0014] pre-designing a splitting module for bifurcation mapping splitting according to a bifurcation mode, and pre-designing a downgrade flip module for channel flipping or channel downgrading;

[0015] for the to-be-processed signal of the separation type of the port-to-channel conversion type, after channel flipping or channel downgrading in the corresponding port, the bifurcation mapping split to-be-processed signal is output to the corresponding channel, comprising:

[0016] instantiating the downgrade flip module according to the maximum supported number of ports, and connecting internal signals of the instantiated downgrade flip module, so as to realize channel flipping or channel downgrading of the received to-be-processed signal in a port.

[0017] instantiating the splitting module, connecting internal signals of the instantiated splitting module according to a bifurcation mode corresponding to the to-be-processed signal, so as to realize bifurcation mapping splitting of the to-be-processed signal subjected to channel flipping or channel downgrading.

[0018] In an optional embodiment, the method further comprises:

[0019] pre-designing a splitting module for bifurcation mapping splitting according to a bifurcation mode, and pre-designing a replication module for signal replication;

[0020] for the to-be-processed signal of the replication type of the port-to-channel conversion type, the to-be-processed signal is replicated according to the number of channels supported by the corresponding port, and the bifurcation mapping split to-be-processed signal is output to the corresponding channel, comprising:

[0021] instantiating the replication module according to the maximum supported number of ports, and connecting internal signals of the instantiated replication module, so as to realize replication of the received to-be-processed signal.

[0022] instantiating the splitting module, connecting internal signals of the instantiated splitting module according to a bifurcation mode corresponding to the to-be-processed signal, so as to realize bifurcation mapping splitting of the to-be-processed signal subjected to channel flipping or channel downgrading.

[0023] In an optional embodiment, the method further comprises:

[0024] obtaining configuration information of the PCIe bifurcation system; wherein the configuration information comprises: a conversion type of the to-be-processed signal, a bifurcation mode of the to-be-processed signal, a width of the to-be-processed signal, a maximum number of supported channels, a maximum number of supported ports, and a number of supported channels per port; wherein a number of bifurcation mapping aggregation splits is equal to the maximum number of supported channels.

[0025] According to a second aspect of the present application, a PCIe bifurcation device is provided, comprising:

[0026] a channel-to-port conversion module configured to, for a to-be-processed signal of a conversion type of channel-to-port, output after channel flipping or channel degradation within a corresponding port after bifurcation mapping aggregation;

[0027] a first port-to-channel conversion module configured to, for a to-be-processed signal of a separation type of a conversion type of port-to-channel, output to a corresponding channel after bifurcation mapping split after channel flipping or channel degradation within a corresponding port;

[0028] a second port-to-channel conversion module configured to, for a to-be-processed signal of a replication type of a conversion type of port-to-channel, replicate according to a number of supported channels per port and output to a corresponding channel after bifurcation mapping split.

[0029] In an optional embodiment, the device further comprises:

[0030] a first design module configured to pre-design an aggregation module for bifurcation mapping aggregation and pre-design a degradation flipping module for channel flipping or channel degradation;

[0031] the channel-to-port conversion module is implemented as:

[0032] instantiating the aggregation module, connecting internal signals of the instantiated aggregation module according to a bifurcation mode corresponding to the to-be-processed signal, to achieve bifurcation mapping aggregation of the received to-be-processed signal;

[0033] instantiating the degradation flipping module according to a maximum number of supported ports, and connecting internal signals of the instantiated degradation flipping module, to achieve channel flipping or channel degradation of the to-be-processed signal within a port after bifurcation mapping aggregation.

[0034] In an optional embodiment, the device further comprises:

[0035] The second design module is configured to pre-design a split module for split mapping and splitting according to a split mode, and pre-design a downgrade flip module for channel flipping or channel downgrading.

[0036] The first port-to-channel conversion module is implemented as:

[0037] The downgrade flip module is instantiated according to the maximum number of supported ports, and internal signals of the instantiated downgrade flip module are connected to achieve channel flipping or channel downgrading of the received to-be-processed signal within a port.

[0038] The split module is instantiated, and internal signals of the instantiated split module are connected according to the split mode corresponding to the to-be-processed signal, to achieve split mapping and splitting of the to-be-processed signal subjected to channel flipping or channel downgrading.

[0039] In an optional embodiment, the apparatus further includes:

[0040] The third design module is configured to pre-design a split module for split mapping and splitting according to a split mode, and pre-design a copy module for signal copying.

[0041] The second port-to-channel conversion module is implemented as:

[0042] The copy module is instantiated according to the maximum number of supported ports, and internal signals of the instantiated copy module are connected to achieve copying of the received to-be-processed signal.

[0043] The split module is instantiated, and internal signals of the instantiated split module are connected according to the split mode corresponding to the to-be-processed signal, to achieve split mapping and splitting of the to-be-processed signal subjected to copying.

[0044] In an optional embodiment, the apparatus further includes:

[0045] The acquisition module is configured to acquire configuration information of a PCIe split system; wherein the configuration information includes: a conversion type of the to-be-processed signal, a split mode of the to-be-processed signal, a width of the to-be-processed signal, a maximum number of supported channels, a maximum number of supported ports, and a number of channels supported by each port; wherein a number of split mapping and splitting is equal to the maximum number of supported channels.

[0046] Compared with the related art, the technical solution of the present application has the following advantages:

[0047] The application solves the problem that the traditional PCIe multi-port controller design needs special customized development of bifurcation function logic, prolongs the chip development cycle and increases the difficulty of verification convergence, can maximize the reuse of lane logic resources, supports flexible customization of interaction signals between multi-port and multi-lane, supports classification and batch processing of interaction signals between multi-port and multi-lane (standardization, scalability, accuracy), automatically generates code, supports flexible configuration of mapping relationship between multi-port and multi-lane, meets various needs, the code has strong maintainability and scalability, can shorten the code delivery cycle by about 2-3 weeks, if frequent changes and iterations are needed, the effect is more significant, greatly reduces the amount of interaction signals, reduces the difficulty and cycle of timing convergence, reduces the difficulty of verification coverage convergence, and shortens the product development time.

[0048] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure and process indicated in the description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiment or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0050] Figure 1 is the working example effect diagram of the PCIe device with 16 channels according to the related art under different bifurcation configurations.

[0051] Figure 2 is the PCIe bifurcation structure diagram designed according to the related art.

[0052] Figure 3 is the MAC layer sending and receiving structure diagram according to the exemplary embodiment of the present application.

[0053] Figure 4 is the PCIe bifurcation method flow diagram according to the exemplary embodiment of the present application.

[0054] Figure 5A is the RTL automatic generation flow processing diagram according to the exemplary embodiment of the present application.

[0055] Figures 5B-5Dis a bifurcation mode schematic diagram of a to-be-processed signal of different conversion types according to an exemplary embodiment of the present application.

[0056] Figure 6 is a code structure schematic diagram of automatically generating RTL according to an exemplary embodiment of the present application.

[0057] Figure 7 is a structure schematic diagram of a p2l_split unit of automatically generating RTL according to an exemplary embodiment of the present application.

[0058] Figure 8 is a structure schematic diagram of a p2l_replication unit of automatically generating RTL according to an exemplary embodiment of the present application.

[0059] Figure 9 is a structure schematic diagram of a l2p unit of automatically generating RTL according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0061] With the rapid development of information technologies such as big data, Internet of Things, artificial intelligence and the digital transformation of traditional industries, these trends have promoted the rapid development of PCIe chips. A PCIe link can be composed of multiple lanes (physical channels), and a PCIe link can usually support 1, 2, 4, 8, 12, 16 and 32 lanes, i.e., PCIe links of x1, x2, x4, x8, x12, x16 and x32 widths. However, due to the limited number of PCIe physical channels of the motherboard card slot, in order to meet the use requirements of different users in multiple devices and multiple scenarios, the motherboard card slot can be flexibly configured through a bifurcation mode to support multiple combinations or split PCIe channel modes to meet different use scenarios. For example, a PCIe x16 slot can be configured to work in 2 PCIe x8 lanes, or 4 PCIe x4 lanes, or 8 PCIe x2 lanes, or 16 PCIe x1 lanes, etc. This bifurcation function does not affect the overall speed, allowing a larger slot to be used independently like multiple smaller slots, so that no additional PCIe bridge chip is needed.

[0062] As Figure 1As shown, one 16 Lane PCIe device can be connected with 1 x16, 2 x8 and 4 x4 PCIe devices to work independently in different Bifurcation configuration modes, wherein the 16 Lane PHY is shared. The PHY is a module used by PCIe to connect the protocol layer and the link, and contains all circuits related to port operation, such as driving and phase-locked loop, serial-to-parallel, parallel-to-serial, etc.

[0063] The related art realizes the Bifurcation function of multiple PCIe controllers and multiple PHYs, which needs to be customized and specially developed and designed, and does not have universality and scalability, which will inevitably cause the chip development cycle to be prolonged and the verification convergence difficulty to be increased.

[0064] Based on the above analysis, the present application provides a PCIe bifurcation method and device, which can maximize the reuse of Lane logic resources, accelerate verification coverage convergence, reduce the difficulty of middle and back-end physical implementation, and shorten the chip development cycle.

[0065] As Figure 2 shown, in the 16 Lane PCIe Bifurcation structure designed in the related art, one x16, two x8 and four x4 PCIe controllers are instantiated, each outputs 16 lanes, a total of 48 lanes, and then 16 lanes are selected by MUX selection logic and connected to the opposite device, thereby realizing the Bifurcation function. Although this design can realize the basic Bifurcation function, it has the following disadvantages and deficiencies:

[0066] 1. Lane logic resources cannot be reused, resulting in resource waste, and each Port (physical port) uses exclusive PHY, which cannot be shared.

[0067] 2. The mapping relationship of the bifurcation module (Bifurcation mode) does not support flexible configuration, cannot meet multiple requirements, needs special MUX design each time, and increases the development difficulty.

[0068] 3. The interaction between multiple Ports and multiple Lanes has a huge amount of signals, and the maintenance and processing are complex.

[0069] 4. Timing convergence is difficult: due to the large amount and non-uniform types of signals that need to be processed by the MUX selection logic, the combination path is too long, and the back-end routing difficulty is increased.

[0070] 5. Poor maintainability and scalability: if the number of signals is increased or decreased subsequently, the MUX selection logic needs to be modified, the range of changes is large, and errors and risks are easily introduced.

[0071] 6. Verification coverage is difficult: Each design change iteration requires additional targeted verification, which increases verification risk and convergence time.

[0072] like Figure 3 As shown, the PCIe bifurcation method and device exemplarily proposed in this application realize the port to channel (Port to Lane) and channel to port (Lane to Port) conversion function of the entire MAC layer of PCIe. Among them, the port to channel conversion is to output each signal in the Port to the corresponding physical channel through Bifurcation mode mapping processing, and the channel to port conversion is to aggregate the signals of each physical channel into the data of each port through Bifurcation mapping. The above port to channel (Port to Lane) and channel to port (Lane to Port) conversion units all adopt parameterized design and support flexible configuration. In this application, after the relevant information of all the signals to be processed can be entered into the configuration file, the corresponding PCIe bifurcation logic can be output with one click according to the configuration file.

[0073] like Figure 3 As shown, the present application exemplarily provides a structure for defining a Port and Lane interaction signal, but is not limited thereto, and the Port and Lane interaction signal can also be flexibly customized.

[0074] Figure 3 In the example, N is the number of ports and M is the number of lanes. The design features are:

[0075] 1. Supports any combination of bifurcation configurations; that is, for N ports, each port can convert to any of the M channels through the P2L_split unit, P2L_replication unit, and L2P unit in the PCIe bifurcation device (Bifurcation in the figure).

[0076] 2. Maximize multiple lane reuse and save resources; Figure 3 The M channels in the CAN bus can be multiplexed by N ports.

[0077] 3. Classify and batch process interactive signals between multiple ports and multiple lanes to reduce the amount of interactive signals, ease the difficulty of timing convergence, and achieve stronger maintainability and scalability.

[0078] 4. Reduce the difficulty of verification coverage and shorten the convergence time.

[0079] The PCIe bifurcation method and device designed by the application realizes the P2L conversion and L2P conversion functions of the entire MAC layer. Among them, the P2L conversion is first processed by Port internal Lane flipping and Lane degradation operation, and then mapped and output as the corresponding Lane through Bifurcation mode. The L2P conversion is to first gather each Lane signal through Bifurcation mapping into each belonging Port data, and then perform Lane flipping and Lane degradation operation processing in each Port. Thus, according to the type of interaction signal, the corresponding processing is performed, and the Bifurcation RTL code is automatically generated.

[0080] Exemplarily, referring to Figure 4 The PCIe bifurcation method proposed by the application includes:

[0081] In step S401, for the to-be-processed signal of the conversion type of channel to port, after being converged through bifurcation mapping, the channel flipping or channel degradation is performed in the belonging port, and then outputted;

[0082] In step S402, for the to-be-processed signal of the split type of the conversion type of port to channel, after the channel flipping or channel degradation is performed in the belonging port, the bifurcation mapping is split, and then outputted to the corresponding channel;

[0083] In step S403, for the to-be-processed signal of the replication type of the conversion type of port to channel, the number of channels supported by the belonging port is replicated, and then the bifurcation mapping is split, and then outputted to the corresponding channel.

[0084] Referring to Figure 5A According to the PCIe MAC layer structure mentioned above, the to-be-processed signals to be processed are divided into two conversion types of port to channel (Port to Lane) and channel to port (Lane to Port).

[0085] Port to Lane conversion type: according to the Bifurcation requirement of the actual input to-be-processed signal, it can be further divided into two subtypes of split type (Split) and replication type (Replication) for processing:

[0086] Split: The input pending signal of each Port covers the signal state of each Lane, and each Lane signal is independent, that is, one-to-one mapping, so the Bifurcation mapping of the input pending signal of each Port is split and output to the corresponding physical channel Lane, wherein the port of the pending signal is the Port receiving the pending signal. For example: each Lane receives the state mark signal of TS (PCIe link training packet format, used to initialize synchronization and optimize link parameters), and each bit value represents the receiving TS state of all Lanes. Taking X8 as an example, Lane0~7 input needs to be taken from the corresponding bit of the state mark signal. After receiving TS, the bit position corresponding to the state mark signal is 1, and four lanes must all receive the TS state. The port end does aggregation.

[0087] Replication: Each Lane in the Port has a common input pending signal, that is, one-to-many mapping, so the number of Lane pending signals is replicated according to the number of Lanes contained in the Port, and then each pending signal is Bifurcation mapping split and output to the corresponding physical channel. For example: the LTSSM state signal of the current Port needs to be copied to each Lane belonging to the current Port, so the input of each Lane in the Port is taken from the same LTSSM state signal.

[0088] Lane to Port (channel to port) conversion: first aggregate the pending signals corresponding to each Lane into data of each belonging Port, and then output after channel flipping or channel degradation in each belonging Port. The pending signal corresponding to each Lane can be understood as the pending signal output from the corresponding Lane, and the belonging Port can be understood as the port to which the pending signal needs to be converted.

[0089] In some optional implementations, the method further comprises:

[0090] The aggregation module for Bifurcation mapping aggregation is designed in advance, and the degradation flipping module for channel flipping or channel degradation is designed in advance;

[0091] After the Bifurcation mapping aggregation, the channel flipping or channel degradation in the belonging port is performed, and then the pending signal of the conversion type of Lane to Port is output, comprising:

[0092] The aggregation module is instantiated, and the internal signals of the instantiated aggregation module are connected according to the Bifurcation mode corresponding to the pending signal, so as to realize the Bifurcation mapping aggregation of the received pending signal;

[0093] According to the maximum number of ports supported, the degradation flip module is instantiated, and the internal signals of the instantiated degradation flip module are connected to realize channel flipping or channel degradation of the to-be-processed signal after the bifurcated mapping convergence within the port.

[0094] For example, in the present application, a convergence module l2p_bif_convert for performing bifurcation mapping and convergence may be pre-designed to realize that the signals to be processed entering each Lane are bifurcation mapped and converged into signals at the Port end through a bifurcation mode.

[0095] The following uses X8 as an example to illustrate the fork mode:

[0096] P2L separation type:

[0097] See also Figure 5B As shown in the figure, the bit width of signal_a output by the port is 8 bits, and it interacts with lanes 0 through 7 in descending order. Therefore, the bifurcation mode required for this type of signal to be processed is split. That is, the port outputs a signal group that covers all lane interaction signals and needs to be split (one-to-one mapping) to each lane.

[0098] P2L replication type:

[0099] See also Figure 5C As shown in the figure, the signal_b bit width of the port output is 1 bit, and lane0 to lane7 all need to use this signal for interaction. Therefore, the fork mode required for this type of processed signal is the replication type, that is, the same interactive signal output by the port is replicated (one-to-many mapping) and transmitted to each lane for interaction.

[0100] L2P type:

[0101] See also Figure 5D As shown in the figure, lanes 0 through 7 all output the same signal_c, with a bit width of 1 bit. Because the states of each lane output vary, the Port uses the signals from each lane to make overall decisions and interactions. Therefore, the processing mode for this type of signal to be processed is L2P. This means that the different interactive signals output by each lane are aggregated into a single signal, signal_c[7:0] (which corresponds to lanes 0 through 7 in descending order of bit width) and transmitted to the Port for interaction.

[0102] Exemplarily, the application can also pre-design a lane flip convert or a lane downgrade flip module lane_flip_convert for implementing lane flip and downgrade functions inside each port. In implementing the scheme of the application, the aggregation module and the lane downgrade flip module can be temporarily designed as digital circuit modules, and can be subsequently designed as hardware circuit modules together with the PCIe bifurcation device of the application.

[0103] In designing the PCIe bifurcation circuit, the pre-designed aggregation module can be directly instantiated for the channel-to-port type of the to-be-processed signal, so as to connect the internal signals of the instantiated aggregation module according to the bifurcation mode corresponding to the to-be-processed signals of the multiple channels aggregated to the same port, so that the to-be-processed signals of the multiple channels can be bifurcated and mapped and aggregated from the channel to the port by the instantiated aggregation module.

[0104] And for each port, a lane downgrade flip module can also be instantiated to perform lane flip or lane downgrade inside the port for the signals aggregated to the port.

[0105] In some optional implementations, the method further includes:

[0106] pre-designing a split module for bifurcated mapping and splitting according to the bifurcation mode, and pre-designing a lane downgrade flip module for lane flip or lane downgrade;

[0107] for the to-be-processed signal of the separation type of the port-to-channel conversion type, after lane flip or lane downgrade inside the corresponding port, the bifurcated mapping and splitting are performed and then output to the corresponding channel, including:

[0108] instantiating the lane downgrade flip module according to the maximum number of supported ports, and connecting the internal signals of the instantiated lane downgrade flip module to achieve lane flip or lane downgrade of the received to-be-processed signal inside the port.

[0109] instantiating the split module, and connecting the internal signals of the instantiated split module according to the bifurcation mode corresponding to the to-be-processed signal to achieve bifurcated mapping and splitting of the to-be-processed signal of lane flip or lane downgrade.

[0110] Exemplarily, the application can pre-design a split module p2l_bif_convert for bifurcated mapping and splitting, which is used to implement bifurcated mapping and splitting of the to-be-processed signals of the same port into corresponding channel signals through the bifurcation mode.

[0111] Exemplarily, the application can also pre-design a lane flip conversion or a lane flip conversion module lane_flip_convert for implementing lane flip and downgrade functions inside each port. It can be understood that the lane flip conversion module lane_flip_convert can be directly used in the implementation without being designed again if it has been pre-designed. In the implementation of the scheme of the application, the split module and the lane flip conversion module can be temporarily designed as digital circuit modules, and can be subsequently designed as hardware circuit modules together with the PCIe bifurcation device of the application.

[0112] In the design of the PCIe bifurcation circuit, for the to-be-processed signals of the port-to-lane split type, the lane flip conversion module can be instantiated first. If the to-be-processed signals include multiple signals and correspond to multiple ports, a lane flip conversion module can be instantiated for each port, so that the to-be-processed signals of the corresponding port are subjected to lane flip conversion or lane downgrade by the instantiated lane flip conversion module, and then output to the instantiated split module.

[0113] In the instantiation of the split module, the internal signals of the instantiated split module are connected according to the bifurcation mode of the to-be-processed signals to be mapped, so that the to-be-processed signals of the same port can be split into signals of multiple lanes by the instantiated split module.

[0114] In some optional implementations, the method further includes:

[0115] The split module pre-designed to split according to the bifurcation mode, and the copy module pre-designed to copy signals;

[0116] For the to-be-processed signals of the conversion type of the port-to-lane copy type, the to-be-processed signals are copied according to the number of lanes supported by the port to which the to-be-processed signals belong, and then split according to the bifurcation mode and output to the corresponding lane, including:

[0117] The copy module is instantiated according to the maximum number of supported ports, and the internal signals of the instantiated copy module are connected to implement copying of the received to-be-processed signals;

[0118] The split module is instantiated, and the internal signals of the instantiated split module are connected according to the bifurcation mode corresponding to the to-be-processed signals to implement bifurcation mapping and splitting of the copied to-be-processed signals.

[0119] Exemplarily, the splitting module p2l_bif_convert for bifurcated mapping splitting can be pre-designed in the application, for realizing that the to-be-processed signals of the same port are bifurcated mapping split into signals of corresponding channels through bifurcated mode. It can be understood that the splitting module p2l_bif_convert can be directly used in the implementation manner if it has been pre-designed, without the need of re-designing.

[0120] Exemplarily, the replication module replication for signal replication can also be pre-designed in the application, for realizing that the input signals of the Port are replicated according to the maximum supported Lane number. In the implementation scheme of the application, the splitting module and the replication module can be temporarily designed as digital circuit modules, and can be subsequently designed as hardware circuit together with the PCIe bifurcation device of the application.

[0121] In the design of the PCIe bifurcation circuit, for the to-be-processed signals of the separation type of the port to the channel, the replication module can be first instantiated. If the to-be-processed signals include multiple signals and correspond to multiple ports, a replication module is instantiated for each port, so that the to-be-processed signals of the corresponding port are replicated by the instantiated replication module, the number of the replicated signals is related to the maximum number of channels supported by the corresponding port, and the multiple replicated signals are output to the instantiated splitting module.

[0122] In the instantiation of the splitting module, the internal signals of the instantiated splitting module are connected according to the bifurcated mode of the to-be-processed signals to be mapped, so that the multiple replicated signals of the same port can be split into signals of multiple channels by the instantiated splitting module.

[0123] In some optional implementation manners, the method further includes:

[0124] obtaining configuration information of the PCIe bifurcation system; wherein the configuration information includes: a conversion type of the to-be-processed signals, a bifurcated mode of the to-be-processed signals, a width of the to-be-processed signals, a maximum number of supported channels, a maximum number of supported ports, and a number of channels supported by each port; wherein the number of bifurcated mapping splitting is equal to the maximum number of supported channels.

[0125] Exemplarily, the application supports the configuration of the number of Ports and Lanes, and only needs to integrate the instantiation, to connect all to-be-processed signals to the input and output ports, to output the corresponding code logic by one key.

[0126] wherein:

[0127] 1. Support Bifurcation mode parameter configuration.

[0128] 2. Support parameter configuration of the number of input and output ports and lanes, and the maximum number of lanes in each port.

[0129] 3. Support parameter configuration of the total bit width of the signal to be processed.

[0130] 4. Support parameter configuration of invalid output port signal processing as a fixed value.

[0131] 5. Automatic RTL generation. That is, after digital design, RTL code can be automatically generated, and PCIe circuit structure can be implemented based on RTL code.

[0132] The present application fills in the corresponding.xlsx configuration file according to the conversion type of the signal to be processed, selects the configuration parameters, and one-key generates the corresponding RTL code. The configuration file is shown in Table 1:

[0133]

[0134] Table 1

[0135] Among them, "port name" is the name of the signal to be processed. If it is a port name connected to the port end, the signal name suffix is "_P", and the rest is consistent with the port name connected to the lane end, which is convenient for signal extraction and code generation of the automatic RTL generation script. "Single lane width": indicates the width of the signal to be processed; "width": the total bit width of the signal to be processed, which is determined by the parameters MNL (maximum supported lane number), MNP (maximum supported port number), NL_P (current port supported lane number) and "single lane width". The script will generate the number of internal selection logic and generate internal signals and corresponding connections according to this information; "conversion type": indicates the type of signal to be processed, which includes channel to port type L2P, port to channel separation type P2L_split and port to channel replication type P2L_replication. The script will call different functional components according to this information; "laneflip": indicates whether to call and connect the lane_flip_convert component. If it is configured not to call and connect the lane_flip_convert component, the component can be omitted.

[0136] The following takes the instantiation of the p2l_split module as an example to illustrate the above parameters:

[0137] 1. The script sets the p2l_split module instantiation parameters according to MNL and NL_P, that is, the bit width of the corresponding input and output port signals of the signal to be processed is determined.

[0138] 2. The instantiation of the p2l_split module is configured according to the MNP, i.e. the number of input and output ports is determined, and the number of lane_flip_convert instances is also determined.

[0139] 3. Then the script calls the instantiation of each module according to the Verilog syntax rules, and connects the signals between the modules according to the signal name and the logic connection rules.

[0140] Referring to Figure 6 The hierarchy of the RTL code generated by the script is described as follows:

[0141] The script extracts all the L2P type signals to be processed, and generates a l2p_wrapper for unified processing. It is determined whether the "lane flip" parameter in the configuration file is configured as l2p_lf or l2p_nlf. Whether it is configured as l2p_lf or l2p_nlf, the l2p_bif_convert (aggregation module) needs to be called for MUX mapping processing of Lane signals to Port signals. If it is configured as l2p_lf, the lane_flip_convert (downgrade flip module) is additionally called for Lane downgrade processing. If it is configured as l2p_nlf, the lane_flip_convert (downgrade flip module) is not called for Lane downgrade processing.

[0142] The script extracts all the P2L type signals to be processed, and generates a p2l_wrapper for unified processing. According to whether the configuration file is configured as split (separation type) or replication type (replication type), the p2l_split branch or the p2l_replication branch is selected for processing. In addition, it is determined whether the "lane flip" parameter in the configuration file is configured as p2l_split_lf or p2l_split_nlf. Whether it is configured as p2l_split_lf or p2l_split_nlf, the p2l_bif_convert (split module) needs to be called for MUX mapping processing of Port signals to Lane signals. If it is configured as p2l_split_lf, the lane_flip_convert is additionally called for Lane downgrade processing. If it is configured as p2l_split_nlf, the lane_flip_convert component is not called for Lane downgrade processing.

[0143] The l2p_bif_convert and the p2l_bif_convert are respectively instantiated according to a total bit width of a signal to be processed, and are internally connected through a selector according to a bifurcation mode configuration.

[0144] Exemplarily, the application utilizes a P2L_split unit to realize input of a signal in a Port unit, and then performs Lane flipping or degradation processing through a lane_flip_convert corresponding to the Port (if the lane_flip_convert is not configured to be called, the lane_flip_convert component is omitted), and then performs splitting and output of the signal to a corresponding Lane through a p2l_bif_convert according to a Bifurcation mapping. Referring to Figure 7 As shown in the figure, the unit is composed of one p2l_bif_convert and multiple lane_flip_convert. In the figure, cfg_bif_mode represents a bifurcation mode, flip_ctrl represents an input control signal of the lane_flip_convert, decides how to perform flipping or degradation processing, port*_din[DL×NL_P*-1:0] is an input signal to be processed, wherein DL represents a width of the signal to be processed, port*_data is data after channel flipping or degradation in a port, and lane*_dout[DL-1:0] represents a signal output to a channel after splitting.

[0145] Exemplarily, the application utilizes a P2L_replication unit to realize input of a signal in a Port unit, and then performs Lane flipping or degradation processing through a lane_flip_convert corresponding to the Port (if the lane_flip_convert is not configured to be called, the lane_flip_convert component is omitted), and then performs splitting and output of the signal to a corresponding Lane through a p2l_bif_convert according to a Bifurcation mapping. Referring to Figure 8 As shown in the figure, the unit is composed of one p2l_bif_convert and multiple lane_flip_convert. In the figure, cfg_bif_mode represents a bifurcation mode, flip_ctrl represents an input control signal of the lane_flip_convert, decides how to perform flipping or degradation processing, port*_din[DL×NL_P*-1:0] is an input signal to be processed, wherein DL represents a width of the signal to be processed, port*_data is data after channel flipping or degradation in a port, and lane*_dout[DL-1:0] represents a signal output to a channel after splitting.

[0146] Exemplarily, the application utilizes a P2L_split unit to realize input of a signal in a Port unit, and then performs Lane flipping or degradation processing through a lane_flip_convert corresponding to the Port (if the lane_flip_convert is not configured to be called, the lane_flip_convert component is omitted), and then performs splitting and output of the signal to a corresponding Lane through a p2l_bif_convert according to a Bifurcation mapping. Referring to Figure 9As shown, the unit is composed of 1 l2p_bif_convert and multiple lane_flip_convert (if the configuration information configures not to call lane_flip_convert, this lane_flip_convert component is omitted here). In the figure, cfg_bif_mode represents the bifurcation mode, flip_ctrl represents the input control signal of lane_flip_convert, lane*_din[DL-1:0] is the input signal to be processed, wherein port*_data represents the data corresponding to the port after aggregation, and port*_dout[DLxNL_P*-1:0] represents the output data after channel flipping or degradation in the port.

[0147] Wherein:

[0148] p2l_bif_convert: realizes the mapping of the Port input signal to the Lane signal through the Bifurcation mode.

[0149] l2p_bif_convert: realizes the mapping of the Lane signal to the Port signal through the Bifurcation mode.

[0150] replication: realizes the replication of the common information of the Port input signal according to the maximum supported Lane number.

[0151] lane_flip_convert: realizes the Lane flipping and degradation function.

[0152] The beneficial effects of the present application are as follows:

[0153] The present application solves the problem that the traditional PCIe multi-Port controller design needs special customized development of Bifurcation function logic, causing the chip development cycle to be prolonged and the verification convergence difficulty to be increased. The Lane logic resource can be maximally reused, the interactive signals between the multi-Port and the multi-Lane can be flexibly customized, the interactive signal classification batch processing (standardization, expansibility, accuracy) between the multi-Port and the multi-Lane is supported, the code is automatically generated, the mapping relationship between the multi-Port and the multi-Lane is flexibly configured, various requirements are met, the code has strong maintainability and expansibility, the code delivery cycle can be shortened by about 2-3 weeks, if frequent changes and iterations are needed, the effect is more significant, the amount of interactive signals is greatly reduced, the timing convergence difficulty and cycle are reduced, the verification coverage convergence difficulty is reduced, and the product development time is shortened.

[0154] Wherein, the effect of maximally reusing the Lane logic resource is further illustrated as follows:

[0155] Taking 8 Port multiplexing 8 Lane as an example, if the traditional design method is used, 8*8=64 Lane logics may need to be instantiated, and the application can save Lane logic resources up to (64-8) / 64=87.5%;

[0156] Exemplarily, the application also provides a PCIe bifurcation device, which comprises:

[0157] The channel-to-port conversion module is configured to, for a to-be-processed signal of a conversion type of channel-to-port, output after channel flipping or channel degradation in the corresponding port after bifurcation mapping convergence;

[0158] The first port-to-channel conversion module is configured to, for a to-be-processed signal of a separation type of a conversion type of port-to-channel, output to the corresponding channel after bifurcation mapping splitting after channel flipping or channel degradation in the corresponding port;

[0159] The second port-to-channel conversion module is configured to, for a to-be-processed signal of a copy type of a conversion type of port-to-channel, copy according to the number of channels supported by the corresponding port, and output to the corresponding channel after bifurcation mapping splitting.

[0160] In some optional implementation manners, the device further comprises:

[0161] The first design module is configured to pre-design a convergence module for bifurcation mapping convergence, and pre-design a degradation flipping module for channel flipping or channel degradation;

[0162] The channel-to-port conversion module is implemented as:

[0163] The convergence module is instantiated, and internal signals of the instantiated convergence module are connected according to the bifurcation mode corresponding to the to-be-processed signal, so as to realize bifurcation mapping convergence of the received to-be-processed signal;

[0164] The degradation flipping module is instantiated according to the maximum number of supported ports, and internal signals of the instantiated degradation flipping module are connected, so as to realize channel flipping or channel degradation of the to-be-processed signal after bifurcation mapping convergence in the port.

[0165] In some optional implementation manners, the device further comprises:

[0166] The second design module is configured to pre-design a splitting module for bifurcation mapping splitting according to the bifurcation mode, and pre-design a degradation flipping module for channel flipping or channel degradation;

[0167] The first port-to-channel conversion module is implemented as:

[0168] instantiating the downgrade flip module according to the maximum supported number of ports, and connecting internal signals of the instantiated downgrade flip module to implement lane flipping or lane downgrading of the received to-be-processed signal within a port;

[0169] instantiating the split module, and connecting internal signals of the instantiated split module according to the branching mode corresponding to the to-be-processed signal to implement split of the to-be-processed signal subjected to the branching mode mapping.

[0170] In some optional implementation manners, the apparatus further includes:

[0171] a third design module configured to pre-design a split module for split mapping and splitting according to a branching mode, and pre-design a copy module for signal copying;

[0172] The second port-to-lane conversion module is implemented as:

[0173] instantiating the copy module according to the maximum supported number of ports, and connecting internal signals of the instantiated copy module to implement copying of the received to-be-processed signal;

[0174] instantiating the split module, and connecting internal signals of the instantiated split module according to the branching mode corresponding to the to-be-processed signal to implement split of the to-be-processed signal subjected to the branching mode mapping.

[0175] In some optional implementation manners, the apparatus further includes:

[0176] a obtaining module configured to obtain configuration information of a PCIe branching system; wherein the configuration information includes: a conversion type of the to-be-processed signal, a branching mode of the to-be-processed signal, a width of the to-be-processed signal, a maximum supported number of lanes, a maximum supported number of ports, and a number of lanes supported by each port; and wherein a number of split mapping and splitting is equal to the maximum supported number of lanes.

[0177] The apparatus can be implemented by the PCIe branching method provided in the above embodiments, and the specific implementation manners can be referred to the description of the PCIe branching method in the above embodiments, which will not be described here.

[0178] It can be understood that the circuit structures, names, and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0179] Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood that modifications can be made to the foregoing embodiments, or additional implementations can be implemented, without departing from the spirit and scope of the embodiments.

Claims

1. A PCIe bifurcation method, characterized in that: include: For signals to be processed with the conversion type of channel to port, after bifurcation mapping and convergence, the channels are flipped or downgraded within the corresponding ports before being output; For signals with a port-to-channel separation conversion type, the signals are flipped or downgraded within the corresponding port and then split through bifurcation mapping before being output to the corresponding channel. For signals to be processed whose conversion type is port-to-channel replication, they are replicated according to the number of channels supported by the port to which they belong, and are output to the corresponding channels after being split through fork mapping. The method further comprises: A convergence module pre-designed for forking map convergence, and a degradation flip module pre-designed for channel flipping or channel degradation; The signal to be processed, whose conversion type is channel to port, is output after undergoing bifurcation mapping and convergence, and then undergoing channel flipping or channel degradation within the corresponding port, including: Instantiating the convergence module, and connecting internal signals of the instantiated convergence module according to the bifurcation pattern corresponding to the signal to be processed, so as to achieve bifurcation mapping and convergence of the received signal to be processed; According to the maximum number of ports supported, the degradation flip module is instantiated, and the internal signals of the instantiated degradation flip module are connected to realize channel flipping or channel degradation of the to-be-processed signal after the bifurcated mapping convergence within the port.

2. The PCIe bifurcation method according to claim 1, wherein: The method further comprises: A splitting module is pre-designed to split the fork mapping according to the fork pattern, and a degradation flipping module is pre-designed to perform channel flipping or channel degradation; For a signal to be processed whose conversion type is port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, the signal is split through bifurcation mapping and then output to the corresponding channel, including: Instantiate the degradation flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated degradation flip module to implement channel flipping or channel degradation of the received signal to be processed within the port; The splitting module is instantiated, and internal signals of the instantiated splitting module are connected according to the bifurcation pattern corresponding to the signal to be processed, so as to realize bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

3. The PCIe bifurcation method according to claim 1, wherein: The method further comprises: A splitting module is pre-designed to split the bifurcation map according to the bifurcation pattern, and a copying module is pre-designed to copy the signal; For the signal to be processed whose conversion type is port-to-channel replication type, the signal is replicated according to the number of channels supported by the port to which it belongs, and is output to the corresponding channel after being split through bifurcation mapping, including: Instantiating the replication module according to the maximum number of supported ports, and connecting internal signals of the instantiated replication module to replicate the received signal to be processed; The splitting module is instantiated, and internal signals of the instantiated splitting module are connected according to the bifurcation pattern corresponding to the signal to be processed, so as to realize bifurcation mapping splitting of the copied signal to be processed.

4. The PCIe bifurcation method according to any one of claims 1 to 3, wherein: The method further comprises: Obtain configuration information of the PCIe bifurcation system; wherein the configuration information includes: the conversion type of the signal to be processed, the bifurcation mode of the signal to be processed, the width of the signal to be processed, the maximum number of channels supported, the maximum number of ports supported, and the number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

5. A PCIe bifurcation device, characterized in that: include: The channel-to-port conversion module is configured to perform channel flipping or channel degradation within the corresponding port and then output the signal to be processed after bifurcation mapping and convergence for the signal of channel-to-port conversion type; The first port-to-channel conversion module is configured to, for a signal to be processed whose conversion type is port-to-channel separation type, perform channel flipping or channel degradation within the corresponding port, split the signal through bifurcation mapping, and then output the signal to the corresponding channel; The second port-to-channel conversion module is configured to replicate the signal to be processed according to the number of channels supported by the corresponding port for the conversion type of port-to-channel replication, and output the signal to the corresponding channel after splitting through bifurcation mapping; The device further comprises: The first design module is configured as a convergence module for pre-designing bifurcated mapping convergence, and a degradation flip module for pre-designing channel flipping or channel degradation; The channel-to-port conversion module is implemented as follows: Instantiating the convergence module, and connecting internal signals of the instantiated convergence module according to the bifurcation pattern corresponding to the signal to be processed, so as to achieve bifurcation mapping and convergence of the received signal to be processed; According to the maximum number of ports supported, the degradation flip module is instantiated, and the internal signals of the instantiated degradation flip module are connected to realize channel flipping or channel degradation of the to-be-processed signal after the bifurcated mapping convergence within the port.

6. The PCIe bifurcation device according to claim 5, wherein: The device further comprises: The second design module is configured to pre-design a splitting module for performing bifurcation mapping splitting according to a bifurcation pattern, and a degradation flipping module for pre-designing channel flipping or channel degradation; The first port-to-channel conversion module is implemented as follows: Instantiate the degradation flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated degradation flip module to implement channel flipping or channel degradation of the received signal to be processed within the port; The splitting module is instantiated, and internal signals of the instantiated splitting module are connected according to the bifurcation pattern corresponding to the signal to be processed, so as to realize bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

7. The PCIe bifurcation device according to claim 5, wherein: The device further comprises: A third design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation pattern, and a replication module for replicating a signal; The second port-to-channel conversion module is implemented as follows: Instantiating the replication module according to the maximum number of supported ports, and connecting internal signals of the instantiated replication module to replicate the received signal to be processed; The splitting module is instantiated, and internal signals of the instantiated splitting module are connected according to the bifurcation pattern corresponding to the signal to be processed, so as to realize bifurcation mapping splitting of the copied signal to be processed.

8. The PCIe bifurcation device according to any one of claims 5 to 7, wherein: The device further comprises: An acquisition module is configured to obtain configuration information of a PCIe bifurcation system; wherein the configuration information includes: a conversion type of the signal to be processed, a bifurcation mode of the signal to be processed, a width of the signal to be processed, a maximum number of channels supported, a maximum number of ports supported, and a number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

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