Chip virtual filling structure adding method, device, electronic device and storage medium

Abstract

The present invention provides a chip virtual filling structure adding method, device, electronic device and storage medium, which relates to the field of chip design technology. The method comprises: obtaining the optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include the optimal number of partitions corresponding to the target chip and the optimal number of processors corresponding to a single partition; determining the filling partition area corresponding to the target chip; the filling partition area does not include the unchanged area; partitioning the filling partition area to obtain the optimal number of partitions; configuring the optimal number of processors for each partition, and controlling each processor to add virtual filling structures to the corresponding partition in parallel. The present invention can shorten the time for adding virtual filling structures and improve the efficiency of chip confirmation work.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip virtual filling structure adding method, device, electronic equipment and storage medium. Background Art

[0002] In the CMP (Chemical Mechanical Polishing) process of modern chip physical design, it is usually necessary to add dummy structures to the metal layer, active layer and polysilicon layer to control the density of the surrounding area so that defects will not be caused by stress deviations in different layers during chip manufacturing. Therefore, accurately adding dummies is crucial to the manufacturability of the chip.

[0003] At present, chip confirmation requires multiple rounds of iterations. The number of iterations determines the quality of chip violation convergence, and the number of iterations depends on the duration of each iteration. That is, the shorter the iteration duration, the more rounds of chip repair, and the higher the chip quality. In each round of iteration, the physical verification and timing check of the full chip rely on the data after the dummy is added to the full chip. The dummy addition takes a long time in each round of iteration. For example, for an area of ​​200mm 2 For chips of about 100 μm, the process of adding dummy takes 12 to 20 hours. The long time of adding dummy leads to low efficiency of chip confirmation. Therefore, how to reduce the time of adding dummy is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a chip dummy filling structure adding method, device, electronic device and storage medium, which are used to solve the defect in the prior art that the dummy adding time is long, resulting in low efficiency of chip confirmation work.

[0005] The present invention provides a chip virtual filling structure adding method, comprising the following steps.

[0006] Obtaining optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition;

[0007] Determine a fill partition area corresponding to the target chip; the fill partition area does not include an unchanged area;

[0008] Partitioning the filled partition area to obtain the optimal number of partitions;

[0009] The optimal number of processors is configured for each partition, and each processor is controlled to add virtual filling structures to the corresponding partition in parallel.

[0010] According to the chip virtual filling structure adding method provided by the present invention, the obtaining of the optimal configuration parameters corresponding to the target chip includes:

[0011] In a case where the current iteration round is the first iteration round, determining the optimal configuration parameters corresponding to the target chip based on at least two preset partition numbers corresponding to the target chip and the processor allocation numbers corresponding to each of the preset partition numbers;

[0012] In the case that the current iteration round is not the first iteration round, the optimal configuration parameters corresponding to the first iteration round are determined as the optimal configuration parameters of the current iteration round.

[0013] According to the chip virtual filling structure adding method provided by the present invention, the determining of the optimal configuration parameters corresponding to the target chip based on at least two preset partition numbers corresponding to the target chip and the processor allocation number corresponding to each of the preset partition numbers includes:

[0014] Based on the preset total number of processors and each of the preset partition numbers, determining the processor allocation number corresponding to each of the preset partition numbers;

[0015] Partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers;

[0016] Allocate a corresponding number of processors to each pre-partition of the preset number of divisions, and add a virtual filling structure to each pre-partition in parallel, and determine a pre-addition duration corresponding to each pre-addition parameter; each pre-addition parameter includes each preset number of divisions and a corresponding number of processors to be allocated; each pre-addition duration is a total addition completion duration for adding a virtual filling structure based on each pre-addition parameter;

[0017] The pre-adding parameters corresponding to the shortest pre-adding duration are determined as the optimal configuration parameters.

[0018] According to the chip virtual filling structure adding method provided by the present invention, the determining of the filling division area corresponding to the target chip includes:

[0019] Obtain the previous repair data corresponding to the previous iteration round;

[0020] Comparing the data corresponding to each historical partition in the previous repair data with the GDS data corresponding to the current iteration round to determine a comparison result; the GDS data is used to characterize the physical layout of the target chip;

[0021] In the case that there is an unchanged region with the same data in the comparison result, determining the remaining region of the target chip after removing the unchanged region as the filling division region corresponding to the target chip;

[0022] In the case that there is no unchanged area with the same data in the comparison result, the complete area corresponding to the target chip is determined as the filled divided area.

[0023] According to the chip virtual filling structure adding method provided by the present invention, partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers includes:

[0024] Identify at least one IP core in the target chip and edge coordinates corresponding to each IP core;

[0025] Determine the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores;

[0026] Based on each of the preset division numbers and the prohibited division area, determining a target bisector corresponding to each of the pre-added parameters;

[0027] The target chip is partitioned according to the target equally divided lines corresponding to the pre-added parameters to obtain pre-partitions corresponding to the preset partition numbers.

[0028] According to the chip virtual filling structure adding method provided by the present invention, the determination of the prohibited partitioning area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores includes:

[0029] In the case where the current layer is a metal layer of the target chip, a preset distance is expanded outward based on edge coordinates corresponding to each of the IP cores to obtain a prohibited division area corresponding to the target chip;

[0030] In the case that the current layer is a base layer in the target chip, the layout blocking area corresponding to each of the IP cores is determined as a prohibited partitioning area corresponding to the target chip.

[0031] According to the chip virtual filling structure adding method provided by the present invention, the target bisector corresponding to each of the pre-adding parameters is determined based on each of the preset division numbers and the prohibited division area, including:

[0032] For each of the preset division numbers, an initial bisector line corresponding to the target chip is determined based on the preset division number; when the initial bisector line intersects and is not tangent to the prohibited division area, based on the boundary line in the prohibited division area that is closest to the initial bisector line, the initial bisector line is updated to obtain a target bisector line corresponding to the pre-added parameter; when the initial bisector line does not intersect or is not tangent to the prohibited division area, the initial bisector line is determined as the target bisector line corresponding to the pre-added parameter.

[0033] The present invention also provides a chip virtual filling structure adding device, comprising the following modules.

[0034] The acquisition module is used to acquire the optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include the optimal number of partitions corresponding to the target chip and the optimal number of processors corresponding to a single partition.

[0035] The determination module is used to determine the filling partition area corresponding to the target chip; the filling partition area does not include the unchanged area.

[0036] A partitioning module is used to partition the filling partition area to obtain the optimal number of partitions.

[0037] The adding module is used to configure the optimal number of processors for each partition, and control each processor to add virtual filling structures to the corresponding partition in parallel.

[0038] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any of the above-mentioned chip virtual filling structure adding methods is implemented.

[0039] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the chip virtual filling structure adding method as described in any one of the above is implemented.

[0040] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the chip dummy filling structure adding method as described in any one of the above is implemented.

[0041] The chip virtual filling structure adding method, device, electronic device and storage medium provided by the present invention determine the filling partition area that does not include the unmodified area in the target chip after obtaining the optimal configuration parameters including the optimal partition number and the optimal number of processors corresponding to a single partition, partition the filling partition area according to the optimal partition number, and configure the optimal number of processors for each partition, and control each processor to add virtual filling structures to the corresponding partitions in parallel. In the present invention, a virtual filling structure is added to the filling partition area that does not include the unmodified area, saving the work of adding the virtual filling structure of the unmodified area, and the filling partition area is reasonably divided and the machine resources of each partition are reasonably allocated through the optimal configuration parameters, so as to improve the speed of adding the virtual filling structure of the filling partition area, greatly shorten the time of adding the virtual filling structure, and thus improve the efficiency of chip confirmation work. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 It is a flow chart of a method for adding a chip virtual filling structure provided in an embodiment of the present invention.

[0044] Figure 2 It is a diagrammatic diagram of a curve showing the relationship between EDA tools and the number of processors provided by the prior art.

[0045] Figure 3 It is a curve diagram of relative operating time corresponding to five groups of pre-added parameters provided in an embodiment of the present invention.

[0046] Figure 4 It is a schematic diagram of edge density control when the metal layer is dummy provided by an embodiment of the present invention.

[0047] Figure 5 It is a schematic diagram of a target bisector line corresponding to a metal layer provided in an embodiment of the present invention.

[0048] Figure 6 It is a schematic diagram of the target bisector line corresponding to the base layer provided in an embodiment of the present invention.

[0049] Figure 7 It is a schematic diagram of a filled divided area excluding undivided areas provided by an embodiment of the present invention.

[0050] Figure 8Schematic diagram of a target chip after adding a dummy barrier according to an embodiment of the present invention.

[0051] Fig. 9 It is a structural schematic diagram of a chip virtual filling structure adding device provided in an embodiment of the present invention.

[0052] Fig.10 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] In view of the problem in the prior art that it takes a long time to add a dummy filling structure, resulting in low efficiency of chip confirmation work, an embodiment of the present invention provides a method for adding a chip dummy filling structure. Figure 1 FIG. 1 is a flow chart of a method for adding a chip virtual filling structure according to an embodiment of the present invention. Figure 1 As shown, the method includes the following steps 110 to 140.

[0055] Step 110: Obtain optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition.

[0056] Figure 2 This is a graph showing the relationship between the relative running time of EDA (Electronic Design Automation) and the number of processors provided by the existing technology, such as Figure 2 As shown in the figure, the relative running time of EDA decreases with the increase of the number of processors, and tends to be stable after a certain number of processors. Therefore, the single-task multi-processor working mode is not conducive to maximizing the use of machine resources. In the ECO (Engineering Change Order) stage where machine resources are relatively abundant and time is relatively tight, it is a waste of machine resources. Based on this, in an embodiment of the present invention, by taking a balance point between machine resources and relative running time, the optimal configuration parameters corresponding to the target chip are obtained, that is, the optimal number of partitions corresponding to the target chip and the optimal number of processors corresponding to a single partition are obtained, and the multi-task multi-processor working mode is adopted to compress the time of adding dummy.

[0057] It should be noted that the target chip is a chip with an area greater than 100mm 2 Big chip.

[0058] In chip design, dummy refers to a semiconductor element or structure without function. Dummy is used to fill the blank area in the target chip and adjust the physical structure of the target chip to ensure that the structure and performance of other parts can be maintained. Adding dummy to the target chip can improve the manufacturing efficiency and chip quality of the target chip.

[0059] Further, the obtaining of the optimal configuration parameters corresponding to the target chip includes:

[0060] In a case where the current iteration round is the first iteration round, determining the optimal configuration parameters corresponding to the target chip based on at least two preset partition numbers corresponding to the target chip and the processor allocation numbers corresponding to each of the preset partition numbers;

[0061] In the case that the current iteration round is not the first iteration round, the optimal configuration parameters corresponding to the first iteration round are determined as the optimal configuration parameters of the current iteration round.

[0062] Specifically, if the current iteration round is the first iteration round, the user's input operation can be responded to, at least two preset division numbers corresponding to the target chip can be obtained, and the target chip can be partitioned according to each preset division number. The finer the regional division, the smaller the running workload of a single task, that is, the shorter the relative running time of a single task. Based on this, a balance point can be determined in machine resources and relative running time. For each pre-partition, the dummy addition time of each pre-partition can be shortened as much as possible with more processors, so as to obtain less running time as a whole, so that the addition time of dummy in the target chip is minimized. If the current iteration round is not the first iteration round, since it is still the target chip, the best configuration parameters determined in the first iteration round can continue to be used. The best configuration parameters determined in the first iteration round correspond to the least overall running time. After the best configuration parameters determined in the first iteration round are determined as the best configuration parameters corresponding to the current iteration round, the overall running time corresponding to the current iteration round is still the least.

[0063] Further, the determining the optimal configuration parameters corresponding to the target chip based on at least two preset partition numbers corresponding to the target chip and the number of processors allocated corresponding to each of the preset partition numbers includes:

[0064] Based on the preset total number of processors and each of the preset partition numbers, determining the processor allocation number corresponding to each of the preset partition numbers;

[0065] Partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers;

[0066] Allocate a corresponding number of processors to each pre-partition of the preset number of divisions, and add a virtual filling structure to each pre-partition in parallel, and determine a pre-addition duration corresponding to each pre-addition parameter; each pre-addition parameter includes each preset number of divisions and a corresponding number of processors to be allocated; each pre-addition duration is a total addition completion duration for adding a virtual filling structure based on each pre-addition parameter;

[0067] The pre-adding parameters corresponding to the shortest pre-adding duration are determined as the optimal configuration parameters.

[0068] Specifically, in an embodiment of the present invention, a dummy addition is performed in a manner similar to "multithreading", that is, the target chip is partitioned according to each preset partition number input by the user, and the preset partition number is different, and the area of ​​each pre-partition obtained is different. The preset total amount of processors is the maximum number of processors that can be configured by the electronic device. For each preset partition number, the ratio of the preset total amount of processors to each preset partition number can be determined, so as to determine the processor allocation number allocated to each pre-partition. Each preset partition number and the corresponding processor allocation number constitute a set of pre-added parameters. For each pre-added parameter, a corresponding processor allocation number processors are allocated to each pre-partition, and a preset partition number tasks are started. Each task adds dummy to the corresponding pre-partition through the processor allocation number processors, and each pre-added parameter adds dummy independently and in parallel. Afterwards, the total addition completion time corresponding to each pre-added parameter is determined as the pre-added time corresponding to the preset partition number. That is, for each group of pre-added parameters, the running time of each task corresponding to the group of pre-added parameters is compared, that is, the dummy addition time of the pre-partition corresponding to each task, and the longest running time is determined as the pre-added time corresponding to the group of pre-added parameters. After determining the pre-addition duration corresponding to each pre-addition parameter, all pre-addition durations may be sorted from short to long, and the pre-addition parameter corresponding to the pre-addition duration at the top of the sort, ie, the shortest pre-addition duration, may be determined as the optimal configuration parameter.

[0069] For example, it is taken that five groups of pre-added parameters are included, the numbers of processor partitions in the five groups of pre-added parameters are n1, n2, n3, n4 and n5 respectively, and n5>n4>n3>n2>n1, Figure 3 is a curve diagram of relative running time corresponding to five groups of pre-added parameters provided in an embodiment of the present invention, such as Figure 3 As shown, the horizontal axis represents the number of processors allocated, and the vertical axis represents the relative running time, which is used to represent the percentage of the pre-added time of different processor allocation numbers relative to the pre-added time of n1 processor allocation number. Figure 3 It can be seen that when the number of processors allocated is n3, the corresponding relative running time is the shortest. Therefore, the number of processors allocated n3 can be determined as the optimal number of processors, and the ratio of the total preset number of processors to the optimal number of processors can be determined as the optimal partition number.

[0070] Furthermore, partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers includes:

[0071] Identify at least one IP core in the target chip and edge coordinates corresponding to each IP core;

[0072] Determine the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores;

[0073] Based on each of the preset division numbers and the prohibited division area, determining a target bisector corresponding to each of the pre-added parameters;

[0074] The target chip is partitioned according to the target equally divided lines corresponding to the pre-added parameters to obtain pre-partitions corresponding to the preset partition numbers.

[0075] Specifically, when partitioning the target chip in the first round of iterations, the continuity requirement is high, and the continuity is reflected in the requirement that each pre-partition after adding dummy can be reasonably spliced. Therefore, first identify each IP core in the target chip, and identify the edge coordinates of each IP core, which are used to characterize the coverage of the IP core. According to the edge coordinates of each IP core, determine the prohibited partition area corresponding to each IP core. After that, for each preset number of partitions, the number of target bisectors corresponding to the preset number of partitions can be determined. The target bisector includes a target horizontal bisector and a target vertical bisector. For example, when the optimal number of partitions is 4, it can be determined that the target bisector includes a target horizontal bisector and a target vertical bisector, and a target horizontal bisector and a target vertical bisector intersect vertically, and the target chip can be divided into 4 pre-partitions. After determining the number of target bisectors, the position of the target bisector can be determined according to the target chip and the prohibited partition area to avoid the target bisector passing through the prohibited partition area. After determining the position of the target equally divided line, the target chip can be pre-partitioned to obtain pre-partitions corresponding to the preset number of partitions, so as to facilitate the subsequent determination of the optimal configuration parameters.

[0076] It should be noted that IP core (Intellectual Property core) refers to a verified design module with specific circuit functions. IP cores are reusable and can be transplanted to semiconductors with different processes to produce chips.

[0077] Optionally, for each IP core, the upper left corner coordinates and the lower right corner coordinates of the IP core, or the lower left corner coordinates and the upper right corner coordinates of the IP core, or the four corner coordinates of the IP core can be identified to determine the edge coordinates of the IP core, which is not limited in this embodiment of the present invention.

[0078] Further, the determining the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores includes:

[0079] In the case where the current layer is a metal layer of the target chip, a preset distance is expanded outward based on edge coordinates corresponding to each of the IP cores to obtain a prohibited division area corresponding to the target chip;

[0080] In the case that the current layer is a base layer in the target chip, the layout blocking area corresponding to each of the IP cores is determined as a prohibited partitioning area corresponding to the target chip.

[0081] Specifically, when adding dummies to the target chip, the metal layer and the base layer are added in parallel, and the rules for adding dummies to different layers are different. For the metal layer, the distance between the added dummies and each IP core must be greater than or equal to the preset distance, and the edge density needs to be controlled when adding dummies after partitioning to ensure that no physical design rule check violations occur after multiple partitions are merged. For example, Figure 4 Schematic diagram of edge density control when the metal layer is dummy provided by an embodiment of the present invention, such as Figure 4 As shown, if the distance 1 between the horizontal dividing line and the IP core is less than the preset distance, the existing dummy adding tool will not add dummies on this side of module 1 (Module1), and if the distance 2 is also less than the preset distance, then dummies will not be added on this side of module 3 (Module3). However, distance 3 = distance 1 + distance 2. After adding dummies to module 1 (Module1) and module 3 (Module3) respectively and merging them, since distance 3 is greater than the preset distance, a Design Rule Check (DRC) violation will occur. Therefore, after determining the edge coordinates of each IP core, based on each edge coordinate, the preset distance is expanded outward in the horizontal direction and the vertical direction respectively, and then the prohibited partition area corresponding to each IP core is obtained. The prohibited partition areas corresponding to each IP core are merged to obtain the prohibited partition area corresponding to the target chip.

[0082] For the base layer, it is required that the target bisection line cannot cut the placement blockage area corresponding to each IP core. The layout blockage area is an area that restricts the placement of standard cells, macro cells or dummies. By defining the layout blockage area, the density of the target chip can be effectively controlled, and the layout and performance of the target chip can be optimized. If the layout blockage area is divided, the rationality of the subsequent dummy splicing cannot be guaranteed, and physical design rule check violations are likely to occur. Therefore, after determining the edge coordinates of each IP core, the layout blockage area corresponding to the IP core can be identified. The layout blockage area includes the area where the IP core is located and the external blockage area outside the IP core. Afterwards, the circumscribed rectangle corresponding to the layout blockage area is determined as the prohibited division area corresponding to each IP core, and the prohibited division areas corresponding to each IP core are merged to obtain the prohibited division area corresponding to the target chip.

[0083] Furthermore, the determining of the target bisector corresponding to each of the pre-added parameters based on each of the preset division numbers and the prohibited division area includes:

[0084] For each of the preset division numbers, an initial bisector line corresponding to the target chip is determined based on the preset division number; when the initial bisector line intersects and is not tangent to the prohibited division area, based on the boundary line in the prohibited division area that is closest to the initial bisector line, the initial bisector line is updated to obtain a target bisector line corresponding to the pre-added parameter; when the initial bisector line does not intersect or is not tangent to the prohibited division area, the initial bisector line is determined as the target bisector line corresponding to the pre-added parameter.

[0085] For example, Figure 5 is a schematic diagram of a target bisector corresponding to a metal layer provided in an embodiment of the present invention, such as Figure 5 As shown in the figure, taking the optimal number of divisions as 4 as an example, it can be determined that the initial bisector includes an initial horizontal bisector and an initial vertical bisector. Then, a vertical bisector point is determined in the vertical direction of the target chip, and the line between the two vertical bisector points is determined as the initial horizontal bisector. Similarly, a horizontal bisector point is determined in the horizontal direction of the target chip, and the line between the two horizontal bisector points is determined as the initial vertical bisector. Then, it is determined whether the initial horizontal bisector and the initial vertical bisector cross the prohibited division area. By Figure 5 From (a) in , it can be seen that the initial horizontal bisector does not intersect or touch the prohibited partitioning area in the horizontal direction, that is, the initial horizontal bisector is outside the prohibited partitioning area. At this time, the initial horizontal bisector can be determined as the target horizontal bisector of the target chip. Figure 5From (b) in the figure, we can see that the initial vertical bisector intersects with the prohibited division area in the vertical direction, which is inconsistent with the division rule of the metal layer. At this time, two vertical boundary lines in the prohibited division area in the vertical direction can be determined, and the horizontal distances between the two vertical boundary lines and the initial vertical bisector are determined respectively. The closest horizontal distance is determined from the two horizontal distances, and the boundary line corresponding to the closest horizontal distance is determined as the latest target vertical bisector.

[0086] also, Figure 6 is a schematic diagram of the target bisector line corresponding to the base layer provided by an embodiment of the present invention, such as Figure 6 As shown, taking the optimal number of divisions as 4 as an example, the area A outside the IP core is the external blocking area of ​​the IP core, and the external blocking area and the area B where the IP core is located constitute the layout blocking area corresponding to the IP core. The target bisector line corresponding to the base layer can be determined by referring to the step of determining the target bisector line of the metal layer, and the embodiments of the present invention will not be repeated here.

[0087] It should be noted that the target bisector may coincide with the boundary line of the prohibited area, but may not pass through the prohibited area.

[0088] In addition, after determining the optimal number of divisions, the target dividing line corresponding to the optimal number of divisions can be determined as the optimal dividing line, and the optimal dividing line can be used for partitioning in subsequent non-first round iterations.

[0089] Step 120: Determine the filling partition area corresponding to the target chip; the filling partition area does not include the unchanged area.

[0090] Specifically, the repair progress of different areas in the target chip is different in each iteration round, and each area cannot participate in each round of full-chip physical design inspection. If the dummy addition process in each iteration round is a reversal and redo of the previous iteration round, the re-addition of dummy in the unchanged area of ​​the target chip will waste a long time. Therefore, in an embodiment of the present invention, in the current iteration round, the unchanged area in the target chip is identified, so as to determine the filled partition area that does not include the unchanged area, so as to facilitate the addition of dummy to the filled partition area.

[0091] Optionally, the unchanged area may be an area to which a dummy has been added in the previous round but not updated, or an area to which a dummy has been added and frozen in the merge phase before chip confirmation. The frozen area has no problem with its own data and does not need to be updated, but needs to be merged with other areas to observe the status of the entire chip. The embodiment of the present invention is not limited to this.

[0092] Further, the determining the filling partition area corresponding to the target chip includes:

[0093] Obtain the previous repair data corresponding to the previous iteration round;

[0094] Comparing the data corresponding to each historical partition in the previous repair data with the GDS data corresponding to the current iteration round to determine a comparison result; the GDS data is used to characterize the physical layout of the target chip;

[0095] In the case that there is an unchanged region with the same data in the comparison result, determining the remaining region of the target chip after removing the unchanged region as the filling division region corresponding to the target chip;

[0096] In the case that there is no unchanged area with the same data in the comparison result, the complete area corresponding to the target chip is determined as the filled divided area.

[0097] Specifically, in order to identify the unchanged area in the target chip, the previous repair data after the full chip physical design check in the previous iteration round can be obtained, and the previous repair data includes the data corresponding to each historical partition in the previous iteration round. The data is compared with the GDS (Graphic Data System) data corresponding to the current iteration round. If the data is the same, it means that the partition corresponding to the data has not been repaired in the previous iteration round. The partition corresponding to the data can be determined as the unchanged area, and the position information of the unchanged area is determined through the DEF (Design ExchangeFormat) file corresponding to the current iteration round. The unchanged area is eliminated in the target chip according to the position information, and the remaining area in the target chip except the unchanged area is determined as the fill partition area corresponding to the target chip. For example, Figure 7 is a schematic diagram of a filled partition area excluding unpartitioned areas provided by an embodiment of the present invention, such as Figure 7 As shown in the figure, Freeze tile 1 and Freeze tile 2 are the unchanged areas, and the remaining areas are the filling partition areas. If the data are different, it means that all partitions have been repaired in the previous iteration round. At this time, the complete area corresponding to the target chip can be determined as the filling partition area.

[0098] Before executing step 130, and after the target chip has merged the GDS files corresponding to all regions, dummy blocks are added at the four corners of the target chip. The dummy blocks are triangular regions. No dummy blocks need to be added in the dummy block regions, thereby protecting key components and ensuring the consistency of chip manufacturing, reducing defects in the chip manufacturing process, and improving chip production efficiency and quality. Figure 8 is a schematic diagram of a target chip after adding a dummy barrier according to an embodiment of the present invention. Figure 8 shown.

[0099] Step 130: partition the filled partition area to obtain the optimal number of partitions.

[0100] Specifically, after determining the filling partition area, the filling partition area is partitioned using the optimal number of partitions and the optimal equal-division line in the optimal configuration parameters, and the filling partition area is divided into the optimal number of partitions, which facilitates the subsequent calling of the optimal number of partition tasks, and independently and in parallel adds dummies to each partition, greatly shortening the time for adding dummies.

[0101] Step 140: configure the optimal number of processors for each partition, and control each processor to add virtual filling structures in parallel for the corresponding partition.

[0102] After determining the optimal number of partitions, the optimal number of processors may be allocated to each partition, and a task may be started for each partition. The processors of each partition are used to add dummies to the partition. The dummy adding work of each partition is performed independently and in parallel.

[0103] According to the experimental results, it takes 10 hours to add dummy using a single-task multiprocessor. The chip virtual filling structure adding method provided by the embodiment of the present invention can compress the dummy adding time to 2 hours. This time can better plan the iteration time of the target chip ECO, and plan the time for merging actions, dummy addition and physical design rule checking in non-working hours, ensuring that the target chip is effectively repaired during working hours, and the iteration time of each iteration round is compressed to one day.

[0104] It should be noted that, for the metal layer or the base layer, when adding dummies, it is required that there is no overlap between the added dummies.

[0105] The chip virtual filling structure adding method provided by the embodiment of the present invention determines the filling partition area excluding the unmodified area in the target chip after obtaining the optimal configuration parameters including the optimal partition number and the optimal number of processors corresponding to a single partition, partitions the filling partition area according to the optimal partition number, and configures the optimal number of processors for each partition, and controls each processor to add virtual filling structures to the corresponding partitions in parallel. In the present invention, a virtual filling structure is added to the filling partition area excluding the unmodified area, saving the work of adding the virtual filling structure of the unmodified area, and reasonably divides the filling partition area and reasonably allocates the machine resources of each partition through the optimal configuration parameters, thereby improving the speed of adding the virtual filling structure of the filling partition area, greatly shortening the time of adding the virtual filling structure, and thus improving the efficiency of the chip confirmation work.

[0106] The chip dummy filling structure adding device provided by the present invention is described below. The chip dummy filling structure adding device described below and the chip dummy filling structure adding method described above can be referred to each other.

[0107] The embodiment of the present invention further provides a device for adding a chip dummy filling structure. Fig. 9 is a schematic diagram of the structure of a device for adding a chip virtual filling structure according to an embodiment of the present invention. Fig. 9 As shown, the chip dummy filling structure adding device 900 includes an acquisition module 910 , a determination module 920 , a partitioning module 930 and an adding module 940 .

[0108] The acquisition module 910 is used to acquire the optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include the optimal number of partitions corresponding to the target chip and the optimal number of processors corresponding to a single partition.

[0109] The determination module 920 is used to determine the filling partition area corresponding to the target chip; the filling partition area does not include the unchanged area.

[0110] The partitioning module 930 is used to partition the filling partition area to obtain the optimal number of partitions.

[0111] The adding module 940 is used to configure the optimal number of processors for each partition, and control each processor to add virtual filling structures for the corresponding partition in parallel.

[0112] The chip virtual filling structure adding device provided by the embodiment of the present invention determines the filling partition area excluding the unmodified area in the target chip after obtaining the optimal configuration parameters including the optimal partition number and the optimal number of processors corresponding to a single partition, partitions the filling partition area according to the optimal partition number, and configures the optimal number of processors for each partition, and controls each processor to add virtual filling structures to the corresponding partitions in parallel. In the present invention, virtual filling structures are added to the filling partition area excluding the unmodified area, saving the work of adding virtual filling structures to the unmodified area, and reasonably divides the filling partition area and reasonably allocates the machine resources of each partition through the optimal configuration parameters, thereby improving the speed of adding virtual filling structures to the filling partition area, greatly shortening the time of adding virtual filling structures, and thus improving the efficiency of chip confirmation work.

[0113] Optionally, the acquisition module 910 is specifically configured to:

[0114] In a case where the current iteration round is the first iteration round, determining the optimal configuration parameters corresponding to the target chip based on at least two preset partition numbers corresponding to the target chip and the processor allocation numbers corresponding to each of the preset partition numbers;

[0115] In the case that the current iteration round is not the first iteration round, the optimal configuration parameters corresponding to the first iteration round are determined as the optimal configuration parameters of the current iteration round.

[0116] Optionally, the acquisition module 910 is specifically configured to:

[0117] Based on the preset total number of processors and each of the preset partition numbers, determining the processor allocation number corresponding to each of the preset partition numbers;

[0118] Partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers;

[0119] Allocate a corresponding number of processors to each pre-partition of the preset number of divisions, and add a virtual filling structure to each pre-partition in parallel, and determine a pre-addition duration corresponding to each pre-addition parameter; each pre-addition parameter includes each preset number of divisions and a corresponding number of processors to be allocated; each pre-addition duration is a total addition completion duration for adding a virtual filling structure based on each pre-addition parameter;

[0120] The pre-adding parameters corresponding to the shortest pre-adding duration are determined as the optimal configuration parameters.

[0121] Optionally, the acquisition module 910 is specifically configured to:

[0122] Identify at least one IP core in the target chip and edge coordinates corresponding to each IP core;

[0123] Determine the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores;

[0124] Based on each of the preset division numbers and the prohibited division area, determining a target bisector corresponding to each of the pre-added parameters;

[0125] The target chip is partitioned according to the target equally divided lines corresponding to the pre-added parameters to obtain pre-partitions corresponding to the preset partition numbers.

[0126] Optionally, the acquisition module 910 is specifically configured to:

[0127] In the case where the current layer is a metal layer of the target chip, a preset distance is expanded outward based on edge coordinates corresponding to each of the IP cores to obtain a prohibited division area corresponding to the target chip;

[0128] In the case that the current layer is a base layer in the target chip, the layout blocking area corresponding to each of the IP cores is determined as a prohibited partitioning area corresponding to the target chip.

[0129] Optionally, the acquisition module 910 is specifically configured to:

[0130] For each of the preset division numbers, an initial bisector line corresponding to the target chip is determined based on the preset division number; when the initial bisector line intersects and is not tangent to the prohibited division area, based on the boundary line in the prohibited division area that is closest to the initial bisector line, the initial bisector line is updated to obtain a target bisector line corresponding to the pre-added parameter; when the initial bisector line does not intersect or is not tangent to the prohibited division area, the initial bisector line is determined as the target bisector line corresponding to the pre-added parameter.

[0131] Optionally, the determination module 920 is specifically configured to:

[0132] Obtain the previous repair data corresponding to the previous iteration round;

[0133] Comparing the data corresponding to each historical partition in the previous repair data with the GDS data corresponding to the current iteration round to determine a comparison result; the GDS data is used to characterize the physical layout of the target chip;

[0134] In the case that there is an unchanged region with the same data in the comparison result, determining the remaining region of the target chip after removing the unchanged region as the filling division region corresponding to the target chip;

[0135] In the case that there is no unchanged area with the same data in the comparison result, the complete area corresponding to the target chip is determined as the filled divided area.

[0136] Fig.10 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Fig.10 As shown, the electronic device may include: a processor 1010, a communication interface 1020, a memory 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020 and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 may call the logic instructions in the memory 1030 to execute the chip virtual filling structure adding method, the method comprising:

[0137] Obtaining optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition;

[0138] Determine a fill partition area corresponding to the target chip; the fill partition area does not include an unchanged area;

[0139] Partitioning the filled partition area to obtain the optimal number of partitions;

[0140] The optimal number of processors is configured for each partition, and each processor is controlled to add virtual filling structures to the corresponding partition in parallel.

[0141] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0142] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the chip dummy filling structure adding method provided by the above methods, the method comprising:

[0143] Obtaining optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition;

[0144] Determine a fill partition area corresponding to the target chip; the fill partition area does not include an unchanged area;

[0145] Partitioning the filled partition area to obtain the optimal number of partitions;

[0146] The optimal number of processors is configured for each partition, and each processor is controlled to add virtual filling structures to the corresponding partition in parallel.

[0147] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the chip dummy filling structure adding method provided by the above methods is implemented, and the method includes:

[0148] Obtaining optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition;

[0149] Determine a fill partition area corresponding to the target chip; the fill partition area does not include an unchanged area;

[0150] Partitioning the filled partition area to obtain the optimal number of partitions;

[0151] The optimal number of processors is configured for each partition, and each processor is controlled to add virtual filling structures to the corresponding partition in parallel.

[0152] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0153] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for adding a chip virtual filling structure, characterized in that: include: Obtaining optimal configuration parameters corresponding to the target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition; Determine a fill partition area corresponding to the target chip; the fill partition area does not include an unchanged area; Partitioning the filled partition area to obtain the optimal number of partitions; configuring the optimal number of processors for each partition, and controlling each processor to add virtual filling structures in parallel for the corresponding partition; The optimal configuration parameters are determined based on the following steps: In the case where the current iteration round is the first iteration round, based on a preset total number of processors and at least two preset partition numbers corresponding to the target chip, determining the number of processors to be allocated corresponding to each preset partition number; Partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers; Allocate a corresponding number of processors to each pre-partition of the preset number of divisions, and add a virtual filling structure to each pre-partition in parallel, and determine a pre-addition duration corresponding to each pre-addition parameter; each pre-addition parameter includes each preset number of divisions and a corresponding number of processors to be allocated; each pre-addition duration is a total addition completion duration for adding a virtual filling structure based on each pre-addition parameter; The pre-adding parameters corresponding to the shortest pre-adding duration are determined as the optimal configuration parameters.

2. The chip dummy filling structure adding method according to claim 1, characterized in that: The obtaining of the optimal configuration parameters corresponding to the target chip includes: In the case that the current iteration round is not the first iteration round, the optimal configuration parameters corresponding to the first iteration round are determined as the optimal configuration parameters of the current iteration round.

3. The chip dummy filling structure adding method according to claim 1 or 2, characterized in that: The determining of the filling partition area corresponding to the target chip includes: Obtain the previous repair data corresponding to the previous iteration round; Comparing the data corresponding to each historical partition in the previous repair data with the GDS data corresponding to the current iteration round to determine a comparison result; the GDS data is used to characterize the physical layout of the target chip; In the case that there is an unchanged region with the same data in the comparison result, determining the remaining region of the target chip after removing the unchanged region as the filling division region corresponding to the target chip; In the case that there is no unchanged area with the same data in the comparison result, the complete area corresponding to the target chip is determined as the filled divided area.

4. The chip dummy filling structure adding method according to claim 1 or 2, characterized in that: Partitioning the target chip based on each of the preset partition numbers to obtain pre-partitions corresponding to each of the preset partition numbers includes: Identify at least one IP core in the target chip and edge coordinates corresponding to each IP core; Determine the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores; Based on each of the preset division numbers and the prohibited division area, determining a target bisector corresponding to each of the pre-added parameters; The target chip is partitioned according to the target equally divided lines corresponding to the pre-added parameters to obtain pre-partitions corresponding to the preset partition numbers.

5. The chip dummy filling structure adding method according to claim 4, characterized in that: The step of determining the prohibited partition area corresponding to the target chip based on the edge coordinates corresponding to each of the IP cores includes: In the case where the current layer is a metal layer of the target chip, a preset distance is expanded outward based on edge coordinates corresponding to each of the IP cores to obtain a prohibited division area corresponding to the target chip; In the case that the current layer is a base layer in the target chip, the layout blocking area corresponding to each of the IP cores is determined as a prohibited partitioning area corresponding to the target chip.

6. The chip dummy filling structure adding method according to claim 4, characterized in that: The determining, based on each of the preset division numbers and the prohibited division area, of a target bisector corresponding to each of the pre-added parameters comprises: For each of the preset division numbers, an initial bisector line corresponding to the target chip is determined based on the preset division number; when the initial bisector line intersects and is not tangent to the prohibited division area, based on the boundary line in the prohibited division area that is closest to the initial bisector line, the initial bisector line is updated to obtain a target bisector line corresponding to the pre-added parameter; when the initial bisector line does not intersect or is not tangent to the prohibited division area, the initial bisector line is determined as the target bisector line corresponding to the pre-added parameter.

7. A device for implementing the chip dummy filling structure adding method according to any one of claims 1 to 6, characterized in that: include: An acquisition module, used for acquiring optimal configuration parameters corresponding to a target chip; the optimal configuration parameters include an optimal number of partitions corresponding to the target chip and an optimal number of processors corresponding to a single partition; A determination module, used for determining a filling partition area corresponding to the target chip; the filling partition area does not include an unmodified area; A partitioning module, used for partitioning the filling partition area to obtain the optimal number of partitions; The adding module is used to configure the optimal number of processors for each partition, and control each processor to add virtual filling structures to the corresponding partition in parallel.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the chip dummy filling structure adding method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip dummy filling structure adding method according to any one of claims 1 to 6 is implemented.

Images