Method for deadlock checking of integrated circuits
By generating security and activity attributes in integrated circuits and marking transfer paths, the high complexity of integrated circuit deadlock detection is solved, enabling fast and automated deadlock detection.
Patent Information
- Application Number
- CN202411593648.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2044-11-08
AI Technical Summary
Existing technologies cannot quickly and effectively detect deadlock problems in integrated circuit designs, and simulation technology is computationally complex and incomplete.
By generating safety and liveness attributes, the transition paths of the finite state machine are marked. All paths are traversed to determine if deadlock exists. Path states are marked with characters to automatically check for deadlock.
It achieves fast and complete deadlock checking, reduces computational complexity to N2, and avoids the need to write test stimuli and iteration cycles.
Smart Images
Figure CN119476151B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of formal verification of integrated circuits, and in particular to a deadlock checking method of integrated circuits. BACKGROUND
[0002] Deadlock refers to a state that an integrated circuit design enters and never escapes, or a state that an integrated circuit design enters and stays in due to avoiding the opportunity to escape.
[0003] It is almost impossible to check deadlock in an integrated circuit design through simulation technology, mainly for the following reasons: 1) it is impossible to directly detect whether the design is deadlocked as in simulation; 2) it is impossible to determine through simulation whether the design enters a state that never escapes or stays in the state due to some reason; 3) a correct stimulus must be provided to find deadlock through simulation. The computational complexity of checking deadlock through simulation technology is N*f(T), where N is the number of states of a finite state machine, and f(T) is the number of periods of jumps of the finite state machine. In order to ensure the completeness of the check, f(T) will be much larger than N, and thus the cost of finding deadlock through simulation is very high.
[0004] Therefore, how to quickly check deadlock in an integrated circuit design is a technical problem to be solved. SUMMARY
[0005] In order to solve the technical problem that deadlock in an integrated circuit cannot be quickly checked in the prior art, the present application provides a deadlock checking method of an integrated circuit.
[0006] The deadlock checking method of the integrated circuit provided by the present application comprises:
[0007] generating a safety property according to each reachable state of a state, and generating a liveness property according to each state transition condition;
[0008] marking a transition path existing between all states, and marking a transition path passing through the safety property and the liveness property as a first mark;
[0009] traversing all transition paths, for a currently traversed transition path, judging whether there is a transition path of the first mark between states at both ends of the currently traversed transition path, if not, marking the currently traversed transition path as a second mark, and if so, judging whether there is a transition path from the first mark to the second mark between states at both ends of the currently traversed transition path, if so, marking the currently traversed transition path as the second mark, and if not, marking the currently traversed transition path as the first mark;
[0010] after all transition paths are traversed, judging whether there is deadlock in the integrated circuit according to the marks of all transition paths.
[0011] Further, the first mark and the second mark are represented by at least one character respectively.
[0012] Further, when marking the safe property and the live property through the transfer path, the rest of the transfer path is marked as a temporary mark.
[0013] Further, the temporary mark is represented by at least one character.
[0014] Further, the character includes at least one of a number, a letter, a Chinese character and a symbol.
[0015] Further, judging whether the integrated circuit has a deadlock according to the marks of all the transfer paths includes:
[0016] When the mark of the transfer path is the second mark, it is determined that the integrated circuit has a deadlock.
[0017] Further, judging whether the integrated circuit has a deadlock according to the marks of all the transfer paths includes:
[0018] When the mark of the transfer path is the first mark, it is determined that the integrated circuit does not have a deadlock.
[0019] The present application automatically generates a safe property and a live property by extracting reachable states and transfer conditions of a finite state machine, marks a known safe transfer path, performs transfer path traversal, marks a transfer path when there is a possible deadlock, updates when there is no possible deadlock, and finally determines whether there is a deadlock according to the final mark of the transfer path, thereby achieving the effect of automatically checking a deadlock. Compared with simulation technology, the present application does not need to write a test excitation and does not need to iterate different periods, and checks a deadlock problem more completely by traversing the entire state space. In addition, compared with the calculation complexity of simulation, the calculation complexity of the present application is N 2 , where N is the number of states of the finite state machine, and the longer the simulation period, the more obvious the advantage of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0020] The present application will be described in detail below with reference to the embodiments and the accompanying drawings, in which:
[0021] Figure 1 is a flow chart of an embodiment of the present application.
[0022] Figure 2 is a state transfer schematic diagram of a finite state machine of an embodiment of the present application.
[0023] Figure 3 is a mark schematic diagram in a path traversal process of an embodiment of the present application. DETAILED DESCRIPTION
[0024] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.
[0025] Thus, one feature described in the specification will be used to illustrate one feature of one embodiment of the present application, rather than implying that every embodiment of the present application must have the described feature. In addition, it should be noted that the present specification describes many features. Although some features can be combined together to show possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.
[0026] As shown in Figure 1 The integrated circuit deadlock checking method provided by the present application mainly includes the following steps.
[0027] Extracting the finite state machine in the design file of the integrated circuit.
[0028] Determining the reachable states of the finite state machine and the state transition conditions of each state.
[0029] For example, assuming that the finite state machine has three states A, B and C, the next state of A is B, and the jump condition is that the input is 1. Then for A, B is its reachable state, and the state transition condition is that the input is 1.
[0030] Generating safety properties according to the reachable states of each state, and generating liveness properties according to the state transition conditions of each state.
[0031] For example, the finite state machine has three states A, B and C, and the next state of A is B. Then for A, its safety property is that the next state of A will not be A or C. If the finite state machine has three states A, B and C, and the next state of A is B, then for A, its liveness property is that the next state of A will eventually be B.
[0032] Marking the transition paths between all states, and marking the transition paths passed by the safety properties and the liveness properties as first marks. Since the transition paths involved in the safety properties and the liveness properties will not have deadlocks, the transition paths can be marked as first marks at this time, i.e. a mark that does not exist deadlock.
[0033] Traverse all the transition paths, for the current traversed transition path, judge whether the states at both ends of the transition path exist the first marked transition path, if not, mark the current traversed transition path as the second mark, if yes, judge whether the states at both ends of the transition path exist the transition path from the first mark to the second mark, if yes, mark the current traversed transition path as the second mark, otherwise mark it as the first mark. In the specific implementation, the transition path related to the start state can be traversed.
[0034] After all the transition paths are traversed, judge whether the integrated circuit exists the deadlock according to the marks of all the transition paths.
[0035] The present application extracts the finite state machine of the integrated circuit, then generates the corresponding safety attribute and activity attribute, then marks each transition path, and updates the mark of the transition path according to the states at both ends of the transition path, finally judges whether the deadlock exists through the mark of the transition path, compared with the prior art, the present application is simpler and easier to implement.
[0036] In one embodiment, the first mark and the second mark are represented by at least one character respectively.
[0037] The implementation of the present application can finally be realized by programming to automatically check the deadlock, thus at least one character is used to represent, which is beneficial to the automatic implementation.
[0038] In one embodiment, when marking the transition path passed by the safety attribute and the activity attribute, the remaining transition paths are marked as temporary marks.
[0039] Since the other transition paths are uncertain, in order to facilitate observation, the other transition paths can be marked as temporary marks first.
[0040] Similarly, the temporary mark can also be represented by at least one character.
[0041] The characters of the present application include at least one of numbers, letters, Chinese characters and symbols. For example, the first mark is represented by 1, the temporary mark is represented by 0, and the second mark is represented by 2, etc., and those skilled in the art can design the marks according to their own naming habits.
[0042] In a further embodiment, judging whether the integrated circuit exists the deadlock according to the marks of all the transition paths comprises:
[0043] When the mark of the transition path exists the second mark, it is determined that the integrated circuit exists the deadlock.
[0044] When the marks of the transition paths are all the first marks, it is determined that the integrated circuit does not exist the deadlock.
[0045] Suppose that a finite state machine as shown in Figure 2 is extracted from an integrated circuit.
[0046] It can be seen that the finite state machine has four states, start, IDLE, (CLEAR) and STOP, and the next state of the state Start can be Start itself, IDLE or STOP, the transition condition from the state START to the state IDLE is!rst_n, and the transition condition from the state START to the state STOP is A==0, wherein rst_n and A are variables.
[0047] Thus, a safety property can be generated: the next state of the state START will not be the state CLEAR.
[0048] If the arrow between START and STOP is taken as the current traversed transition path X, the states at the two ends of the transition path X are START and STOP, and the START corresponds to three transition paths, path 1: START→START, path 2: START→IDEL and path 3: START→STOP.
[0049] As shown in Figure 3 , if the verification of the safety property and the liveness property is performed, the paths 1 and 2 pass, and are marked as 1, and the path 3 does not pass, and is marked as 0, because the path 3 is not marked as 1, the path 3 is marked as 2. If there is a path marked as 2 in the finite state machine, the finite state machine has a deadlock.
[0050] The above only describes the preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A deadlock detection method for integrated circuits, characterized in that, include: Extract the finite state machine from the integrated circuit design file; Determine the states that the finite state machine can reach, and the transition conditions for each state; A security attribute is generated based on the reachable states for each state, and an activity attribute is generated based on each state transition condition. All transition paths existing between states are marked. The transition paths through which the security attribute and the activity attribute pass are marked as the first mark, and the remaining transition paths are marked as temporary marks. Iterate through all transition paths. For the currently traversed transition path, check if there is a transition path with the first mark at both ends. If not, mark the currently traversed transition path with the second mark. If it exists, check if there is a transition path with the first mark at both ends that changes to the second mark. If it exists, mark the currently traversed transition path with the second mark; otherwise, mark it with the first mark. After all transfer paths have been traversed, the presence of deadlock in the integrated circuit is determined based on the markings of all transfer paths, including: if a transfer path has a second marking, then the integrated circuit is determined to be deadlocked. If all the markers on the transfer path are the first marker, then the integrated circuit is determined not to be deadlocked.
2. The deadlock detection method for integrated circuits as described in claim 1, characterized in that, The first mark and the second mark are each represented by at least one character.
3. The deadlock detection method for integrated circuits as described in claim 1, characterized in that, The temporary marker is represented by at least one character.
4. The deadlock detection method for integrated circuits as described in claim 2 or 3, characterized in that, The characters include at least one of numbers, letters, Chinese characters, and symbols.
Citation Information
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