An AMS circuit automatic design method using large language models

Abstract

The present invention relates to the field of electronic design automation (EDA) and provides an AMS circuit automatic design method using a large language model. This method aims to address the problem of insufficient automation in existing AMS circuit design. The main steps include extracting circuit schematics and text descriptions from literature, constructing a data set containing circuit schematics, netlists, and annotation information; performing connectivity testing on the circuit schematics and extracting netlists; performing annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; using a large language model to obtain design strategies and describe circuit architectures; retrieving relevant circuits and test platforms based on design strategies and local annotations, assembling a complete circuit topology, and performing simulations; performing size optimization based on constraints and solving using a Bayesian optimization algorithm; and performing topology reconstruction if the initial topology fails to meet performance targets. The present invention improves the automation level and efficiency of analog and mixed-signal circuit design.

Description

Technical Field

[0001] The present invention relates to the field of automatic AMS circuit design and provides an automatic AMS circuit design method using a large language model. Background Art

[0002] Digital circuit synthesis technology has been widely used in the field of electronic design automation (EDA), enabling modern large-scale digital integrated circuits (ICs) to comply with Moore's Law. However, the level of automation in analog and mixed-signal (AMS) circuit design lags significantly behind that of digital circuit design. Currently, AMS circuits are primarily designed using a full-custom approach, and the design process still heavily relies on human experts to determine circuit topology and component sizing. This time-consuming and labor-intensive design process significantly limits the scalability of AMS circuits.

[0003] Large language models (LLMs) have recently demonstrated great potential in addressing various electronic design automation (EDA) challenges, offering new possibilities for the automated design of analog and mixed-signal (AMS) circuits. Artisian utilizes LLMs for the automated design of AMS circuits. However, their proposed method is only applicable to operational amplifier circuits and cannot be directly generalized to other types of circuits, resulting in poor versatility. This poor versatility primarily refers to the limitations of the large language models (LLMs) used by Artisian in the automated design of analog and mixed-signal (AMS) circuits. Specifically, this method's poor versatility is reflected in the following aspects:

[0004] Limitations to Specific Circuit Types: Artisian's approach is primarily targeted at operational amplifier circuit design, which limits its applicability. Because different AMS circuit types have different design requirements and performance metrics, this approach cannot be directly applied to other circuit types, such as comparators and filters.

[0005] Behavioral-level design limitations: This method can only generate behavioral-level circuits, describing the circuit's behavior at a high level, and cannot be directly converted to precise transistor-level circuits. In practical applications, behavioral-level circuits need to be further converted to transistor-level circuits, a process that can increase the number of transistors and reduce design efficiency.

[0006] Parameter design limitations: Artisian's approach only provides circuit topology, but does not include the design of key parameters such as transistor size. In actual AMS circuit design, transistor size has a significant impact on circuit performance, so the lack of this key step limits the practical application of the design solution.

[0007] Lack of generalization: Because the method relies on a specific type of circuit and design requirements, its generalization ability is limited when faced with new or different design scenarios. This means that the method cannot be easily adapted and optimized for other types of AMS circuit designs.

[0008] In summary, the limitations of Artisian's method in terms of versatility, design efficiency and parameter design restrict its application in the field of automatic design of analog and mixed-signal circuits. Summary of the Invention

[0009] The purpose of the present invention is to solve the problem that the existing technology only provides behavioral-level operational amplifier circuits, and modeling the behavioral-level circuits to transistor-level circuits will cause the number of transistors to exceed that of directly designing transistor-level circuits, resulting in low design efficiency.

[0010] The technical solution adopted by the present invention to solve the above-mentioned technical problems is:

[0011] An automatic circuit design method using an AMS language model includes the following steps:

[0012] Step 1: Extract circuit schematics and text descriptions from the original literature to obtain circuit schematics, netlists, and annotation information for constructing the AMSnet-KG knowledge graph;

[0013] The steps in Step 1 include:

[0014] Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset.

[0015] Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are annotated on a subset of page images and an object detection model is trained to identify and extract all circuit schematics on the remaining pages.

[0016] Step 1.3: Leverage the uniformity of printed schematics from the literature for template matching. Manually annotate one copy of each component type and quickly identify other identical components through template matching.

[0017] Step 1.4: Label each direction of each component category, including direction information for determining component connections;

[0018] Step 1.5: Use the template matching data to train the model and apply it to annotate the remaining circuit schematics.

[0019] Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirements, and obtain the position labels and category labels of all components in the circuit schematic;

[0020] Step 1.7. Output a dataset containing circuit schematics, netlists, and annotation information for constructing the AMSnet-KG knowledge graph.

[0021] Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist;

[0022] The steps in Step 2 include:

[0023] Step 2.1, perform component identification processing on the circuit schematic to obtain component annotations;

[0024] Step 2.2: Perform network cable identification processing on the component labels to obtain a netlist;

[0025] Step 2.2.1. Traverse each component annotation in the circuit schematic to identify the connection relationship between the components.

[0026] Step 2.2.2: Classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rule is that all wires are represented by solid lines, and wires that intersect but do not have intersection points are not considered connected.

[0027] Step 2.2.3: Perform an extended search on the wire pixels around each component until other components or boundaries are encountered to form a component cluster.

[0028] Step 2.2.4: Analyze each component cluster to determine its connectivity:

[0029] Step 2.2.4.1: If the cluster contains only the starting component, mark it as no connectivity detected.

[0030] Step 2.2.4.2. If the cluster contains exactly two components, mark these two components as connected.

[0031] Step 2.2.4.3. If the cluster contains an odd number of components, and it is greater than two, mark the circuit diagram as abnormal and require manual inspection.

[0032] Step 2.2.4.4. If the cluster contains an even number of components, and it is greater than two, assume that the circuit diagram has no missing nodes and the intersecting wires are not connected.

[0033] Step 2.2.5: Apply a 2D convolution to the searched wires to locate the intersection. The convolution kernel dimensions are adjusted based on the line thickness and layout.

[0034] Step 2.2.6: The index of the maximum pixel density near the intersection point is considered as the intersection point and added to the component annotation;

[0035] Step 2.2.7. Repeat the grouping process, connecting each component in the group to the intersection point to eliminate the four-component cluster;

[0036] Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group.

[0037] Step 2.2.9. Rearrange the relative connections, delete the intersections, and complete the network cable identification process.

[0038] Step 2.2.10. For some components, correctly order the connections according to the SPICE netlist format requirements. For example, the connections of a four-terminal MOSFET must follow the order of drain, gate, source, and body / substrate.

[0039] Step 2.2.11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection.

[0040] Step 2.2.12. For the symbol, use MLLM to determine the function of each pin;

[0041] Step 2.2.13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96% and manually correct any erroneous results to ensure data quality.

[0042] Step 2.2.14. Output a netlist containing circuit components, symbols, and net lines.

[0043] Step 3: Annotate the circuit schematic and netlist to obtain annotation information;

[0044] The steps in Step 3 include:

[0045] Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include:

[0046] Label each component in the circuit schematic, including identifying the network wires as input, bias, and output;

[0047] Labeling groups of components, such as identifying a group of components as a building block, including a current mirror or a differential pair;

[0048] Dimensioning constraints, marking certain sets of components to follow symmetry constraints such as length and width;

[0049] Label the nets that connect the circuit's pins to the testbench.

[0050] Step 3.2: Perform MLLM generation on the circuit schematic and netlist to obtain global annotations. The operations include:

[0051] The qualitative descriptions are summarized into key-value pairs using a multilingual large language model (MLLM), including: {gain: high} or {load: current mirror};

[0052] Generate JSON files to introduce more structure in annotation information;

[0053] Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph;

[0054] Step 3.5: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and the obtained local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing the complete circuit design information.

[0055] Step 4: Build a knowledge graph for the circuit schematic, netlist, and annotation information to obtain AMSnet-KG.

[0056] The steps in Step 4 include:

[0057] Step 4.1: Perform entity relationship definition processing on the circuit schematic, netlist, and annotation information to obtain a knowledge graph structure;

[0058] Step 4.1.1. Entity definition

[0059] Define entities as strings or circuits;

[0060] String entities are used to represent circuit components, test platforms, etc., such as "NMOS", "PMOS", or circuit structure functions.

[0061] A circuit entity is used to represent a complete circuit topology, including information such as schematics, netlists, local annotations, and global annotations.

[0062] Step 1.4.2: Relationship Definition

[0063] Relationships are used to connect entities to form a graph structure;

[0064] The relationship type can be a string, such as "connects", "contains", "drives", etc.

[0065] The start and end points of a relationship are entities, such as "M1 is connected to M2" or "Comparator contains NMOS".

[0066] Step 1.4.4: Triplet construction

[0067] The basic building block in the graph is the "entity-relationship-entity" relationship query triple.

[0068] Triples are used to represent the relationship between entities. For example, “M1 is connected to M2” can be represented as a triple (“M1”, “connected”, “M2”).

[0069] Step 1.4.5: Merge equivalent annotations

[0070] Merge equivalent annotations into a knowledge graph for efficient retrieval.

[0071] For example, multiple circuits may use the same bias circuit. The bias circuit annotations of these circuits can be merged into one entity and a relationship can be established, such as "M1 contains bias circuit."

[0072] Step 1.4.6: Knowledge graph retrieval * Use triples to search in the knowledge graph, for example: * Retrieve all circuits using differential pairs: MATCH(node:circuit{input:'Differential pair'}) RETURN node * Retrieve all circuits using current mirrors as loads: MATCH(node:circuit{load:'Current mirror'}) RETURN node * Use Cypher or other graph database query languages ​​for retrieval.

[0073] Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG;

[0074] Step 5. Select the topology through KG-RAG

[0075] Using performance specifications as input, the large language model (LLM) is used to obtain design strategies, describe circuit architectures, convert design strategies into relational query triples, use the triples to retrieve relevant circuits and test platforms in the knowledge graph, and use local annotations to assemble the retrieved circuit components and test platforms into a complete circuit topology for simulation.

[0076] Step 5.1: Convert the performance specifications into relational query triples.

[0077] Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms.

[0078] Step 5.3: Based on the local annotations, the retrieved circuit components and test platform are assembled into a complete circuit topology.

[0079] Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

[0080] Step 6: Constraint-based size optimization

[0081] Formulate the sizing optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). Use local annotations as constraints to reduce the parameter search space. Use expert insights, such as parameter sharing constraints, to further refine the search space. Use a Bayesian optimization algorithm to select the next sampling point and update the surrogate model. Repeat this process until the performance target or the iteration limit is reached.

[0082] Step 6.1. Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted sum of the squares of the performance index, as shown below:

[0083]

[0084] where f i (x) represents the performance index of the i-th simulation, and N represents the number of performance indicators;

[0085] is a performance limit, after which no additional performance points will be awarded.

[0086] and is the normalization factor obtained by the initial random sample set,

[0087] w i is the weight of the importance control item of each performance indicator.

[0088] Step 6.2: Use local annotations as constraints

[0089] The local annotation information retrieved by AMSnet-KG is used as constraints to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified according to the local annotations should maintain equality or a certain ratio, and the number of parameters is reduced accordingly.

[0090] Step 6.2.1. Define local annotations as prior knowledge of parameters, such as the value range of the parameters;

[0091] Step 6.2.2: Update the prior distribution of the parameters based on the local annotations, thereby limiting the parameter search space;

[0092] Step 6.3: Introducing Expert Knowledge

[0093] We use expert knowledge, such as parameter sharing constraints, to further refine the search space and guide the optimization process. An exhaustive search of all transistor parameters is inefficient, so we use expert knowledge as constraints on the search space.

[0094] Step 6.3.1. Define parameter sharing constraints as the relationship between parameters provided by experts, for example, some parameters must take the same value;

[0095] Step 6.3.2: Update the prior distribution of the parameters based on the parameter sharing constraint, thereby further restricting the parameter search space.

[0096] Step 6.4: Use Bayesian optimization to select the next sampling point

[0097] The Bayesian optimization algorithm uses a series of initial data to define a surrogate model (usually a Gaussian process) and selects the next sampling point by maximizing the acquisition function and updating the surrogate model with the new sampled data.

[0098] Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached. The optimal circuit parameters are found through iterative simulation and model update.

[0099] Step 7: Topology Reconstruction

[0100] If the initial topology fails to meet the performance target after size optimization, a topology refactoring is performed. The LLM proposes a new design strategy based on the previous performance target and design. This strategy uses the LLM's comparative knowledge to select a topology that better suits the target performance. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

[0101] Because the present invention adopts the above technical means, it has the following beneficial effects:

[0102] The present invention provides an automatic AMS circuit design method using a large language model, which solves the problem of insufficient automation in existing AMS circuit design by means of the following technical means:

[0103] 1. Data Extraction and Knowledge Graph Construction: By extracting circuit schematics and text descriptions from literature, we construct a dataset containing schematics, netlists, and annotations. This in turn creates a knowledge graph to store circuit information. This approach solves the existing challenges of acquiring and storing the data required for AMS circuit design, providing a rich information resource for subsequent automated design.

[0104] 2. Schematic and Netlist Processing: Connectivity checks and annotations are performed on schematics, and netlists are extracted, increasing the automation level of circuit design. This step reduces manual intervention and improves design efficiency by automatically identifying circuit components and connection relationships.

[0105] 3. Design Strategy Acquisition and Circuit Assembly: This approach leverages large language models to capture design strategies, describe circuit architectures, and assemble complete circuit topologies based on these strategies and local annotations. This approach, combined with artificial intelligence (AI), automatically generates circuit design strategies based on performance specifications, enhancing the intelligence of design.

[0106] 4. Size Optimization and Topology Reconstruction: The size optimization problem is formulated as a black-box optimization problem and solved using a Bayesian optimization algorithm, improving optimization efficiency. Furthermore, if the initial topology fails to meet performance targets, topology reconstruction is performed to further optimize the design. This step improves the performance and practicality of the design by automatically optimizing circuit parameters and topology.

[0107] 5. Application of Expert Knowledge and Large-Scale Multilingual Language Models: Introducing expert knowledge, such as parameter sharing constraints, further optimizes the search space. Large-scale multilingual language models are used for annotation processing and design strategy description, enhancing the accuracy and flexibility of the design.

[0108] Compared with the prior art, the present invention has advantages in the following aspects:

[0109] High degree of automation: greatly reduces manual intervention and improves design efficiency.

[0110] Intelligent design strategies: Combined with large language models, they can automatically generate design strategies based on performance specifications.

[0111] Optimization efficiency: Bayesian optimization algorithm is used for size optimization to improve optimization efficiency.

[0112] Flexibility and applicability: The introduction of expert knowledge and multilingual large-scale language models enhances the flexibility and applicability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0113] Figure 1 It is a simple block diagram of the process of the present invention;

[0114] Figure 2 A simplified flowchart of the detailed steps of step 1;

[0115] Figure 3 A simple block diagram is provided for analyzing each component cluster to determine its connectivity. DETAILED DESCRIPTION

[0116] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with certain specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions of the present invention are intended to fall within the scope of the claims of the present invention.

[0117] In addition, in order to better illustrate the present invention, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0118] The present invention provides an AMS circuit automatic design method using a large language model, comprising the following steps:

[0119] Step 1: Extract circuit schematics and text descriptions from the original literature to obtain circuit schematics, netlists, and annotation information for constructing the AMSnet-KG knowledge graph;

[0120] The steps in Step 1 include:

[0121] Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset.

[0122] Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are annotated on a subset of page images and an object detection model is trained to identify and extract all circuit schematics on the remaining pages.

[0123] Step 1.3: Leverage the uniformity of printed schematics from the literature for template matching. Manually annotate one copy of each component type and quickly identify other identical components through template matching.

[0124] Step 1.4: Label each direction of each component category, including direction information for determining component connections;

[0125] Step 1.5: Use the template matching data to train the model and apply it to annotate the remaining circuit schematics.

[0126] Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirements, and obtain the position labels and category labels of all components in the circuit schematic;

[0127] Step 1.7. Output a dataset containing circuit schematics, netlists, and annotation information for constructing the AMSnet-KG knowledge graph.

[0128] To facilitate a better understanding of the technical concepts of this invention for those skilled in the art, we first collected a large amount of raw data from textbooks and academic papers. This material is rich in circuit schematics and textual descriptions, providing a sufficient foundation for us to form the <Circuit Schematics, Netlists, Annotation Information> dataset. To reduce the cost of manually extracting circuit schematics, we employed a semi-supervised learning approach. We annotated bounding boxes of schematics on a subset of page images and trained an object detection model using this labeled data. This model was then used to identify and extract all circuit schematics from the remaining pages. Since most literature prints their schematics in a very uniform manner, individual components are often printed in a uniform pattern, which allows us to perform template matching. Instead of manually annotating the bounding boxes of components in schematics to form a training set, as we would for literature pages, we only need to annotate one copy of each component type. For example, after annotating a PMOS transistor, we can perform template matching on the region of interest (RoI) within the bounding box against other schematics to quickly identify all other PMOS transistors. This significantly reduces the manual annotation effort. It is important to note that orientation information will be used in a subsequent step to determine component connectivity. Therefore, we need to provide a label for each orientation for each component class.

[0129] Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist;

[0130] The steps in Step 2 include:

[0131] Step 2.1, perform component identification processing on the circuit schematic to obtain component annotations;

[0132] Step 2.2: Perform network cable identification processing on the component labels to obtain a netlist;

[0133] Step 2.2.1. Traverse each component annotation in the circuit schematic to identify the connection relationship between the components.

[0134] Step 2.2.2: Classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rule is that all wires are represented by solid lines, and wires that intersect but do not have intersection points are not considered connected.

[0135] Step 2.2.3: Perform an extended search on the wire pixels around each component until other components or boundaries are encountered to form a component cluster.

[0136] Step 2.2.4: Analyze each component cluster to determine its connectivity:

[0137] Step 2.2.4.1: If the cluster contains only the starting component, mark it as no connectivity detected.

[0138] Step 2.2.4.2. If the cluster contains exactly two components, mark these two components as connected.

[0139] Step 2.2.4.3. If the cluster contains an odd number of components, and it is greater than two, mark the circuit diagram as abnormal and require manual inspection.

[0140] Step 2.2.4.4. If the cluster contains an even number of components, and it is greater than two, assume that the circuit diagram has no missing nodes and the intersecting wires are not connected.

[0141] Step 2.2.5: Apply a 2D convolution to the searched wires to locate the intersection. The convolution kernel dimensions are adjusted based on the line thickness and layout.

[0142] Step 2.2.6: The index of the maximum pixel density near the intersection point is considered as the intersection point and added to the component annotation;

[0143] Step 2.2.7. Repeat the grouping process, connecting each component in the group to the intersection point to eliminate the four-component cluster;

[0144] Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group.

[0145] Step 2.2.9. Rearrange the relative connections, delete the intersections, and complete the network cable identification process.

[0146] Step 2.2.10. For some components, correctly order the connections according to the SPICE netlist format requirements. For example, the connections of a four-terminal MOSFET must follow the order of drain, gate, source, and body / substrate.

[0147] Step 2.2.11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection.

[0148] Step 2.2.12. For the symbol, use MLLM to determine the function of each pin;

[0149] Step 2.2.13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96% and manually correct any erroneous results to ensure data quality.

[0150] Step 2.2.14. Output a netlist containing circuit components, symbols, and net lines.

[0151] Step 3: Annotate the circuit schematic and netlist to obtain annotation information;

[0152] The steps in Step 3 include:

[0153] Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include:

[0154] Label each component in the circuit schematic, including identifying the network wires as input, bias, and output;

[0155] Labeling groups of components, such as identifying a group of components as a building block, including a current mirror or a differential pair;

[0156] Dimensioning constraints, marking certain sets of components to follow symmetry constraints such as length and width;

[0157] Label the nets that connect the circuit's pins to the testbench.

[0158] Step 3.2: Perform MLLM generation on the circuit schematic and netlist to obtain global annotations. The operations include:

[0159] The qualitative descriptions are summarized into key-value pairs using a multilingual large language model (MLLM), including: {gain: high} or {load: current mirror};

[0160] Generate JSON files to introduce more structure in annotation information;

[0161] Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph;

[0162] Step 3.5: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and the obtained local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing the complete circuit design information.

[0163] Step 4: Build a knowledge graph for the circuit schematic, netlist, and annotation information to obtain AMSnet-KG.

[0164] The steps in Step 4 include:

[0165] Step 4.1: Perform entity relationship definition processing on the circuit schematic, netlist, and annotation information to obtain a knowledge graph structure;

[0166] Step 4.1.1. Entity definition

[0167] Define entities as strings or circuits;

[0168] String entities are used to represent circuit components, test benches, etc., such as "NMOS", "PMOS", "Comparator", etc.

[0169] A circuit entity is used to represent a complete circuit topology, including information such as schematics, netlists, local annotations, and global annotations.

[0170] Step 1.4.2: Relationship Definition

[0171] Relationships are used to connect entities to form a graph structure;

[0172] The relationship type can be a string, such as "connects", "contains", "drives", etc.

[0173] The start and end points of a relationship are entities, such as "M1 is connected to M2" or "Comparator contains NMOS".

[0174] Step 1.4.4: Triplet construction

[0175] The basic building block in the graph is the "entity-relationship-entity" relationship query triple.

[0176] Triples are used to represent the relationship between entities. For example, “M1 is connected to M2” can be represented as a triple (“M1”, “connected”, “M2”).

[0177] Step 1.4.5: Merge equivalent annotations

[0178] Merge equivalent annotations into a knowledge graph for efficient retrieval.

[0179] For example, multiple circuits may use the same bias circuit. The bias circuit annotations of these circuits can be merged into one entity and a relationship can be established, such as "M1 contains the bias circuit."

[0180] Step 1.4.6: Knowledge graph retrieval * Use triples to search in the knowledge graph, for example: * Retrieve all circuits using differential pairs: MATCH(node:circuit{input:'Differential pair'}) RETURN node * Retrieve all circuits using current mirrors as loads: MATCH(node:circuit{load:'Current mirror'}) RETURN node * Use Cypher or other graph database query languages ​​for retrieval.

[0181] Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG;

[0182] Step 5. Select the topology through KG-RAG

[0183] Using performance specifications as input, the large language model (LLM) is used to obtain design strategies, describe circuit architectures, convert design strategies into relational query triples, use the triples to retrieve relevant circuits and test platforms in the knowledge graph, and use local annotations to assemble the retrieved circuit components and test platforms into a complete circuit topology for simulation.

[0184] Step 5.1: Convert the performance specifications into relational query triples.

[0185] Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms.

[0186] Step 5.3: Based on the local annotations, the retrieved circuit components and test platform are assembled into a complete circuit topology.

[0187] Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

[0188] Step 6: Constraint-based size optimization

[0189] Formulate the sizing optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). Use local annotations as constraints to reduce the parameter search space. Use expert insights, such as parameter sharing constraints, to further refine the search space. Use a Bayesian optimization algorithm to select the next sampling point and update the surrogate model. Repeat this process until the performance target or the iteration limit is reached.

[0190] Step 6.1. Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted sum of the squares of the performance index, as shown below:

[0191]

[0192] where f i (x) represents the performance index of the i-th simulation, and N represents the number of performance indicators;

[0193] is a performance limit, after which no additional performance points will be awarded.

[0194] and is the normalization factor obtained by the initial random sample set,

[0195] w i is the weight of the importance control item of each performance indicator.

[0196] Step 6.2: Use local annotations as constraints

[0197] The local annotation information retrieved by AMSnet-KG is used as constraints to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified according to the local annotations should maintain equality or a certain ratio, and the number of parameters is reduced accordingly.

[0198] Step 6.2.1. Define local annotations as prior knowledge of parameters, such as the value range of the parameters;

[0199] Step 6.2.2: Update the prior distribution of the parameters based on the local annotations, thereby limiting the parameter search space;

[0200] Step 6.3: Introducing Expert Knowledge

[0201] We use expert knowledge, such as parameter sharing constraints, to further refine the search space and guide the optimization process. An exhaustive search of all transistor parameters is inefficient, so we use expert knowledge as constraints on the search space.

[0202] Step 6.3.1. Define parameter sharing constraints as the relationship between parameters provided by experts, for example, some parameters must take the same value;

[0203] Step 6.3.2: Update the prior distribution of the parameters based on the parameter sharing constraint, thereby further restricting the parameter search space.

[0204] Step 6.4: Use Bayesian optimization to select the next sampling point

[0205] The Bayesian optimization algorithm uses a series of initial data to define a surrogate model (usually a Gaussian process) and selects the next sampling point by maximizing the acquisition function and updating the surrogate model with the new sampled data.

[0206] Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached. The optimal circuit parameters are found through iterative simulation and model update.

[0207] To facilitate better understanding for those skilled in the art, refer to the following example:

[0208] Step 6: Optimize size based on constraints

[0209] Step 6.1: Problem Formulation and Initialization Formulate the size optimization problem as a black box optimization problem and solve it using the Bayesian Optimization (BO) method. Initialize the input data size N init , the number of iterations N iter , and the parameter design space S with constraint enhancement param ;

[0210] Step 6.2: Generate initial samples from the design space S param Sampling N init Initial point x init, define local annotations as prior knowledge of parameters, and update the prior distribution of parameters based on local annotations, thereby limiting the search space of parameters.

[0211] Step 6.3: Performance simulation using x init Perform simulation and get performance output y init .

[0212] Step 6.4: Fit the Gaussian process model using x init and y init To fit the Gaussian process (GP) model.

[0213] Step 6.5: Define local annotations as prior knowledge of parameters and update the prior distribution of parameters based on local annotations to limit the search space of parameters. iter Perform the following steps:

[0214] Select the next sampling point: select the next simulation point through the acquisition function α(x), and use the maximization acquisition function to find the x that maximizes α(x) next .

[0215] Performance simulation: Using x next Perform simulation and obtain performance output y next .

[0216] Update the Gaussian process model: Use x next and y next Update the Gaussian process (GP) model.

[0217] End the loop: when the predetermined number of iterations N is reached iter When , the loop ends.

[0218] Return Optimal Parameters: Returns the optimal size determination parameter x * .

[0219] This algorithm describes a sizing process based on Bayesian optimization that finds the optimal circuit parameters through iterative simulation and model updating.

[0220] Step 7: Topology Reconstruction

[0221] If the initial topology fails to meet the performance target after size optimization, a topology refactoring is performed. The LLM proposes a new design strategy based on the previous performance target and design. This strategy uses the LLM's comparative knowledge to select a topology that better suits the target performance. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

Claims

1. An AMS circuit automatic design method using a large language model, characterized in that: The following steps are involved: Step 1: Extract circuit schematics from original literature data; Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist; Step 3: Annotate the circuit schematic and netlist to obtain annotation information; Step 4: Construct a knowledge graph for the circuit schematic, netlist, and annotation information to obtain the AMSnet-KG knowledge graph; Step 5. Select the topology through KG-RAG Using performance specifications as input, the large language model (LLM) is used to extract design strategies and describe circuit architectures. The design strategies are converted into relational query triples. The triples are used to retrieve relevant circuits and test benches in the knowledge graph. Local annotations are used to assemble the retrieved circuit components and test benches into a complete circuit topology and perform simulations. Step 6: Constraint-based size optimization Formulate the sizing optimization problem as a black-box optimization problem and solve it using Bayesian optimization. Use local annotations as constraints to reduce the parameter search space. Use expert insights, including parameter sharing constraints, to further refine the search space. Use Bayesian optimization to select the next sampling point and update the surrogate model until the performance target or iteration limit is reached. Step 6.

1. Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization. The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted sum of the squares of the performance index, as shown below: where f i (x) represents the performance index of the i-th simulation, and N represents the number of performance indicators; is a performance limit, after which no additional performance points will be awarded. and is the normalization factor obtained by the initial random sample set, w i is the weight of the importance control item of each performance indicator; Step 6.2: Use local annotations as constraints The local annotation information retrieved by AMSnet-KG is used as a constraint to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified by the local annotation should maintain equality or a certain ratio, and the number of parameters can be reduced accordingly. Step 6.2.

1. Define the local annotation as a priori knowledge of the parameters, including the range of the parameters; Step 6.2.2: Update the prior distribution of the parameters based on the local annotations, thereby limiting the parameter search space; Step 6.3: Introducing Expert Knowledge Use expert knowledge, including parameter sharing constraints, to further optimize the search space; Step 6.3.1: Define parameter sharing constraints as the relationship between the parameters provided by the experts, including that some parameters must take the same value. Step 6.3.2: Update the prior distribution of the parameters based on the parameter sharing constraints, thereby further restricting the parameter search space. Step 6.4: Use Bayesian optimization to select the next sampling point The next sampling point is selected by maximizing the acquisition function and the surrogate model is updated using the new sampled data. The Bayesian optimization algorithm uses a series of initial data to define a surrogate model and selects the next sampling point by maximizing the acquisition function. Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached. The optimal circuit parameters are found through iterative simulation and model update. Step 7: Topology Reconstruction If the initial topology fails to meet the performance target after size optimization, a topology reconstruction is performed, and a new design strategy is proposed using LLM. This strategy is based on the previous performance target and design, and the comparative knowledge of LLM is used to select a topology that is more suitable for the target performance. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

2. The AMS automatic circuit design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in Step 1 include: Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset. Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are annotated on a subset of page images and an object detection model is trained to identify and extract all circuit schematics on the remaining pages. Step 1.3: Manually annotate one copy of each component type using template matching on the schematic, and quickly identify other identical components through template matching. Step 1.4: Label each direction of each component category, including direction information for determining component connections; Step 1.5: Use the template matching data to train the model and apply the trained model to annotate the remaining circuit schematics. Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirement, and obtain the position labels and category labels of all components in the circuit schematic.

3. The AMS automatic circuit design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in Step 2 include: Step 2.1, perform component identification processing on the circuit schematic to obtain component annotations; Step 2.2: Perform network cable identification processing on the component labels to obtain a netlist.

4. The AMS automatic circuit design method using a large language model according to claim 3, characterized in that: Step 2.2: Perform network cable identification on the component labels to obtain the netlist. The specific steps include: Step 2.2.

1. Traverse each component annotation in the circuit schematic to identify the connection relationship between components; Step 2.2.2: Classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rule is that all wires are represented by solid lines, and wires that intersect but do not have intersection points are not considered connected. Step 2.2.3: Expand the search for the wire pixels around each component until other components or boundaries are encountered, forming a component cluster. Step 2.2.4: Analyze each component cluster to determine its connectivity: Step 2.2.5: Apply a two-dimensional convolution to the searched wires to locate the intersection. The convolution kernel dimensions are adjusted based on the line thickness and layout. Step 2.2.6: Consider the index of the maximum pixel density near the intersection as the intersection and add it to the component annotation. Step 2.2.

7. Repeat the grouping process, connecting each component in the group to the intersection point to eliminate the four-component cluster; Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group. Step 2.2.

9. Rearrange component connections, delete intersections, and complete the network cable identification process. Step 2.2.10: For some components, correctly arrange the connections according to the SPICE netlist format requirements; Step 2.2.

11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection. Step 2.2.12: For the symbol, use the multilingual large language model (MLLM) to determine the function of each pin. Step 2.2.

13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96% and manually correct any erroneous results to ensure data quality. Step 2.2.

14. Output a netlist containing circuit components, symbols, and net lines.

5. The AMS circuit automatic design method using a large language model according to claim 4, characterized in that: Step 2.2.4 analyzes each component cluster to determine its connectivity, as follows: Step 2.2.4.1: If the cluster contains only the starting component, mark it as no connectivity detected; Step 2.2.4.2: If the cluster contains exactly two components, mark these two components as connected. Step 2.2.4.

3. If the cluster contains an odd number of components, and is greater than two, mark the circuit diagram as abnormal and require manual inspection; Step 2.2.4.

4. If the cluster contains an even number of components, and it is greater than two, then the circuit diagram has no missing nodes and intersecting wires are not connected.

6. The AMS automatic circuit design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in Step 3 include: Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include: Label each component in the circuit schematic, including identifying nets as input, bias, and output; label component groups, identifying a group of components as a building block, including current mirrors or differential pairs; Dimensioning constraints, marking certain sets of components to follow symmetry constraints including length and width; Label the nets used to connect the circuit's pins to the testbench. Step 3.2: Generate and process the circuit schematic and netlist using a multilingual large language model (MLLM) to obtain global annotations. The operations include: Use the multilingual large language model MLLM to summarize qualitative descriptions into key-value pairs; Generate JSON files to introduce more structure in annotation information; Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph; Step 3.3: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and the obtained local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing the complete circuit design information.

7. The AMS automatic circuit design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in Step 4 include: Step 4.1: Perform entity relationship definition processing on the circuit schematic, netlist, and annotation information to obtain a knowledge graph structure; Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG.

8. The AMS automatic circuit design method using a large language model according to claim 7, characterized in that: The following steps are involved: The steps in step 4.1 include: Step 4.1.

1. Entity definition Define entities as strings or circuits; String entities are used to represent circuit components, test benches, including "NMOS", "PMOS", or circuit structure functions; circuit entities are used to represent complete circuit topology, including schematics, netlists, local annotations, and global annotation information; Step 4.1.2: Relationship Definition Relationships are used to connect entities to form a graph structure; The relationship type is a string, including "connect", "contains", and "drive"; The starting point and end point of a relationship are entities; Step 4.1.3: Triplet construction The constituent units in the graph are "entity-relationship-entity" relationship query triples; Triples are used to represent relationships between entities; Step 4.1.4: Merge equivalent annotations Merge equivalent annotations into a knowledge graph for efficient retrieval.

9. The AMS circuit automatic design method using a large language model according to claim 1, It is characterized by: The steps of step 5 include: Step 5.1, convert the performance specification into a relational query triple; Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms; Step 5.3: Assemble the retrieved circuit components and test platform into a complete circuit topology based on the local annotations; Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

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