A detailed layout method of integrated circuit based on clock tree drive

Abstract

The present invention discloses a detailed layout method of integrated circuit based on clock tree drive, comprising the steps of: S10, first reading in the layout file after global layout, obtaining the physical and timing information of the register; S20, performing register layout, first using capacitor balanced binary K-means clustering, constructing a virtual clock tree for each partition after clustering, searching for the optimal position of the register according to the constructed clock tree, and moving the register to a comprehensive favorable position of the clock tree; S30, performing non-register layout, legalizing the overlapping units in the search process, and finally optimizing the signal line length using the nearest neighbor search based on the priority queue. The present invention ensures the optimal balance between the signal line length and the clock tree line length, optimizes the clock tree, optimizes the power consumption, and improves the circuit stability and reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a detailed layout method of integrated circuits based on clock tree driving. Background Art

[0002] The existing integrated circuit detailed layout method does not give special consideration to the register position, and therefore pays little attention to the clock tree composed of registers. It only considers the signal line length and density balance issues, and does not consider the power consumption caused by the clock tree line length. Specifically, the current detailed layout method does not give special treatment to registers, and will minimize the changes relative to the global layout during the layout process. The existing global layout algorithm does not consider the clock tree, which leads to the continuation or even deterioration of the clock tree in the global layout stage after the detailed layout, resulting in a large amount of power consumption.

[0003] The current clock tree synthesis stage and detailed layout stage are basically separated. The advantage of this is that the signal line length can be optimized to the greatest extent, but this also brings certain challenges. After the detailed layout is completed, the clock tree is constructed by clock tree synthesis, which is highly dependent on the register position in the layout stage. Since the existing detailed layout technology does not specifically consider the position of the register, the length of the clock tree is unbalanced, the delay time of the clock signal is different, and a larger clock skew is generated, which affects the stability and reliability of the circuit. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a detailed layout method of integrated circuit based on clock tree drive to ensure the optimized balance between signal line length and clock tree line length, optimize the clock tree, optimize power consumption, and improve circuit stability and reliability.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a detailed layout method of integrated circuit based on clock tree drive, comprising the steps of:

[0006] S10, first read the layout file after global layout, and obtain the physical and timing information of the register;

[0007] S20, performing register layout, first using capacitor-balanced bisection K-means clustering, constructing a virtual clock tree for each partition after clustering, searching for the optimal position of the register according to the constructed clock tree, and moving the register to a comprehensive favorable position of the clock tree;

[0008] S30, perform non-register layout, legalize the overlapping units in the search process, and finally use the nearest neighbor search based on the priority queue to optimize the signal line length.

[0009] Furthermore, the bisection K-means clustering for capacitor balancing includes the following steps:

[0010] Create a clustered priority queue and group all registers into an initial cluster;

[0011] In the following process, a target cluster is selected from the head of the queue;

[0012] The target cluster is divided into two sub-clusters using the K-means algorithm, and the cluster center is selected using the bisection method, that is, the cluster is roughly divided into two regions based on the perpendicular bisector of the longest side of the bounding box; the coordinate centroid of the register in each region is selected as the initial cluster center of the K-means algorithm to balance the capacitance within each cluster.

[0013] Furthermore, a comprehensive penalty function is constructed to evaluate the clustering quality, where the capacitance entropy is used to quantify the balance of register capacitance within a cluster, and the sum of squared errors (SSE) evaluates the deviation between the register position and the cluster centroid, leading to a balanced clustering effect.

[0014] Furthermore, the comprehensive penalty function is:

[0015] ;

[0016] Among them, H i is the capacitance entropy of the ith cluster, p capi represents the ratio of the total pin capacitance of the ith cluster to the total pin capacitance of all clusters, SSE i is the centroid of cluster i according to each register (x, y) The Manhattan distance is calculated, C i is the set of registers in the i-th cluster; λ is the weight coefficient, max(SEE) represents the maximum SSE value among all clusters, Penalty i Represents the penalty value of the i-th cluster.

[0017] Furthermore, the register optimal position search comprises the steps of:

[0018] Sort the registers according to virtual delay, and search one by one starting from the register with the highest delay;

[0019] Diamond search is used in the search. The maximum displacement is selected as the maximum radius with the current register position as the center, and the bounding box of the cluster is set as the boundary condition. The search window is continuously expanded from a radius of 1 until candidate points are gradually found in the window. After finding the candidate points, the score of the specified candidate points is calculated. The score is obtained by comprehensively considering the length of the signal network line connected to the current unit, the density of the corresponding position, and the normalized Manhattan distance from the guide point combination; the optimal position of the clock register is obtained according to the score.

[0020] Furthermore, the calculation formula of virtual delay is:

[0021] ;

[0022] Among them, R e is the unit line resistance of the clock network, L reg is the line length of the clock path where the register is located, C reg Represents the pin capacitance of the register, C e is the unit line capacitance of the register.

[0023] Furthermore, the score formula is:

[0024] ;

[0025] NetsHPWL is the length of the signal network cable connected to the current unit, D p is the density of the corresponding position, Ds is the normalized Manhattan distance from the guide point combination, p represents the position of the candidate point, reg is the register currently being searched, δ, ò and ζ are parameters, which are 0.5, 5 and 1 respectively;

[0026] The formula for Ds is:

[0027] ;

[0028] D Ⅰ , D Ⅱ and D Ⅲ They respectively represent the first, second and third level ancestor nodes of the current register in the constructed virtual clock tree, and Na represents the number of ancestor nodes.

[0029] The beneficial effects of adopting this technical solution are:

[0030] The present invention can generate higher quality detailed layout results, which not only ensures that the signal line length is not too long, but also significantly improves the clock tree line length. By constructing a virtual clock tree to guide the register layout in the detailed layout stage, it can lay a good foundation for the clock tree synthesis stage and effectively reduce power consumption, clock skew and clock delay. This design makes the entire circuit have better effects in both the detailed layout and clock tree synthesis stages, and is more efficient and coordinated.

[0031] The present invention proposes to integrate the clock tree into the detailed layout, construct several local clock trees by clustering registers, and guide the search for the optimal position of the register according to the constructed virtual clock tree to optimize power consumption and reduce clock skew. In the process, the optimization of the signal network is comprehensively considered to ensure the optimal balance between the length of the signal line and the length of the clock tree.

[0032] The present invention takes into account both the length of signal lines and the length of clock trees on the basis of the existing detailed layout methods, optimizes power consumption, clock skew and clock delay to the greatest extent, and provides more convenience and optimization for subsequent clock tree synthesis compared to the existing methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic flow chart of a detailed integrated circuit layout method based on clock tree drive according to the present invention;

[0034] Figure 2 A schematic diagram of a clustering process in an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of register search in an embodiment of the present invention, (a) is the search window, (b) is the first position, and (c) is the next station. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0037] In this embodiment, see Figure 1 As shown, the present invention proposes a detailed layout method of integrated circuit based on clock tree driving, comprising the steps of:

[0038] S10, first read the layout file after global layout, and obtain the physical and timing information of the register;

[0039] S20, performing register layout, first using capacitor-balanced bisection K-means clustering, constructing a virtual clock tree for each partition after clustering, searching for the optimal position of the register according to the constructed clock tree, and moving the register to a comprehensive favorable position of the clock tree;

[0040] S30, perform non-register layout, legalize the overlapping units in the search process, and finally use the nearest neighbor search based on the priority queue to optimize the signal line length.

[0041] As an optimization solution of the above embodiment, bisection K-means clustering of capacitor balancing includes the following steps:

[0042] Create a clustered priority queue and group all registers into an initial cluster;

[0043] In the following process, a target cluster is selected from the head of the queue;

[0044] The target cluster is divided into two sub-clusters using the K-means algorithm. In order to reduce the influence of random factors, the cluster center is selected using the bisection method, that is, the cluster is roughly divided into two regions based on the perpendicular bisector of the longest side of the bounding box; the coordinate centroid of the register in each region is selected as the initial cluster center of the K-means algorithm to balance the capacitance within each cluster to avoid clock deviation caused by uneven capacitance in clock tree synthesis.

[0045] A comprehensive penalty function is constructed to evaluate the clustering quality, where the capacitance entropy is used to quantify the balance of register capacitance within the cluster, and the sum of squared errors (SSE) evaluates the deviation between the register position and the cluster centroid, leading to a balanced clustering effect.

[0046] The comprehensive penalty function is:

[0047] ;

[0048] Among them, H i is the capacitance entropy of the ith cluster, p capi represents the ratio of the total pin capacitance of the ith cluster to the total pin capacitance of all clusters, SSE i is the centroid of cluster i according to each register (x, y) The Manhattan distance is calculated, C i is the set of registers in the i-th cluster; λ is the weight coefficient, max(SEE) represents the maximum SSE value among all clusters, Penalty i Represents the penalty value of the i-th cluster.

[0049] Figure 2 A simple clustering process is shown in Figure 1, which gradually divides the whole cluster into K clusters, where K=4, and each time divides into two regions according to the perpendicular bisector. The number of clusters K is empirically set to max(N / 60,1), where N is the total number of registers. The weight coefficient λ is empirically set to 0.4.

[0050] In order to minimize the impact on the global layout results, especially for timing-aware layout, the present invention uses register clustering to limit register displacement and preliminarily avoid excessive loss of signal network length. Another advantage is that each cluster can be processed in parallel to speed up the operation of the entire algorithm. In addition, a key point is that the subtree capacitance in each cluster needs to be balanced to avoid winding in clock tree synthesis. Therefore, the present invention improves the binary K-means clustering algorithm to perform register clustering, and develops a comprehensive penalty function that combines capacitance entropy and square error and SSE to weigh capacitance balance and clustering effects.

[0051] As an optimization scheme for the above embodiment, the movement of registers is guided by the guide point set composed of the constructed virtual clock tree. The solution space in the fence area is smaller than that in the default area. Therefore, the selection of registers is more likely to affect the signal network. Therefore, in the optimal position search of the fence area, the position overlapping with the non-register is set as an illegal position to minimize the impact on the signal network. Since the registers in the default area have a subtree built in the cluster, the movement range has been greatly limited. Therefore, the clock network is optimized to a greater extent, and the overlap with non-registers is chosen to expand the solution space, and the selected position is limited by the comprehensive score.

[0052] The search for the optimal position of the register includes the following steps:

[0053] Since the registers searched first can obtain more valid locations, the registers are sorted according to the virtual delay, giving priority to the registers with high delay. reg Larger registers are searched first.

[0054] The calculation formula for virtual delay is:

[0055] ;

[0056] Among them, R e is the unit line resistance of the clock network, L reg is the line length of the clock path where the register is located, C reg Represents the pin capacitance of the register, C e is the unit line capacitance of the register.

[0057] According to the virtual delay d reg The registers are ordered so that higher latency registers can more effectively reduce the path length and more wire resources are allocated to short paths to balance the skew.

[0058] Diamond search is used in the search. The maximum displacement is selected as the maximum radius with the current register position as the center, and the bounding box of the cluster is set as the boundary condition. The search window is continuously expanded from a radius of 1 until candidate points are gradually found in the window. After finding the candidate points, the score of the specified candidate points is calculated. The score is obtained by comprehensively considering the length of the signal network line connected to the current unit, the density of the corresponding position, and the normalized Manhattan distance from the guide point combination; the optimal position of the clock register is obtained according to the score.

[0059] Score formula:

[0060] ;

[0061] NetsHPWL is the length of the signal network cable connected to the current unit, D pis the density of the corresponding position, Ds is the normalized Manhattan distance from the guide point combination, p represents the position of the candidate point, reg is the register currently being searched, δ, ò and ζ are parameters, which are 0.5, 5 and 1 respectively;

[0062] The formula for Ds is:

[0063] ;

[0064] D Ⅰ , D Ⅱ and D Ⅲ They respectively represent the first, second and third level ancestor nodes of the current register in the constructed virtual clock tree, and Na represents the number of ancestor nodes.

[0065] The following is an example of searching for the optimal location of the clock register: Figure 3 shown. Figure 3 (a) illustrates a search window with different radii for diamond search. Taking the shaded area in (a) as an example, a binary search is performed on the search window. The total length of the binary search is the step length in the x direction. Here, in order to expand the solution space as much as possible, a step length of 10 sites is selected to search the valid positions on both sides starting from the middle site. Then (b) shows the invalid position of the starting position, and (c) shows the valid position of the next search site.

[0066] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A detailed layout method for integrated circuits based on clock tree drive, characterized in that: Includes steps: S10, first read the layout file after global layout, and obtain the physical and timing information of the register; S20, performing register layout, first using capacitor-balanced bisection K-means clustering, constructing a virtual clock tree for each partition after clustering, searching for the optimal position of the register according to the constructed clock tree, and moving the register to a comprehensive favorable position of the clock tree; S30, performing non-register layout, legalizing the overlapping units in the search process, and finally optimizing the signal line length using the nearest neighbor search based on the priority queue; The search for the optimal position of the register includes the following steps: Sort the registers according to virtual delay, and search one by one starting from the register with the highest delay; Diamond search is used in the search. The maximum displacement is selected as the maximum radius with the current register position as the center, and the bounding box of the cluster is set as the boundary condition. The search window is continuously expanded from a radius of 1 until candidate points are gradually found in the window. After finding the candidate points, the score of the specified candidate points is calculated. The score is obtained by comprehensively considering the length of the signal network line connected to the current unit, the density of the corresponding position, and the normalized Manhattan distance from the guide point combination; the optimal position of the clock register is obtained according to the score.

2. The integrated circuit detailed layout method based on clock tree drive according to claim 1, characterized in that: The bisection K-means clustering for capacitor balancing includes the following steps: Create a clustered priority queue and group all registers into an initial cluster; In the following process, a target cluster is selected from the head of the queue; The target cluster is divided into two sub-clusters using the K-means algorithm, and the cluster center is selected using the bisection method, that is, the cluster is roughly divided into two regions based on the perpendicular bisector of the longest side of the bounding box; the coordinate centroid of the register in each region is selected as the initial cluster center of the K-means algorithm to balance the capacitance within each cluster.

3. The integrated circuit detailed layout method based on clock tree drive according to claim 2, characterized in that: A comprehensive penalty function is constructed to evaluate the clustering quality, where the capacitance entropy is used to quantify the balance of register capacitance within the cluster, and the sum of squared errors (SSE) evaluates the deviation between the register position and the cluster centroid, leading to a balanced clustering effect.

4. The integrated circuit detailed layout method based on clock tree drive according to claim 3, characterized in that: The comprehensive penalty function is: ； Among them, H i is the capacitance entropy of the ith cluster, p capi represents the ratio of the total pin capacitance of the ith cluster to the total pin capacitance of all clusters, SSE i is the centroid of cluster i according to each register (x, y) The Manhattan distance is calculated, C i is the set of registers in the i-th cluster; λ is the weight coefficient, max(SEE) represents the maximum SSE value among all clusters, Penalty i Represents the penalty value of the i-th cluster.

5. The integrated circuit detailed layout method based on clock tree drive according to claim 1, characterized in that: The calculation formula for virtual delay is: ； Among them, R e is the unit line resistance of the clock network, L reg is the line length of the clock path where the register is located, C reg Represents the pin capacitance of the register, C e is the unit line capacitance of the register.

6. The integrated circuit detailed layout method based on clock tree drive according to claim 1, characterized in that: Score formula: ； NetsHPWL is the length of the signal network cable connected to the current unit, Den p is the density of the corresponding position, Ds is the normalized Manhattan distance from the guide point combination, p represents the position of the candidate point, reg is the register currently being searched, δ, ò and ζ are parameters, which are 0.5, 5 and 1 respectively; The formula for Ds is: ； D Ⅰ , D Ⅱ and D Ⅲ They respectively represent the first, second and third level ancestor nodes of the current register in the constructed virtual clock tree, and Na represents the number of ancestor nodes.

Images