Method for transmitting data in display device and display device

Abstract

The invention discloses a method for transmitting data in a display device. The method includes monitoring a data rate of a packet of pixels in an active area of a frame; synchronizing the clocks according to the data rates of the pixel packets to generate synchronous clocks; and extracting data in the pixel packet by using the synchronous clock.

Description

Technical Field

[0001] The present disclosure relates to the field of signal processing, and more particularly, to a data transmission method and a display device thereof for reducing data loss. Background Art

[0002] Nowadays, the electronics industry is developing rapidly. Various electronic products such as mobile phones, computers, and game consoles have become an indispensable part of people's lives. In order to meet more diverse usage needs, the functions of electronic products are becoming more and more powerful, and their internal circuits are becoming more and more complex. Therefore, issues such as electromagnetic interference (EMI) and information transmission performance improvement have also become the focus of current electronic product research and development.

[0003] Electromagnetic interference refers to the impact of a circuit system on the surrounding circuit system through conduction or radiation. EMI can cause a decrease in circuit performance, and in severe cases, it may cause the entire device to fail. With the evolution of technology, high-resolution images and high image update rates are inevitable trends for display devices in the future. However, with the increase in resolution and image update rate, the amount of data transmission becomes quite large. In order to adapt to this trend, the frequency and energy of the signal used to transmit data must be increased. When the frequency and energy of the signal used to transmit data are increased to transmit data, serious electromagnetic radiation interference effects will be generated. Therefore, how to reduce the electromagnetic radiation interference effect of electronic display devices and ensure high-quality transmission of display images to meet the increasingly rich display needs is a problem that needs to be solved urgently. Summary of the invention

[0004] The present disclosure provides a method for transmitting data in a display device, which comprises monitoring the data rate of a pixel packet in an effective area of ​​a frame; synchronizing a clock according to the data rate of the pixel packet to generate a synchronous clock; and using the synchronous clock to fetch data in the pixel packet.

[0005] The present disclosure further provides a display device. The display device includes a timing controller, a transmission line, a clock line, and a source driver. The source driver is coupled to the timing controller via the transmission line to monitor the data rate of the pixel packet in the effective area of ​​the frame; synchronizes the clock according to the data rate of the pixel packet to generate a synchronous clock; and uses the synchronous clock to fetch the data in the pixel packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a schematic diagram showing a point-to-point transmission architecture according to an embodiment of the present disclosure;

[0007] Figure 1B-1Cis a schematic diagram showing a display signal when a spread spectrum is performed with a unit period (UI) as a basic unit of jitter according to an embodiment of the present disclosure;

[0008] Figure 2A-2B is a schematic diagram showing a change in data rate within a signal transmission period according to an embodiment of the present disclosure;

[0009] Figure 3 is a schematic diagram showing a data rate adjustment process based on a frame period according to an embodiment of the present disclosure;

[0010] Figure 4A-4B is a schematic diagram showing a data rate adjusted based on a row period according to an embodiment of the present disclosure;

[0011] Figure 5 It shows that for Figure 4A-4B A schematic diagram of a signal spectrum of the embodiment shown;

[0012] Figure 6A-6B is a schematic diagram showing a data rate adjusted based on a row period according to an embodiment of the present disclosure;

[0013] Figure 7A-7B is another schematic diagram showing a data rate adjusted based on a row period according to an embodiment of the present disclosure;

[0014] Figures 8A-8B is another schematic diagram showing a data rate adjusted based on a row period according to an embodiment of the present disclosure;

[0015] Fig. 9 is a schematic flow chart showing a signal transmission method for a display device according to an embodiment of the present disclosure;

[0016] Fig.10 is a schematic diagram showing the composition of a signal transmission device for a display device according to an embodiment of the present disclosure;

[0017] Fig.11 is a schematic diagram showing a micro low voltage differential signal (Mini-LVDS) transmission architecture according to an embodiment of the present disclosure;

[0018] Fig. 12A It is a schematic diagram of a mini-low voltage differential signaling (mini-LVDS) architecture in another display device according to an embodiment of the present invention;

[0019] Fig. 12B show Fig. 12A The eye diagram of the display device;

[0020] Fig.13 is Fig. 12A A flowchart of a method for transmitting a signal in a display device;

[0021] Fig.14A , Fig. 14B and Fig. 14C Diagram showing various data rate cycles for Fig. 12A A display device in;

[0022] Fig.15A and Fig. 15B Schematic diagram showing various line-based data rate cycles for Fig. 12A A display device in;

[0023] Fig.16 represents the frequency response of the display device;

[0024] Fig.17 express Fig. 12A A waveform diagram of a display device in which a data rate cycle is used; and

[0025] Fig.18 express Fig. 12A A waveform diagram of a display device in FIG. 1 , using a line-based data rate cycle.

[0026] Fig.19 A flow chart showing an exemplary method of transmitting data in the display device of FIG. 1 .

[0027] Fig. 20 A timing diagram showing a frame displayed on a display device.

[0028] Fig.21 Schematic diagram representing packets of pixels in consecutive rows.

[0029] The reference numerals are described as follows:

[0030] 1-1~1-6、11-1~11-6、11-a~11-f: Transmission lines

[0031] T-CON: Timing Controller

[0032] SD: Source Driver

[0033] UI: Unit transmission cycle

[0034] DC: Data rate adjustment time

[0035] CT:Current Training Time

[0036] f1~f7: data rate

[0037] 900: Signal transmission method

[0038] S901, S902: Steps

[0039] 1000:Signal transmission device

[0040] 1010: rate adjustment circuit

[0041] 1020: signal transmission circuit

[0042] 12: Display device

[0043] 120: Controller

[0044] 121 to 126: Source driver

[0045] 1300: Method

[0046] 160: Traditional data signal

[0047] 162: New data signal

[0048] 164: Background noise signal

[0049] S1302 to S1308: Steps

[0050] AF,AL: Effective image period

[0051] F(n-1), F(n) and F(n+1): frame

[0052] f: data rate

[0053] H1 to H4: Hump

[0054] HB: horizontal blanking period

[0055] L(n-1), L(n) and L(n+1), L, L': row

[0056] Lck: Clock Line

[0057] Ld: Data line

[0058] Sck: clock signal

[0059] Sd: data signal

[0060] STV: Vertical start pulse signal

[0061] t, t1 to t8: time

[0062] VB: vertical blanking period

[0063] w and z: non-zero

[0064] V: Voltage

[0065] AA: Effective Area

[0066] VB: vertical blanking period

[0067] Post-DE1, Post-DE2, Post-DE3, Pre-DE1: dummy rows

[0068] Ldat: data signal

[0069] LD: Load signal

[0070] Output: Output signal

[0071] Fsw: frequency switching signal

[0072] PD1-PD8: Pulse

[0073] PSW1-PSW8: Pulse

[0074] SD CLK: clock signal

[0075] SD lock: lock signal DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solution and advantages of the present disclosure more obvious, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0077] Furthermore, in the present specification and the drawings, steps and elements having substantially the same or similar features are denoted by the same or similar reference numerals, and repeated description of these steps and elements will be omitted.

[0078] In addition, in this specification and the accompanying drawings, elements are described in singular or plural form, depending on the embodiment. However, the singular and plural forms are appropriately selected for the proposed situation only for the convenience of explanation and are not intended to limit the present disclosure thereto. Therefore, the singular form may include the plural form, and the plural form may also include the singular form, unless the context clearly indicates otherwise.

[0079] In addition, in this specification and the drawings, the terms "first / second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0080] In addition, in this specification and the drawings, the terms "upper", "lower", "vertical", "horizontal", etc., which are used to refer to orientation or positional relationships, are only used to facilitate the description of the embodiments according to the present disclosure, and are not intended to limit the present disclosure thereto. Therefore, they should not be understood as limiting the present disclosure.

[0081] Furthermore, in this specification and the drawings, unless expressly stated otherwise, “connection” does not necessarily mean “direct connection” or “direct contact”; here, “connection” may refer to both a fixed function and electrical connectivity.

[0082] To facilitate description of the present disclosure, concepts related to the present disclosure are introduced below.

[0083] Electromagnetic radiation is widely present in the use of various electronic products. As electronic products become more powerful and operate faster, electromagnetic interference becomes a key consideration in the design of electronic products. The main methods to reduce electromagnetic interference include: reducing the energy of the electromagnetic signal transmitter, spread spectrum clocking (SSC), etc. Among them, spread spectrum clocking is to make the frequency of the high-speed clock continuously jitter within a certain range over time, so that the energy of electromagnetic radiation in the frequency domain is evenly distributed within a certain bandwidth frequency range, so that the peak and average values ​​of the electromagnetic radiation energy are reduced accordingly.

[0084] Figure 1A is a schematic diagram showing a point-to-point transmission architecture according to an embodiment of the present disclosure. Figure 1A As shown, the timing controller (T-CON) is coupled to multiple source drivers (SD) via multiple transmission lines (for example, transmission lines 1-1, 1-2, 1-3, 1-4, 1-5 and 1-5). The timing controller (T-CON) is an integrated circuit chip of a display device, which is used to transmit display-related signals to multiple source drivers (SD) to drive multiple pixels on the display screen for display. Display-related signals include clock signals and data signals, wherein the clock signal is used to control the transmission rate of data, and the data signal is used to transmit RGB (Red Green Blue) data to be displayed. For a point-to-point transmission architecture, the clock signal and the data signal share a signal transmission path. That is, Figure 1A In the example, each transmission line between T-CON and SD (for example, Figure 1A The transmission lines 1-1, 1-2, 1-3, 1-4, 1-5, and 1-6 in FIG. 1 transmit both clock signals and data signals. The data signal can be transmitted during the effective time, and the clock signal can be transmitted during the blanking time.

[0085] At present, for display devices based on a point-to-point transmission architecture, the spread spectrum of the display signal (i.e., data signal) between T-CON and SD uses the unit transmission period (Unit interval, UI) as the basic unit of frequency jitter (i.e., the frequency of the display signal changes in each UI, without distinguishing between effective time and blanking time). Although it can effectively reduce electromagnetic interference, it will also increase the total jitter (Total Jitter, TJ), which increases the difficulty of processing the display signal of the display device.

[0086] Specifically, for the spread spectrum method that uses the unit transmission cycle as the basic unit of frequency jitter, the data rate of signal transmission will be constantly changed with the unit transmission cycle as the basic unit during the entire signal transmission process. Therefore, although this method can avoid the accumulation of electromagnetic radiation energy at a fixed frequency, so that the energy of electromagnetic radiation in the frequency domain is evenly distributed within a certain bandwidth frequency range, thereby reducing the peak value and average value of electromagnetic radiation energy, it will introduce more jitter to the display signal within the effective time of display signal transmission. Therefore, this spread spectrum method reduces the accuracy of the display signal and increases the difficulty of processing the display signal. Moreover, in order to avoid the frequency jitter from affecting the display signal too much, thereby hindering the normal transmission and processing of the display signal, the change range of the data rate brought by the spread spectrum is usually not more than 3% of the display signal transmission data rate. Since the change range of the data rate brought by this spread spectrum method is not large, the waveforms under each state of the display signal (for example, it can include eight states of 000, 001, 010, 011, 100, 101, 110, 111) can be repeatedly superimposed by an oscilloscope to form an eye diagram corresponding to the display signal. Assuming that no spread spectrum is performed, the eye diagram corresponding to the displayed signal is as follows: Figure 1B As shown, when the spread spectrum is performed, the eye diagram corresponding to the displayed signal is as follows Figure 1C As shown, Figure 1B and Figure 1C The vertical axis in the figure represents the amplitude of the displayed signal (unit: mV), and the horizontal axis in the figure represents the time (unit: ns). Figure 1B and Figure 1C It can be seen that the jitter of the eye diagram is greater when spread spectrum is performed.

[0087] Therefore, the present disclosure proposes a signal transmission method for a display device, which can effectively reduce the electromagnetic interference of the display device while avoiding introducing disturbance into the display signal of the display device.

[0088] As an example, the present disclosure relates to a technology for reducing electromagnetic interference of a display device. The embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings.

[0089] Generally, for a display device based on a point-to-point transmission architecture, a signal transmission cycle of the display device includes a blanking time and an effective time.

[0090] More specifically, in the scanning process in which the display device converts electrical signals into optical signals, for example, the scan may start from the upper left corner of the display screen and move horizontally to the right. When the scanning point moves to the rightmost side of the display screen, the scanning point quickly returns to the leftmost side and restarts scanning the next line. The time between the scanning point moving from the rightmost side of the Nth line to the leftmost side of the N+1th line is called the horizontal blanking (H-Blank) time, where N is a positive integer. After completing the scanning of all lines (i.e., the scanning point reaches the lower right corner of the display screen), it returns to the upper left corner of the display screen to prepare for the next scan of the display screen (i.e., the next frame). The time between the scanning point moving from the lower right corner of the display screen to the upper left corner of the display screen is called the vertical blanking (V-Blank) time.

[0091] It can be seen that the display signal of the display device is actually only transmitted during the effective time, and the blanking time is used to prepare for the transmission of the display signal. Therefore, the present application proposes a signal transmission method for a display device, comprising: adjusting the data rate used for signal transmission during the blanking time; and performing signal transmission during the effective time using the data rate adjusted during the blanking time. Since the adjusted data rate is used for signal transmission during the effective time (i.e., the data rate used for signal transmission is not adjusted during the effective time), the jitter of the display signal transmission can be reduced and the display signal transmission quality can be improved.

[0092] Taking the signal transmission period as a line period and the blanking time as a horizontal blanking time as an example, Figure 2A is a schematic diagram showing the change of data rate within a row period according to an embodiment of the present disclosure.

[0093] exist Figure 2A In the example, a line cycle may include an effective time and a horizontal blanking time, wherein the display device transmits a display signal for a line during the effective time, and performs operations such as data rate adjustment and clock training during the horizontal blanking time. Therefore, assuming that for the Nth line, the data rate of the display signal transmission can be f a-1 , then after the data rate is adjusted during the horizontal blanking time, for the N+1th row, the data rate of the display signal transmission can be f a-2 , where N is a positive integer. Data rate f a-2 Can be used with data rate f a-1 Optionally, after adjusting the data rate for display signal transmission in the horizontal blanking time, the adjusted data rate can be used for signal transmission in one line after the horizontal blanking time, and the adjusted data rate can also be used for signal transmission in multiple lines after the horizontal blanking time.

[0094] Similarly, taking the signal transmission period as a frame period and the blanking time as a vertical blanking time as an example, Figure 2B is a schematic diagram showing the change of data rate within a frame period according to an embodiment of the present disclosure.

[0095] exist Figure 2B In the example, the frame period may include an effective time and a vertical blanking time, wherein the display device transmits a display signal for a frame (including multiple lines) during the effective time, and performs operations such as data rate adjustment and clock training during the vertical blanking time. Therefore, assuming that for the last line of the Mth frame, the data rate of the display signal transmission may be f b-1 , then after the data rate is adjusted during the vertical blanking time, for the first line of the M+1 frame, the data rate of the display signal transmission can be f b-2 , where M is a positive integer. Data rate f b-2 can be compared with the data rate f b-1 Optionally, after adjusting the data rate for display signal transmission in the vertical blanking time, the adjusted data rate can be used for signal transmission in one frame after the vertical blanking time, and the adjusted data rate can also be used for signal transmission in multiple frames after the vertical blanking time.

[0096] It should be noted that the signal transmission method disclosed in the present invention can adjust the data rate used for signal transmission only in the horizontal blanking time, or can adjust the data rate used for signal transmission only in the vertical blanking time, or can adjust the data rate used for signal transmission in both the horizontal blanking time and the vertical blanking time.

[0097] Different from the aforementioned spread spectrum method which uses unit period as the basic unit of jitter, Figure 2A and Figure 2B The signal transmission method of the embodiment shown can adjust the data rate used for signal transmission only during the blanking time and maintain the data rate used for signal transmission during the effective time. Therefore, the change of the data rate does not cause jitter to the display signal transmitted during the effective time, effectively ensuring the transmission quality of the display signal. In addition, after multiple data rate adjustments, Figure 2A and Figure 2B The signal transmission method of the embodiment shown can adjust the data rate for display signal transmission within a wider range, so that the energy of electromagnetic radiation in the frequency domain is evenly distributed within a wider bandwidth frequency range, thereby significantly reducing the peak and average values ​​of electromagnetic radiation energy. The data transmission range that can be processed by the receiving end of display signal transmission can be applied to the signal transmission method of the present disclosure. For example, through the signal transmission method of the present disclosure, the data rate can be changed by 30% of the data rate of display signal transmission.

[0098] It should be understood that, for the signal transmission method for a display device of the present application, the data rate used for signal transmission varies greatly, so the corresponding eye diagram cannot be obtained by repeatedly superimposing the waveforms of the display signal in various states, that is, the eye diagram cannot be obtained by oscilloscope analysis. Figure 1B or Figure 1C Image shown. Figure 3 is a schematic diagram showing a data rate adjustment process based on a frame period according to an embodiment of the present disclosure. Figure 3 As shown, each frame period may have a structure as shown in 310, that is, each frame period may include a vertical blanking time and an effective time. The vertical blanking time may include a data rate adjustment time (such as Figure 3 DC (Data rate change) in ), and the clock training time (as shown in Figure 3 In the effective time, a signal for display can be transmitted, and the signal may include RGB (Red Green Blue) data.

[0099] For multiple frames, the data rate used for signal transmission can be adjusted in each frame period; alternatively, the frame period can be selected at fixed intervals to adjust the data rate used for signal transmission (for example, the data rate used for signal transmission is adjusted every 2 frame periods); alternatively, the frame period can be randomly selected to adjust the data rate used for signal transmission; alternatively, the frame period can be selected in real time to adjust the data rate used for signal transmission based on other parameters of the circuit.

[0100] For example, in Figure 3 In the figure, from the 1st frame to the 2nd frame, the data rate used for signal transmission changes from f1 to f2; from the 2nd frame to the 5th frame, the data rate used for signal transmission changes from f2 to f3; from the 5th frame to the 6th frame, the data rate used for signal transmission changes from f3 to f4; from the 6th frame to the 7th frame, the data rate used for signal transmission changes from f4 to f5; from the 7th frame to the 10th frame, the data rate used for signal transmission changes from f5 to f6; from the 10th frame to the 11th frame, the data rate used for signal transmission changes from f6 to f7.

[0101] According to an embodiment of the present disclosure, for multiple frame periods, the data rate used for signal transmission can also be periodically adjusted. For example, a first number of frame periods can be used as an adjustment cycle period, and the data rate used for signal transmission can be adjusted so that the data rate changes periodically within the adjustment cycle period, and a second number of frame periods is used as a holding time, and signal transmission is performed at the same data rate within the holding time, wherein the first number and the second number are integers, and the first number is greater than the second number.

[0102] For example, 11 frame periods (i.e., a first number of frame periods) can be used as an adjustment cycle to adjust the data rate used for signal transmission so that the data rate changes periodically within the adjustment cycle. One or more (e.g., 2, 3, 5, etc.) frame periods (i.e., a second number of frame periods) can be used as a holding time, and signal transmission is performed at the same data rate within the holding time, wherein the number of frame periods within the holding time is less than 11.

[0103] For another example, taking 24 frame periods (i.e., the first number of frame periods) as the adjustment cycle, the data rate is adjusted once every 4 frame periods, that is, the maintenance time of each data rate is 4 frame periods (i.e., the second number of frame periods). Specifically, the data rate of the 1st to 4th frame periods is f1, the data rate of the 5th to 8th frame periods is f2, the data rate of the 9th to 12th frame periods is f3, the data rate of the 13th to 16th frame periods is f4, the data rate of the 17th to 20th frame periods is f3, the data rate of the 21st to 24th frame periods is f2, and then the data rate of the 25th to 28th frame periods becomes f1 again.

[0104] Optionally, for a frame period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on the current data rate according to a predetermined adjustment rule (e.g., monotonically increased or decreased by a certain percentage). For example, the data rate may be monotonically increased with a first step length in the first part of the adjustment cycle and monotonically decreased with a second step length in the second part of the adjustment cycle, and the first step length may be the same as or different from the second step length.

[0105] In addition, for a frame period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may also be randomly determined.

[0106] It should be understood that Figure 3 Similar to the embodiment shown, for multiple lines, it can also be determined that the data rate for signal transmission is adjusted in each line period; or, the line period can be selected at fixed intervals to adjust the data rate for signal transmission (for example, the data rate for signal transmission is adjusted every 2 line periods); or, the line period can be randomly selected to adjust the data rate for signal transmission; or, the line period can be selected to adjust the data rate for signal transmission based on other parameters of the circuit.

[0107] In addition, for multiple row periods, the data rate for signal transmission can be periodically adjusted. For example, the third number of row periods can be used as the adjustment cycle period, and the data rate for signal transmission can be adjusted so that the data rate changes periodically within the adjustment cycle period, and the fourth number of row periods is used as the holding time, and the signal transmission is performed at the same data rate within the holding time, wherein the third number and the fourth number are integers, and the third number is greater than the fourth number.

[0108] Optionally, for a row period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on the current data rate according to a predetermined adjustment rule (e.g., monotonically increased or decreased by a certain percentage). For example, the data rate may be monotonically increased with a first step length in a first part of the adjustment cycle and monotonically decreased with a second step length in a second part of the adjustment cycle, and the first step length may be the same as or different from the second step length.

[0109] For example, 20 line periods (i.e., the third number of line periods) can be used as the adjustment cycle, and the data rate can be adjusted once every 5 line periods (i.e., the fourth number of line periods), that is, the maintenance time of each data rate is 5 line periods. Specifically, the data rate of the 1st to 5th line periods is f1, the data rate of the 6th to 10th line periods is f2, the data rate of the 11th to 15th line periods is f3, the data rate of the 16th to 20th line periods is f2, and then the data rate of the 21st to 25th frame periods becomes f1 again.

[0110] Furthermore, for a line period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may also be determined randomly.

[0111] According to an embodiment of the present disclosure, the time length of the frame period and / or the line period may be fixed. The length of the line effective time is associated with the adjusted data rate. The length of the horizontal blanking time may be determined by the length of the line period and the effective time. For example, the horizontal blanking time = line period - line effective time.

[0112] Figure 4A is a schematic diagram showing a data rate adjusted based on a line period according to an embodiment of the present disclosure.

[0113] exist Figure 4AIn the example, the data rate for signal transmission is adjusted with 20 row periods (i.e., the third number of row periods) as the adjustment cycle period and 1 row period (i.e., the fourth number of row periods) as the holding time. Assuming that 870 Mbps is used as the reference data rate, the data rate during the effective time of the first row may be 653 Mbps (i.e., 25% lower than the reference data rate 870 Mbps); the data rate during the effective time of the second row may be 696 Mbps (i.e., 20% lower than the reference data rate 870 Mbps); the data rate during the effective time of the third row may be 740 Mbps (i.e., 15% lower than the reference data rate 870 Mbps)... The data rate during the effective time of the 20th row may be 696 Mbps (i.e., 20% lower than the reference data rate 870 Mbps); the data rate during the effective time of the 21st row may be 653 Mbps (i.e., 25% lower than the reference data rate 870 Mbps). It should be understood that the reference data rate may be the rated data rate for signal transmission, but is not limited thereto.

[0114] for Figure 4A In the example shown, the data rate of each row period in the cycle is adjusted as follows Figure 4B That is, the data rate increases monotonically in the 1st to 11th rows of the adjustment cycle and decreases monotonically in the 12th to 21st rows of the adjustment cycle. The adjustment range of the data rate is ±25% within the data transmission range that the receiving end of the signal transmission can process.

[0115] Figure 5 It shows that for Figure 4A-4B A schematic diagram of the signal spectrum of the embodiment shown.

[0116] like Figure 5 As shown, for Figure 4A-4B In the embodiment shown, the spectrum of a single line period is as follows: Line 1-21 (data rate varies between 653 Mbps and 1088 Mbps). Figure 5 The spectrum of the entire adjustment cycle obtained by integrating the spectrum of each row period is as follows: Figure 5 As shown in the gray thick curve in the middle and lower part, it can be seen that, through the signal transmission method of the present application, the electromagnetic radiation energy is much lower than the electromagnetic radiation energy when a single data rate is used for signal transmission.

[0117] Fig. 6A is a schematic diagram showing a data rate adjusted based on a line period according to an embodiment of the present disclosure.

[0118] exist Fig. 6AIn the example, 4 row periods are used as the adjustment cycle period, and 1 row period is used as the holding time to adjust the data rate used for signal transmission. Assuming that 600Mbps is used as the reference data rate, the data rate during the effective time of the first row can be 594Mbps (i.e., 1% lower than the reference data rate of 600Mbps); the data rate during the effective time of the second row can be 600Mbps; the data rate during the effective time of the third row can be 606Mbps (i.e., 1% higher than the reference data rate of 600Mbps); the data rate during the effective time of the fourth row can be 600Mbps, so the first to fourth rows can be used as one adjustment cycle period. Similarly, the fifth to eighth rows, the ninth to twelfth rows, ..., the 4n-3rd to 4nth rows can respectively constitute adjustment cycles, where n is an integer greater than or equal to 1.

[0119] for Fig. 6A In the example shown, the data rate of each line period varies as follows Figure 6B As shown, Figure 6B The vertical axis represents the data rate (unit: Mbps), and the horizontal axis represents the time (unit: μs). That is, the data rate changes regularly around the reference data rate based on the reference data rate of 600Mbps, with 4 line periods as the adjustment cycle and 1 line period as the holding time.

[0120] Similarly, according to the embodiment of the present disclosure, Fig. 6A and Figure 6B In a similar manner as shown, the data rate is adjusted based on the frame period.

[0121] Fig. 7A is another schematic diagram showing a data rate adjusted based on a line period according to an embodiment of the present disclosure.

[0122] exist Fig. 7A In the example, 8 row periods are used as the adjustment cycle period, and 2 row periods are used as the holding time to adjust the data rate used for signal transmission. Assuming that 600Mbps is used as the reference data rate, the data rate during the effective time of the 1st and 2nd rows can be 600Mbps; the data rate during the effective time of the 3rd and 4th rows can be 594Mbps (i.e., 1% lower than the reference data rate of 600Mbps); the data rate during the effective time of the 5th and 6th rows can be 600Mbps; the data rate during the effective time of the 7th and 8th rows can be 606Mbps (i.e., 1% higher than the reference data rate of 600Mbps), so the 1st to 8th rows can be used as 1 adjustment cycle period. Similarly, the 9th to 16th rows, the 17th to 24th rows, ..., the 8n-7th to 8nth rows can respectively constitute adjustment cycles, where n is an integer greater than or equal to 1.

[0123] for Fig. 7A In the example shown, the data rate of each line period varies as follows Figure 7B As shown, Figure 7B The vertical axis represents the data rate (unit: Mbps), and the horizontal axis represents the time (unit: μs). That is, the data rate is adjusted by 8 line periods and maintained for 2 line periods, and changes regularly around the reference data rate of 600 Mbps.

[0124] Similarly, according to the embodiment of the present disclosure, Fig. 7A and Figure 7B In a similar manner as shown, the data rate is adjusted based on the frame period.

[0125] Fig. 8A is another schematic diagram showing the data rate adjusted based on the line period according to an embodiment of the present disclosure.

[0126] exist Fig. 8A In the example, the data rate used for signal transmission is randomly adjusted. Assuming that 600Mbps is used as the reference data rate, the data rate during the effective time of the first row may be 594Mbps (i.e., 1% lower than the reference data rate of 600Mbps); the data rate during the effective time of the second row may be 600Mbps; the data rate during the effective time of the third row may be 606Mbps (i.e., 1% higher than the reference data rate of 600Mbps)... The data rate during the effective time of the 11th row may be 588Mbps (i.e., 2% lower than the reference data rate of 600Mbps), so the data rates of each row may not have a periodic cycle pattern.

[0127] for Fig. 8A In the example shown, the data rate of each line period varies as follows Figure 8B As shown, Figure 8B The vertical axis represents the data rate (unit: Mbps), and the horizontal axis represents the time (unit: μs). That is, the data rate changes randomly, wherein the adjustment range of the data rate is within the data transmission range that the receiving end of the signal transmission can handle. For example, the maximum data rate should be lower than the maximum allowable data rate of the receiving end of the signal transmission, and the minimum data rate should ensure that the data transmission of the corresponding row can be completed within the effective time of the row cycle. Similarly, according to the embodiments of the present disclosure, it is also possible to Fig. 8A and Figure 8B In a similar manner as shown, the data rate is adjusted based on the frame period.

[0128] For the signal transmission method of the present application, the data rate within the line period and the data rate within the frame period can both change randomly.

[0129] For example, assuming that the data rate during the effective time of the Nth row is f, the data rate during the effective time of the Nath row can be f±c%, and the data rate during the effective time of the N+bth row can be f±d%, wherein a and b are the number of rows different from the Nth row, c and d are the amplitude of the data rate change, and a and b can be the same or different values, and c and d can also be the same or different values.

[0130] For another example, assuming that the data rate during the effective time of the Mth frame is f, the data rate during the effective time of the Mxth frame can be f±w%, and the data rate during the effective time of the M+yth frame can be f±z%, wherein x, y are the number of frames different from the Mth frame, w, z are the amplitude of the data rate change, and x, y can be the same or different values, and w, z can also be the same or different values.

[0131] By arbitrarily changing the data rate within the data transmission range that can be processed by the receiving end, the signal transmission method of the present application can be used in a richer range of application scenarios to meet a richer range of data rate change requirements. Fig. 9 900 is a schematic flowchart illustrating a signal transmission method for a display device according to an embodiment of the present disclosure.

[0132] In step S901, the data rate for signal transmission is adjusted during the blanking time. In step S902, signal transmission is performed using the data rate adjusted during the blanking time, wherein the signal transmission cycle of the display device may include the blanking time and the effective time.

[0133] According to an embodiment of the present disclosure, the signal transmission period may be a frame period, the blanking time may be a vertical blanking time, and the data rate used for signal transmission may be adjusted during the vertical blanking time, wherein the adjusted data rate is used for signal transmission in at least one frame after the vertical blanking time, or for signal transmission in at least one line after the vertical blanking time. Optionally, a first number of frame periods may be used as an adjustment cycle period, and the data rate used for signal transmission may be adjusted so that the data rate changes periodically during the adjustment cycle period, and a second number of frame periods is used as a holding time, and signal transmission is performed at the same data rate during the holding time, wherein the first number and the second number are integers, and the first number is greater than the second number. According to an embodiment of the present disclosure, the signal transmission period may be a line period, the blanking time may be a horizontal blanking time, and the data rate used for signal transmission may be adjusted during the horizontal blanking time, wherein the adjusted data rate is used for signal transmission in at least one line after the horizontal blanking time.

[0134] Optionally, a third number of row periods can be used as an adjustment cycle, and a data rate for signal transmission can be adjusted so that the data rate changes periodically within the adjustment cycle, and a fourth number of row periods can be used as a holding time, and signal transmission is performed at the same data rate within the holding time, wherein the third number and the fourth number are integers, and the third number is greater than the fourth number. The row period can have a preset time length, and the length of the effective time is associated with the adjusted data rate; and the length of the horizontal blanking time is determined by the length of the row period and the effective time.

[0135] According to an embodiment of the present disclosure, the data rate change within the adjustment cycle may be less than or equal to a first threshold, and the data rate change between two adjacent data rates may be less than or equal to a second threshold, wherein the first threshold is greater than or equal to the second threshold. For example, the first threshold may be 25% of the reference data rate, and the second threshold may be 5% of the reference data rate. The first threshold and the second threshold may be determined according to actual needs or the performance of the display device hardware. According to an embodiment of the present disclosure, the first threshold and the second threshold may be determined by the maximum allowable data rate and the minimum allowable data rate of the display device hardware, wherein the maximum allowable data rate is determined by the data receiving / processing capability of the receiving end of the signal transmission, and the minimum allowable data rate is determined by the length of the effective time and the amount of data to be transmitted.

[0136] According to an embodiment of the present disclosure, the data rate may increase monotonically in a first portion of the adjustment cycle and decrease monotonically in a second portion of the adjustment cycle, wherein the data rate is lower than a maximum allowable data rate of a receiving end of the signal transmission.

[0137] In addition, both the timing for adjusting signal transmission and the data rate for signal transmission can be determined in a random manner. That is, for a plurality of consecutive signal transmission cycles of the display device, at least one signal transmission cycle for adjusting the data rate of signal transmission can be randomly determined. And, for each signal transmission cycle of the display device, it can also be randomly determined whether to adjust the data rate for signal transmission. It should be understood that the signal transmission cycle here can be either a frame cycle or a line cycle.

[0138] For each signal transmission cycle of the display device, when it is determined that the data rate for signal transmission needs to be adjusted, the adjusted data rate is determined based on the current data rate in accordance with a predetermined adjustment rule (for example, the adjusted data rate may be determined by multiplying the current data rate by a certain proportional coefficient, or the current data rate may be increased or decreased by a certain value to determine the adjusted data rate, etc.); or the adjusted data rate is determined randomly.

[0139] Fig.10FIG. 1 is a schematic diagram showing the composition of a signal transmission device 1000 for a display device according to an embodiment of the present disclosure.

[0140] like Fig.10 As shown, a signal transmission device 1000 for a display device may include: a rate adjustment circuit 1010, configured to: adjust the data rate for signal transmission during a blanking time; a signal transmission circuit 1020, configured to: perform signal transmission during an effective time using the data rate adjusted during the blanking time; wherein the signal transmission cycle of the display device includes the blanking time and the effective time. The rate adjustment circuit 1010 and the signal transmission circuit 1020 are connected by electrical connection.

[0141] Optionally, the signal transmission period may be a frame period, and the blanking time may be a vertical blanking time. In this case, the rate adjustment circuit 1010 may also be configured to: adjust the data rate used for signal transmission during the vertical blanking time, wherein the adjusted data rate is used for signal transmission in at least one continuous frame after the vertical blanking time, or for signal transmission in at least one continuous line after the vertical blanking time.

[0142] Optionally, the signal transmission period may be a line period, and the blanking time may be a horizontal blanking time. In this case, the rate adjustment circuit 1010 may also be configured to: adjust the data rate for signal transmission during the horizontal blanking time, wherein the adjusted data rate is used for signal transmission in at least one continuous line after the horizontal blanking time.

[0143] According to an embodiment of the present disclosure, the rate adjustment circuit 1010 may adjust the data rate used for signal transmission periodically or randomly.

[0144] For example, in the case where the rate adjustment circuit 1010 periodically adjusts the data rate for signal transmission, the data rate may increase monotonically in the first part of the adjustment cycle and decrease monotonically in the second part of the adjustment cycle, wherein the data rate is lower than the maximum allowable data rate of the receiving end of the signal transmission. Optionally, the data rate may increase monotonically with a first step size and decrease monotonically with a second step size, wherein the first step size is the same as or different from the second step size. In the case where the rate adjustment circuit 1010 randomly adjusts the data rate for signal transmission, the rate adjustment circuit 1010 may also be configured to: for a plurality of consecutive signal transmission cycles of the display device, randomly determine at least one signal transmission cycle for adjusting the data rate of signal transmission. In addition, the rate adjustment circuit 1010 may also be configured to: for each signal transmission cycle of the display device, randomly determine whether to adjust the data rate for signal transmission. Optionally, for each signal transmission cycle of the display device, in the case of determining that the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on the current data rate according to a predetermined adjustment rule; or the adjusted data rate may be determined randomly.

[0145] The embodiments of the present disclosure further provide a display device, which may include the signal transmission device described in any of the above embodiments, and transmit a display signal by the signal transmission method described in any of the above embodiments. Optionally, the display device of the present disclosure may include various devices including display screens, such as mobile phones, computers, game consoles, and projectors. The display device of the present disclosure may be based on a point-to-point transmission architecture.

[0146] Therefore, the present disclosure provides a signal transmission method, device and display device for a display device. According to an embodiment of the present disclosure, the signal transmission method for a display device includes: adjusting the data rate for signal transmission during a blanking time; and performing signal transmission during an effective time using the data rate adjusted during the blanking time; wherein the signal transmission cycle of the display device includes the blanking time and the effective time.

[0147] Since the present disclosure adjusts the data rate used for signal transmission during the blanking time, and uses the data rate adjusted during the blanking time for signal transmission during the effective time, it can not only reduce the electromagnetic interference during signal transmission, but also prevent the frequency change from affecting the quality of the picture displayed by the display device, thereby improving the comprehensive performance of the display device. Furthermore, since the present disclosure adjusts the data rate used for signal transmission during the blanking time, it can also significantly expand the range of data rates used for signal transmission, meet the needs of richer data rate transmission, and make the energy of electromagnetic radiation evenly distributed within a larger bandwidth frequency range, thereby further improving the effect of reducing electromagnetic interference during signal transmission. It should be noted that although the above embodiments of the present disclosure are mainly described by taking a display device based on a point-to-point transmission architecture as an example, the data rate adjustment method of the present disclosure can also be applied to a display device with a multi-drop transmission architecture (for example, a micro low voltage differential signal (Mini-LVDS) transmission architecture). That is, in the case of a display device using a Mini-LVDS transmission architecture, the data rate used for signal transmission can also be adjusted in order to expand the range of data rates used for signal transmission and evenly distribute the energy of electromagnetic radiation within a wider bandwidth frequency range, thereby reducing electromagnetic interference during signal transmission.

[0148] Fig.11 is a schematic diagram showing a Mini-LVDS transmission architecture according to an embodiment of the present disclosure. A timing controller (T-CON) is connected to a plurality of source drivers (SD) to drive a plurality of pixels on a display screen for display. Figure 1A Unlike the point-to-point transmission architecture shown in the figure, for the Mini-LVDS transmission architecture, the clock signal and the data signal each have their own transmission path. Fig.11 The transmission lines 11-1, 11-2, 11-3, 11-4, 11-5 and 11-6 shown by the solid lines transmit clock signals. Fig.11 The transmission lines 11-a, 11-b, 11-c, 11-d, 11-e and 11-f shown by the dotted lines transmit data signals. For the Mini-LVDS transmission architecture, since the transmission of data signals and clock signals are independent of each other, there is no need to distinguish between the effective time and the blanking time for transmission, as long as the data signal and the clock signal are adjusted synchronously.

[0149] Therefore, under the Mini-LVDS transmission architecture, it is not necessary to adjust the data rate used for signal transmission during the blanking time as in the point-to-point architecture to ensure that changes in the data rate will not affect the quality of the picture displayed by the display device. Optionally, the data rate used for signal transmission can be adjusted by the following methods and any combination thereof: adjusting the data rate used for signal transmission in units of frame periods, adjusting the data rate used for signal transmission in units of line periods, and adjusting the data rate used for signal transmission in units of unit transmission periods (UI). In addition, the data rate used for signal transmission can also be adjusted within a frame and / or within a line. Under the Mini-LVDS transmission architecture, the above-mentioned various data rate adjustment methods are used to control the specifications of the eye diagrams of the clock signal and the data signal (similar to Figure 1B As shown), to ensure the transmission quality of data signals and clock signals without causing Figure 1C Large jitter shown.

[0150] Fig. 12A 1 is a schematic diagram of a mini-LVDS (mini-low voltage differential signaling) architecture in another display device according to an embodiment of the present invention. The display device 12 includes a controller 120, a data line Ld, a clock line Lck, and source drivers 121 to 126. The mini-LVDS architecture is used for multi-point applications, wherein the controller 120 is coupled to the source drivers 121 to 126 via the data line Ld and the clock line Lck. The controller 120 may be a timing controller that simultaneously transmits a data signal Sd to the source drivers 121 to 126 via the data line Ld and transmits a clock signal Sck to the source drivers 121 to 126 via the clock line Lck. Therefore, the source drivers 121 to 126 may use the clock signal Sck to sample the data signal Sd without the need for clock training. Since the mini-LVDS architecture does not require clock training, the controller 120 may change the data rate of generating the data signal Sd and the clock rate of generating the clock signal Sck at any time. In some embodiments, the controller 120 may change the data rate of the data signal Sd and the clock rate of the clock signal Sck during the active video intervals of the image frame. In other embodiments, the controller 120 may change the data rate of the data signal Sd and the clock rate of the clock signal Sck during the vertical blanking intervals of the image frame. In other embodiments, the controller 120 may change the data rate of the data signal Sd and the clock rate of the clock signal Sck during the horizontal blanking intervals of the image frame.

[0151] The data signal Sd and the clock signal Sck may be transmitted via differential signals, and the data line Ld and the clock line Lck may be a differential pair, respectively used to transmit the data signal Sd and the clock signal Sck. The data signal Sd may carry pixel data. The source drivers 121 to 126 may be further coupled to a display panel, the display panel including a plurality of columns of pixels (hereinafter referred to as pixel columns), and each of the source drivers 121 to 126 may be coupled to a predetermined pixel column. For example, the display panel may have a full high definition (FHD) resolution including 1920 pixel columns, each pixel column including 1080 pixels. The source driver 121 may be connected to the 1st to 320th pixel columns, the source driver 122 may be coupled to the 321st to 640th pixel columns, ..., and the source driver 126 may be coupled to the 1601st to 1920th pixel columns, thereby driving the pixel data to the 1920 pixel columns. The source driver 121 can sample and drive pixel data to the 1st to 320th pixel rows during the first period, the source driver 122 can sample and drive pixel data to the 321st to 640th pixel rows during the second period, ..., the source driver 126 can sample and drive pixel data to the 1601st to 1920th pixel rows during the sixth period, and the first duration to the sixth duration are adjacent in sequence.

[0152] The data rate can be matched with the clock rate. In some embodiments, the data rate can be equal to the clock rate. For example, if the data rate is 600 megahertz (MHz), the clock rate is also 600 MHz. Since the data signal Sd and the clock signal Sck are generated at a continuously changing but same rate, the electromagnetic interference can be evenly distributed on the spectrum of different data rates, effectively reducing electromagnetic interference, reducing total jitter, reducing data loss, and enhancing data security.

[0153] Fig. 12BThe waveform diagram of the display signal Sd and the clock signal Sck and the eye diagram of the display device 12 are shown. FIG.12B shows. The clock signal Sck and the data signal Sd are both differential signals, and therefore each includes an inverted signal and a positive signal. At time t1, the source drivers 121 to 126 receive the first data bit of the data signal Sd. At time t3, the source drivers 121 to 126 receive the clock edge of the clock signal Sck. At time t5, the first data bit ends, and the source drivers 121 to 126 receive the second data bit of the data signal Sd. Therefore, the period between time t1 and time t4 can be called an adjustment period, and the period between time t4 and time t6 can be called a normal period. The interference specification of mini-LVDS defines an eye mask to define the minimum setup time and the minimum hold time. Therefore, the period between time t1 and time t4 can be called an adjustment period, and the period between time t4 and time t6 can be called a normal period. In order to ensure accurate data sampling, the setup time or hold time must exceed the minimum setup time and the minimum hold time, respectively. The setup time and the hold time may vary due to jitter in the data signal Sd and jitter in the clock signal Sck. The sum of the jitter in the data signal Sd and the jitter in the clock signal Sck can be referred to as the total jitter. The greater the total jitter, the shorter the setup time or the hold time. If the total jitter is too large, the setup time or the hold time will be too short to meet the minimum setup time or the minimum hold time, resulting in data loss and reduced performance of the display device 12.

[0154] Fig.13 1 is a flow chart of a method 1300 for transmitting a signal in a display device 12. The method 1300 includes steps S1302 to S1308, which are used to change the data rate of the data signal Sd and the clock rate of the clock signal Sck over time. Any reasonable technical changes or step adjustments fall within the scope of the present invention. Steps S1302 to S1308 are explained as follows:

[0155] Step S1302: the controller 120 sets a data rate cycle;

[0156] Step S1304: the source drivers 121 to 126 simultaneously receive the first data signal and the first clock signal in the first period;

[0157] Step S1306: In the second period, the source drivers 121 to 126 simultaneously receive the second data signal and the second clock signal;

[0158] Step S1308: In the third period, the source drivers 121 to 126 simultaneously receive the third data signal and the third clock signal.

[0159] In step S1302, the controller 120 sets a data rate cycle, and the data rate of the data signal Sd and the clock rate of the clock signal Sck change periodically during the data rate cycle. The data rate cycle may include a group of time periods of equal or unequal length. For example, each time period in the data rate cycle may have a length of 1 line. In another example, 1 time period in the data rate cycle may have a length of 2 lines, another time period in the data rate cycle may have a length of 5 lines, and another time period in the data rate cycle may have a length of 10 lines. In some embodiments, the group of time periods may include a first time period, a second time period, and a third time period, and the first time period, the second time period, and the third time period do not overlap with each other. In some embodiments, the first time period, the second time period, and the third time period may be sequentially adjacent.

[0160] In step S1304, during the first period, the source drivers 121 to 126 simultaneously receive the first data signal generated at the first data rate from the controller 120 via the data line Ld, and simultaneously receive the first clock signal generated at the first clock rate from the controller 120 via the clock line Lck. That is, during the first period, the source drivers 121 to 126 receive the first data signal from the controller 120 via the data line Ld, and simultaneously receive the first clock signal from the controller 120 via the clock line Lck.

[0161] In step S1306, during the second period, the source drivers 121 to 126 simultaneously receive the second data signal generated at the second data rate from the controller 120 via the data line Ld, and simultaneously receive the second clock signal generated at the second clock rate from the controller 120 via the clock line Lck. That is, during the second period, the source drivers 121 to 126 receive the second data signal from the controller 120 via the data line Ld, and simultaneously receive the second clock signal from the controller 120 via the clock line Lck.

[0162] In step S1308, during the third period, the source drivers 121 to 126 simultaneously receive the third data signal generated at the third data rate from the controller 120 via the data line Ld, and simultaneously receive the third clock signal generated at the third clock rate from the controller 120 via the clock line Lck. That is, during the third period, the source drivers 121 to 126 receive the third data signal from the controller 120 via the data line Ld, and simultaneously receive the third clock signal from the controller 120 via the clock line Lck.

[0163] The data signal Sd may include a first data signal, a second data signal, and a third data signal, and the data rate may include a first data rate, a second data rate, and a third data rate, and the first data rate, the second data rate, and the third data rate are different from each other. Similarly, the clock signal Sck may include a first clock signal, a second clock signal, and a third clock signal, and the clock rate may include a first clock rate, a second clock rate, and a third clock rate, and the second clock rate and the third clock rate match the first data rate, the second data rate, and the third data rate, respectively. In some embodiments, the first data rate may be equal to the first clock rate, the second data rate may be equal to the second clock rate, and the third data rate may be equal to the third clock rate.

[0164] Generally speaking, the greater the difference between the data rates of two adjacent time periods, the smaller the interference. For example, a 50 MHz difference between the first data rate and the second data rate may produce less interference than a 5 MHz difference between the first data rate and the second data rate. The data rate cycle may be line-based. In a data rate cycle, the source drivers 121 to 126 may receive a first number of frames, and in each time period in the group of time periods of the data rate cycle, the source drivers 121 to 126 may receive a second number of frames. The first number and the second number may be positive integers, and the first number may exceed the second number. For example, if the first number is 21 and the second number is 1, the source drivers 121 to 126 may receive 21 frames in each data rate cycle and 1 frame in each time period. Fig.14A shown. Fig.14A This will be explained in detail in the following paragraphs. In another example, if the first number is 20 and the second number is 2, the source drivers 121 to 126 can receive 21 frames in each data rate cycle, and receive 2 frames in each time period.

[0165] Fig.14A , Fig. 14B and Fig. 14C A schematic diagram showing various data rate cycles is suitable for display device 12. Fig.14AIn the embodiment, the data rate cycle includes a group of time periods, which includes 21 frames (frames 1 to 21), and each time period has a duration of 1 frame. In the data rate cycle, the data rate of the data signal Sd is adjusted within a range of plus or minus 25% with 870 MHz as the center data rate. In each time period in the data rate cycle, the data rate of the data signal Sd is adjusted from the previous data rate with 5% of the center data rate as the difference. In the present embodiment, the data rate of the data signal Sd increases from a minimum data rate of 653 MHz to a maximum data rate of 1088 MHz from frames 1 to 11, and then decreases from a maximum data rate of 1088 MHz to a minimum data rate of 653 MHz from frames 11 to 21, and the data rate of each time period differs from the previous time period by 43.5 MHz (=870*5%). For example, the data rate of the data signal Sd in the first time period (frame 1) is 653 MHz, the data rate of the data signal Sd in the second time period (frame 2) is 696 MHz (≈653+43.5), and the data rate of the data signal Sd in the third time period (frame 3) is 740 MHz (≈696+43.5). The minimum data rate can be determined by the frame rate, resolution, number of channels (e.g., red, green, and blue channels) of the display device 12, and the number of source drivers. The maximum data rate can be determined by the smallest of the maximum data rates of the controller 120 and the source drivers 121 to 126. Fig. 14B and Fig. 14C , frame F(n-1) may be sent between time t1 and time t3, frame F(n) may be sent between time t3 and time t5, and frame F(n+1) may be sent between time t5 and time t7, where n is a positive integer. For example, n=5, 3 consecutive frames are frames F(4), F(5), and F(6). Each frame may include a vertical blanking period VB and an effective image period AF. Although Fig. 14B and Fig. 14C 3 consecutive frames F(n-1), F(n) and F(n+1) are displayed. In some embodiments, these 3 frames may also be discontinuous frames. In some embodiments, the 3 frames may be frames F(nx), F(n) and F(n+y), where x and y are non-zero numbers, and x and y may be the same or different. For example, n=5, x=2, y=3, and the 3 frames are frames F(3), F(5) and F(8).

[0166] exist Fig. 14B, the first time period, the second time period and the third time period start at the vertical blanking period VB of the frame F(n-1) to F(n+1). The first time period may occur between time t2 and time t4, the second time period may occur between time t4 and time t6, and the third time period may occur between time t6 and time t8. In the first time period, the first data rate of the first data signal may be fw%, in the second time period, the second data rate of the second data signal may be f, and in the third time period, the third data rate of the third data signal may be f+z%, where f is a positive number, w and z are non-zero numbers, and w and z may be the same or different.

[0167] In some embodiments, the first data rate fw% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by a non-zero fixed difference z%, that is, w=z. For example, f=870MHz, w%=z%=5%, then the first data rate is 827MHz (=870-870*5%), the second data rate is 870MHz, and the third data rate is 914MHz (=870+870*5%).

[0168] In other embodiments, the first data rate fw% and the second data rate f differ by a first non-zero random difference w%; the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, i.e., w≠z. For example, f=870MHz, w%=8%, z%=6%, then the first data rate is 800MHz (=870-870*8%), the second data rate is 870MHz, and the third data rate is 922MHz (=870+870*6%).

[0169] Since each period may start in the vertical blanking period VB of the frame (eg, t2 may be located in VB), the data signal Sd may have sufficient time (eg, from t2 to the start of AF) to be stable before transmitting effective image data in the effective image period AF.

[0170] exist Fig. 14C , the first time period, the second time period, and the third time period start in the effective image time period AF of the frame F(n-1) to F(n+1). The first time period may occur between time t2 and time t4, the second time period may occur between time t4 and time t6, and the third time period may occur between time t6 and the end time. In the first time period, the first data rate of the first data signal may be fw%; in the second time period, the second data rate of the second data signal may be f, and in the third time period, the third data rate of the third data signal may be f+z%, where f may be a positive number, w and z may be non-zero numbers, and w and z may be the same or different.

[0171] In some embodiments, the first data rate fw% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by a non-zero fixed difference z%, that is, w=z. For example, f=870MHz, w%=z%=5%, then the first data rate is 827MHz (=870-870*5%), the second data rate is 870MHz, and the third data rate is 914MHz (=870+870*5%).

[0172] In other embodiments, the first data rate fw% and the second data rate f differ by a first non-zero random difference w%; the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, i.e., w≠z. For example, f=870MHz, w%=8%, z%=6%, then the first data rate is 800MHz (=870-870*8%), the second data rate is 870MHz, and the third data rate is 922MHz (=870+870*6%).

[0173] Since each period starts in the effective image period AF of the frame, the controller 120 can change the data rate of the data signal Sd more flexibly.

[0174] For a line-based data rate cycle, the data rate cycle and each time period in the data rate cycle are calculated in terms of lines. In a line-based data rate cycle, the source drivers 121 to 126 may receive a first number of lines, and in each time period in the group of time periods of the line-based data rate cycle, the source drivers 121 to 126 may receive a second number of lines. The first number and the second number may be positive integers, and the first number may exceed the second number. For example, if the first number is 21 and the second number is 1, the source drivers 121 to 126 may receive 21 lines in each data rate cycle, and 1 line in each time period. In another example, if the first number is 20 and the second number is 2, the source drivers 121 to 126 may receive 21 lines in each data rate cycle, and 2 lines in each time period.

[0175] Fig.15A and Fig. 15B A schematic diagram showing various line-based data rate cycles is applicable to the display device 12. Fig.15A and Fig. 15B , row L(n-1) may be sent between time t1 and time t3, row L(n) may be sent between time t3 and time t5, and row L(n+1) may be sent between time t5 and time t7, where n is a positive integer. For example, n=5, and 3 consecutive rows are rows L(4), L(5), and L(6). Each row of pixels may include a horizontal blanking period HB and an effective image period AL. Although Fig.15A and 15B3 consecutive rows L(n-1), L(n) and L(n+1) are shown. In some embodiments, these 3 rows may also be discontinuous rows. In some embodiments, these 3 rows may be rows L(nx), L(n) and L(n+y), where x and y are non-zero numbers, and x and y may be the same or different. For example, n=5, x=2, y=3, and the 3 rows are rows L(3), L(5) and L(8).

[0176] exist Fig.15A , the first time period, the second time period, and the third time period start at the horizontal blanking period HB of the lines L(n-1) to L(n+1). The first time period may occur between time t2 and time t4, the second time period may occur between time t4 and time t6, and the third time period may occur between time t6 and time t8. In the first time period, the first data rate of the first data signal may be fw%, in the second time period, the second data rate of the second data signal may be f, and in the third time period, the third data rate of the third data signal may be f+z%, where f is a positive number, w and z are non-zero numbers, and w and z may be the same or different.

[0177] In some embodiments, the first data rate fw% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by a non-zero fixed difference z%, that is, w=z. For example, f=870MHz, w%=z%=5%, then the first data rate is 827MHz (=870-870*5%), the second data rate is 870MHz, and the third data rate is 915MHz (=870+870*5%).

[0178] In other embodiments, the first data rate fw% and the second data rate f differ by a first non-zero random difference w%; the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, i.e., w≠z. For example, f=870MHz, w%=8%, z%=6%, then the first data rate is 800MHz (=870-870*8%), the second data rate is 870MHz, and the third data rate is 922MHz (=870+870*6%).

[0179] Since each period starts in the horizontal blanking period HB of the row (eg, t2 may be located in HB), the data signal Sd may have enough time (eg, from t2 to the beginning of AL) to be stable before transmitting effective image data in the effective image period AL.

[0180] exist Fig. 15B, the first time period, the second time period and the third time period start in the effective image time period AL of the lines L(n-1) to L(n+1). The first time period may occur between time t2 and time t4, the second time period may occur between time t4 and time t6, and the third time period may occur between time t6 and the end time. In the first time period, the first data rate of the first data signal may be fw%; in the second time period, the second data rate of the second data signal may be f, and in the third time period, the third data rate of the third data signal may be f+z%, where f may be a positive number, w and z may be non-zero numbers, and w and z may be the same or different.

[0181] In some embodiments, the first data rate fw% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by a non-zero fixed difference z%, that is, w=z. For example, f=870MHz, w%=z%=5%, then the first data rate is 827MHz (=870-870*5%), the second data rate is 870MHz, and the third data rate is 915MHz (=870+870*5%).

[0182] In other embodiments, the first data rate fw% and the second data rate f differ by a first non-zero random difference w%; the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, i.e., w≠z. For example, f=870MHz, w%=8%, z%=6%, then the first data rate is 800MHz (=870-870*8%), the second data rate is 870MHz, and the third data rate is 922MHz (=870+870*6%).

[0183] Since each period starts in the effective image period AL of a row, the controller 120 can change the data rate of the data signal Sd more flexibly.

[0184] Fig.16 : represents the frequency response of the display device, where the horizontal axis represents the frequency in MHz and the vertical axis represents the amplitude in decibel milliwatts (dBm). Specifically, Fig.16The conventional data signal 160 using a constant data rate in the conventional display device, the new data signal 162 using a variable data rate in the display device 12, and the background noise signal 164 representing the background noise on the data line Ld in the display device 12 are shown. The conventional data signal 160 shows humps H1 to H4, wherein the hump H1 indicates that the gain is too large between 720 MHz and 770 MHz, the hump H2 indicates that the gain is too large between 770 MHz and 820 MHz, the hump H3 indicates that the gain is too large between 820 MHz and 870 MHz, and the hump H4 indicates that the gain is too large between 870 MHz and 920 MHz. Since data transmission generates energy accumulation at a constant data rate and harmonic frequencies, the conventional data signal 160 generates humps H1 to H4, thereby generating significant electromagnetic interference. In contrast, since the energy of data transmission is evenly distributed over the spectrum by varying the data rate, the new data signal 162 does not have a bump in the spectrum from 720 MHz to 920 MHz, thereby reducing electromagnetic interference, reducing overall jitter, reducing data loss, and enhancing data security.

[0185] Fig.17 The waveforms of the data signal Sd and the vertical start pulse signal STV of the display device 12 are represented by a data rate cycle, wherein the data rate of the data signal Sd is adjusted in each frame, the horizontal axis represents time t, and the vertical axis represents voltage V. At the beginning of each frame, a pulse of the vertical start pulse signal STV occurs. At time t1, the vertical start pulse signal STV has a first pulse, indicating that the frame F(n) begins. Between time t1 and time t2, the data of the frame F(n) is transmitted on the data signal Sd at a first data rate. At time t2, the vertical start pulse signal STV has a second pulse, indicating that the frame F(n+1) begins. Between time t2 and time t3, the data of the frame F(n+1) is transmitted on the data signal Sd at a second data rate. At time t3, the vertical start pulse signal STV has a third pulse, indicating that the subsequent frame begins. The first data rate and the second data rate are different, thereby reducing electromagnetic interference, reducing total jitter, reducing data loss, and enhancing data security.

[0186] Fig.18 The waveform of the data signal Sd of the display device 12 adopts a data rate cycle based on a line, wherein the data rate of the data signal Sd is adjusted in each line.

[0187] Between time t1 and time t2, data of row L(n-1) is transmitted on data signal Sd at a first data rate. Between time t2 and time t3, data of row L(n) is transmitted on data signal Sd at a second data rate. Between time t3 and time t4, data of row L(n+1) is transmitted on data signal Sd at a third data rate. The first data rate, the second data rate, and the third data rate are different from each other, thereby reducing electromagnetic interference, reducing overall jitter, reducing data loss, and enhancing data security.

[0188] In the point-to-point architecture shown in FIG. 1 , when the display device is started, clock training is performed between the source driver SD and the timing controller T-CON. The source driver SD responsible for driving the display data to the display panel can first receive a training clock from the timing controller T-CON to train and lock the clock of the source driver SD. Once the clock is locked, the display device can execute a programmable dynamic frequency change (PDFC) procedure. In the PDFC procedure, the timing controller T-CON can dynamically change the data rate of the pixel packet in the active area of ​​each frame without sending additional training clocks, thereby providing flexible dynamic data rate adjustment capabilities. As long as the data rate change remains within a preset range, the source driver SD can track the phase and frequency of the clock based on the clock information embedded in the pixel packet. For a center data rate of 1390Mbps, the preset range can be ±100Mps, and for a center data rate of 870Mbps, the preset range can be ±130Mps. In this way, the source driver SD can continuously adjust the clock based on each line or even each pixel packet, and adaptively update the clock to keep synchronization with the changing data rate in a single frame without the need to perform independent clock training every time the data rate changes, thereby minimizing electromagnetic interference, reducing overall jitter, reducing data loss, and improving data security.

[0189] Fig.19 express Figure 1A Flowchart of an exemplary method 19 for transmitting data in a display device in FIG. 19. Method 19 includes steps S1902 to S1912 for changing the data rate of a pixel packet in a point-to-point architecture. Any reasonable step changes or adjustments are within the scope of the present disclosure. Steps S1902 to S1912 are specifically as follows: Step S1902: The timing controller T-CON changes the data rates of a plurality of pixel packets in a set of lines in an active area on a per-line basis;

[0190] Step S1904: the source driver SD monitors the data rate of the pixel packets in the effective area of ​​the frame;

[0191] Step S1906: The source driver SD generates a synchronization clock according to the data rate synchronization clock of the pixel packet;

[0192] Step S1908: The source driver SD determines whether the clock is locked. If yes, proceed to step S1910; if no, proceed to step S1912;

[0193] Step S1910: The source driver SD uses the synchronous clock to fetch the data in the pixel packet;

[0194] Step S1912: The source driver SD performs clock training; proceed to step S1908.

[0195] In step S1902, the timing controller T-CON changes the data rates of the plurality of pixel packets of a row group in the active area on a row-by-row basis by increasing or decreasing the data rate within a preset data rate range. The preset data rate range can be calculated based on a first ratio of the center data rate, such as ±25% of the center data rate. For example, if the center data rate is 870 Mbps, the preset data rate range is 653 Mbps (=

[0196] 870*0.75) to 1088Mbps (=870*1.25). In some embodiments, the increase or decrease of the data rate can be performed in one direction with a fixed value, and this fixed value can be a second ratio of the center data rate within the preset data rate range. This fixed value can be less than the preset limit value (such as 100Mbps) to improve the success rate of the source driver SD in achieving clock synchronization. For example, Figure 4A As shown, the timing controller T-CON increases the data rate of the pixel packets on rows 1 to 11 (row group) from 653Mbps to 1088Mbps (preset data rate range). The increase in the data rate of each row may be the data rate of the previous row plus a fixed value (such as 5% of the center data rate of 870Mbps, i.e., plus 43.5Mbps). In addition, the timing controller T-CON reduces the data rate of the pixel packets on rows 11 to 21 (row group) from 1088Mbps to 653Mbps (within the preset data rate range). The reduction in the data rate of each row may be the data rate of the previous row minus a fixed value (such as 43.5Mbps (=870*0.05)). In other embodiments, the increase or decrease in the data rate may also be an indefinite value. The indefinite value may be less than the preset limit value (such as 100Mbps) to increase the success rate of the source driver SD in achieving clock synchronization. For example, if Fig. 8AAs shown, the timing controller T-CON reduces the data rate of row 1 to 594Mbps (1% lower than the center data rate of 600Mbps), maintains the data rate of row 2 at the center data rate of 600Mbps, and increases the data rate of row 3 to 606Mbps (1% higher than the center data rate of 600Mbps). In addition, the timing controller T-CON reduces the data rate of row 7 to 588Mbps (2% lower than the center data rate of 600Mbps), maintains the data rate of row 8 at the center data rate of 600Mbps, and increases the data rate of row 9 to 612Mbps (2% higher than the center data rate of 600Mbps).

[0197] In steps S1904 and S1906 , the source driver SD monitors the data rate of the pixel packets in the effective area of ​​the frame and synchronizes the clock of the source driver SD according to the data rate of the pixel packets to generate a synchronization clock. Fig. 20 A timing diagram representing frames F(p) and F(p+1) displayed on a display device, where p is a positive integer. Each frame includes a vertical blanking period VB and an active area AA. The vertical blanking period VB may include a training clock CT. The active area AA may include a dummy row Pre-DE1, N pixel rows, and dummy rows Post-DE1 to Post-DE3, where N is a positive integer (e.g., N=1080). The dummy row Pre-DE1, N pixel rows, and dummy rows Post-DE1 to Post-DE3 may be transmitted at different data rates, but a consistent data rate is maintained within each row. Each of the dummy row Pre-DE1, N pixel rows, and dummy rows Post-DE1 to Post-DE3 may include M pixel packets, where M is a positive integer (e.g., M=1920). The pixel packets in the N pixel rows can carry the color data of the pixels (such as RGB data), while the pixel packets in the dummy rows Pre-DE1, Post-DE1 to Post-DE3 can serve as a protection interval between the N pixel rows and the vertical blanking period VB and do not contain any color data.

[0198] The format of the pixel packet is as follows Fig.21 As shown, the horizontal axis represents time t and the vertical axis represents voltage. Fig.21A schematic diagram showing pixel packets in consecutive rows L(n) and L(n+1), where n is an integer from 1 to N. Each pixel packet may include a delimiter field of 2 UI and a load field of 12 UI, the delimiter field including clock information and the load field including color data of the pixel. The source driver SD identifies a delimiter pulse from the delimiter field Dlimt(M) of the pixel packet P(M) in row L(n) to monitor the data rate of the pixel packet P(M) in row L(n). The delimiter field Dlimt(M) may be 2 bits long and may include a logic value of "0", and the next bit may be a logic value of "1". The source driver SD detects a clock edge (falling edge) at time t0 and another clock edge (rising edge) at time t1, thereby identifying the phase t0 and width UI(M) (=t1-t0) of the delimiter pulse of the pixel packet P(M). Subsequently, the source driver SD calculates the inverse of the width UI(M) to estimate the data rate of the pixel packet P(M). In addition, the source driver SD adjusts the phase of the clock according to the phase t0 of the delimiting pulse and adjusts the frequency of the clock according to the data rate of the pixel packet P(M) to synchronize the clock. In some embodiments, the source driver SD adjusts the phase of the clock to match the phase t0 of the delimiting pulse of the pixel packet P(M), and adjusts the frequency of the clock to match the data rate of the pixel packet P(M). Between time t2 and time t5, the source driver SD receives 12 bits of payload data in the payload field Dpx(M) of the pixel packet P(M) in row L(n), and each bit of the payload data has a length of 1UI(M). In this embodiment, the first bit of the payload data arrives between time t2 and time t3, and the last bit of the payload data arrives between time t4 and time t5. The length of each bit in the payload field Dpx(M) is 1UI(M).

[0199] In step S1908, the source driver SD determines whether the pulse is locked after the clock is synchronized. Since the clock is locked, the source driver SD uses the synchronous clock to extract the load data of the pixel packet P(M) in the row L(n) (S1910). If the clock is not locked, the source driver SD may send a signal to the timing controller T-CON to indicate that it is no longer synchronized. After receiving the signal, the timing controller T-CON may transmit the training clock to the source driver SD, prompting the source driver SD to perform clock training (step S1912). Subsequently, the source driver SD determines whether the clock is locked (step S1908). Steps S1912 and S1908 are repeatedly executed until the clock is synchronized. Once locked, the load data of the pixel packet can be generated using the synchronous clock.

[0200] Similarly, steps S1902 to S1910 may send the pixel packet P(1) in row L(n+1) at a data rate different from that of the pixel packet P(M) in row L(n). In step S1902, the timing controller T-CON changes the data rate of the pixel packet P(1) in row L(n+1). In steps S1904 and S1906, the source driver SD identifies the delimiting pulse from the delimiting field Dlimt(1) of the pixel packet P(1) in row L(n+1) to monitor the data rate of the pixel packet P(1) in row L(n+1). The source driver SD detects a clock edge (falling edge) at time t5 and another clock edge (rising edge) at time t6, thereby identifying the phase t5 and width UI(1) (=t6-t5) of the delimiting pulse of the pixel packet P(1). Subsequently, the source driver SD calculates the inverse of the width UI(1) to estimate the data rate of the pixel packet P(1). Since the width UI(1) is different from the width UI(M), the data rate of the pixel packet P(1) is different from the data rate of the pixel packet P(M). In addition, the source driver SD adjusts the phase of the clock according to the phase t5 of the delimiting pulse of the pixel packet P(1) and adjusts the frequency of the clock according to the data rate of the pixel packet P(1) to synchronize the clock. Between time t7 and time t8, the source driver SD receives the first bit of the load data in the load field Dpx(1) of the pixel packet P(1), and in step S1908, the source driver SD determines whether the clock is locked after the clock synchronization. The length of each bit in the load field Dpx(1) is 1UI(1). Since the clock is locked, the source driver SD uses the synchronous clock to fetch the load data of the pixel packet P(1) in row L(n+1) (S1910).

[0201] Fig. 20 The signal timing diagram in the source driver SD is shown, including the data signal Ldat, the clock signal Tx CLK, the load signal LD, the output signal Output, the frequency switching signal Fsw, the clock signal SD CLK and the lock signal SD lock. The timing controller T-CON operates based on the clock signal Tx CLK, and the source driver SD operates based on the clock signal SD CLK. In the frame F(p), the data rates of the rows L(N-1) and L(N) and the dummy rows Post-DE1 to Post-DE3 can be changed. In the frame F(p+1), the data rates of the dummy row Pre-DE1 and the rows L(1) and L(2) can be changed.

[0202] At time t1, the timing controller T-CON switches the clock signal Tx CLK from 696Mbps to 740Mbps to generate a pixel packet in the row L(N) of the frame F(p), which is then transmitted on the data signal Ldat. Therefore, the row L(N) of the frame F(p) has a data rate of "740Mbps". At the same time, the timing controller T-CON transmits the pulse psw1 in the frequency switching signal Fsw to the source driver SD. Between time t1 and time t2, the pulse psw1 appears in the frequency switching signal Fsw, and the clock signal SD CLK is converted from 696Mbps to 740Mbps according to the data rate "740Mbps" of the row L(N), thereby synchronizing the clock signal SD CLK with the clock signal Tx CLK. The source driver SD obtains the pixel packet in the row L(N) of the frame F(p) according to the update data rate "740Mbps" of the clock signal SD CLK. At time t3, the source driver SD completes receiving the pixel packet in row L(N-1) of frame F(p). Between time t3 and time t4, a pulse pd1 is generated in the load signal LD, prompting the source driver SD to convert row L(N-1) from digital to analog, thereby generating row L'(N-1) in the output signal Output). Between time t2 and time t5, the frequency of the clock signal SDCLK ​​is maintained at 740Mbps. The lock signal SD lock is maintained at a logic value "1" between time t1 and time t5, indicating that the clock signal SD CLK is synchronized.

[0203] At time t5, the timing controller T-CON switches the clock signal Tx CLK from 740Mbps to 783Mbps, and generates a pixel packet in the dummy row Post-DE1 of the frame F(p) to be transmitted on the data signal Ldat. Therefore, the dummy row Post-DE1 of the frame F(p) has a data rate of "783Mbps". At the same time, the timing controller T-CON transmits the pulse psw2 in the frequency switching signal Fsw to the source driver SD. The pulse psw2 converts the clock signal SD CLK from 740Mbps to 783Mbps according to the data rate "783Mbps" of the dummy row Post-DE1, thereby synchronizing the clock signal SD CLK with the clock signal Tx CLK. The source driver SD obtains the pixel packet in the dummy row Post-DE1 of the frame F(p) according to the update data rate "783Mbps" of the clock signal SD CLK. At time t6, the source driver SD completes receiving the pixel packet in row L(N) of frame F(p), and a pulse pd2 is generated in the load signal LD, causing the source driver SD to convert row L(N) from digital to analog, thereby generating row L'(N) in the output signal Output. Until time t7, the clock signal SD CLK maintains a frequency of 783Mbps. The lock signal SD lock maintains a logic value of "1" between time t5 and time t7, indicating that the clock signal SD CLK is synchronized.

[0204] At time t7, the timing controller T-CON switches the clock signal Tx CLK from 783Mbps to 827Mbps, and generates a pixel packet in the dummy row Post-DE2 of the frame F(p) to be transmitted on the data signal Ldat. Therefore, the dummy row Post-DE2 of the frame F(p) has a data rate of "827Mbps". At the same time, the timing controller T-CON transmits the pulse psw3 in the frequency switching signal Fsw to the source driver SD. The pulse psw3 converts the clock signal SD CLK from 783Mbps to 827Mbps according to the data rate "827Mbps" of the dummy row Post-DE2, thereby synchronizing the clock signal SD CLK with the clock signal Tx CLK. The source driver SD obtains the pixel packet in the dummy row Post-DE2 of the frame F(p) according to the update data rate "827Mbps" of the clock signal SD CLK. At time t8, the source driver SD completes receiving the pixel packet in the dummy row Post-DE1 of the frame F(p), and a pulse pd3 is generated in the load signal LD, prompting the source driver SD to convert the dummy row Post-DE1 from digital to analog, thereby generating a dummy row Post-DE1' in the output signal Output. Until time t9, the clock signal SD CLK maintains a frequency of 827Mbps. The lock signal SD lock maintains a logic value of "1" between time t7 and time t9, indicating that the clock signal SD CLK is synchronized.

[0205] At time t9, the timing controller T-CON switches the clock signal Tx CLK from 827Mbps to 870Mbps, and generates a pixel packet in the dummy row Post-DE3 of the frame F(p) to be transmitted on the data signal Ldat. Therefore, the dummy row Post-DE3 of the frame F(p) has a data rate of "870Mbps". At the same time, the timing controller T-CON transmits the pulse psw4 in the frequency switching signal Fsw to the source driver SD. The pulse psw4 converts the clock signal SD CLK from 827Mbps to 870Mbps according to the data rate "870Mbps" of the dummy row Post-DE3, thereby synchronizing the clock signal SD CLK with the clock signal Tx CLK. The source driver SD obtains the pixel packet in the dummy row Post-DE3 of the frame F(p) according to the update data rate "870Mbps" of the clock signal SD CLK. At time t10, the source driver SD completes receiving the pixel packet in the dummy row Post-DE2 of the frame F(p), and a pulse pd4 is generated in the load signal LD, prompting the source driver SD to convert the dummy row Post-DE2 from digital to analog, thereby generating a dummy row Post-DE2' in the output signal Output. Until time t11, the clock signal SD CLK remains at a frequency of 870Mbps. The lock signal SD lock remains at a logic value "1" between time t9 and time t11, indicating that the clock signal SD CLK is synchronized. At time t11, the timing controller T-CON switches the clock signal Tx CLK from 870Mbps to 696Mbps, generating a pixel packet in a row of the frame F(p+1) for transmission on the data signal Ldat. At the same time, the timing controller T-CON transmits a pulse psw5 in the frequency switching signal Fsw to the source driver SD. The pulse psw5 attempts to convert the clock signal SD CLK from 870Mbps to 696Mbps. However, the clock signal SD CLK fails to achieve synchronization at 696Mbps, so the frequency of the clock signal SD CLK decreases to 0Mbps, resulting in the lock signal SD lock being a logic value "0". After time t11, the source driver SD continues to synchronize the clock signal SD CLK with the clock signal Tx CLK according to the data rate "696Mbps" of the training clock CT. At time t12, the source driver SD successfully synchronizes the clock signal SD CLK with the clock signal Tx CLK to achieve a frequency of 696Mbps. Once the clock signal SD CLK is synchronized, the lock signal SD lock switches from a logic value "0" to a logic value "1". Since the clock signal SD CLK is not synchronized, the source driver SD cannot decode the pulse corresponding to the dummy row Post-DE3 in the load signal LD. Therefore, between time t11 and time t18, the dummy row Post-DE2' remains in the output signal OUTPUT.At time t13, the timing controller T-CON transmits the pulse psw6 in the frequency switching signal Fsw to the source driver SD. The pulse psw6 converts the clock signal SD CLK from 696Mbps to 653Mbps according to the training clock CT of "653Mbps", thereby synchronizing the clock signal SD CLK. The frequency of the clock signal SD CLK is synchronized to 635Mbps. Therefore, the lock signal SD lock remains at the logic value "1" between time t14 and time t15, indicating that the clock signal SD CLK is synchronized.

[0206] At time t15, the timing controller T-CON switches the clock signal Tx CLK from 653Mbps to 696Mbps, and generates a pixel packet in the dummy row Pre-DE1 of the frame F(p+1) to be transmitted on the data signal Ldat. Therefore, the dummy row Pre-DE1 of the frame F(p+1) has a data rate of "696Mbps". At the same time, the timing controller T-CON transmits the pulse psw7 in the frequency switching signal Fsw to the source driver SD. The pulse psw7 converts the clock signal SD CLK from 653Mbps to 696Mbps according to the data rate "696Mbps" of the dummy row re-DE1, thereby synchronizing the clock signal SD CLK with the clock signal Tx CLK. The source driver SD obtains the pixel packet in the dummy row Pre-DE1 of the frame F(p+1) according to the update data rate "696Mbps" of the clock signal SD CLK. At time t16, a pulse pd5 is generated in the load signal LD, so that the dummy row Post-DE2' remains in the output signal OUTPUT. Until time t17, the clock signal SD CLK maintains a frequency of 696Mbps. The lock signal SD lock maintains a logic value "1" between time t15 and time t17, indicating that the clock signal SD CLK is synchronized.

[0207] At time t17, the timing controller T-CON switches the clock signal Tx CLK from 696Mbps to 740Mbps, generating a pixel packet in row L(1) of frame F(p+1) for transmission on the data signal Ldat. Therefore, row L(1) of frame F(p+1) has a data rate of "740Mbps". At the same time, the timing controller T-CON transmits pulse psw8 in the frequency switching signal Fsw to the source driver SD. Pulse psw8 converts the clock signal SD CLK from 696Mbps to 740Mbps according to the data rate "740Mbps" of row L(1) of frame F(p+1), thereby synchronizing the clock signal SD CLK with row L(1) of frame F(p+1). The source driver SD obtains the pixel packet in the dummy row Pre-DE1 of frame F(p) according to the update data rate "740Mbps" of the clock signal SD CLK. At time t18, the source driver SD completes receiving the pixel packet in the dummy row Pre-DE1 of the frame F(p+1), and a pulse pd6 is generated in the load signal LD, prompting the source driver SD to convert the dummy row Pre-DE1 from digital to analog, thereby generating a dummy row Pre-DE1' in the output signal Output. Until time t19, the clock signal SD CLK maintains a frequency of 740Mbps. The lock signal SDlock maintains a logic value of "1" between time t17 and time t19, indicating that the clock signal SD CLK is synchronized.

[0208] At time t19, the timing controller T-CON switches the clock signal Tx CLK from 740Mbps to 783Mbps, generating a pixel packet in row L(2) of frame F(p+1) for transmission on the data signal Ldat. Therefore, row L(2) of frame F(p+1) has a data rate of "783Mbps". At the same time, the timing controller T-CON transmits pulse psw9 in the frequency switching signal Fsw to the source driver SD. Pulse psw9 converts the clock signal SD CLK from 740Mbps to 783Mbps according to the data rate "783Mbps" of row L(2) of frame F(p+1), thereby synchronizing the clock signal SD CLK with row L(2) of frame F(p+1). The source driver SD obtains the pixel packet in row L(2) of frame F(p+1) according to the update data rate "783Mbps" of the clock signal SD CLK. At time t20, the source driver SD completes receiving the pixel packet in row L(1) of frame F(p+1), and a pulse pd7 is generated in the load signal LD, prompting the source driver SD to convert row L(1) of frame F(p+1) from digital to analog, thereby generating row L'(1) in the output signal Output. After psw9 is completed, the clock signal SD CLK maintains a frequency of 740Mbps. The lock signal SD lock remains at a logic value "1", indicating that the clock signal SD CLK is synchronized.

[0209] Although Fig.21 Only pixel packets of 2 pixel rows are shown, but those skilled in the art can extend the embodiment to dummy rows Pre-DE1, Post-DE1 to Post-DE3 based on similar principles, so as to dynamically adjust the data rate of the dummy rows without affecting the visual display area. In other words, the rate change can occur in the pixel rows or dummy rows in the effective area. In addition, although Fig. 20 Only line-based rate changes are shown, but it is obvious to the skilled person to modify the embodiment to change the data rate based on each pixel packet. That is, within the active area AA of a frame, the display device has the flexibility to change the data rate of any individual pixel packet as needed.

[0210] Figures 19 to 21 The embodiments enable the data rate of a pixel packet to vary on a per-row basis, or even on a per-pixel packet basis in a point-to-point architecture, adaptively updating the clock to keep pace with the changing data, thereby minimizing electromagnetic interference, reducing overall jitter, reducing data loss, and enhancing data security.

[0211] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for transmitting data in a display device, characterized in that: The method comprises: Monitoring a data rate of a pixel packet in an effective area of ​​a frame; Synchronize a clock according to the data rate of the pixel packet to generate a synchronization clock; and The data in the pixel packet is fetched using the synchronization clock.

2. The method according to claim 1, characterized in that Monitoring the data rate of the pixel packets in the active area of ​​the frame includes: Identify a delimiter pulse in a pixel packet.

3. The method according to claim 2, characterized in that Synchronizing the clock according to the data rate of the pixel packet to generate the synchronization clock comprises: A phase and a frequency of the clock are adjusted according to the delimiting pulse in the pixel packet to generate the synchronous clock.

4. The method according to claim 1, characterized in that Also includes: A plurality of data rates of a plurality of pixel packets of a set of lines in the active area are varied on a per-line basis.

5. The method according to claim 4, characterized in that Changing the plurality of data rates of the plurality of pixel packets of the row group in the active area on a per row basis includes: for The plurality of data rates of the plurality of pixel packets of the row group are changed within a predetermined data rate range.

6. The method according to claim 5, characterized in that Changing the plurality of data rates of the plurality of pixel packets of the row group within the predetermined data rate range comprises: A data rate of a previous row is increased by a certain value to generate a data rate of a plurality of pixel packets of each row in the row group.

7. The method according to claim 5, characterized in that Changing the plurality of data rates of the plurality of pixel packets of the row group within the predetermined data rate range comprises: A data rate of a previous row is increased by a variable value to generate a data rate of a plurality of pixel packets for each row in the row group.

8. The method according to claim 5, characterized in that Changing the plurality of data rates of the plurality of pixel packets of the row group within the predetermined data rate range comprises: A data rate of a previous row is reduced by a certain value to generate a data rate of a plurality of pixel packets for each row in the row group.

9. The method according to claim 5, characterized in that Changing the plurality of data rates of the plurality of pixel packets of the row group within the predetermined data rate range comprises: A data rate of a previous row is reduced by a variable value to generate a data rate of a plurality of pixel packets for each row in the row group.

10. The method according to claim 1, characterized in that The pixel packet is located on a dummy line of the active area.

11. The method according to claim 1, characterized in that The pixel packet is located on a pixel row in the active area.

12. A display device, characterized in that: Include: a timing controller; a transmission line; a momentary pulse line; and A source driver is coupled to the timing controller via the transmission line to monitor a data rate of a pixel packet in an effective area of ​​a frame; a clock is synchronized according to the data rate of the pixel packet to generate a synchronization clock; And use the synchronization clock to fetch the data in the pixel packet.

13. The device according to claim 12, characterized in that The source driver recognizes a delimiting pulse in a pixel packet.

14. The device according to claim 13, characterized in that The source driver adjusts a phase and a frequency of the clock according to the delimiting pulse in the pixel packet to generate the synchronous clock.

15. The device according to claim 12, characterized in that The timing controller changes a plurality of data rates of a plurality of pixel packets of a row group in the active area on a per-row basis.

16. The device according to claim 15, characterized in that The timing controller changes the plurality of data rates of the plurality of pixel packets of the row group within a preset data rate range of the row group.

17. The device according to claim 16, characterized in that The timing controller increases a data rate of a previous row by a certain value to generate a data rate of a plurality of pixel packets of each row in the row group.

18. The device according to claim 16, characterized in that The timing controller increases a data rate of a previous row by a variable value to generate a data rate of a plurality of pixel packets of each row in the row group.

19. The device according to claim 16, characterized in that The timing controller reduces a data rate of a previous row by a certain value to generate a data rate of a plurality of pixel packets of each row in the row group.

20. The device according to claim 16, characterized in that The timing controller reduces a data rate of a previous row by an indefinite value to generate a data rate of a plurality of pixel packets of each row in the row group.

21. The device according to claim 12, characterized in that The pixel packet is located on a dummy row of the active area.

22. The device according to claim 12, characterized in that The pixel packet is located on a pixel row in the active area.

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