Liquid crystal driving system

Abstract

The application provides a liquid crystal driving system, which comprises a CPU and a liquid crystal connected with the CPU; the CPU has a maximum drivable resolution W max ×H max , and a driving layer is configured to drive the liquid crystal at the maximum drivable resolution; a row synchronization signal port and a field synchronization signal port of the CPU are vacant, and the original row synchronization signal output by the row synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to an application layer; the CPU is connected with a row driving signal pin and a field driving signal pin of the liquid crystal through a first configurable IO port and a second configurable IO port respectively, and the first configurable IO port and the second configurable IO port output the actual row synchronization signal and the actual field synchronization signal which are adapted to the resolution of the liquid crystal by configuration in the application layer. The application can be easily adapted by configuration in the application layer.

Description

Technical Field

[0001] This invention relates to the field of communication technology within embedded systems, and more specifically to a liquid crystal driving system. Background Technology

[0002] In the field of embedded systems, existing LCD driver systems are generally designed with fixed memory size based on the specific resolution of the selected LCD, so they can only drive a single LCD. If the system is upgraded to use an LCD with a different resolution, the underlying layer (driver layer) needs to be rewritten and the driver program updated, which brings certain troubles to system upgrades and maintenance and is inefficient. Summary of the Invention

[0003] The purpose of this invention is to provide a liquid crystal driving system that, when switching to liquid crystals with different resolutions, does not require rewriting the driving layer; adaptation can be easily achieved by directly configuring the application layer, resulting in high efficiency.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] This invention provides a liquid crystal driving system, the liquid crystal driving system including a CPU and a liquid crystal connected to the CPU; the CPU has a maximum driveable resolution W. max ×H max The driving layer is configured to drive the liquid crystal at a maximum driveable resolution of W×H. max H max W, H, and W are all integers greater than 0, and W is less than or equal to W. max H is less than or equal to H max The CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, and a second configurable I / O port. The liquid crystal has a horizontal drive signal pin and a vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU is connected to the horizontal drive signal pin and the vertical drive signal pin of the liquid crystal through the first configurable I / O port and the second configurable I / O port, respectively, and is configured in the application layer to make the horizontal synchronization signal and the vertical synchronization signal output from the first configurable I / O port and the second configurable I / O port compatible with the resolution of the liquid crystal.

[0006] In one embodiment, the CPU configures the display area of ​​the liquid crystal at the starting position (x0, y0) of the display area driven by the CPU, a line counter Count_H, and a field counter Count_V at the application layer. x0 and y0 can be arbitrarily set as needed, and x0 is less than H. max, y0 is less than W max ;

[0007] The line counter Count_H is reset when the original vertical synchronization signal switches to valid, and is incremented when the original horizontal synchronization signal switches to valid: Count_H = Count_H + 1;

[0008] The field counter Count_V is reset when the original vertical synchronization signal switches to valid, and is also reset when the original horizontal synchronization signal switches to valid. It is incremented every time a pixel data is output: Count_V = Count_V + 1;

[0009] When Count_H > y0 and Count_H < y0 + H, the real vertical synchronization signal of the liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0010] When Count_H > y0 and Count_H0 < y0 + H, and at the same time Count_V > x0 and Count_V < x0 + W, the real horizontal synchronization signal of the liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state.

[0011] In one embodiment, the liquid crystal driving system further includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max .

[0012] In one embodiment, the liquid crystal driving system further includes a parallel data bus. The CPU is connected to the liquid crystal via the parallel data bus and sends the data to be displayed to the liquid crystal.

[0013] The present invention also provides a liquid crystal driving system, which includes a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum drivable resolution of W max ×H max , and the driving layer is configured to drive the first liquid crystal and the second liquid crystal according to the maximum drivable resolution. The resolution of the first liquid crystal is W1×H1, and the resolution of the second liquid crystal is W2×H2. W max , H max , W1, H1, W2, H2 are all integers greater than 0, and both W1 and W2 are less than W max , and both H1 and H2 are less than H maxThe CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, a second configurable I / O port, a third configurable I / O port, and a fourth configurable I / O port. The first liquid crystal has a first horizontal drive signal pin and a first vertical drive signal pin, and the second liquid crystal has a second horizontal drive signal pin and a second vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU communicates with the application layer through the first configurable I / O port and the second configurable I / O port, respectively. The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and the second row drive signal pin and the second field drive signal pin of the second liquid crystal are connected through the third configurable I / O port and the fourth configurable I / O port, respectively. The configuration is performed at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable I / O port and the second configurable I / O port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable I / O port and the fourth configurable I / O port are adapted to the resolution of the second liquid crystal.

[0014] In one embodiment, the CPU is configured at the application layer with the following: the display area of ​​the first liquid crystal at a first starting position (x1, y1) in the display area driven by the CPU; the display area of ​​the second liquid crystal at a second starting position (x2, y2) in the display area driven by the CPU; a first line counter Count_H1; a first field counter Count_V1; a second line counter Count_H2; and a second field counter Count_V2. x1, y1, x2, and y2 can be arbitrarily set as needed, and x1 and x2 are both less than H. max y1 and y2 are both less than W max ;

[0015] The first row counter Count_H1 and the second row counter Count_H2 are reset when the original field synchronization signal is switched to valid, and are incremented when the original row synchronization signal is switched to valid: Count_H1 = Count_H1 + 1, Count_H2 = Count_H2 + 1;

[0016] The first field counter Count_V1 and the second field counter Count_V2 are reset when the original field synchronization signal is switched to active, and are also reset when the original line synchronization signal is switched to active. They are incremented every time a pixel data is output: Count_V1 = Count_V1 + 1, Count_V2 = Count_V2 + 1;

[0017] When Count_H1 > y1 and Count_H1 < y1 + H1, the first real field synchronization signal of the first liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0018] When Count_H1 > y1 and Count_H1 < y1 + H1, and at the same time Count_V1 > x1 and Count_V1 < x1 + W1, the first real implementation synchronization signal of the first liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0019] When Count_H2 > y2 and Count_H2 < y2 + H2, the second real field synchronization signal of the second liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0020] When Count_H2 > y2 and Count_H2 < y2 + H2, and at the same time Count_V2 > x2 and Count_V2 < x2 + W2, the second real implementation synchronization signal of the second liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state.

[0021] In one embodiment, x1 + W1 < x2.

[0022] In one embodiment, x1 = x2, y1 = y2, W1 = W2, H1 = H2.

[0023] In one embodiment, x1 + W1 = x2, y1 = y2, W1 = W2, H1 = H2.

[0024] In one embodiment, the liquid crystal driving system further includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max .

[0025] In one embodiment, the liquid crystal driving system further includes a parallel data bus, and the CPU is respectively connected to the first liquid crystal and the second liquid crystal via the parallel data bus, and sends the data to be displayed to the first liquid crystal and the second liquid crystal.

[0026] In one embodiment, a signal buffer is further provided in the parallel data bus to improve the driving ability.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] This invention relates to a liquid crystal driving system. The driving layer drives the liquid crystal according to the maximum driveable resolution of the CPU, but the CPU's horizontal and vertical synchronization signal ports are left unused. The original horizontal and vertical synchronization signals output from the horizontal and vertical synchronization signal ports are fed back to the application layer. Furthermore, the CPU connects to the liquid crystal's horizontal and vertical driving signal pins via a first and a second configurable I / O port, respectively. Configuration is performed at the application layer to ensure that the horizontal and vertical synchronization signals output from the first and second configurable I / O ports are adapted to the liquid crystal's resolution. Thus, whenever a different liquid crystal resolution needs to be installed, adaptation can be easily achieved by configuring at the application layer without rewriting the driving layer, improving efficiency. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a liquid crystal driving system provided in the first embodiment of the present invention;

[0031] Figure 2 for Figure 1 The diagram shows the relationship between the display area driven by the CPU and the display area of ​​the liquid crystal in the liquid crystal driving system.

[0032] Figure 3 This is a schematic diagram of a liquid crystal driving system provided in the second embodiment of the present invention;

[0033] Figure 4 The three parts (a), (b), and (c) are respectively Figure 2 The diagram shows a relationship between the display area driven by the CPU and the display area of ​​the liquid crystal in the liquid crystal driving system. Detailed Implementation

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of the present invention. Moreover, in the following embodiments, the description of each embodiment has its own emphasis, and for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0035] Please see Figure 1 As shown, the first embodiment of the present invention provides a liquid crystal driving system, the liquid crystal driving system including a CPU and a liquid crystal connected to the CPU; the CPU has a maximum driveable resolution W. max ×H max The driving layer is configured to drive the liquid crystal at the maximum driveable resolution (for example, Freescale's iMX6 has a maximum driveable resolution of 2048*2048, and the liquid crystal's driving timing is directly configured to drive it at 2080*2048), and the resolution of the liquid crystal is W×H, W max H max W, H, and W are all integers greater than 0, and W is less than or equal to W. max H is less than or equal to H max The CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, and a second configurable I / O port. The liquid crystal has a horizontal drive signal pin and a vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU is connected to the horizontal drive signal pin and the vertical drive signal pin of the liquid crystal through the first configurable I / O port and the second configurable I / O port, respectively, and is configured in the application layer to make the horizontal synchronization signal and the vertical synchronization signal output from the first configurable I / O port and the second configurable I / O port compatible with the resolution of the liquid crystal.

[0036] This invention relates to a liquid crystal driving system. The driving layer drives the liquid crystal according to the maximum drive resolution of the CPU, but the CPU's horizontal and vertical sync signal ports (which are present by default at the factory) are left unused. The original horizontal and vertical sync signals output from the horizontal and vertical sync signal ports are fed back to the application layer. Furthermore, the CPU connects to the liquid crystal's horizontal and vertical drive signal pins via a first and a second configurable I / O port, respectively. Configuration at the application layer ensures that the horizontal and vertical sync signals output from the first and second configurable I / O ports are adapted to the liquid crystal's resolution. Thus, whenever a different liquid crystal resolution needs to be installed, adaptation can be easily achieved by configuring at the application layer without rewriting the driving layer, improving efficiency.

[0037] For details, please refer to Figure 2As shown, in one embodiment, the CPU is configured in the application layer with the starting position (x0, y0) of the display area of the liquid crystal in the display area driven by the CPU, a line counter Count_H, and a field counter Count_V. x0 and y0 can be set arbitrarily according to needs, and x0 is less than H max , y0 is less than W max ;

[0038] The line counter Count_H is reset when the original field synchronization signal switches to valid, and is incremented when the original line synchronization signal switches to valid: Count_H = Count_H + 1; that is, the line counter Count_H is used to record the current row where the scanned pixel data is located;

[0039] The field counter Count_V is reset when the original field synchronization signal switches to valid, and is also reset when the original line synchronization signal switches to valid, and is incremented every time a pixel data is output: Count_V = Count_V + 1; that is, the field counter Count_V is used to record the current column where the scanned pixel data is located;

[0040] When Count_H > y0 and Count_H < y0 + H, the real field synchronization signal of the liquid crystal is configured to be in an effective state (such as high level), and in other cases it is configured to be in an invalid state (such as low level);

[0041] When Count_H > y0 and Count_H0 < y0 + H, and at the same time Count_V > x0 and Count_V < x0 + W, the real line synchronization signal of the liquid crystal is configured to be in an effective state (such as high level), and in other cases it is configured to be in an invalid state (such as low level).

[0042] In this way, only by configuring the starting position (x0, y0) of the display area of the actually used liquid crystal in the display area driven by the CPU and the size (resolution) W×H of the liquid crystal in the application layer, it can be adapted to the actually used liquid crystal.

[0043] Moreover, in the display area (W_max×H_max) driven by the CPU, the area outside the display area (W×H) corresponding to the actually used liquid crystal is called the off-screen area. Since the liquid crystal driving system of the present invention drives at the maximum resolution of W_max×H_max in the driving layer, it is possible to operate the entire continuous area of W_max×H_max in the application layer, that is, off-screen rendering can also be performed on the off-screen area outside the liquid crystal screen, and then the display area of the liquid crystal can be adjusted by adjusting the coordinates of the starting position (x0, y0) of the display area of the liquid crystal. This off-screen rendering method directly controlled by hardware for the display area is much more efficient and smoother in sliding than the off-screen rendering method implemented by software.

[0044] In addition, it can be easily expanded to multi-screen display, as described later in the description of the second embodiment of the present invention.

[0045] In one embodiment, the liquid crystal driving system further includes video memory (not shown) connected to the CPU, and the size of the video memory is also W. max ×H max The size of the video memory is also configured according to the maximum resolution that the CPU can drive.

[0046] Please refer to the following: Figure 1 As shown, in one embodiment, the liquid crystal driving system of the present invention further includes a parallel data bus, and the CPU is connected to the liquid crystal via the parallel data bus to send data to be displayed to the liquid crystal.

[0047] Please see Figure 3 As shown, a second embodiment of the present invention provides a liquid crystal driving system, the liquid crystal driving system including a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum driveable resolution W. max ×H max The driving layer is configured to drive the first liquid crystal and the second liquid crystal at the maximum driveable resolution, wherein the resolution of the first liquid crystal is W1×H1, the resolution of the second liquid crystal is W2×H2, and W... max H max W1, H1, W2, and H2 are all integers greater than 0, and W1 and W2 are both less than W. max H1 and H2 are both less than H maxThe CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, a second configurable I / O port, a third configurable I / O port, and a fourth configurable I / O port. The first liquid crystal has a first horizontal drive signal pin and a first vertical drive signal pin, and the second liquid crystal has a second horizontal drive signal pin and a second vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU communicates with the application layer through the first configurable I / O port and the second configurable I / O port, respectively. The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and the second row drive signal pin and the second field drive signal pin of the second liquid crystal are connected through the third configurable I / O port and the fourth configurable I / O port, respectively. The configuration is performed at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable I / O port and the second configurable I / O port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable I / O port and the fourth configurable I / O port are adapted to the resolution of the second liquid crystal.

[0048] The main difference between the second and first embodiments lies in the fact that the second embodiment connects two liquid crystals simultaneously. Of course, three or more liquid crystals can also be connected simultaneously as needed, and all of these should be included within the scope of this invention. This is because the core idea of ​​the second embodiment is exactly the same as the first embodiment: driving the liquid crystals at the maximum driveable resolution of the CPU in the driver layer, and configuring them in the application layer easily achieves adaptation for each liquid crystal without rewriting the driver layer, thus improving efficiency. The use of two liquid crystals in the second embodiment is merely an example. Through the second embodiment, it is easy to understand that, through expansion, a single port (original horizontal and vertical sync signal ports) can easily achieve multi-screen display. On a CPU with limited resources, one liquid crystal driver port (original horizontal and vertical sync signal ports) can drive multiple liquid crystal screens, maintaining highly synchronized display without needing to separately handle the synchronous refresh problem of multiple screens.

[0049] For details, please refer to Figure 4 As shown in section (a), in one embodiment, the CPU is configured at the application layer with a first starting position (x1, y1) of the display area of ​​the first liquid crystal in the display area driven by the CPU, a second starting position (x2, y2) of the display area of ​​the second liquid crystal in the display area driven by the CPU, a first line counter Count_H1, a first field counter Count_V1, a second line counter Count_H2, and a second field counter Count_V2. x1, y1, x2, and y2 can be arbitrarily set as needed, and x1 and x2 are both less than H.max where both y1 and y2 are less than W max ;

[0050] The first line counter Count_H1 and the second line counter Count_H2 are reset when the original vertical synchronization signal switches to valid, and are incremented when the original horizontal synchronization signal switches to valid: Count_H1 = Count_H1 + 1, Count_H2 = Count_H2 + 1;

[0051] The first field counter Count_V1 and the second field counter Count_V2 are reset when the original vertical synchronization signal switches to valid, and are also reset when the original horizontal synchronization signal switches to valid, and are incremented every time a pixel data is output: Count_V1 = Count_V1 + 1, Count_V2 = Count_V2 + 1;

[0052] When Count_H1 > y1 and Count_H1 < y1 + H1, the first real vertical synchronization signal of the first liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0053] When Count_H1 > y1 and Count_H1 < y1 + H1, and at the same time Count_V1 > x1 and Count_V1 < x1 + W1, the first real horizontal synchronization signal of the first liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0054] When Count_H2 > y2 and Count_H2 < y2 + H2, the second real vertical synchronization signal of the second liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0055] When Count_H2 > y2 and Count_H2 < y2 + H2, and at the same time Count_V2 > x2 and Count_V2 < x2 + W2, the second real horizontal synchronization signal of the second liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state.

[0056] Similarly, only by configuring the starting position (x1, y1) of the display area of the first liquid crystal actually used in the application layer in the display area driven by the CPU and the size (resolution) W1×H1 of the first liquid crystal, and the starting position (x2, y2) of the display area of the second liquid crystal in the display area driven by the CPU and the size (resolution) W2×H2 of the second liquid crystal, it can be adapted to both the first liquid crystal and the second liquid crystal actually used.

[0057] Moreover, Figure 4In the embodiment shown in part (a), the display areas of the first liquid crystal and the second liquid crystal are completely separated, that is, each liquid crystal selects a different display area for driving and displaying. At this time, only x1 + W1 < x2 needs to be noted. As for the relationships among y1, y2, W1, H1, W2, and H2, they can be appropriately configured according to actual needs. For example, y1 > y2 can be set, or y1 < y2 can be set. W1 = W2 can be set, or W1 ≠ W2 can be set. H1 = H2 can be set, or H1 ≠ H2 can be set. That is, the first liquid crystal and the second liquid crystal can have the same resolution or different resolutions.

[0058] Please refer to Figure 4 As shown in part (b), in an embodiment, the display areas of the first liquid crystal and the second liquid crystal completely overlap, that is, the two liquid crystals have the same resolution and select the same display area for driving and displaying. At this time, x1 = x2, y1 = y2, W1 = W2, and H1 = H2.

[0059] Please refer to Figure 4 As shown in part (c), in an embodiment, the display areas of the first liquid crystal and the second liquid crystal exactly form a seamless splicing, that is, the two liquid crystals have the same resolution and select different display areas for driving and displaying. At this time, x1 + W1 = x2, y1 = y2, W1 = W2, and H1 = H2.

[0060] Similarly, in an embodiment, the liquid crystal driving system further includes a video memory (not shown) connected to the CPU, and the size of the video memory is also W max ×H max . That is, the size of the video memory is also configured according to the maximum resolvable resolution of the CPU.

[0061] Please refer to again Figure 3 As shown, similarly, in an embodiment, the liquid crystal driving system further includes a parallel data bus, and the CPU is connected to the first liquid crystal and the second liquid crystal via the parallel data bus respectively, and sends the data to be displayed to the first liquid crystal and the second liquid crystal.

[0062] Moreover, in an embodiment, a signal buffer is further provided in the parallel data bus to improve the driving ability.

[0063] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0064] This invention relates to a liquid crystal driving system. The driving layer drives the liquid crystal according to the maximum driveable resolution of the CPU, but the CPU's horizontal and vertical synchronization signal ports are left unused. The original horizontal and vertical synchronization signals output from the horizontal and vertical synchronization signal ports are fed back to the application layer. Furthermore, the CPU connects to the liquid crystal's horizontal and vertical driving signal pins via a first and a second configurable I / O port, respectively. Configuration is performed at the application layer to ensure that the horizontal and vertical synchronization signals output from the first and second configurable I / O ports are adapted to the liquid crystal's resolution. Thus, whenever a different liquid crystal resolution needs to be installed, adaptation can be easily achieved by configuring at the application layer without rewriting the driving layer, improving efficiency.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of the present invention. The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention, and the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A liquid crystal driving system, characterized in that, The liquid crystal driving system includes a CPU and a liquid crystal connected to the CPU; the CPU has a maximum driveable resolution W. max ×H max The driving layer is configured to drive the liquid crystal at a maximum driveable resolution of W×H. max H max W, H, and H are all integers greater than 0, and W is less than or equal to W. max H is less than or equal to H max The CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, and a second configurable I / O port. The liquid crystal has a horizontal drive signal pin and a vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU is connected to the horizontal drive signal pin and the vertical drive signal pin of the liquid crystal through the first configurable I / O port and the second configurable I / O port, respectively, and is configured in the application layer to make the horizontal synchronization signal and the vertical synchronization signal output from the first configurable I / O port and the second configurable I / O port compatible with the resolution of the liquid crystal. The CPU, at the application layer, configures the display area of ​​the liquid crystal at the starting position (x0, y0) of the display area driven by the CPU, a line counter Count_H, and a field counter Count_V. x0 and y0 can be arbitrarily set as needed, and x0 is less than H. max y0 is less than W max ; The line counter Count_H is reset when the original field synchronization signal is switched to active, and is incremented when the original line synchronization signal is switched to active: Count_H = Count_H + 1; The field counter Count_V is reset when the original field synchronization signal is switched to active, and it is also reset when the original line synchronization signal is switched to active. It is incremented every time a pixel data is output: Count_V = Count_V + 1; The real-field synchronization signal of the liquid crystal is configured to be active when Count_H > y0 and Count_H < y0 + H, and to be inactive at other times. When Count_H > y0 and Count_H0 < y0 + H, and Count_V > x0 and Count_V < x0 + W, the synchronization signal of the liquid crystal is configured to be active; otherwise, it is configured to be inactive.

2. The liquid crystal driving system according to claim 1, characterized in that, The liquid crystal driving system also includes video memory connected to the CPU, and the size of the video memory is also W. max ×H max .

3. The liquid crystal driving system according to claim 1, characterized in that, The liquid crystal driving system also includes a parallel data bus, through which the CPU is connected to the liquid crystal and sends data to be displayed to the liquid crystal.

4. A liquid crystal driving system, characterized in that, The liquid crystal driving system includes a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum driveable resolution W. max ×H max The driving layer is configured to drive the first liquid crystal and the second liquid crystal at the maximum driveable resolution, wherein the resolution of the first liquid crystal is W1×H1, and the resolution of the second liquid crystal is W2×H2. max H max W1, H1, W2, and H2 are all integers greater than 0, and W1 and W2 are both less than W. max H1 and H2 are both less than H max The CPU has a horizontal synchronization signal port, a vertical synchronization signal port, a first configurable I / O port, a second configurable I / O port, a third configurable I / O port, and a fourth configurable I / O port. The first liquid crystal has a first horizontal drive signal pin and a first vertical drive signal pin, and the second liquid crystal has a second horizontal drive signal pin and a second vertical drive signal pin. The horizontal synchronization signal port and the vertical synchronization signal port of the CPU are left unused, and the original horizontal synchronization signal output from the horizontal synchronization signal port and the original vertical synchronization signal output from the vertical synchronization signal port are fed back to the application layer. The CPU communicates with the application layer through the first configurable I / O port and the second configurable I / O port, respectively. The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and the second row drive signal pin and the second field drive signal pin of the second liquid crystal are connected through the third configurable I / O port and the fourth configurable I / O port, respectively. The configuration is performed at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable I / O port and the second configurable I / O port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable I / O port and the fourth configurable I / O port are adapted to the resolution of the second liquid crystal. The CPU, at the application layer, is configured with the following: the display area of ​​the first liquid crystal at a first starting position (x1, y1) in the CPU-driven display area; the display area of ​​the second liquid crystal at a second starting position (x2, y2) in the CPU-driven display area; a first line counter Count_H1; a first field counter Count_V1; a second line counter Count_H2; and a second field counter Count_V2. x1, y1, x2, and y2 can be arbitrarily set as needed, and x1 and x2 are both less than H. max y1 and y2 are both less than W max ; The first row counter Count_H1 and the second row counter Count_H2 are reset when the original field synchronization signal is switched to active, and are incremented when the original row synchronization signal is switched to active: Count_H1 = Count_H1 + 1, Count_H2 = Count_H2 + 1; The first field counter Count_V1 and the second field counter Count_V2 are reset when the original field synchronization signal is switched to active, and are also reset when the original line synchronization signal is switched to active. They are incremented each time a pixel data is output: Count_V1 = Count_V1 + 1, Count_V2 = Count_V2 + 1; When Count_H1 > y1 and Count_H1 < y1 + H1, the first real-field synchronization signal of the first liquid crystal is configured to be active; otherwise, it is configured to be inactive. When Count_H1 > y1 and Count_H1 < y1 + H1, and Count_V1 > x1 and Count_V1 < x1 + W1, the first synchronization signal of the first liquid crystal is configured to be active; otherwise, it is configured to be inactive. When Count_H2 > y2 and Count_H2 < y2 + H2, the second real-field synchronization signal of the second liquid crystal is configured to be active; otherwise, it is configured to be inactive. When Count_H2 > y2 and Count_H2 < y2 + H2, and Count_V2 > x2 and Count_V2 < x2 + W2, the second synchronization signal of the second liquid crystal is configured to be active; otherwise, it is configured to be inactive.

5. The liquid crystal driving system according to claim 4, characterized in that, x1 + W1 < x2.

6. The liquid crystal driving system according to claim 4, characterized in that, x1 = x2, y1 = y2, W1 = W2, H1 = H2.

7. The liquid crystal driving system according to claim 4, characterized in that, x1 + W1 = x2, y1 = y2, W1 = W2, H1 = H2.

8. The liquid crystal driving system according to claim 4, characterized in that, The liquid crystal driving system also includes video memory connected to the CPU, and the size of the video memory is also W. max ×H max The liquid crystal driving system also includes a parallel data bus, through which the CPU is connected to the first liquid crystal and the second liquid crystal respectively, and sends data to be displayed to the first liquid crystal and the second liquid crystal; the parallel data bus is also provided with a signal buffer to improve the driving capability.

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