Gate driving circuit, display panel and display device

Abstract

The application provides a gate drive circuit, a display panel and a display device. The gate drive circuit comprises a plurality of cascaded shift registers. Each shift register comprises a cascaded selection module and a row drive module which are electrically connected. The first control end of the cascaded selection module is used for inputting a first control signal. The second control end of the cascaded selection module is used for inputting a second control signal. The output end of the cascaded selection module is used for outputting a scanning control signal. In the case that the first control signal is a first level and the second control signal is a second level, each shift register is cascaded in a first cascaded mode. In the case that the first control signal is a second level and the second control signal is a first level, each shift register is cascaded in a second cascaded mode. The row drive module is used for outputting a gate drive signal under the action of the scanning control signal. The circuit can realize the switching of two sets of cascaded relationships on the same panel and meet different functional requirements of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Display panels mostly use Gate Driver on Array (GOA) technology. GOA technology uses the thin film transistor (TFT) liquid crystal display array manufacturing process to fabricate the gate scanning drive circuit on the thin film transistor array substrate to achieve line-by-line scanning drive technology. It has the advantages of reducing production costs and enabling narrow bezel design of the panel.

[0003] The existing gate driving circuit consists of multiple cascaded shift registers: SR(1), SR(2)...SR(n), SR(n+1)...SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N). Each shift register SR(n) is used to provide a gate enable signal to the gate line connected to the signal output terminal Output_n of the shift register SR(n) to enable the TFT of the pixel area of ​​the corresponding row.

[0004] However, the existing cascading method for shift registers is fixed in one way, which cannot simultaneously meet the functional requirements of different display panels and ensure both high performance and low cost. Summary of the Invention

[0005] The main objective of this application is to provide a gate driving circuit, a display panel, and a display device, so as to at least solve the problem that in the prior art, the cascading method of shift registers is fixed in one way, and it is impossible to simultaneously achieve high performance and low cost of the display panel under different functional requirements of the display panel.

[0006] To achieve the above objectives, according to one aspect of this application, a gate driving circuit is provided, comprising a plurality of cascaded shift registers. Each shift register includes a cascaded selection module and a row driving module electrically connected. A first control terminal of the cascaded selection module is used to input a first control signal, a second control terminal of the cascaded selection module is used to input a second control signal, and an output terminal of the cascaded selection module is used to output a scan control signal. When the first control signal is at a first level and the second control signal is at a second level, the shift registers are cascaded in a first cascade configuration; when the first control signal is at a second level and the second control signal is at a first level, the shift registers are cascaded in a second cascade configuration. The row driving module outputs a gate driving signal under the action of the scan control signal, and the gate driving signal is used to drive the display element of the current row to display or not display.

[0007] According to another aspect of this application, a display panel is provided, comprising: an array substrate and an opposing substrate disposed opposite each other; the array substrate includes a substrate and a gate driving circuit of any kind located on the substrate.

[0008] According to another aspect of this application, a display device is provided, comprising: a display area and any type of display panel.

[0009] Applying the technical solution of this application, the aforementioned gate driving circuit includes multiple cascaded shift registers. Each shift register includes a cascaded selection module and a row driving module electrically connected. When a first control signal input to the first control terminal of the cascaded selection module is at a first level and a second control signal input to the second control terminal of the cascaded selection module is at a second level, the shift registers are cascaded in a first cascade configuration. When the first control signal is at a second level and the second control signal is at a first level, the shift registers are cascaded in a second cascade configuration. The row driving module outputs a gate driving signal based on the scan control signal output by the cascaded selection module. This circuit can switch between two cascaded configurations on the same panel, meeting different functional requirements of the display panel. It can simultaneously meet the high-performance and low-cost requirements of the display panel, solving the problem in the prior art where the cascaded configuration of shift registers is fixed in one way, making it impossible to simultaneously achieve both high performance and low cost for different display panel functional requirements. Attached Figure Description

[0010] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0011] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown;

[0012] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0013] Figure 3 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0014] Figure 4 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0015] Figure 5 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0016] Figure 6A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0017] Figure 7 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0018] Figure 8 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown;

[0019] Figure 9 A timing diagram of a gate drive circuit with a clock count of 2 phases provided in an embodiment of this application is shown;

[0020] Figure 10 A timing diagram of a gate drive circuit with 4 clock phases provided in an embodiment of this application is shown;

[0021] Figure 11 A schematic diagram of the structure of a display panel provided in an embodiment of this application is shown;

[0022] Figure 12 A schematic diagram of the structure of a display device provided in an embodiment of this application is shown.

[0023] The above figures include the following reference numerals:

[0024] 01. Cascade selection module; 10. Forward scan signal input unit; 11. Reverse scan signal input unit; 02. Horizontal drive module; 20. Scan control module; 21. Reset module; 22. Output control module; 221. First switch unit; 222. Second switch unit; 223. Third switch unit; 23. Output module; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M9. Ninth transistor; M10. Tenth transistor; M11. Eleventh transistor; M12. Twelfth transistor; M13. Thirteenth transistor; M14. Fourteenth transistor; M15. Fifteenth transistor; M16. Sixteenth transistor; C1. First capacitor; C2. Second capacitor; 100. Substrate; 200. Gate drive circuit; 300. Display panel. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] As described in the background section, existing technologies typically use ASG circuits to drive display panels to emit light in order to save costs. However, with the increase in panel size, resolution, and reliability requirements, the number of clock cycles required by the ASG circuits is constantly increasing, leading to a continuous increase in cost. Furthermore, during the use of display panels, there are times when high performance is not required. This results in unnecessary cost increases due to the fixed cascading mode of the display panels. In other words, existing display panels can only be cascaded in one fixed way. When a low-cost, low-performance cascading method is used, it cannot meet the user's high-performance requirements; conversely, when a high-cost, high-performance cascading method is used, it cannot meet the user's low-cost requirements.

[0029] To address the problem that existing technologies only have one fixed method for cascading shift registers, which cannot simultaneously achieve high performance and low cost for different display panels, embodiments of this application provide a gate driving circuit, a display panel, and a display device.

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] An embodiment of the present invention provides a shift register, such as Figure 1As shown, the system includes multiple cascaded shift registers. Each shift register includes a cascaded selection module 01 and a row drive module 02 electrically connected. The first control terminal of the cascaded selection module 01 is used to input a first control signal RES1, and the second control terminal of the cascaded selection module 01 is used to input a second control signal RES2. The output terminal of the cascaded selection module 01 is used to output a scan control signal. When the first control signal RES1 is at a first level and the second control signal RES2 is at a second level, the shift registers are cascaded in a first cascade manner. When the first control signal RES1 is at a second level and the second control signal RES2 is at a first level, the shift registers are cascaded in a second cascade manner. The row drive module 02 outputs a gate drive signal Gout under the action of the scan control signal. The gate drive signal Gout is used to drive the display element of the current row to display or not display.

[0032] The gate driving circuit described in this application includes multiple cascaded shift registers. Each shift register includes a cascaded selection module and a row driving module electrically connected. When the first control signal RES1 input to the first control terminal of the cascaded selection module is at a first level and the second control signal RES2 input to the second control terminal of the cascaded selection module is at a second level, the shift registers are cascaded in a first cascade configuration. When the first control signal RES1 is at a second level and the second control signal RES2 is at a first level, the shift registers are cascaded in a second cascade configuration. The row driving module outputs a gate driving signal Gout based on the scan control signal output by the cascaded selection module. This circuit allows for switching between two cascaded configurations on the same panel, meeting different functional requirements of the display panel. It can simultaneously meet the high-performance and low-cost requirements of the display panel, solving the problem in the prior art where the cascaded configuration of shift registers is fixed in one way, making it impossible to simultaneously achieve both high performance and low cost for different display panel functional requirements.

[0033] In this configuration, the first level is high, the second level is low, and the number of pulses in the first cascaded method is half that of the second cascaded method. That is, if the first cascaded method has 2 phases of pulses, the second cascaded method has 4 phases, and so on. Furthermore, since the clock signal for the gate drive circuit in this example consists of multiple complementary clock signals, the number of pulses in both the first and second cascaded methods is even.

[0034] In some instances, the number of pulses in the first cascade method is 2 phases, and the number of pulses in the second cascade method is 4 phases. When the shift registers are cascaded in the first cascade method, the clock signals of the Nth row shift register and the (N+1)th row shift register are the same. When the shift registers are cascaded in the second cascade method, the clock signals of the Nth row shift register and the (N+2)th row shift register are the same.

[0035] In some instances, the first cascaded method has 4 pulses and the second cascaded method has 8 pulses. When the shift registers are cascaded in the first cascaded method, the clock signals of the Nth row shift register and the (N+2)th row shift register are the same. When the shift registers are cascaded in the second cascaded method, the clock signals of the Nth row shift register and the (N+4)th row shift register are the same.

[0036] That is, the number of rows between two adjacent cascaded shift registers is half the number of pulses in the current cascade mode, and the clock signal of the shift register corresponding to the current row is the same as the clock signal of the shift register corresponding to the row one pulse later.

[0037] In some instances, such as Figure 2 As shown, the cascade selection module 01 includes: a forward scan signal input unit 10, which is used to input the first forward scan signal G under the control of the first control signal RES1. n-i The input is sent to the line drive module 02, and under the control of the second control signal RES2, the second forward scan signal G... n-2i Input to line drive module 02, first forward scan signal G n-i When the shift registers are cascaded in a first-stage cascade configuration, the first gate drive signal Gout1 and the second forward scan signal G output from the previous-stage shift register... n-2i When the shift registers are cascaded in a second cascade configuration, the second gate drive signal Gout2 output from the previous stage shift register; the backscan signal input unit 11, which is used to input the first backscan signal G under the control of the first control signal RES1. n+i The input is sent to the line drive module 02, and under the control of the second control signal RES2, the second backscan signal G is... n+2i Input to row drive module 02, first reverse scan signal G n+i When all shift registers are cascaded in a first-stage cascade configuration, the third gate drive signal Gout3 and the second backscan signal G are output from the next-stage shift register.n+2i When all shift registers are cascaded in a second-stage cascade configuration, the fourth gate drive signal Gout4 is output from the next-stage shift register.

[0038] In the case of i=1, since the number of pulses in the first cascade method is half that in the second cascade method, the nth and (n+1)th level shift registers in the second cascade method are the same as the nth and (n+2)th level shift registers in the first cascade method.

[0039] Specifically, in a display device, during forward scanning, the forward scan input signal terminal INF of the first-stage shift register is generally used to receive the start signal. The forward scan input signal terminals INF of other shift registers (excluding the first-stage shift register) are used to receive the signal output from the gate signal output terminal Gout of the previous-stage shift register. During reverse scanning, the reverse scan input signal terminal INB of the last-stage shift register is generally used to receive the start signal. The reverse scan input signal terminals INB of other shift registers (excluding the last-stage shift register) are used to receive the signal output from the gate signal output terminal Gout of the next-stage shift register.

[0040] In some instances, such as Figure 3 As shown, the forward scan signal input unit 10 includes: a first transistor M1, the gate of the first transistor M1 is used to input a first control signal RES1, and the first terminal of the first transistor M1 is used to input a first forward scan signal G. n-i The second terminal of the first transistor M1 is electrically connected to the forward scan signal input terminal of the row drive module O2; the gate of the second transistor M2 is used to input the second control signal RES2, and the first terminal of the second transistor M2 is used to input the second forward scan signal G. n-2i The second terminal of the second transistor M2 is used to be electrically connected to the positive scan signal input terminal of the row drive module 02.

[0041] In this configuration, the first transistor M1 is an n-type TFT, and the second transistor M2 is an n-type TFT. When the first control signal RES1 is high and the second control signal RES2 is low, the first transistor M1 is turned on, and the second transistor M2 is turned off. The first transistor M1 transmits the first forward scan signal G... n-i The data is transmitted to the row drive module 02, where each shift register is cascaded in a first cascade configuration. When the first control signal RES1 is low and the second control signal RES2 is high, the first transistor M1 is off, and the second transistor M2 is on. The second transistor M2 transmits the second forward scan signal G... n-2i The data is transmitted to the row driver module 02, where each shift register is cascaded in a second cascade manner.

[0042] In some instances, such as Figure 3 As shown, the reverse scan signal input unit 11 includes: a third transistor M3, the gate of the third transistor M3 is used to input the first control signal RES1, and the first terminal of the third transistor M3 is used to input the first reverse scan signal G. n+i The second terminal of the third transistor M3 is electrically connected to the reverse scan signal input terminal of the row drive module O2; the gate of the fourth transistor M4 is used to input the second control signal RES2, and the first terminal of the fourth transistor M4 is used to input the second reverse scan signal G. n+2i The second terminal of the fourth transistor M4 is used to electrically connect to the reverse scan signal input terminal of the row drive module 02.

[0043] In this configuration, the third transistor M3 is an n-type TFT, and the fourth transistor M4 is an n-type TFT. When the first control signal RES1 is high and the second control signal RES2 is low, the third transistor M3 is turned on, and the fourth transistor M4 is turned off. The third transistor M3 transmits the first reverse scan signal G... n+i The data is transmitted to the row drive module 02, where each shift register is cascaded in a first-level cascade configuration. When the first control signal RES1 is low and the second control signal RES2 is high, the third transistor M3 is off, and the fourth transistor M4 is on. The fourth transistor M4 transmits the second backscan signal G... n+2i The data is transmitted to the row driver module 02, where each shift register is cascaded in a second cascade manner.

[0044] In some instances, such as Figure 4 As shown, the row drive module 02 includes a scan control module 20, a reset module 21, an output control module 22, and an output module 23 electrically connected. The scan control module 20 provides the signal of the forward scan control signal terminal INF to the input node N1 under the control of the signal of the forward scan input signal terminal INF, or provides the signal of the reverse scan control signal terminal INB to the input node N1 under the control of the signal of the reverse scan input signal terminal INB. The reset module 21 resets the input node N1 and the gate signal output terminal Gout under the control of the reset signal RES. The output control modules 22 and 23 are connected to the scan control module 20 at the input node N1. All three modules are connected to the gate signal output terminal Gout, which outputs the gate drive signal Gout. The output control module 22 controls the level of the gate drive signal Gout under the control of the signal from the input node N1. The output module 23 outputs the gate drive signal Gout under the control of the signal from the input node N1.

[0045] The output control module is used to control the gate drive signal to a low level under the control of the input node signal.

[0046] In some instances, such as Figure 4 and Figure 5 As shown, the scan control module 20 includes: a fifth transistor M5, the gate of which is connected to the forward scan input signal terminal INF, the first terminal of which is connected to the forward scan control signal terminal FW, and the second terminal of which is connected to the input node N1; and a sixth transistor M6, the gate of which is connected to the reverse scan input signal terminal INB, the first terminal of which is connected to the reverse scan control signal terminal BW, and the second terminal of which is connected to the input node N1.

[0047] The fifth transistor M5 is an n-type TFT, and the sixth transistor M6 is an n-type TFT. The fifth transistor M5 is used to input the signal of the forward scan control signal terminal FW to the input node N1 under the control of the signal of the forward scan input signal terminal INF. The sixth transistor M6 is used to input the signal of the reverse scan control signal terminal BW to the input node N1 under the control of the signal of the reverse scan input signal terminal INB.

[0048] In such Figure 6 In the embodiment shown, the forward scan input signal terminal INF is used to control the conduction or cutoff of the fifth transistor M5. When the fifth transistor M5 is on, the signal of the forward scan control signal terminal FW can be transmitted to the input node N1. The reverse scan input signal terminal INB is used to control the conduction or cutoff of the sixth transistor M6. When the sixth transistor M6 is on, the signal of the reverse scan control signal terminal BW can be transmitted to the input node N1.

[0049] In some instances, such as Figure 5 As shown, the output control module 22 includes: a first switching unit 221, the first end of which is connected to the input node N1, the second end of which is connected to the first node N2, the third end of which is connected to the first reference voltage terminal VGL, and the fourth end of which is connected to the gate signal output terminal Gout; a second switching unit 222, the first end of which is connected to the input node N1, the second end of which is connected to the first node N2, and the third end of which is connected to the first reference voltage terminal VGL; and a third switching unit 223, the first end of which is connected to the first node N2, the second end of which is connected to the input node N1, the third end of which is connected to the first reference voltage terminal VGL, and the fourth end of which is connected to the second reference voltage terminal VGH.

[0050] The present invention will now be described in detail with reference to specific embodiments. It should be noted that these embodiments are for better explanation of the present invention and do not limit the scope of the invention.

[0051] It should be noted that in specific implementations, depending on the type of transistor and the signal at its gate, the first terminal of the transistor can be used as its source and the second terminal as its drain; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. No specific distinction is made here.

[0052] It should be noted that transistors are generally classified into N-type transistors and P-type transistors. N-type transistors conduct under the control of a high-level signal and are turned off under the control of a low-level signal; P-type transistors conduct under the control of a low-level signal and are turned off under the control of a high-level signal.

[0053] Optionally, in the shift register provided in the embodiments of the present invention, such as Figure 6 As shown, the first switching unit includes: a seventh transistor M7, the gate of the seventh transistor M7 is connected to the first node N2, the first terminal of the seventh transistor M7 is connected to the input node N1, and the second terminal of the seventh transistor M7 is connected to the first reference voltage terminal VGL; and an eighth transistor M8, the gate of the eighth transistor M8 is connected to the first node N2, the first terminal of the eighth transistor M8 is connected to the gate signal output terminal Gout, and the second terminal of the seventh transistor M7 is connected to the first reference voltage terminal VGL.

[0054] In this configuration, both the seventh transistor M7 and the eighth transistor M8 are n-type TFTs. When the signal at the first node N2 is high, both transistors M7 and M8 are turned on. Transistor M7 transmits the signal from the first reference voltage terminal VGL to the input node N1, keeping N1 at a low level. Transistor M8 transmits the signal from the first reference voltage terminal VGL to the gate signal output terminal Gout, keeping Gout at a low level. When the signal at the first node N2 is low, both transistors M7 and M8 are turned off.

[0055] In some instances, such as Figure 6 As shown, the second switching unit includes: a ninth transistor M9, the gate of the ninth transistor M9 is connected to the input node N1, the first terminal of the ninth transistor M9 is connected to the first node N2, and the second terminal of the ninth transistor M9 is connected to the first reference voltage terminal VGL.

[0056] Among them, the ninth transistor M9 is an n-type TFT. When the signal at the input node N1 is high, the ninth transistor M9 is turned on and transmits the signal at the first reference voltage terminal VGL to the first node N2, so that the signal at the first node N2 is low, and the seventh transistor M7 and the eighth transistor M8 are turned off under the action of the signal at the first node N2.

[0057] In some instances, such as Figure 6 As shown, the third switching unit includes: a tenth transistor M10, the gate of which is connected to the input node N1, and the first terminal of which is connected to the first reference voltage terminal VGL; an eleventh transistor M11, the gate of which is connected to the second terminal of which is connected to the tenth transistor M10, the first terminal of which is connected to the first node N2, and the second terminal of which is connected to the second reference voltage terminal VGH; and a twelfth transistor M12, the gate of which is connected to the second reference voltage terminal VGH, the first terminal of which is connected to the second reference voltage terminal VGH, and the second terminal of which is connected to the gate of which is connected to the eleventh transistor M11.

[0058] Among them, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all n-type TFTs. The twelfth transistor M12 is turned on under the control of the signal at the second reference voltage terminal VGH. The twelfth transistor M12 is used to transmit the signal at the second reference voltage terminal VGH to the gate of the eleventh transistor M11 under the control of the signal at the second reference voltage terminal VGH. The eleventh transistor M11 is turned on under the control of the signal at the second reference voltage terminal VGH. The eleventh transistor M11 is used to transmit the signal at the second reference voltage terminal VGH to the first node N2 under the control of the signal at the first node N2. When the signal at the first node N2 is high, the seventh transistor M7 and the eighth transistor M8 are turned on. The seventh transistor M7 is used to transmit the signal at the first reference voltage terminal VGL to the input node N1 under the control of the signal at the first node N2. When the input node N1 is low, the ninth transistor M9 and the tenth transistor M10 are turned off. At the same time, the eighth transistor M8 is used to transmit the signal at the first reference voltage terminal VGL to the gate signal output terminal Gout under the control of the signal at the first node N2, so as to ensure that the signal output at the gate signal output terminal Gout is low.

[0059] In some instances, such as Figure 7As shown, the output control module 22 includes: a first switch unit 221, the first end of which is connected to the input node N1, the second end of which is connected to the first node N2, the third end of which is connected to the first reference voltage terminal VGL, and the fourth end of which is connected to the gate signal output terminal Gout; a second switch unit 222, the first end of which is connected to the input node N1, the second end of which is connected to the first node N2, and the third end of which is connected to the first reference voltage terminal VGL; a thirteenth transistor M13, the gate of which is connected to the first clock signal terminal CK, the first terminal of which is connected to the gate signal output terminal Gout, and the second terminal of which is connected to the first reference voltage terminal VGL; and a first capacitor C1, the first terminal of which is connected to the second clock signal terminal CKB, and the second terminal of which is connected to the first node N2.

[0060] Among them, the thirteenth transistor M13 is an n-type TFT, and the output control module can be connected in two ways. The first connection method is... Figure 6 The connection method between the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 is as follows: The second connection method is... Figure 8 The connection methods between the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the thirteenth transistor M13, and the first capacitor C1. Both connection methods can achieve control of the low-level signal at the gate signal output terminal Gout.

[0061] In some instances, such as Figure 6 and Figure 8 As shown, the reset module 21 includes: a fourteenth transistor M14, the gate of which is connected to the reset signal terminal RES, the first terminal of which is connected to the input node N1, and the second terminal of which is connected to the first reference voltage terminal VGL; and a fifteenth transistor M15, the gate of which is connected to the reset signal terminal RES, the first terminal of which is connected to the gate signal output terminal Gout, and the second terminal of which is connected to the first reference voltage terminal VGL.

[0062] Among them, the fourteenth transistor M14 and the fifteenth transistor M15 are both n-type TFTs. The fourteenth transistor is used to transmit the first reference voltage terminal VGL to the input node N1 to reset the input node N1 when the reset signal terminal RES is high. The fifteenth transistor M15 is used to transmit the first reference voltage terminal VGL to the gate signal output terminal Gout to reset the gate signal output terminal Gout when the reset signal terminal RES is high.

[0063] In some instances, such as Figure 6 and Figure 8 As shown, the output module 23 includes: a sixteenth transistor M16, the gate of which is connected to the input node N1, the first terminal of which is connected to the second clock signal terminal CKB, and the second terminal of which is connected to the gate signal output terminal Gout; and a second capacitor C2, the first terminal of which is connected to the input node N1, and the second terminal of which is connected to the gate signal output terminal Gout.

[0064] The sixteenth transistor is an n-type TFT. The sixteenth transistor M16 is used to transmit the signal of the second clock signal terminal CKB to the gate signal output terminal Gout when the signal of the input node N1 is high.

[0065] In some instances, the clock cycle of the gate drive signal Gout output by the shift register when cascaded in the second cascaded manner is twice that of the gate drive signal Gout output by the shift register when cascaded in the first cascaded manner.

[0066] This allows for switching between two cascaded relationships on the same panel, satisfying different functional requirements of the display panel and simultaneously meeting both high-performance and low-cost requirements.

[0067] In some examples, the shift registers are cascaded in a first-order cascade configuration. When the gate drive circuit operates in forward-scan mode, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward-scan input signal terminal INF of the (N+k)th shift register. The signal output from Gout of the Nth shift register is used to drive the (N+k)th shift register, where N ≥ 1 and k ≥ 1. When the gate drive circuit operates in reverse-scan mode, the gate signal output terminal Gout of the (M+k)th shift register is electrically connected to the reverse-scan input signal terminal INB of the Mth shift register. The signal output from Gout of the (M+k)th shift register is used to drive the Mth shift register, where M ≥ 1. The high and low levels of the forward-scan input signal terminal INF and the reverse-scan input signal terminal INB are opposite.

[0068] Specifically, in a display device, during forward scanning, the forward scan input signal terminal INF of the first-stage shift register is generally used to receive the start signal. The forward scan input signal terminals INF of other shift registers (excluding the first-stage shift register) are used to receive the signal output from the gate signal output terminal Gout of the previous-stage shift register. During reverse scanning, the reverse scan input signal terminal INB of the last-stage shift register is generally used to receive the start signal. The reverse scan input signal terminals INB of other shift registers (excluding the last-stage shift register) are used to receive the signal output from the gate signal output terminal Gout of the next-stage shift register.

[0069] The value of k is related to the number of pulses in the shift register. k is half of the number of pulses in the shift register, and the number of pulses in the shift register is always an even number. For example, when the number of pulses in the shift register is 2, k = 1; when the number of pulses in the shift register is 4, k = 2.

[0070] It should be noted that... Figure 6 For example, when the shift register pulse count is 2, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k-th row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the (k+2)-th row on the display panel. Similarly, when the shift register pulse count is 4, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k-th row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the (k+4)-th row on the display panel. That is, when the shift register pulse count is j, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k-th row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the (k+j)-th row on the display panel.

[0071] In some instances, the shift registers are cascaded in a second-level cascade configuration. When the gate drive circuit operates in forward-scan mode, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward-scan input signal terminal of the (N+2k)th shift register. The signal output from Gout of the Nth shift register is used to drive the (N+2k)th shift register, where N ≥ 1 and k ≥ 1. When the gate drive circuit operates in reverse-scan mode, the gate signal output terminal Gout of the (M+2k)th shift register is electrically connected to the reverse-scan input signal terminal of the Mth shift register. The signal output from Gout of the (M+2k)th shift register is used to drive the Mth shift register, where M ≥ 1. The high and low levels of the forward-scan and reverse-scan input signal terminals are opposite.

[0072] Since the number of pulses of the shift register when cascaded in the second cascade method is twice the number of pulses when cascaded in the first cascade method, therefore,

[0073] When the shift register pulse count is 2 in the first cascade configuration, k = 1. Correspondingly, the shift register pulse count in the first cascade configuration is 4. When the gate drive circuit is in forward scan mode, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward scan input signal terminal of the (N+2)th shift register. That is, when the gate drive circuit is in forward scan mode, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward scan input signal terminal of the (N+2k)th shift register. Other quantitative relationships can be obtained similarly.

[0074] Figure 9 This is the timing diagram for a gate drive circuit using the first cascade method and with a clock cycle of 2 phases. Figure 10 This is a timing diagram of a gate drive circuit using a second cascaded configuration and a 4-phase clock cycle. Gout1 is the signal output from the gate signal output terminal of the shift register corresponding to the first row on the display panel; Gout2 is the signal output from the gate signal output terminal of the shift register corresponding to the second row on the display panel; Gout3 is the signal output from the gate signal output terminal of the shift register corresponding to the third row on the display panel; Gout4 is the signal output from the gate signal output terminal of the shift register corresponding to the fourth row on the display panel; ck1 is the clock signal input to the second clock signal terminal of the shift register corresponding to the first row on the display panel; ck2 is the clock signal input to the second clock signal terminal of the shift register corresponding to the second row on the display panel; ck3 is the clock signal input to the second clock signal terminal of the shift register corresponding to the third row on the display panel; and ck4 is the clock signal input to the second clock signal terminal of the shift register corresponding to the fourth row on the display panel.

[0075] like Figure 9 As shown, when the clock count is 2 phases, the gate drive circuit is cascaded row by row, that is, the number of cascaded rows is 1, 2, ... n. The clock signal input to the second clock signal terminal of the first row is the same as the clock signal input to the second clock signal terminal of the third row, and the clock signal input to the second clock signal terminal of the second row is the same as the clock signal input to the second clock signal terminal of the fourth row. That is, there are only two clock signals in the entire display panel, and the high and low levels of these two signals are opposite.

[0076] like Figure 10As shown, when the clock count is 4 phases, the gate drive circuit is cascaded in an interlaced manner, meaning the number of cascaded rows is 1, 3, 5, 7, ... and 2, 4, 6, 8, ... . The clock signals input to the second clock signal terminal of the first row are the same as those input to the second clock signal terminal of the fifth row, the same as those input to the second clock signal terminal of the second row, the same as those input to the second clock signal terminal of the sixth row, the same as those input to the second clock signal terminal of the third row, the same as those input to the second clock signal terminal of the seventh row, and the same as those input to the second clock signal terminal of the fourth row and the same as those input to the second clock signal terminal of the eighth row. Furthermore, the first clock signal ck1 and the third clock signal ck3 are clock signals with opposite high and low levels, and the second clock signal ck2 and the fourth clock signal ck4 are clock signals with opposite high and low levels. In other words, the entire display panel has four clock signals, which are two sets of complementary signals.

[0077] Based on the same inventive concept, the present invention also provides a display panel, such as... Figure 11 As shown, it includes: an array substrate and a counter substrate disposed opposite each other; the array substrate includes a substrate 100 and a gate driving circuit 200 of any kind located on the substrate 100.

[0078] The display panel described in this application can switch between two cascaded sets to meet different functional requirements of the display panel. It can simultaneously meet the high performance and low cost requirements of the display panel, solving the problem that in the prior art, the cascaded method of shift registers is fixed in one way, and it is impossible to simultaneously meet the high performance and low cost of the display panel under different functional requirements.

[0079] In some instances, the display panel also includes: multiple rows of pixel units, with gate drive circuitry configured to provide gate drive signal Gout to the pixel units.

[0080] The present invention also provides a display device, such as Figure 12 As shown, it includes: a display area and any type of display panel 300. The display device can be: electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, or any product or component with display function.

[0081] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0082] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0083] 1) The gate driving circuit described in this application includes multiple cascaded shift registers. Each shift register includes a cascaded selection module and a row driving module electrically connected. When a first control signal input to the first control terminal of the cascaded selection module is at a first level and a second control signal input to the second control terminal of the cascaded selection module is at a second level, the shift registers are cascaded in a first cascade configuration. When the first control signal is at a second level and the second control signal is at a first level, the shift registers are cascaded in a second cascade configuration. The row driving module outputs a gate driving signal based on the scan control signal output by the cascaded selection module. This circuit allows for switching between two cascaded configurations on the same panel, meeting different functional requirements of the display panel. It can simultaneously meet the high-performance and low-cost requirements of the display panel, solving the problem in the prior art where the cascaded configuration of shift registers is fixed in one way, making it impossible to simultaneously achieve both high performance and low cost for different display panel functional requirements.

[0084] 2) The above-mentioned display panel of this application can realize the switching of two cascaded relationships, meet the different functional requirements of the display panel, and can simultaneously meet the high performance and low cost requirements of the display panel. This solves the problem that the cascaded method of the shift register in the prior art is fixed in one way, and cannot simultaneously meet the high performance and low cost of the display panel under different functional requirements of the display panel.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, This includes multiple cascaded shift registers, each comprising an electrically connected cascaded selection module and a row drive module, wherein... The first control terminal of the cascade selection module is used to input a first control signal, the second control terminal of the cascade selection module is used to input a second control signal, and the output terminal of the cascade selection module is used to output a scan control signal. When the first control signal is at a first level and the second control signal is at a second level, each shift register is cascaded in a first cascade manner. When the first control signal is at a second level and the second control signal is at a first level, each shift register is cascaded in a second cascade manner. The row driving module is used to output a gate driving signal under the action of the scan control signal. The gate driving signal is used to drive the display element of the current row to display or not display. The cascade selection module includes: A forward scan signal input unit is configured to input a first forward scan signal to the row driving module under the control of the first control signal, and to input a second forward scan signal to the row driving module under the control of the second control signal. The first forward scan signal is the first gate driving signal output by the previous level shift register when the shift registers are cascaded in a first cascade manner, and the second forward scan signal is the second gate driving signal output by the previous level shift register when the shift registers are cascaded in a second cascade manner. A backscan signal input unit is configured to input a first backscan signal to the row drive module under the control of the first control signal, and to input a second backscan signal to the row drive module under the control of the second control signal. The first backscan signal is the third gate drive signal output by the next-stage shift register when the shift registers are cascaded in a first cascade manner, and the second backscan signal is the fourth gate drive signal output by the next-stage shift register when the shift registers are cascaded in a second cascade manner.

2. The gate driving circuit according to claim 1, characterized in that, The forward scan signal input unit includes: The first transistor has a gate for inputting the first control signal, a first electrode for inputting the first forward scan signal, and a second electrode for being electrically connected to the forward scan signal input terminal of the row drive module. The second transistor has a gate for inputting the second control signal, a first terminal for inputting the second forward scan signal, and a second terminal for electrical connection to the forward scan signal input terminal of the row drive module.

3. The gate driving circuit according to claim 1, characterized in that, The reverse scan signal input unit includes: The third transistor has its gate used to input the first control signal, its first terminal used to input the first reverse scan signal, and its second terminal used to be electrically connected to the reverse scan signal input terminal of the row drive module. The fourth transistor has its gate used to input the second control signal, its first terminal used to input the second reverse scan signal, and its second terminal used to be electrically connected to the reverse scan signal input terminal of the row drive module.

4. The gate driving circuit according to claim 1, characterized in that, The row drive module includes a scan control module, a reset module, an output control module, and an output module that are electrically connected, wherein... The scanning control module is used to provide the signal from the forward scan control signal terminal to the input node under the control of the signal from the forward scan input signal terminal, or to provide the signal from the reverse scan control signal terminal to the input node under the control of the signal from the reverse scan input signal terminal. The reset module is used to reset the input node and the gate signal output terminal under the control of a reset signal; The output control module, the output module, and the scan control module are connected at the input node. The output control module, the output module, and the reset module are all connected to the gate signal output terminal. The gate signal output terminal is used to output the gate drive signal. The output control module is used to control the level of the gate drive signal under the control of the signal at the input node. The output module is used to output the gate drive signal under the control of the signal from the input node.

5. The gate driving circuit according to claim 4, characterized in that, The scanning control module includes: The fifth transistor has its gate connected to the forward scan input signal terminal, its first terminal connected to the forward scan control signal terminal, and its second terminal connected to the input node. The sixth transistor has its gate connected to the reverse scan input signal terminal, its first terminal connected to the reverse scan control signal terminal, and its second terminal connected to the input node.

6. The gate driving circuit according to claim 4, characterized in that, The output control module includes: A first switching unit, wherein a first terminal of the first switching unit is connected to the input node, a second terminal of the first switching unit is connected to the first node, a third terminal of the first switching unit is connected to the first reference voltage terminal, and a fourth terminal of the first switching unit is connected to the gate signal output terminal; The second switching unit has a first terminal connected to the input node, a second terminal connected to the first node, and a third terminal connected to the first reference voltage terminal. The third switching unit has a first terminal connected to the first node, a second terminal connected to the input node, a third terminal connected to the first reference voltage terminal, and a fourth terminal connected to the second reference voltage terminal.

7. The gate driving circuit according to claim 6, characterized in that, The first switching unit includes: A seventh transistor, wherein the gate of the seventh transistor is connected to the first node, the first terminal of the seventh transistor is connected to the input node, and the second terminal of the seventh transistor is connected to the first reference voltage terminal; The eighth transistor has its gate connected to the first node, its first terminal connected to the gate signal output terminal, and the second terminal of the seventh transistor connected to the first reference voltage terminal.

8. The gate driving circuit according to claim 6, characterized in that, The second switching unit includes: The ninth transistor has its gate connected to the input node, its first terminal connected to the first node, and its second terminal connected to the first reference voltage terminal.

9. The gate driving circuit according to claim 6, characterized in that, The third switching unit includes: The tenth transistor has its gate connected to the input node and its first terminal connected to the first reference voltage terminal. The eleventh transistor has its gate connected to the second terminal of the tenth transistor, its first terminal connected to the first node, and its second terminal connected to the second reference voltage terminal. The twelfth transistor has its gate connected to the second reference voltage terminal, its first terminal connected to the second reference voltage terminal, and its second terminal connected to the gate of the eleventh transistor.

10. The gate driving circuit according to claim 4, characterized in that, The output control module includes: A first switching unit, wherein a first terminal of the first switching unit is connected to the input node, a second terminal of the first switching unit is connected to the first node, a third terminal of the first switching unit is connected to the first reference voltage terminal, and a fourth terminal of the first switching unit is connected to the gate signal output terminal; The second switching unit has a first terminal connected to the input node, a second terminal connected to the first node, and a third terminal connected to the first reference voltage terminal. The thirteenth transistor has its gate connected to the first clock signal terminal, its first terminal connected to the gate signal output terminal, and its second terminal connected to the first reference voltage terminal. A first capacitor, the first terminal of which is connected to a second clock signal terminal, and the second terminal of which is connected to the first node.

11. The gate driving circuit according to claim 4, characterized in that, The reset module includes: The fourteenth transistor has its gate connected to the reset signal terminal, its first terminal connected to the input node, and its second terminal connected to the first reference voltage terminal. The fifteenth transistor has its gate connected to the reset signal terminal, its first terminal connected to the gate signal output terminal, and its second terminal connected to the first reference voltage terminal.

12. The gate driving circuit according to claim 4, characterized in that, The output module includes: The sixteenth transistor has its gate connected to the input node, its first terminal connected to the second clock signal terminal, and its second terminal connected to the gate signal output terminal. The second capacitor has its first terminal connected to the input node and its second terminal connected to the gate signal output terminal.

13. The gate driving circuit according to claim 1, characterized in that, When cascading in the second cascading method, the clock count of the gate drive signal output by the shift register is twice the clock count of the gate drive signal output by the shift register when cascading in the first cascading method.

14. The gate driving circuit according to claim 1, characterized in that, The cascading method of the shift registers is the first cascading method, wherein, When the gate driving circuit is driven in a forward scan mode, the gate signal output terminal of the Nth shift register is electrically connected to the forward scan input signal terminal of the (N+k)th shift register, and the signal output from the gate signal output terminal of the Nth shift register is used to drive the (N+k)th shift register, where N≥1 and k≥1. In the case of reverse sweep drive in the gate drive circuit, the gate signal output terminal of the (M+k)th shift register is electrically connected to the reverse sweep input signal terminal in the Mth shift register, and the signal output from the gate signal output terminal of the (M+k)th shift register is used to drive the Mth shift register, where M≥1. The high and low levels of the forward scan input signal terminal and the reverse scan input signal terminal are opposite.

15. The gate driving circuit according to claim 1, characterized in that, The cascading method of each shift register is the second cascading method, wherein, When the gate driving circuit is driven in a forward scan mode, the gate signal output terminal of the Nth shift register is electrically connected to the forward scan input signal terminal of the (N+2k)th shift register, and the signal output from the gate signal output terminal of the Nth shift register is used to drive the (N+2k)th shift register, where N≥1 and k≥1. In the case of reverse sweep drive in the gate drive circuit, the gate signal output terminal of the (M+2k)th shift register is electrically connected to the reverse sweep input signal terminal in the Mth shift register, and the signal output from the gate signal output terminal of the (M+2k)th shift register is used to drive the Mth shift register, where M≥1; The high and low levels of the forward scan input signal terminal and the reverse scan input signal terminal are opposite.

16. A display panel, characterized in that, include: The array substrate and the opposing substrate are arranged opposite each other; The array substrate includes a substrate and a gate driving circuit according to any one of claims 1 to 15 located on the substrate.

17. The display panel according to claim 16, characterized in that, The display panel also includes: A multi-row pixel unit, wherein the gate driving circuit is configured to provide a gate driving signal to the pixel unit.

18. A display device, characterized in that, include: The display area and the display panel as described in any one of claims 16 to 17.

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