Memory system

Abstract

The invention relates to a memory system. A memory system includes a memory having memory blocks. A first logic circuit performs an XOR combinatorial logic function on a current value of a data addressing pattern and at least one bit of a first data packet comprising an error correction code of a data element to be written. A second data packet generated by the first logic circuit is stored in one of the memory blocks. A second logic circuit performs a XOR combinatorial logic function on at least one bit of a second data packet, such as read from one of the memory blocks, and a current value of the addressing mode. The weight of the bit of the first data packet corresponds to the weight of at least one bit of the read second data packet.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French Patent Application No. 2308604, filed on August 9, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to memory systems and methods implemented by these memory systems. Background Art

[0004] Many applications use memory systems to implement data storage in volatile or non-volatile memory. These systems can implement multiple linear or interleaved modes of addressing data to different memory blocks. However, continuous changes in addressing patterns can, in some cases, lead to reduced security of stored data.

[0005] There is a need to obtain a memory system that enables storage data to be kept safe during addressing mode changes.There is a need to overcome all or part of the disadvantages of known memory systems. Summary of the invention

[0006] An embodiment provides a memory system, comprising: a memory, including memory blocks; a first logic circuit, configured to perform an XOR combinational logic function on a current value of a data addressing mode and at least one bit of a first data packet, the first data packet including an error correction code of a data element to be written or the data element to be written or the error correction code of the data element to be written and the data element to be written; a second data packet generated by the first logic circuit is stored in one of the memory blocks; and a second logic circuit, configured to perform an XOR combinational logic function on at least one bit of a second data packet, such as read from one of the memory blocks, and the current value of the addressing mode during or after reading the second data packet, the weight of the at least one bit of the first data packet corresponding to the weight of the at least one bit of the second read data packet.

[0007] An embodiment provides a method for protecting a memory system, the system being provided with a memory including a memory block, the method comprising: using a first logic circuit to perform an XOR combinational logic function on a current value of a data addressing mode and at least one bit of a first data packet, the first data packet comprising an error correction code of a data element to be written or the data element to be written or the error correction code of the data element to be written and the data element to be written; storing a second data packet generated by the first logic circuit into one of the memory blocks; during or subsequently reading the second data packet, using a second logic circuit to perform an XOR combinational logic function on at least one bit of a second data packet, such as read from one of the memory blocks, and the current value of the addressing mode, the weight of the at least one bit of the first data packet corresponding to the weight of the at least one bit of the second read data packet.

[0008] In an embodiment, such a system or method further includes an error correction code decoder configured to decode the third data packet generated by the second logic circuit.

[0009] In an embodiment, such a system or method further comprises an error correction code encoder configured to calculate the error correction code associated with the data element to be written.

[0010] In an embodiment, the first logic circuit is configured to perform an XOR combinational logic function based on bits of a first data packet; and the second logic circuit is configured to perform an XOR combinational logic function based on bits of a second data packet, such as read from one of the memory blocks; the weights of the bits of the first data packet correspond to the corresponding weights of the bits of the second data packet after reading.

[0011] In an embodiment, the error correction code encoder and decoder are of the self-encrypting device (SED) type.

[0012] In an embodiment, the first logic circuit is configured to perform an XOR combinational logic function based on two bits of a first data packet; and the second logic circuit is configured to perform an XOR combinational logic function based on two bits of a second data packet, such as read from one of the memory blocks; the weights of the two bits of the first data packet correspond to the corresponding weights of the two bits of the second data packet after reading.

[0013] In an embodiment, the error correction code encoder and decoder are of the single error correction double error detection (SECDED) type.

[0014] In an embodiment, the first logic circuit is configured to perform an XOR combinational logic function based on three bits of a first data packet; and the second logic circuit is configured to perform an XOR combinational logic function based on three bits of a second data packet, such as read from one of the memory blocks; the weights of the three bits of the first data packet correspond to the corresponding weights of the three bits of the second data packet after reading.

[0015] In an embodiment, the error correction code encoder and decoder are of the double error correction triple error detection (DECTED) type.

[0016] In an embodiment, if the error correction code decoder detects an error, the memory system generates an error value.

[0017] In an embodiment, if the error correction code decoder detects two errors, the system generates an error value.

[0018] In an embodiment, if the error correction code decoder detects three errors, the memory system generates an error value.

[0019] In an embodiment, the value of the addressing mode corresponds to an interleaved mode or a linear mode for writing data into the memory block.

[0020] In an embodiment, the first data packet further includes a data element to be written. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0022] Figure 1 shows examples of integrated circuits of the type to which the described embodiments are applicable;

[0023] Figure 2 Picture shows Figure 1 An example of a memory system of an integrated circuit;

[0024] Figure 3 Picture shows Figure 1 Examples of memories of integrated circuits;

[0025] Figure 4 The diagram shows a Figure 1 An example of a memory system of an integrated circuit; and

[0026] Figure 5 FIG. 1 illustrates a protection circuit according to an embodiment of the present invention. Figure 4 A method for a memory system. DETAILED DESCRIPTION

[0027] The same features in the various figures are denoted by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structures, dimensions and material properties.

[0028] For clarity, only the steps and elements that are useful for understanding the described embodiments are illustrated and described in detail.

[0029] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0030] In the following description, when reference is made to terms that define absolute positions, such as terms "edge", "back", "top", "bottom", "left", "right", etc., or terms that define relative positions, such as terms "up", "down", "upper", "lower", etc., or terms that define directions, such as terms "horizontal", "vertical", etc., unless otherwise specified, they refer to the orientation of the drawing.

[0031] Unless otherwise indicated, the expressions "approximately", "approximately", "substantially" and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0032] Figure 1 An example of an integrated circuit of the type to which the described embodiments are applicable is shown.

[0033] More precisely, Figure 1 An example of an integrated circuit device 100 in which a memory system 130 is integrated is shown. The memory system 130 integrates a volatile memory 104 (memory), such as a RAM, or a non-volatile type, such as a FLASH type. The memory 104 includes, for example, a plurality of memory blocks 107, 109 (CUT1, CUT2). The memory 104 can communicate with a driver circuit 106 (memory controller) via one or more of the communication buses 103, 105, and the driver circuit 106 is configured to write data to the memory 104 or read data from the memory 104. In an example, the bus 105 is dedicated to the memory block 107, and the bus 103 is dedicated to the memory block 109. The buses 103 and 105 are, for example, aggregated in a single bus.

[0034] The memory system 130 integrates, for example, a memory controller 106, which includes a dedicated hardware encoder circuit that, when activated, is configured to calculate an error correction code (ECC) during writing each element to one of the memory blocks 107, 109. The communication buses 103, 105 are, for example, address buses and buses for data packets, which include data to be written and its associated error correction code (Data+ECC, Addrc2 and Data+ECC, Addrc1, respectively). The memory controller implements, for example, multiple linear or interleaved addressing modes to write data to different memory blocks. The memory controller 106 receives information (md), for example in the form of bits, related to the addressing mode for writing and / or reading data from different memory blocks 107, 109, for example, via the bus 114 or via another bus.

[0035] The device 100 further comprises, for example, a processing unit 110 (CPU) comprising one or more processors controlled by instructions stored in an instruction memory 112 (INSTRMEM). The instruction memory 112 is, for example, of a random access type (RAM). The processing unit 110 and the memory 112 communicate (data, address and control) for example via a system bus 140. The memory controller 106 is coupled to the system bus 140, for example via a firewall 113 and one or more communication buses 114. The communication bus 114 enables, for example, the exchange of addresses, data and error-related data on error correction codes (Data, Addr, ECCError).

[0036] The firewall 113 protects critical data by filtering the critical data based on the address of the critical data. The firewall cooperates with, for example, the bus 140 to process data and system addresses (Data, SystemAddr).

[0037] The device 100 also includes an input / output interface 108 (I / O interface) coupled to the system bus 140 for communicating with the outside.

[0038] The device 100 may integrate other circuits for implementing other functions (eg, one or more volatile and / or non-volatile memories, other processing units). Figure 1 This is indicated by box 116 (FCT).

[0039] Figure 2 Picture shows Figure 1 An example of a memory system 130 of an integrated circuit.

[0040] In the example shown, the memory controller 106 of the memory system 130 includes an error correction code encoder circuit 206 (ECC encoder) configured to calculate an error correction code (ECC WRTO mem) associated with a data element to be written (Data WR in) supplied, for example, via the bus 114. The data element (Data WR TO mem) and its associated error correction code ECC WRTO mem are supplied, for example, in the form of one or more data packets to the bus 105 to be written to the memory 104. When the data elements and their associated error correction codes are arranged in data packets (also referred to as words), they may be arranged in the form of ECC_Data.

[0041] In an example, the encoder and decoder 206 , 216 apply Hamming codes or Golay codes.

[0042] In the example shown, the memory controller 106 of the memory system 130 also includes an error correction code decoder circuit 216 (ECC Decoder) configured to decode an error correction code (ECC RD from mem) of a data packet (ECC RD from mem + Data RD from mem) that results from a read of a data packet that has been previously written to the memory 104. The decoder 216 issues a flag (ECC Error), for example, via the bus 114, indicating that an error has been found in the read data packet and including, for example, the error correction code (ECC RD from mem) and the read data element (Data RD in).

[0043] The circuits 206 and 216 are, for example, hardware circuits.

[0044] In certain cases, during the memory writing of (one or more) data packets, it may happen that one or more bits of the data packet are flipped (i.e., for a bit of a given weight, an opposite value is recorded) (a phenomenon known as bit flipping). In such cases, an error correction code ECC can be used.

[0045] During the decoding step, an error correction code may be used to correct one or more errors in the data packet read from the memory.

[0046] There are different types of error correction codes: Single Error Detection (SED) is an error correction code that allows only one error to be detected for each data packet read from memory. When an error is detected in a data packet read from memory, an error code or a zero value is returned. Single and Double Error Correction (SECDED) is an error correction code that allows one error to be corrected and a maximum of two errors to be detected for each data packet read from memory. When two errors are detected in a data packet read from memory, an error code or a zero value is returned. Double and Triple Error Correction (DECTED) is an error correction code that allows a maximum of two errors to be corrected and a maximum of three errors to be detected for each data packet read from memory. When three errors are detected in a data packet read from memory, an error code or a zero value is returned.

[0047] Thus, when the encoder and decoder 206, 216 are of the SED type, they allow correction of a one-bit flip of a data packet. When they are of the SECDED type, they allow correction of a one-bit flip of a data packet and detection of a two-bit modification. When they are of the DECTED type, they allow correction of a two-bit flip and detection of a three-bit modification.

[0048] In summary, for the SECDED type encoder 206 and decoder 216, if there is one bit flip in the error correction code or read data element, then the data element Data RD in is equal to the data element Data WR in, because the decoder has corrected the read data element or ECC code of the data packet. If two bits are flipped, then the data element Data RD in has switched to 0, and the decoder issues an ECC Error flag. In the case of 3 or more bit reversals, the results of the decoder 216 are unpredictable.

[0049] Figure 3 Picture shows Figure 1 An example of a memory 104 of an integrated circuit.

[0050] More precisely, Figure 3 The example illustrates the memory blocks 107 and 109 in the case where the addressing mode is a linear type (linear mode) (the case shown on the left side) and in the case where the addressing mode is an interleaved type (the case shown on the right side).

[0051] In the case of linear mode, the memory block 107 is filled with data according to linearly increasing system addresses (SystemAddr), for example from 0x0 to 0x7. The data sequence is replicated in the same way with system addresses 0x8 to 0xF.

[0052] In the case of interleaved mode, data is written, for example, at addresses increasing from two to two. In the example shown, the addresses in the first memory block 107 are 0x0, then 0x2, then 0x4, etc., all the way to 0xE, and the addresses in the second memory block 109 are 0x1, then 0x3, then 0x5, etc., all the way to 0xF.

[0053] In the example in linear mode shown, the firewall defines data at addresses 0x4, 0x5, 0x6, 0x7 (region 310) of block 107 and addresses 0x8, 0x9, 0xA, 0xB to 0xB (region 320) of block 109 as data to be protected, such as encryption keys.

[0054] During a change in addressing mode, such as during a transition from a linear addressing mode to an interleaved addressing mode, system addresses are used differently in memory blocks 107 and 109 .

[0055] For each addressing mode, a secure address area is defined and intended for storing secure data. In addition, a non-secure address area is defined and intended for storing non-secure data.

[0056] Certain addresses may constitute part of the secure address region in linear mode and part of the non-secure address region in interleaved mode.

[0057] In the example shown, addresses 0x4 and 0x6 as well as 0x9 and 0xB are not included in the address areas 310 and 320 defining secure data, whereas they are in linear mode. During the change of the addressing mode from linear mode to interleaved mode, addresses 0x4 and 0x6 as well as 0x9 and 0xB thus become accessible, resulting in a hacker being able to exploit this mode change to access secure data.

[0058] To overcome these problems, memory blocks can be erased. However, such erasure requires a significant duration, especially in the case of non-volatile memories. In another solution, the error correction code can be based on data elements and their addresses. However, this requires increased hardware resources and affects execution speed. An alternative solution is to add additional bits to store the addressing mode used during the write operation, but this results in an increase in the size of the memory 104.

[0059] An embodiment provides a memory system comprising: a first logic circuit configured to perform an XOR combinational logic function (XOR) on a current value of a data addressing mode and at least one bit of a first data packet, the first data packet including an error correction code of a data element to be written, a second data packet generated by the first logic circuit being stored in one of the memory blocks; and a second logic circuit configured to perform an XOR combinational logic function on at least one bit of a second data packet, such as read from one of the memory blocks, and the current value of the addressing mode during or after reading the second data packet, the weight of the at least one bit of the first data packet corresponding to the weight of the at least one bit of the second data packet after reading.

[0060] Thanks to such a memory system, if the addressing mode changes (from linear mode to interleaved mode or vice versa) between writing a data element to be written and its associated error correction code to the memory and reading the data element and its error correction code, the decoder can be used to detect the error, which will, for example, enable access to the written data element to be disabled. This further enables secure data to be made inaccessible during the addressing mode change, and this does not require an increase in memory size.

[0061] In fact, if the addressing mode is changed between writing and reading a data element, and the value of the addressing mode is different, the data packet read will contain at least one error. In the case where the error correction code is of the SED type, an error detection flag will be issued and an error code or a zero value will be returned during reading.

[0062] When the error correction code is of another type, such as SECDED or DECTED, then the logic circuit is configured to perform operations on two bits and three bits, respectively, so that an error code or a zero value is returned if the addressing mode changes between writing and reading.

[0063] An XOR operation is performed on the first data packet, which may be an error correction code or data to be written or a concatenation of the error correction code and the data to be written.

[0064] Figure 4 The diagram shows a Figure 1 An example of a memory system 130 of an integrated circuit.

[0065] Figure 4 The memory system and Figure 2The memory controller 106 is similar to the memory system of , except that the memory controller 106 includes a first combinational logic circuit 406 (performing an exclusive OR (XOR) logic combination on one or more bits and md) and a second combinational logic circuit 416 (performing an XOR logic combination on one or more bits and md), which are configured to perform an XOR combinational logic function (XOR) on at least one selected bit of the bits received as input. In the case where the encoder and decoder 206, 216 are of the SED type, the XOR operation is applied to a single bit. In the case where the encoder and decoder 206, 216 are of the SECDED type, the XOR operation is applied to two selected bits. In the case where the encoder and decoder 206, 216 are of the DECTED type, the XOR operation is applied to three selected bits. The selected bits to be submitted to the XOR operation are either on the error correction code, on the data element, or on both.

[0066] The first logic circuit 406 performs an XOR combination logic function based on the current value md of the addressing mode (i.e., the value md when encoding the ECC or until the XOR operation is performed). The XOR combination logic function is also performed based on at least one bit of the data packet containing the data element DataWRin to be written and its associated error correction code ECCin. The error correction code ECCin associated with the data element Data WRin to be written is obtained by the encoder 206.

[0067] As an illustration, in the case where the encoder 206 and the decoder 216 are of the SECDED type, if ECCin = 111 and Data WR in = 0101, the associated data packet is, for example, of the form 111_0101 (or 0101_111). If the current addressing mode is, for example, interleaved and the value 1 is associated with the mode in any way, and if it is desired to apply the XOR combinational logic function of the first logic circuit 406 to the least significant bit of ECCin 111 and the most significant bit of Data WR in 0101, then at the output of the first logic circuit, a data element XOR Data WR TO mem = 1101 and an error correction code XOR ECCWR TO mem = 110 will be obtained. Before being written into one of the memory blocks, the data packet at the output of the block 406 is then 110_1101.

[0068] The data elements XOR Data WR TO mem and the code ECC, XOR ECC WR TO mem, generated by the logic circuit 406 are either supplied individually via the bus 105 or in the form of a data packet (eg in the form of 110_1101 in the previous example) via the bus 105 .

[0069] The data element XOR Data WR TO mem and the code ECC, XOR ECC WR TO mem, are then stored in one of the memory blocks of the memory 104 .

[0070] The data element and its associated error code are then read and are then referred to, for example, as Data RDfrom mem and ECC RD from mem.

[0071] The data element Data RD from mem and its associated error code ECC RD from mem that have been read are then used, for example in the form of a data packet ECC RD from mem_DataRD from mem, at the input of the second logic circuit 416. The second logic circuit 416 then performs an XOR combinational logic function (XOR) on at least one bit of the data packet ECC RD from mem_DataRD from mem and the current value md of the addressing mode. During the reading of the data element Data RD from mem and its associated error code ECC RD from mem (or the data packet formed by the latter), or after this reading, for example when performing the XOR operation, the current value md corresponds to the value of the addressing mode.

[0072] The XOR combinatorial logic function is performed on the same bit(s) as those already used in the first logic circuit 406. In other words, the operation of the second logic circuit 406 is applied to bits having the same weights as those used when applying the XOR combinatorial logic function to the data elements Data WR in and / or ECC in.

[0073] Referring to the previous illustrated example, if the current addressing mode has changed during or after reading and becomes, for example, linear and the value 0 is associated with the linear mode in any way, then the XOR combinational logic function of the second logic circuit 416 is applied to, for example, the least significant bit of ECC RDfrom mem and the most significant bit of Data RDfrom mem, and then, at the output of the second logic circuit 416, a data element XOR Data RDin = 1101 and an error correction code XOR ECC RD = 110 are obtained. XOR Data RDin and XOR ECC RD are, for example, arranged in an output data packet of block 416 and have a 110_1101 form in this example.

[0074] The decoder 216 analyzes the error correction code XOR ECC RD and the data element XOR Data RD. At the output of the decoder 216, if the addressing mode md has not changed between the block 206 and the block 416, and no write or read error has occurred, then the flag ECC Error will not be issued, and the data element Data RD in will be the same as Data WR in. However, if, as in the illustrated example, the addressing mode md has changed between the block 206 and the block 416, then the decoder will issue the flag ECC Error—for example, by switching it to 1—because the error correction code XOR ECC RD and the data element XOR Data RD are inconsistent with each other. In this case, the data element Data RD in is set to, for example, 0, and an error or zero value of the bus error type is sent to the processing unit 110. This makes it possible to make the security data inaccessible during the addressing mode change, and this does not require an increase in the memory size.

[0075] Figure 5 FIG. 1 illustrates a protection circuit according to an embodiment of the present invention. Figure 4 A method for a memory system.

[0076] In this example, the first step 502 (Start) signals the start of the protection method.

[0077] At the subsequent step 504 (Provide Word Containing ECCinfrom Data to be Written), the error correction code ECCin is calculated by the encoder 206 based on the data elements Data WR in to be written.

[0078] At the subsequent step 506 (XOR one or more bits of the word with the address mode value md), an XOR combinational logic function XOR is performed on the current value of the data addressing mode md and at least one bit of the first data packet, the first data packet is, for example, in the form of ECCin_DataWR in, including the error correction code ECCin and the data element Data WR in to be written.

[0079] At the subsequent step 508 (store word resulting from XOR operation in memory), the second data packet generated by the first logic circuit 406 c , for example in the form of XOR ECC WR TO mem_XORData WR TO mem, is stored in one of the memory blocks 107 , 109 .

[0080] At a subsequent step 510 (XOR one or more bits of the read word with the address mode value md), an XOR combination logic function XOR is performed on at least one bit of the second data packet, such as read from one of the memory blocks 107, 109, and the current value md of the addressing mode during or after reading the second data packet using the second logic circuit 416. The weight of the bit(s) of the first data packet submitted to the XOR combination logic function corresponds to the weight of the bit(s) of the second data packet submitted to the XOR combination logic function after reading.

[0081] Various embodiments and variants have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variants may be combined, and those skilled in the art will recognize other variants. In particular, the bit(s) on which the XOR operation is performed are, for example, only on the code ECCin and ECC RDfrom mem, or also only on the data DataRDfrommem and Data WR in.

[0082] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, with regard to the arrangement of the error correction codes and the corresponding data elements, it is possible to process in the form of data packets in the illustrated example or individually. In addition, the number of bits implicit in the logic circuits 406 and 416 is a function of the encoding and decoding of the SED, SECDED, DECTED type. In addition, other types of codes other than Hamming or Golay can be used for the error correction codes.

Claims

1. A memory system, comprising: Memory, including memory blocks; a first logic circuit configured to perform an XOR combinational logic function on a current value of a data addressing mode and at least one bit of a first data packet, the first data packet comprising one of: an error correction code of a data element to be written; the data element to be written; or a combination of the error correction code of the data element to be written and the data element to be written; wherein a second data packet output by the first logic circuit is stored in one of the memory blocks; as well as a second logic circuit configured to perform an XOR combinational logic function on at least one bit of the second data packet read from one of the memory blocks and a current value of the addressing mode during or after the reading of the second data packet; The weight of the at least one bit of the first data packet corresponds to the weight of the at least one bit of the read second data packet.

2. The system of claim 1, further comprising an error correction code decoder configured to decode the third data packet generated by the second logic circuit. 3 . The system of claim 2 , further comprising an error correction code encoder configured to calculate the error correction code associated with the data element to be written.

4. The system of claim 3, wherein: The first logic circuit is configured to perform an XOR combinational logic function based on the bits of the first data packet; and The second logic circuit is configured to perform an XOR combinational logic function based on bits of a second data packet, such as read from one of the memory blocks.

5. The system according to claim 4, wherein the ECC encoder and the ECC decoder are of single error detection (SED) type.

6. The system according to claim 5, wherein: If the error correction code decoder detects an error, the memory system generates an error value.

7. The system of claim 3, wherein: The first logic circuit is configured to perform an XOR combinational logic function based on two bits of the first data packet; and The second logic circuit is configured to perform an XOR combinational logic function based on two bits of a second data packet, such as read from one of the memory blocks; The weights of the two bits of the first data packet correspond to the corresponding weights of the two bits of the second data packet after reading.

8. The system according to claim 7, wherein the error correction code encoder and the error correction code decoder are of single error correction double error detection SECDED type.

9. The system according to claim 8, wherein: If the error correction code decoder detects two errors, the system generates an error value.

10. The system of claim 3, wherein: The first logic circuit is configured to perform an XOR combinational logic function based on three bits of the first data packet; and The second logic circuit is configured to perform an XOR combinational logic function based on three bits of a second data packet, such as read from one of the memory blocks; The weights of the three bits of the first data packet correspond to the corresponding weights of the three bits of the second data packet after reading.

11. The system according to claim 10, wherein the error correction code encoder and the error correction code decoder are of double error correction triple error detection DECTED type.

12. The system of claim 1, wherein: If the error correction code decoder detects three errors, the memory system generates an error value.

13. The system of claim 1, wherein the value of the addressing mode corresponds to one of an interleaved mode of writing data into the memory block or a linear mode of writing data into the memory block.

14. The system of claim 1, wherein the first data packet further comprises a data element to be written.

15. A method for protecting a memory system, the memory system comprising a memory having a memory block, the method comprising: Performing a first logical combination of the current value of the data addressing mode and at least one bit of the first data packet using an XOR combination logic function, the first data packet comprising one of: an error correction code of a data element to be written; the data element to be written; or a combination of the error correction code of the data element to be written and the data element to be written; storing a second data packet generated by the first logical combination in one of the memory blocks; performing a second logical combination of at least one bit of the second data packet, such as read from one of the memory blocks, with the current value of the addressing mode using an XOR combinational logic function during or after the reading of the second data packet; The weight of the at least one bit of the first data packet corresponds to the weight of the at least one bit of the read second data packet.

16. The method of claim 15, further comprising decoding the third data packet generated by the second logic circuit using an error correction code.

17. The method of claim 16, further comprising encoding to compute the error correction code associated with the data element to be written.

18. The method of claim 17, wherein: The first logical combination performs an XOR combinational logic function based on the bits of the first data packet; and The second logical combination performs an XOR combinational logic function based on bits of a second data packet, such as read from one of the memory blocks.

19. The method of claim 17, wherein: The first logical combination performs an XOR combinational logic function based on two bits of the first data packet; and a second logical combination performing an XOR combinational logic function based on two bits of a second data packet such as read from one of the memory blocks; The weights of the two bits of the first data packet correspond to the corresponding weights of the two bits of the second data packet after reading.

20. The method of claim 17, wherein: The first logical combination performs an XOR combinational logic function based on three bits of the first data packet; and a second logical combination performing an XOR combinational logic function based on three bits of a second data packet, such as read from one of the memory blocks; The weights of the three bits of the first data packet correspond to the corresponding weights of the three bits of the second data packet after reading.

21. The method of claim 15, wherein the value of the addressing mode corresponds to one of an interleaved mode of writing data into the memory block or a linear mode of writing data into the memory block.

22. The method of claim 15, wherein the first data packet further comprises a data element to be written.

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