Phased array transmitter based on intermediate frequency local oscillator (IFLO) phase shift architecture

Abstract

A phased array transmitter system includes a plurality of signal paths and a power amplifier. Each of the signal paths includes: a phase shifter configured to generate a phase shifted signal; a first mixer configured to mix the phase shifted signal with a baseband signal to generate a first mixed signal; a variable gain amplifier (VGA) configured to perform a phase-invariant gain-controlled amplification of the first mixed signal; a second mixer configured to mix the amplified first mixed signal with a radio frequency local oscillator (RFLO) signal to generate a radio frequency (RF) signal; and a power amplifier configured to amplify the RF signal and feed the amplified RF signal to the antenna.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 518,882, filed on August 11, 2023, the entire contents of which are incorporated herein by reference. Background Art

[0003] Phased array transmitters that integrate multiple on-chip elements can be used as building blocks for large-scale beamforming systems. Precise phase shifting, gain control, and orthogonality between functions are considered when ensuring beam pointing with high directivity and low sidelobe levels.

[0004] Traditional RF phase shifting (RF PS) schemes rely on I / Q vector generation and high-resolution I / Q gain control to achieve phase shifting. This approach is known to suffer from poor PS linearity, PS-induced gain variation, and area and power overhead. In addition, the use of RF PS and RF variable gain amplifiers (VGAs) requires large power and area, and in RF phase shifting schemes, phase gain control is not orthogonal and there is phase control nonlinearity.

[0005] Newer RF local oscillator (RFLO) PS technology provides highly linear and gain-invariant PS capabilities, but at the expense of additional area and power consumption. That is, the combination of the RFLO PS, additional RFLO buffer, VGA, and RFLO PS requires large power and area. In addition, in the RFLO phase shifting scheme, there is a gain control problem that causes phase variation due to the use of the RF VGA.

[0006] Baseband PS technology provides improved area efficiency. However, baseband phase shifting schemes require complex algorithms to avoid beam tilt problems. There is also the additional issue of the tradeoff between PS resolution and power consumption. Summary of the invention

[0007] In an exemplary embodiment, the present invention provides a phased array transmitter system. The phased array transmitter system includes multiple signal paths. Each signal path includes: a phase shifter configured to generate a phase-shifted signal; a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal; a variable gain amplifier (VGA) configured to perform phase-invariant gain-controlled amplification on the first mixed signal; a second mixer configured to mix the amplified first mixed signal with a radio frequency local oscillator (RFLO) signal to generate a radio frequency (RF) signal; and a power amplifier configured to amplify the RF signal and feed the amplified RF signal to an antenna.

[0008] In another exemplary embodiment, the plurality of signal paths includes four signal paths, and the phase shifter of each of the four signal paths includes an 8-2 phase multiplexer.

[0009] In another exemplary embodiment, the phased array transmitter system further includes a divide-by-4 (Div-4) circuit configured to generate an 8-phase intermediate frequency local oscillator (IFLO) signal.

[0010] In another exemplary embodiment, the phase shifter of each of the four signal paths takes as input a pair of 8-phase IFLO signals generated by the Div-4 circuit.

[0011] In another exemplary embodiment, the 8-phase IFLO signals are equally spaced with 45 degree intervals between adjacent signals.

[0012] In another exemplary embodiment, the phased array transmitter system further includes: an 8-phase IFLO signal distribution circuit configured to reorder the 8-phase IFLO signals to be input to the phase shifters of the plurality of signal paths.

[0013] In another exemplary embodiment, a phase shifter includes a first set of switches, a set of integral mode phase interpolators (IMPIs), and a second set of switches.

[0014] In another exemplary embodiment, a first set of switches is configured to be controlled by a first plurality of bits to select four consecutive phases from eight available phases; wherein the set of IMPIs is configured to be controlled by a second plurality of bits corresponding to a phase interpolation code; and the second set of switches is configured to be controlled by at least one third bit to achieve phase inversion.

[0015] In another exemplary embodiment, each IMPI in the set of IMPIs comprises a first branch and a second branch; wherein the first branch and the second branch are configured to be controlled by the phase interpolation code so that only one of the first branch and the second branch is enabled for charging an integration capacitor.

[0016] In another exemplary embodiment, the set of IMPIs includes four switchable segments, and the set of IMPIs is configured to change the number of activated branches in the four switchable segments to create a linear phase shift for an integrated signal; and the phased array transmitter system also includes an inverter-based comparator configured to convert the integrated signal, wherein the integrated signal is configured to be converted into an IMPI output signal.

[0017] In another exemplary embodiment, the phased array transmitter system further includes: an inductorless RFLO buffer; and a phase locked loop configured to provide a first RFLO signal to the Div-4 circuit and a second RFLO signal to the RFLO buffer. The RFLO buffer is configured to provide the RFLO signal to a second mixer in each of the four signal paths.

[0018] In another exemplary embodiment, the first RFLO signal and the second RFLO signal are millimeter wave RFLO signals.

[0019] In another exemplary embodiment, a phase locked loop includes a passive proportional path and an active integral path.

[0020] In another exemplary embodiment, the phase-locked loop further includes a voltage controlled oscillator (VCO); and the active integration path is configured to bridge an offset between a target frequency and a free-running frequency of the VCO.

[0021] In another exemplary embodiment, the passive proportional path includes a loop filter capacitor.

[0022] In another exemplary embodiment, the phase locked loop further includes an inductorless true single phase circuit (TSPC) Div-4 circuit and a sub-sampling (SS) buffer.

[0023] In another exemplary embodiment, the phase shifter of each of the four signal paths includes a phase multiplexer and an intermediate frequency local oscillator (IFLO) phase interpolation based phase shifter.

[0024] In another exemplary embodiment, the VGA of each of the four signal paths is a transadmittance-transimpedance (TAS-TIS) VGA.

[0025] In another exemplary embodiment, a TAS-TIS VGA includes a Q-VGA transadmittance stage, an I-VGA transadmittance stage, and a transimpedance stage.

[0026] In another exemplary embodiment, the Q-VGA transadmittance stage and the I-VGA transadmittance stage are configured to convert the I-IF signal and the Q-IF signal into current signals; and the TAS-TIS VGA is configured to combine the current signals.

[0027] In another exemplary embodiment, the Q-VGA transadmittance stage and the I-VGA transadmittance stage include Gilbert cell structures.

[0028] In another exemplary embodiment, the present invention provides a phased array transmitter system. The phased array transmitter system includes: a phase shifter configured to generate a phase-shifted signal; a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal; a variable gain amplifier (VGA) configured to perform phase-invariant gain-controlled amplification on the first mixed signal; a second mixer configured to mix the amplified first mixed signal with a radio frequency local oscillator (RFLO) signal to generate a radio frequency (RF) signal; and a power amplifier configured to amplify the RF signal and feed the amplified RF signal to an antenna.

[0029] In another exemplary embodiment, the present invention provides a method for operating a phased array transmitter system. The method includes: generating an output frequency by a phase-locked loop; dividing the output frequency to generate a multi-phase signal; distributing the multi-phase signal to a plurality of signal paths; and

[0030] On each of the plurality of signal paths: phase shifting a corresponding signal; mixing the corresponding signal with a baseband signal; amplifying the mixed signal; mixing the amplified mixed signal with a radio frequency local oscillator (RFLO) signal to generate a radio frequency (RF) signal; amplifying the RF signal; and sending the RF signal to an antenna. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1A to 1D An example embodiment of an IFLO architecture is depicted according to an example embodiment of the present disclosure.

[0032] Figure 2 Depicted are examples of IFLO generation, distribution, and implementation of a 7-bit IFLO phase shifter according to example embodiments of the present disclosure.

[0033] Figure 3 An example block diagram of an integral mode phase interpolator (IMPI) consisting of 16 equally weighted tiles according to an example embodiment of the present disclosure is shown.

[0034] Figure 4 An example of a transadmittance-transimpedance (TAS-TIS) variable gain amplifier (VGA) according to an example embodiment of the present disclosure is shown.

[0035] Figure 5 An exemplary system diagram of a DP-SSPLL according to an example embodiment of the present disclosure is shown.

[0036] Figure 6 Depicted is an example circuit diagram of a true single phase circuit (TSPC) divide-by-4 circuit according to an example embodiment of the present disclosure.

[0037] Figure 7An example of an RF mixer according to an example embodiment of the present disclosure is depicted.

[0038] Figure 8 A schematic flowchart of a phased array transmission method according to an embodiment of the present application is described. DETAILED DESCRIPTION

[0039] Example embodiments of the present disclosure include a 2×2 phased array transmitter design utilizing an intermediate frequency local oscillator phase shift (IFLO PS) architecture. The IFLO PS architecture achieves highly linear and gain-invariant phase shifting and phase-invariant gain control by integrating a phase interpolator-based IFLO phase shifter and a transadmittance-transimpedance (TAS-TIS) intermediate frequency (IF) variable gain amplifier into the IF path. Thus, these example embodiments of the present disclosure can ensure full orthogonality between phase shifting and gain control while also providing superior area and power efficiency compared to conventional approaches.

[0040] Various example embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, the embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein; on the contrary, these example embodiments are provided for illustrative purposes.

[0041] Unless otherwise indicated, the term "or" is used herein in an alternative and conjunctive sense. The terms "illustrative" and "exemplary" are used as examples without a preferred indication. The same reference numerals refer to the same elements throughout.

[0042] Figure 1A An example embodiment of an IFLO architecture is shown. The IFLO phase shifting scheme in the depicted architecture includes an IFLO phase shifter 102, an IF mixer 104, an IF VGA 106, a current source-free RF mixer 108, a power amplifier 110, a divide-by-4 (Div-4) circuit 112, an on-chip phase-locked loop (PLL) 114, and an inductor-free RFLO buffer 116.

[0043] The IFLO phase shift architecture adopts a sliding IF design. The local oscillator includes an intermediate frequency IFLO and a millimeter wave frequency RFLO. The RFLO is generated from an on-chip phase-locked loop 114.

[0044] For the target final output RF frequency of f_rf, the PLL frequency is set to N / (N+1)f_rf, where N can be any integer greater than 1. In an exemplary embodiment, N=4 is selected because a 4-divide-by-four circuit can be designed with lower complexity. The IFLO is then obtained by dividing the PLL output by N, resulting in an IFLO frequency of 1 / (N+1)f_rf. During this division process, 2N equally spaced IFLO phases can be obtained, where the phase interval is 360 / (2N) degrees. Phase shifting and variable gain control functions are then implemented in the IF path to obtain optimal accuracy, power efficiency, and area efficiency. The RF mixer 108 multiplexes the IF signal (at a frequency of 1 / (N+1)f_rf) and the RFLO signal (at a frequency of N / (N+1)f_rf) to produce the desired RF signal at the frequency of f_rf.

[0045] like Figure 1A As shown in the example of , the DIV-4 circuit can be used to divide the 22.4GHz RFLO by 4 to 5.6GHz, and this divided output is used as the IFLO. During this 4-divide process, eight equally spaced phases with 45 degree intervals are generated. Next, the IFLO phase shifter (PS) 102 based on Mux & Phase Interpolation (PI) is used to perform the IFLO phase shift function. The Mux & PI-based IFLO PS 102 may include an 8-to-2 phase multiplexer (Mux) that selects eight phases of adjacent pairs generated from the IFLO divider. This selection process provides a coarse phase shift with a resolution of 45 degrees. The two selected phases are then sent to the PI to perform fine phase shifting.

[0046] The phase-shifted IFLO is then mixed with the baseband signal (BB) to obtain the IF signal. The following trans-admittance trans-impedance variable gain amplifier (TAS-TIS VGA) 106 provides gain-controlled amplification to the IF signal. The amplified IF signal is distributed to the RF mixer 108 and mixed with the RFLO to achieve the second stage of frequency up-conversion.

[0047] The second stage frequency up-conversion produces the final RF signal, which is then boosted by a power amplifier (PA) 110 and fed to the off-chip antenna. The RF signal is then radiated from the antenna into free space.

[0048] Figure 1A The example embodiment shown in the invention provides superior power and area efficiency using a simple millimeter wave (mmWave) path and an inductor-free RFLO buffer. In addition, the IFLO PS provides power efficient, highly linear and gain-invariant phase shifting, while the TAS-TIS IF VGA provides phase-invariant gain control.

[0049] Compared with traditional methods, Figure 1A The example embodiments shown in provide better power efficiency, better (smaller) area usage, better phase control accuracy, and better gain control accuracy. In addition, Figure 1A The example embodiments shown provide complete orthogonality between phase and gain control (there is almost no interaction between phase shift and gain control, while all conventional approaches have severe interaction or gain control that affects phase shift), good phase linearity, and an on-chip frequency synthesizer solution (none of the conventional approaches provide this).

[0050] Figure 1B to Figure 1C Another example embodiment of the IFLO architecture is shown on a prototype chip in a 40 nm CMOS process. Figure 1B This is the block diagram of the chip. Figure 1C The area occupied by the chip is shown.

[0051] like Figure 1B As depicted, the IFLO phase-shift based phased array transmitter chip includes a PLL with harmonic mixing injection locked frequency divide-by-4 (ILFD) for global IF & RFLO generation, four IF paths, and four RF paths. A dual-path subsampling PLL architecture was chosen for 22.4 GHz RFLO generation due to its small loop filter capacitors, which enables a compact layout suitable for on-chip integration.

[0052] A single resonant mode global buffer and four inductor-free local buffers are used to effectively distribute the RFLO to the four RF paths. The ILFD is also used to divide the RFLO by 4 to generate eight 45-degree equally spaced IFLO phases (PH-0°, 45°, ..., 315°). In each of the four IF paths, an 8-to-2 phase multiplexer (mux) followed by an integral mode phase interpolator (IMPI) forms a highly linear phase shifter.

[0053] The IFLO phase shifter performs interpolation between the eight phases from the ILFD to generate the IFLO-I signal and the IFLO-Q signal, and then uses a double-balanced passive mixer to mix the IFLO-I signal and the IFLO-Q signal with the I baseband signal and the Q baseband signal to generate the IF-I signal and the IF-Q signal. The trans-admittance trans-impedance (TAS-TIS) IF VGA first amplifies the IF-I signal and the IF-Q signal, then combines them, and finally distributes the combined IF signal to the RF mixer. In the RF path, the 5.6 GHz IF is up-converted to a 28 GHz RF signal. The RF signal is then amplified by a power amplifier (PA) and sent to the off-chip antenna.

[0054] like Figure 1C As shown, in an exemplary embodiment, the area occupied by the chip may be 2.1×1.3 mm2 , which is smaller than traditional architectures (e.g., some traditional architectures have 15.8×10.5 mm 2 , 3.2×2.3mm 2 , 4×3mm 2 、5.2×6.6mm 2 、5.2×6.6mm 2 size).

[0055] Figure 1D yes Figure 1B Another illustration of the IFLO architecture. Figure 1D Depicted, all four IF and RF paths of a 2×2 phased array transmitter and the IF / RF LO generation block are shown.

[0056] A low jitter RFLO cantered at 22.4 GHz is generated from a dual-path sub-sampling phase-locked loop (DP-SSPLL) and then distributed to four RF paths with inductor-free buffers. Driven by the RFLO, a harmonic mixing injection-locked divider (ILFD) produces an 8-phase (8-PH) 5.6 GHz IFLO, which is delivered to four IF paths using an inversion-based buffer. In each IF path, a 7-phase shifter (PS) is implemented with 3-bit phase selection and 4-bit integral mode phase interpolation (IMPI). Due to the 8-PH IFLO, IMPI achieves better accuracy than traditional I / Q phase interpolation by utilizing X and Y input phases spaced 45 degrees apart. The PS generates the I IFLO signal and the Q IFLO signal, which are then mixed with the I and Q baseband input data using a pair of double-balanced passive mixers.

[0057] Compared to the conventional method of using an RF VGA that consumes large area and power, a TAS-TIS VGA that supports four functions is provided in the exemplary embodiment of the present disclosure. The four functions include: (1) I IF signal and Q IF signal combination; (2) 20 dB phase-invariant gain control range; (3) 8 dB maximum gain; and (4) 7 dBm P about 50 ohms. O1dB . TAS-TISVGA is capable of driving a capacitive load of 120fF with a 3dB bandwidth of more than 8GHz. Therefore, VGA 110 can support chip-level IF signal distribution to four RF mixers 120 located in the RF path. In the RF path, the RF mixer 120 without a current source multiplexes the RFLO signal and the IF signal to generate an RF signal, which is then amplified by a power amplifier (PA) and sent out of the chip. The coupling between the RF mixer 120, the PA, and the chip pad is implemented using a transformer (XFMR).

[0058] Figure 2 Depicted are examples of IFLO generation, distribution, and implementation of a 7-bit IFLO phase shifter according to example embodiments of the present disclosure.

[0059] The ring oscillator-based harmonic mixing injection locked frequency divide-by-4 circuit (ILFDiv-4) 202 generates an 8-phase IFLO (from 0°, 45°, 90° to 315°) including 4 pairs of differential signals. Initially, the 4 pairs of differential signals are arranged in the order of 0°, 180°, 45°, 225°, 90°, 270°, 135°, 315°, which may make subsequent phase interpolation difficult to achieve. To solve this problem, the differential signals are first rearranged by the symmetrical 8-PH IFLO distribution circuit 204 to the order of 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°. This new order allows the signals to be symmetrically distributed to the IFLO phase shifter (PS) 210, thereby facilitating the phase interpolation process.

[0060] The IFLO PS210 has a 7-bit resolution, where the most significant bit (Bit-6) controls the cross-connected switches to achieve 180-degree phase reversal. The subsequent bits Bit-4 to Bit-5 control sw1 to sw4 to select a set of 4 consecutive phases from the 8 available phases. For illustration, when Bit-4:Bit-5 are set to 01, sw2 is activated, causing PH-45, PH-90, PH-135, and PH-180 to switch to output IX, IY, QX, and QY, respectively. The four selected phases are converted into differential signals and then sent to four integral mode phase interpolators (IMPI) to generate two pairs of orthogonal differential IFLO signals, namely I-IFLO PN and Q-IFLO PN .

[0061] Figure 3 An example block diagram of an IMPI consisting of 16 equally weighted slices according to an example embodiment of the present disclosure is shown.

[0062] IMPI can be classified into five segments, including one fixed segment and four binary ratio switchable segments, such as Figure 3 Each segment includes an X branch 301 and a Y branch 302. Under the control of the phase interpolation code (Bit-0 to Bit-3), in each segment, only one of the X branch or the Y branch is connected to C INT By changing the number of activated X branches and Y branches in the four switchable segments, the integrated signal V INT A linear phase shift is produced in V using an inverter-based comparator 311 with rail-to-rail swing. INT Convert to IMPI OUT Then, IMPI OUTIt is converted into a differential IFLO signal to drive the next IF passive mixer.

[0063] Figure 4 An example of TAS-TIS VGA according to an example embodiment of the present disclosure is shown.

[0064] The trans-admittance-trans-impedance (TAS-TIS) IF VGA is responsible for phase-invariant gain control, I / QIF signal combination, and chip-level IF distribution. The I-IF and Q-IF signals from the previous passive mixer are converted into current signals by the first-stage TAS and combined by directly connecting the two TAS output nodes. The Gilbert cell structure is implemented in the TAS to achieve variable gain control. The second-stage TIS presents a low impedance (R shunt / Gain TIS ), and achieves a wide bandwidth for the node. Due to the wide bandwidth, the nonlinear parasitic capacitance changes in the Gilbert cell during the gain tuning process cause minimal phase changes, resulting in phase-invariant gain control. The large transimpedance (R in TIS) of about 1 kΩ shunt ) contributes to large VGA peak gain. In addition, TIS exhibits a value equal to 1 / (gm P +gm N ) to support a wide overall VGA bandwidth. In a post-layout simulation, it is shown that Figure 4 The exemplary implementation of the TAS-TIS IF VGA depicted in achieves a 20 dB gain tuning range with 0.38° RMS VGA induced phase error. The wide bandwidth of the VGA also facilitates chip-level IF signal distribution from the IF path to the RF mixer.

[0065] Figure 4 The illustrative TAS-TIS VGA depicted in FIG. 1 ensures several functions in the overall system, such as phase-invariant gain control, wide-range gain tuning, proper PO1dB, chip-level distribution of IF signals, and combination of I / Q IF signals. The conventional method of using a pair of Gilbert cells to sum the I and Q signals of the I / Q combination suffers from both gain-bandwidth and gain-linearity tradeoffs due to the use of resistive loads. Therefore, it cannot support sufficient gain, PO1dB, and a large capacitive load from the IF distribution. On the other hand, Figure 4 The TAS-TIS VGA provides all of the above functions through the following three features:

[0066] The first characteristic: VGA voltage gain is determined by TAS transconductance (Gm ITAS and Gm QTAS ) and TIS shunt impedance (R shunt), while the bandwidth is determined by the output parasitic capacitance and the TIS output impedance (gm P and gm N ) is determined by . This allows independent optimization of gain and bandwidth.

[0067] Second feature: Since the I IF signal and the Q IF signal are converted into current signals by TAS, the I-VGA-TAS output node and the Q-VGA-TAS output node can be directly connected to realize current domain I&Q combination. Since it is not affected by the voltage headroom limitation, this method significantly improves linearity.

[0068] The third feature: The Gilbert topology used in TAS achieves variable gain control by adjusting the gate voltage of the bias current source (VB+ and VB-). The wide bandwidth of the VGA allows it to maintain negligible phase variation within the 18dB gain control range. In addition, it can facilitate the distribution of IF signals from the VGA 110 to the RF mixer 120 and accommodate the large parasitic capacitance associated with such long-distance distribution.

[0069] Figure 5 An exemplary system diagram of a DP-SSPLL according to an example embodiment of the present disclosure is shown.

[0070] The DPSS PLL architecture includes a fully passive proportional path 501, an active integral path 502, a class C voltage-controlled oscillator (VCO) 503, and a true single-phase circuit (TSPC) 4-division (DIV-4) circuit 504 with an SS buffer 505. The proportional path 501 dominates the entire loop dynamics. It is used to track phase noise and determine the PLL bandwidth. In order to achieve gain and bandwidth allocation, the passive charge domain gain control circuit can achieve a wide range of bandwidth adjustment with negligible phase noise contribution and power consumption. On the other hand, the integral path 502 bridges the offset between the target frequency and the free-running frequency of the VCO. It includes an SSCP and CRC loop filter with small transconductance (Gm). Reducing Gm in the integral path 502 has two purposes: minimizing bandwidth to prevent additional phase noise contribution, and avoiding large integral capacitors (C9, C 10 ) needs. For the pre-scaling and VCO buffering functions, an inductor-free true single-phase clock type divide-by-4 (DIV-4) circuit 504 is used. Compared with the resonant mode buffer, the TSPC divider 504 is not only power efficient, but also area efficient. After the TSPC DIV-4 504, a SSBUF 505 is used to drive the SSPD through an AC coupling network. The AC coupling is used to establish the appropriate bias voltage to ensure that the SSCP in the integration path 502 has sufficient overdrive voltage.

[0071] Figure 5The dual path architecture depicted in the example embodiment, including a differential proportional path 501 and a single-ended integral path 502, provides the following:

[0072] First, the high gain of the integral path 502 ensures that the voltage offset (V PROP_P -V PROP_N ) approaches zero when the lock state is reached. Therefore, the value stored in the loop filter C LFP With C LFN The charge on includes a common DC component and a differential AC component, and the polarities of the two are opposite.

[0073] Second, considering reasonable reference phase noise and VCO power consumption, the passive proportional path 501 alone provides a maximum loop bandwidth of about 8 MHz, which exceeds the optimal loop bandwidth in most cases. In order to optimize the bandwidth and achieve a balance between in-band PN and out-of-band PN, a controllable charge neutralization can be used to partially neutralize the P-side and N-side loop filter capacitors C LFP and C LFN AC charge stored on the PROP_P With V PROP_N The DC voltage of the MOSFET is the same, so charge neutralization only affects the AC signal, allowing gain adjustment without causing false lock.

[0074] To achieve controllable charge neutralization, a 4-bit capacitor bank is used for the loop filter capacitor on the proportional path 501. The capacitance values ​​range from 8×C U , 4×C U , 2×C U To 1×C U , where the most significant bit (MSB), C LFP,N <3> , fixed to the P side and N side. The remaining three bits C LFP,N <2:0> redistributes the charge to the opposite side. The capacitance (charge) involved in the neutralization process is controlled by the 3-bit switch SW SEL <2:0> control. Ensuring proper capacitance matching in the 4-bit capacitor bank requires a sufficiently large total loop filter value. However, the conventional switched capacitor I-type configuration cannot meet this requirement due to the tight phase margin. To overcome this problem, a dual-branch SSPD is utilized to accommodate large loop filter capacitance without compromising phase margin.

[0075] in other words, Figure 5 The DP-SSPLL consists of a passive proportional path (P path) and an active integral path (I path). Although the traditional passive PLL loop has low phase noise, it may suffer from phase margin-bandwidth tradeoff and cannot achieve loop gain tuning. To address these limitations, the P path is optimized by using a sample-and-hold switch (SWSH3,4 ), loop filter switch (SW LF3,4 ) and the sampling capacitor C 3～5 Introducing an in-band zero. This design ensures sufficient phase margin even at large loop bandwidths. In addition, the loop filter capacitor C 10 It consists of three sheets with a capacitance ratio of 4:2:1. By controlling the charge sharing switch (SW CS ), C9 and C 10 The sampled charge on the P path can be shared with the opposite side loop filter capacitors (C8 and C7), allowing adjustable gain of the P path. The I path is responsible for enhancing the SS phase detector gain of the voltage controlled oscillator and attenuating flicker noise in its vicinity.

[0076] In the feedback path, an inductor-less true single-phase circuit (TSPC) divider is employed to achieve power and area efficient frequency division.

[0077] Figure 6 Depicted is an example circuit diagram of a TSPC divide-by-4 circuit according to an example embodiment of the present disclosure.

[0078] The TSPC DIV-4 circuit includes two proportional TSPC DFFs and an inverter. TSPC DFF1 601 receives an input signal from node A and produces an inverted output signal at node D during each falling edge of CK. TSPC DFF2 602, together with the inverter, forms a latch that holds the signal level on node D for one input clock cycle. As a result, a complete output cycle on DIVOUT requires four input clock cycles, achieving a divide-by-4 operation. The input clock is derived directly from the VCO.

[0079] In one exemplary implementation, the TSPC frequency divider consists of two TSPC D flip-flops and an inverter, and is capable of operating at speeds up to 27 GHz at a slow-slow corner while consuming only 1.4 mW of power.

[0080] Figure 7 An example of an RF mixer according to an example embodiment of the present disclosure is depicted.

[0081] The RF mixer circuit includes a bias circuit 701 ( Figure 7 ) and the Gilbert mixer core 702 ( Figure 7The input MOSFETs M1 and M2 of the Gilbert mixer core 702 serve two purposes. First, the input MOSFETs M1 and M2 accept the input IF signal. Second, the input MOSFETs M1 and M2 control the bias current of the Gilbert mixer core circuit 702. The IF signal from the previous IF VGA stage (IF VGA OUT + / -) is fed to M1 and M2 through AC coupling capacitors. The bias voltage level is generated by the bias circuit and then enters M1 and M2 through the RCR network. The RFLO+ / - signal has a rail-to-rail swing, which can fully saturate the switching MOSFETs M3 / 4 and M5 / 6. This allows the RFLO signal to up-convert the IF signal to the desired RF frequency. Second, the output RF signal is coupled to the next stage power amplifier (PA) through a transformer (XFMR). The XFMR also has the added benefit of resonating with the mixer output parasitic capacitance to enhance power gain.

[0082] In other words, since there is no RF VGA between the RF mixer and the PA, the RF mixer should obtain sufficient gain and wide PO1dB. To solve this problem, the RF mixer does not use a current source, but uses the IF input MOSFET as a pair of current mirrors with an RCR bias network. This improves the dynamic range of the mixer output by about 0.2V. To further increase the PO1dB, a transformer (XFMR) is used to match the PA input to the mixer output impedance. The XFMR also has the added benefit of resonating with the mixer output parasitic capacitance to enhance the power gain.

[0083] Figure 8 Depicted is a flow chart of a phased array transmission method according to an example embodiment of the present disclosure.

[0084] In step 801 , assuming the target RF frequency is f_rf, the on-chip PLL generates an output frequency of N / (N+1)f_rf, where N can be any integer greater than 1. In an exemplary embodiment, the value of N is 4.

[0085] At step 803, the PLL output is divided by N to generate a multi-phase IFLO signal with a frequency of 1 / (N+1)f_rf. In the example of N=4, a set of 8 IFLO phases can be obtained.

[0086] The IFLO signal is distributed and fed to the IFLO PS for phase shifting at step 805. In an exemplary embodiment, an 8-PH IFLO signal is distributed and fed to a subsequent 7-bit IFLO PS.

[0087] In step 807, the IF mixer mixes the phase-shifted IFLO signal with the baseband signal (BB).

[0088] At step 809, the signal enters the TAS-TIS IF VGA for IF signal gain control and chip-level distribution.

[0089] At step 811, the current-free RF mixer mixes the amplified IF signal with the RFLO signal to generate an RF signal (at f_rf).

[0090] In step 813, the power amplifier amplifies the RF signal and sends it outside the chip.

[0091] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference was individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0092] The use of the terms "a and an" and "the" and "at least one" and similar indicators in the context of describing the present invention (especially in the context of the appended claims) should be interpreted as covering the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein or clearly contradicted by the context, the use of the term "at least one" followed by a list of one or more items (e.g., "at least one of A and B") should be understood to refer to one item (A or B) selected from the listed items or any combination of two or more of the listed items (A and B). The terms "comprising and including", "having" and "comprising" should be interpreted as open terms (i.e., meaning "including but not limited to") unless otherwise indicated herein. Unless otherwise indicated herein, the recitation of numerical ranges herein is intended to be used only as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Unless otherwise required, the use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the invention and does not impose limitations on the scope of the invention. No language in the specification should be construed as indicating any non-claimed element is essential to the practice of the invention.

[0093] Preferred embodiments of the present invention are described herein, including the best mode of implementing the present invention known to the inventor. After reading the foregoing description, variations of those preferred embodiments will be apparent to those of ordinary skill in the art. The inventor expects that the skilled person will appropriately adopt these variations, and the inventor intends that the present invention be implemented in a manner different from that specifically described herein. Therefore, the present invention includes all modifications and equivalents of the subject matter described in the appended claims as permitted by applicable law. In addition, the present invention includes any combination of the above-mentioned elements in all possible variations thereof, unless otherwise stated herein or clearly contradictory to the context.

Claims

1. A phased array transmitter system, comprising: A plurality of signal paths, wherein each of the signal paths comprises: a phase shifter configured to generate a phase-shifted signal; a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal; a variable gain amplifier configured to perform phase-invariant gain-controlled amplification on the first mixed signal; a second mixer configured to mix the amplified first mixed signal with a radio frequency local oscillator signal to generate a radio frequency signal; and A power amplifier is configured to amplify the radio frequency signal and feed the amplified radio frequency signal to the antenna.

2. The phased array transmitter system according to claim 1, wherein: The plurality of signal paths includes four signal paths, and wherein the phase shifter of each of the four signal paths includes an 8-2 phase multiplexer.

3. The phased array transmitter system of claim 1 , further comprising: A divide-by-4 circuit is configured to generate an 8-phase intermediate frequency local oscillator signal.

4. The phased array transmitter system according to claim 3, wherein: The phase shifter of each of the four signal paths takes as input a pair of 8-phase IF local oscillator signals generated by the divide-by-4 circuit.

5. The phased array transmitter system of claim 4, wherein: The 8-phase IF local oscillator signals are equally spaced at 45 degree intervals between adjacent signals.

6. The phased array transmitter system of claim 5, further comprising: An 8-phase intermediate frequency local oscillator signal distribution circuit is configured to reorder the 8-phase intermediate frequency local oscillator signals to be input to the phase shifters of the plurality of signal paths.

7. The phased array transmitter system of claim 6, wherein: The phase shifter includes a first set of switches, a set of integral mode phase interpolators, and a second set of switches.

8. The phased array transmitter system of claim 7, wherein: The first set of switches is configured to be controlled by a first plurality of bits to select four consecutive phases from eight available phases; wherein the set of integration-mode phase interpolators are configured to be controlled by a second plurality of bits corresponding to a phase interpolation code; and Wherein, the second set of switches is configured to be controlled by at least one third bit to achieve phase inversion.

9. The phased array transmitter system of claim 8, wherein: Each integration mode phase interpolator in the set of integration mode phase interpolators includes a first branch and a second branch; The first branch and the second branch are configured to be controlled by the phase interpolation code so that only one of the first branch and the second branch is enabled for charging the integration capacitor.

10. The phased array transmitter system of claim 9, wherein: The set of integration-mode phase interpolators comprises four switchable segments, and wherein the set of integration-mode phase interpolators is configured to vary the number of activated branches in the four switchable segments to create a linear phase shift for the integrated signal; and The phased array transmitter system further comprises an inverter-based comparator configured to convert the integrated signal, wherein the integrated signal is configured to be converted into an integration mode phase interpolator output signal.

11. The phased array transmitter system of claim 3, further comprising: Inductorless RF local oscillator buffer; as well as a phase locked loop configured to provide a first radio frequency local oscillator signal to the divide-by-4 circuit and to provide a second radio frequency local oscillator signal to the radio frequency local oscillator buffer; Wherein, the RF local oscillator buffer is configured to provide the RF local oscillator signal to the second mixer of each of the four signal paths.

12. The phased array transmitter system of claim 11, wherein: The first radio frequency local oscillator signal and the second radio frequency local oscillator signal are millimeter wave radio frequency local oscillator signals.

13. The phased array transmitter system of claim 11, wherein: The phase-locked loop includes a passive proportional path and an active integral path.

14. The phased array transmitter system of claim 13, wherein: The phase-locked loop also includes a voltage-controlled oscillator; and The active integrator path is configured to bridge an offset between a target frequency and a free-running frequency of the voltage-controlled oscillator.

15. The phased array transmitter system of claim 11, wherein: The passive proportional path includes a loop filter capacitor.

16. The phased array transmitter system of claim 11, wherein: The phase-locked loop also includes an inductor-free true single-phase circuit 4-frequency division circuit and a sub-sampling buffer.

17. The phased array transmitter system of claim 1, wherein: The phase shifter of each of the four signal paths includes a phase multiplexer and a phase shifter based on intermediate frequency local oscillator phase interpolation.

18. The phased array transmitter system of claim 1, wherein: The variable gain amplifier of each of the four signal paths is a transadmittance-transimpedance variable gain amplifier.

19. The phased array transmitter system of claim 18, wherein: The transadmittance and transimpedance variable gain amplifier comprises a Q variable gain amplifier transadmittance stage, an I variable gain amplifier transadmittance stage and a transimpedance stage.

20. The phased array transmitter system of claim 19, wherein: The Q variable gain amplifier transadmittance stage and the I variable gain amplifier transadmittance stage are configured to convert the I intermediate frequency signal and the Q intermediate frequency signal into current signals; as well as Wherein, the transadmittance-transimpedance variable gain amplifier is configured to combine the current signals.

21. The phased array transmitter system of claim 19, wherein: The Q variable gain amplifier transadmittance stage and the I variable gain amplifier transadmittance stage include Gilbert cell structures.

22. A phased array transmitter system comprising: a phase shifter configured to generate a phase-shifted signal; a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal; a variable gain amplifier configured to perform phase-invariant gain-controlled amplification on the first mixed signal; a second mixer configured to mix the amplified first mixed signal with a radio frequency local oscillator signal to generate a radio frequency signal; as well as A power amplifier is configured to amplify the radio frequency signal and feed the amplified radio frequency signal to the antenna.

23. A method for operating a phased array transmitter system, comprising: The output frequency is generated by a phase-locked loop; dividing the output frequency to generate a multi-phase signal; distributing the multiphase signal to a plurality of signal paths; as well as On each of the plurality of signal paths: Phase shifting of corresponding signals; mixing the corresponding signal with a baseband signal; amplifying the mixed signal; mixing the amplified mixed signal with a radio frequency local oscillator signal to generate a radio frequency signal; amplifying the radio frequency signal; as well as The radio frequency signal is sent to an antenna.

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