Linear speed current testing methods, apparatus, electronic equipment and readable storage media

Abstract

The embodiments of the present application provide a line-speed streaming test method, device, electronic device and readable storage medium, which relate to the field of communication technology. The method is applied to a device under test that is connected to a test device for communication, and the method includes: obtaining a target frequency deviation adjustment amount; adjusting the frequency deviation of a first initial reference clock of the device under test obtained based on a local first clock according to the target frequency deviation adjustment amount to obtain a first reference clock, and the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device; and performing a line-speed streaming test based on the first reference clock. In this way, by adjusting the frequency deviation range of the reference clock of the device under test based on the target frequency deviation adjustment amount, so that the minimum value of the frequency deviation range of the device under test is not less than the maximum value of the frequency deviation range of the test device, the line-speed streaming packet loss caused by the clock frequency deviation of the device under test being less than the clock frequency deviation of the test device is avoided.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a line speed flow test method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] Currently, the network device under test is typically connected to a testing instrument, and then flow testing is performed on the network device. Network devices may exhibit frequency offset, which can cause the network device's actual reference clock frequency to be lower than the testing instrument's reference clock frequency. In other words, the network device's data processing frequency is lower than the testing instrument's data processing frequency. Under these circumstances, continuous line-rate flow testing will accumulate over time, causing the amount of unprocessed data to gradually increase until it reaches the network device's data buffer limit and overflows, leading to packet loss and consequently inaccurate flow test results. Summary of the Invention

[0003] This application provides a line-speed stream testing method, apparatus, electronic device, and readable storage medium. It adjusts the frequency offset range of the reference clock of the device under test based on the target frequency offset adjustment amount, so that the minimum value of the frequency offset range of the device under test is not less than the maximum value of the frequency offset range of the test device, thereby avoiding packet loss in line-speed stream testing caused by the clock frequency offset of the device under test being less than the clock frequency offset of the test device.

[0004] The embodiments of this application can be implemented as follows:

[0005] In a first aspect, embodiments of this application provide a line-speed current testing method, applied to a device under test that is communicatively connected to a testing device, the method comprising:

[0006] Obtain the target frequency offset adjustment;

[0007] The frequency offset of the first initial reference clock obtained by the device under test based on the local first clock is adjusted according to the target frequency offset adjustment amount to obtain the first reference clock, wherein the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test device.

[0008] Perform line-rate flow testing based on the first reference clock.

[0009] Secondly, embodiments of this application provide a line-speed current testing device, applied to a device under test that is communicatively connected to a testing device, the device comprising:

[0010] The processing module is used to obtain the target frequency offset adjustment amount;

[0011] The processing module is further configured to adjust the frequency offset of the first initial reference clock obtained by the device under test based on the local first clock according to the target frequency offset adjustment amount, so as to obtain the first reference clock, wherein the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test device.

[0012] The test module is used to perform line-rate current testing based on the first reference clock.

[0013] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the line-rate flow testing method described in the foregoing embodiments.

[0014] Fourthly, embodiments of this application provide a readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the line-rate flow testing method as described in the foregoing embodiments.

[0015] The line-rate stream testing method, apparatus, electronic device, and readable storage medium provided in this application embodiment allow the testing device to obtain a target frequency offset adjustment amount and adjust the frequency offset of a first initial reference clock obtained from a local first clock of the device under test (DUT) according to the target frequency offset adjustment amount to obtain a first reference clock. Line-rate stream testing is then performed based on the first reference clock, wherein the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the testing device. Thus, by adjusting the frequency offset range of the reference clock of the DUT based on the target frequency offset adjustment amount, the minimum value of the frequency offset range of the DUT is not less than the maximum value of the frequency offset range of the testing device, thereby avoiding packet loss during line-rate stream testing due to the clock frequency offset of the DUT being less than that of the testing device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A block diagram illustrating an electronic device provided in an embodiment of this application;

[0018] Figure 2 This is one of the flowcharts illustrating the line-speed flow testing method provided in the embodiments of this application;

[0019] Figure 3 A second schematic flowchart of the line-speed flow testing method provided in the embodiments of this application;

[0020] Figure 4 A block diagram of the testing system provided in the embodiments of this application;

[0021] Figure 5 This is one of the block diagrams of the line speed flow testing device provided in the embodiments of this application;

[0022] Figure 6 This is a second block diagram of the line speed flow testing device provided in the embodiments of this application.

[0023] Icons: 100 - Electronic device; 110 - Memory; 120 - Processor; 130 - Communication unit; 200 - Linear flow test device; 210 - Detection module; 220 - Processing module; 230 - Test module. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0026] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] Please refer to Figure 1 , Figure 1 This is a block diagram of an electronic device 100 provided in an embodiment of this application. The electronic device 100 may be, but is not limited to, a switch, etc. The electronic device 100 is a device that needs to undergo line-speed current testing, i.e., the device under test. The electronic device 100 is communicatively connected to a testing device to perform line-speed current testing. The testing device may be a testing instrument. The electronic device 100 may include a memory 110, a processor 120, and a communication unit 130. The memory 110, processor 120, and communication unit 130 are electrically connected directly or indirectly to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0029] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0030] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, the memory 110 stores a line-rate current testing device 200, which includes at least one software functional module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running the software programs and modules stored in the memory 110, such as the line-rate current testing device 200 in this embodiment, thereby implementing the line-rate current testing method in this embodiment.

[0031] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through the network, and to send and receive data through the network.

[0032] It should be understood that, Figure 1 The structure shown is only a schematic diagram of the electronic device 100. The electronic device 100 may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof. It is worth noting that... Figure 1 The components shown can be implemented in hardware, software, or a combination thereof. In other words, the implementation of the flow table resource management method in the above embodiments is not limited to the processor reading and running purely computer-readable program code from memory; it can also be implemented using hardware or logic devices.

[0033] It should be understood here that improvements to a technology can be divided into hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) and software improvements (improvements to the methodology). However, with technological advancements, many improvements to the methodology can now be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that an improvement to the methodology cannot be implemented using a hardware entity module. For example, a Programmable Logic Device (PLD) (e.g., a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and Verilog are the most commonly used. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0034] Please refer to Figure 2 , Figure 2This is one of the flowcharts illustrating the line-rate flow testing method provided in this application. The method is applied to the device under test (DUT) that is communicatively connected to the testing equipment. This method can be applied to Ethernet environments with high requirements for upstream and downstream clock synchronization, such as data center networks and industrial networks. The specific flow of the line-rate flow testing method is described in detail below. In this embodiment, the method may include steps S120 to S140.

[0035] Step S120: Obtain the target frequency offset adjustment amount.

[0036] Step S130: Adjust the frequency offset of the first initial reference clock obtained by the device under test based on the local first clock according to the target frequency offset adjustment amount to obtain the first reference clock.

[0037] Step S140: Perform a line-speed current test based on the first reference clock.

[0038] In this embodiment, the local first clock of the device under test can be a crystal oscillator. This first clock can be directly used as the first initial reference clock, or it can be obtained by frequency multiplication, frequency division, or other processing based on the first clock. The frequency offset of the first initial reference clock is the same as the frequency offset of the first clock, thus the frequency offset of the first initial reference clock can be determined. If the target frequency offset adjustment is greater than 0, a target frequency offset adjustment can be determined in any way. For example, a value can be set as the target frequency offset adjustment based on experience.

[0039] When line-speed current testing is required, a target frequency offset adjustment amount can be obtained. Then, for the first initial reference clock, a fixed frequency offset is added based on the target frequency offset adjustment amount to obtain the first reference clock. The specific amount of frequency offset added can be equal to or greater than the target frequency offset adjustment amount, depending on the actual needs. The minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test equipment. After adjustment, line-speed current testing is performed based on this first reference clock.

[0040] In this way, by adjusting the frequency offset range of the reference clock of the device under test based on the target frequency offset adjustment amount, the minimum value of the frequency offset range of the device under test is not less than the maximum value of the frequency offset range of the test device, thereby avoiding the situation of line speed packet loss caused by the clock frequency offset of the device under test being less than the clock frequency offset of the test device.

[0041] Devices that support synchronous Ethernet can recover the clock signal from the upstream device and use it as a reference clock for their own use, ultimately achieving the goal of being on the same frequency as the upstream device, thereby achieving frequency consistency of the entire network of devices.

[0042] The solution for implementing synchronous Ethernet in the device primarily relies on the system's clock circuit design. To achieve this, the device's own reference clock requires very high frequency accuracy, needing a deviation range of + / - 4.6 ppm. Because the frequency accuracy of the reference clock is affected by the manufacturing process, it's impossible to guarantee that all deviations are completely consistent. Within the acceptable deviation range, the specific deviation value will be relatively random, potentially exhibiting both positive and negative deviations. Here, ppm stands for parts per million.

[0043] For devices supporting Synchronous Ethernet, when connected to a tester for streaming tests, the tester, as a standard testing device, has very high frequency accuracy, achieving or nearly achieving 0ppm deviation. If the device under test (DUT) enables Synchronous Ethernet, it has no frequency offset relative to the tester. With both sides maintaining consistent frequencies, it can naturally meet the scenario of 100% line-speed streaming. However, if Synchronous Ethernet is not enabled, the reference clock frequency of the DUT will inevitably deviate from the reference clock frequency of the tester. If the deviation is positive, meaning the DUT's data processing frequency will be slightly higher than the tester's, data can be processed promptly, and line-speed streaming will not be a problem. But if the DUT has a negative deviation relative to the tester, and line-speed streaming is performed simultaneously, the DUT's data processing frequency will be lower than the tester's. Over time, the amount of unprocessed data will gradually increase, eventually reaching the upper limit of the DUT's data buffer, causing data overflow and packet loss.

[0044] Therefore, before executing step S120, the device under test can first determine whether it supports synchronous Ethernet. If not, it can directly execute step S120. If it does, then proceed as follows: Figure 3 As shown, before step S120, the method may further include step S110.

[0045] Step S110: Determine whether the synchronous Ethernet function of the device under test is enabled.

[0046] In this embodiment, if the device under test (DUT) supports synchronous Ethernet, when line-speed stream testing is required, the local synchronous Ethernet function can be checked for enablement (i.e., whether it is enabled). If the synchronous Ethernet function of the DUT is disabled, the DUT's clock chip will use the local clock as the reference source. If no processing is performed, the clock frequency offset of the DUT system will depend entirely on the local clock frequency offset (i.e., the system clock frequency offset equals the local clock frequency offset). This means it cannot be determined whether the DUT's frequency offset is greater than or equal to the test device's frequency. In this case, line-speed stream testing may result in probabilistic packet loss. To avoid this situation, if the synchronous Ethernet function of the DUT is determined to be disabled, step S120 can be executed to adjust the frequency offset to obtain a first reference clock, and then line-speed stream testing can be performed based on the first reference clock.

[0047] One possible implementation is to obtain the target frequency offset adjustment amount as follows: A first frequency offset range of the device under test (DUT) and a second frequency offset range of the DUT can be obtained. The first frequency offset range of the DUT is the frequency offset range of the first initial reference clock obtained based on the local first clock of the DUT. Then, the target frequency offset adjustment amount can be determined based on the first frequency offset range and the second frequency offset range. Next, the frequency offset of the first frequency offset range of the first initial reference clock is increased by the second target frequency offset adjustment amount, and the first initial clock after frequency offset adjustment is used as the first reference clock. The frequency offset range obtained by increasing the frequency offset of the first frequency offset range by the target frequency offset adjustment amount is the frequency offset range of the first reference clock, and the minimum value of the frequency offset range of the first reference clock is greater than or equal to the maximum value of the second frequency offset range.

[0048] For example, if the frequency offset range of the reference clock (i.e., the local first clock) of the device under test is +4.6 to -4.6 ppm, then the first frequency offset range can be determined to be +4.6 to -4.6 ppm; if the frequency offset of the test device is 0, then the second frequency offset range is only 0; based on the first frequency offset range of +4.6 to -4.6 ppm and the second frequency offset range of 0, the target frequency offset adjustment amount can be determined to be 10 ppm. After increasing the frequency offset of the first frequency offset range of +4.6 to -4.6 ppm by 10 ppm, a new frequency offset range of 10+4.6 to 10-4.6 can be obtained, that is, the minimum value of the frequency offset range of the first reference clock of the device under test is greater than 0. Therefore, there will be no line speed packet loss caused by the clock frequency offset of the device under test being less than that of the clock frequency offset of the test device.

[0049] Optionally, such as Figure 4As shown, the device under test (DUT) may include a first clock and a clock chip connected to the first clock. The first clock may be a high-precision clock, which may be a crystal oscillator. The DUT may also include a CPU. Upon obtaining the target frequency offset adjustment amount, the CPU can configure the clock chip, activate the DCO (Digital Control Oscillator) function of the clock chip, and then use the DCO function to increase the frequency offset of the first initial reference clock, i.e., increase the frequency offset by a fixed amount, to obtain the first reference clock. The increased frequency offset amount is the target frequency offset adjustment amount.

[0050] For example, the frequency offset range of the high-precision clock of the device under test is +4.6 to -4.6 ppm, that is, the first frequency offset range is +4.6 to -4.6 ppm, and the frequency offset of the test device is 0. Assuming that the target frequency offset is adjusted to 10 ppm, the DCO function of the clock chip is activated to increase the frequency offset by 10 ppm. This can ensure that the frequency offset of the first reference clock provided by the clock chip to the switching chip is in the range of 10-4.6 to 10+4.6 ppm, so that the frequency offset of the device under test is greater than that of the test device, thereby achieving the goal of line-speed packet generation without packet loss.

[0051] In this embodiment, if it is determined that the synchronous Ethernet function of the device under test is enabled, then the following can be executed. Figure 3 Steps S150 to S160 in the process.

[0052] Step S150: Obtain a second reference clock based on the signal of the test device through the synchronous Ethernet function.

[0053] Step S160: Perform a line-speed current test based on the second reference clock.

[0054] In this embodiment, frequency offset adjustment based on the target frequency offset adjustment amount is achieved by activating the DCO function of the clock chip in the device under test (DUT). If the DUT enables synchronous Ethernet, the software senses this need and can first determine whether the DCO function is enabled. If the DCO function is enabled, the CPU can configure the clock chip to disable the DCO function and prevent the output clock frequency offset. Then, the switching chip can be controlled to recover the clock from the data carrying the clock sent by the test device and send the clock to the input of the clock chip. The clock chip locks the clock and uses it as a reference source. It then performs digital frequency multiplication and division on this signal and outputs a reference clock (i.e., the second reference clock) to the switching chip. Line-speed stream testing can then be performed based on this second reference clock. At this time, it is equivalent to the entire reference clock of the DUT coming from the test device, that is, the two sides maintain frequency synchronization. In this case, there will be no packet loss problem when performing line-speed stream testing.

[0055] Optionally, the specific timing for determining whether the synchronous Ethernet function of the device under test (DUT) is enabled can be determined based on actual needs, and this action can be continuously executed. For example, when the DUT starts up, it checks whether the synchronous Ethernet function is enabled. If it is not enabled, the target frequency offset adjustment amount is determined, and then the frequency offset is adjusted based on the target frequency offset adjustment amount through the DCO function. Line-speed streaming tests are then performed based on the first reference clock obtained after the frequency offset adjustment. If it is enabled, the DCO function is disabled, and the synchronous Ethernet function is provided to obtain a second reference clock. Then, line-speed streaming tests are performed based on the second reference clock. If the DUT has enabled the synchronous Ethernet function for a period of time and then disables the synchronous Ethernet function (i.e., it does not obtain clock information from the upstream device), according to the synchronous Ethernet protocol requirements, after the clock is unlocked, it still needs to maintain operation according to the previous state (i.e., the frequency offset of the DUT is greater than or equal to the frequency offset of the test device). At this time, the software senses that the function has been disabled and will actively configure the clock chip to enable the DCO function and enable a fixed frequency offset, thereby ensuring that the frequency offset of the DUT is higher than that of the test device, so that there is no packet loss during streaming tests.

[0056] The line-speed stream testing method provided in this embodiment seamlessly integrates the synchronous Ethernet function of the device with the frequency offset adjustment function of the clock chip. When the synchronous Ethernet function is enabled, line-speed stream testing is performed based on a second reference clock obtained from the synchronous Ethernet function; when the synchronous Ethernet function is disabled, line-speed stream testing is performed based on a first reference clock obtained from the frequency offset adjustment function of the clock chip. This method dynamically adjusts the reference clock output frequency offset of the clock chip according to the real-time requirements of the synchronous Ethernet enable command, that is, it adjusts the input reference clock frequency offset of the switching chip to ensure that the clock frequency offset of the device under test is greater than or equal to the clock frequency offset of the device under test. In this way, the frequency offset of the device under test system can be controlled, and the device under test can achieve line-speed stream testing without packet loss regardless of whether the synchronous Ethernet function is enabled, thus adapting to a wider range of testing scenarios.

[0057] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a line speed current testing device 200 is given below. Optionally, the line speed current testing device 200 can adopt the above-described... Figure 1 The device structure of the electronic device 100 shown. Further, please refer to... Figure 5 , Figure 5This is one of the block diagrams of the line speed current testing device 200 provided in this application embodiment. It should be noted that the basic principle and technical effects of the line speed current testing device 200 provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. In this embodiment, the line speed current testing device 200 may include: a processing module 220 and a testing module 230.

[0058] The processing module 220 is used to obtain the target frequency offset adjustment amount.

[0059] The processing module 220 is further configured to adjust the frequency offset of the first initial reference clock obtained by the device under test based on the local first clock according to the target frequency offset adjustment amount, so as to obtain the first reference clock. Wherein, the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test device.

[0060] The test module 230 is used to perform line-speed flow testing based on the first reference clock.

[0061] In this embodiment, the device under test includes a first clock and a clock chip connected to the first clock. The processing module 220 is specifically used to: activate the digitally controlled oscillator (DCO) function of the clock chip, and perform frequency offset increase processing on the first initial reference clock through the DCO function to obtain the first reference clock, wherein the increased frequency offset amount is the target frequency offset adjustment amount.

[0062] In this embodiment, the device under test supports synchronous Ethernet functionality. Please refer to... Figure 6 , Figure 6 This is a second block diagram of the line-speed flow testing device 200 provided in this embodiment. In this embodiment, the line-speed flow testing device 200 may further include a detection module 210. The detection module 210 is used to: determine whether the synchronous Ethernet function of the device under test is enabled; if it is determined that the synchronous Ethernet function of the device under test is not enabled, then the processing module 220 obtains the target frequency offset adjustment amount.

[0063] In this embodiment, if it is determined that the synchronous Ethernet function of the device under test is enabled, the processing module 220 is further configured to: obtain a second reference clock based on the signal of the test device through the synchronous Ethernet function, wherein the second reference clock is the reference clock of the test device; the test module 230 is further configured to perform line-speed flow testing based on the second reference clock.

[0064] In this embodiment, frequency offset adjustment is achieved by activating the DCO function of the clock chip. The processing module 220 is further specifically used to: determine whether the DCO function is in the activated state when the synchronous Ethernet function is enabled; if the DCO function is in the activated state, then disable the DCO function; after disabling the DCO function, obtain the second reference clock through the synchronous Ethernet function using the clock chip.

[0065] In this embodiment, the processing module 220 is specifically used to: obtain the first frequency offset range of the local machine and the second frequency offset range of the test equipment; and determine the target frequency offset adjustment amount based on the first frequency offset range and the second frequency offset range.

[0066] Optionally, the above modules can be stored in the form of software or firmware. Figure 1 The memory 110 shown is either stored in or embedded in the operating system (OS) of the electronic device 100, and can be used by... Figure 1 The processor 120 executes the program. Meanwhile, the data and program code required to execute the above modules can be stored in the memory 110.

[0067] This application also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, implements the described line-rate flow testing method.

[0068] In summary, this application provides a line-speed stream testing method, apparatus, electronic device, and readable storage medium. The testing device obtains a target frequency offset adjustment amount and adjusts the frequency offset of a first initial reference clock obtained from a local first clock of the device under test (DUT) according to the target frequency offset adjustment amount to obtain a first reference clock. Then, line-speed stream testing is performed based on the first reference clock. The minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the testing device. Thus, by adjusting the frequency offset range of the reference clock of the DUT based on the target frequency offset adjustment amount, the minimum value of the frequency offset range of the DUT is not less than the maximum value of the frequency offset range of the testing device, thereby avoiding packet loss during line-speed stream testing due to the clock frequency offset of the DUT being less than that of the testing device.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0070] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0071] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for testing linear velocity flow, characterized in that, The method, applied to a device under test that is communicatively connected to test equipment, includes: Obtain the target frequency offset adjustment; The frequency offset of the first initial reference clock obtained by the device under test based on the local first clock is adjusted according to the target frequency offset adjustment amount to obtain the first reference clock, wherein the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test device. Perform line-rate flow testing based on the first reference clock.

2. The method according to claim 1, characterized in that, The device under test includes a clock chip connected to the first clock. Adjusting the frequency offset of the first initial reference clock obtained from the local first clock of the device under test according to the target frequency offset adjustment amount to obtain the first reference clock includes: The digitally controlled oscillator (DCO) function of the clock chip is activated, and the frequency offset of the first initial reference clock is increased through the DCO function to obtain the first reference clock, wherein the increased frequency offset is the target frequency offset adjustment amount.

3. The method according to claim 1, characterized in that, The device under test supports synchronous Ethernet functionality. Before obtaining the target frequency offset adjustment, the method further includes: Determine whether the synchronous Ethernet function of the device under test is enabled; If it is determined that the synchronous Ethernet function of the device under test is not enabled, then the step of obtaining the target frequency offset adjustment is performed.

4. The method according to claim 3, characterized in that, The method further includes: If the synchronous Ethernet function of the device under test is enabled, a second reference clock is obtained based on the signal of the test device through the synchronous Ethernet function, wherein the second reference clock is the reference clock of the test device; Linear flow testing was performed based on the second reference clock.

5. The method according to claim 4, characterized in that, Frequency offset adjustment is achieved by activating the DCO function of the clock chip in the device under test. Obtaining a second reference clock based on the signal from the test device via the synchronous Ethernet function includes: If the synchronous Ethernet function is enabled, determine whether the DCO function is in the enabled state. If the DCO function is in the enabled state, then disable the DCO function. After disabling the DCO function, the second reference clock is obtained using the clock chip via the synchronous Ethernet function.

6. The method according to any one of claims 1-5, characterized in that, The process of obtaining the target frequency offset adjustment includes: Obtain the first frequency offset range of the local machine and the second frequency offset range of the test equipment; The target frequency offset adjustment amount is determined based on the first frequency offset range and the second frequency offset range.

7. A linear velocity flow testing device, characterized in that, The device is used for a device under test that is communicatively connected to test equipment, and includes: The processing module is used to obtain the target frequency offset adjustment amount; The processing module is further configured to adjust the frequency offset of the first initial reference clock obtained by the device under test based on the local first clock according to the target frequency offset adjustment amount, so as to obtain the first reference clock, wherein the minimum value of the frequency offset range of the first reference clock is not less than the maximum value of the second frequency offset range of the test device. The test module is used to perform line-rate current testing based on the first reference clock.

8. The apparatus according to claim 7, characterized in that, The device under test supports synchronous Ethernet functionality, and the device also includes a detection module. The detection module is used to determine whether the synchronous Ethernet function of the device under test is enabled; If the synchronous Ethernet function of the device under test is enabled, the processing module obtains a second reference clock based on the signal of the device under test through the synchronous Ethernet function, wherein the second reference clock is the reference clock of the device under test, and the testing module performs line-speed flow testing based on the second reference clock.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the line-rate flow testing method according to any one of claims 1-6.

10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the line-rate flow testing method as described in any one of claims 1-6.

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