Message reordering device and method, chip and electronic equipment

Abstract

The invention provides a message reordering device and method, a chip and electronic equipment. The message reordering device comprises a Burst Fifo, a segment storage module, a segment selection module and a segment check module, wherein the Burst Fifo is configured to store segment data acquired by the message reordering device, and the Burst Fifo is configured to store the segment data acquired by the message reordering device; the segment storage module is configured to be used for storing the segmented data, and the segment storage module is configured to be used for storing the segmented data; the segment Select module is configured to acquire segment number information, acquire a lowest number on the basis of the segment number information, and sequentially send the segment data on the basis of the lowest number and the segment number information; the segment Check module is configured to determine whether the segment data associated with the lowest number is the segment data of the first transmission or not. According to the message reordering device, the first sending sequence of the messages can be guaranteed, so that the messages can be sent in sequence.

Description

Technical Field

[0001] The present disclosure belongs to the field of switching chip design, and relates to message reordering, and in particular to a message reordering device and method, a chip, and an electronic device. Background Art

[0002] At present, the switching capacity of a single chip can no longer meet the growing demand for network bandwidth. Multiple switching chips are interconnected through stacking technology to form a large switching chip matrix to provide sufficient network bandwidth for high-performance Internet networks. Since network data transmission will be out of order in chip stacking technology, the order of message delivery is difficult to guarantee. Therefore, there is a problem that the order of message delivery cannot be guaranteed in the current chip stacking technology. Summary of the invention

[0003] The purpose of the present disclosure is to provide a message reordering device and method, a chip and an electronic device, so as to solve the problem that the initial transmission order of messages cannot be guaranteed in the current chip stacking technology.

[0004] In a first aspect, an embodiment of the present disclosure provides a message reordering device, which includes a burst queue BurstFifo, a segment storage Segment Storage module, a segment selection Segment Select module and a segment check Segment Check module: the BurstFifo is configured to store the segmented data received by the message reordering device; the Segment Storage module is configured to store the segmented data, which is the fragments into which the message is cut during transmission; the Segment Select module is configured to obtain segment numbering information, and based on the segment numbering information, obtain the lowest number, and sequentially send the segmented data based on the lowest number and the segment numbering information; the Segment Check module is configured to determine whether the segmented data associated with the lowest number is the first transmitted segmented data, if the segmented data subsequently received by the message reordering device are all in sequence after the first transmitted segmented data, then the segmented data associated with the lowest number is the first transmitted segmented data, otherwise the segmented data associated with the lowest number is not the first transmitted segmented data.

[0005] In the message reordering device, the segment number information and segment data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, which can ensure the initial order of messages, so that the messages can be sent sequentially.

[0006] In one embodiment of the present disclosure, the message reordering device also includes a data cyclic redundancy check DataCrcChecker module; the DataCrcChecker module has: a segmented data receiving unit, configured to receive the segmented data read from the BurstFifo; a CRC check unit, configured to perform a CRC check on the segmented data to obtain a CRC check result, the CRC check result being a CRC check success or a CRC check failure; a segmented data processing unit, configured to process the segmented data based on the CRC check result; the segmented data stored in the Segment Storage module is the segmented data that has successfully undergone the CRC check.

[0007] In one embodiment of the present disclosure, the segmented data processing unit is further configured to: when the CRC check result is a CRC check failure, discard the segmented data that failed the CRC check; when the CRC check result is a CRC check success, write the segmented data that succeeded the CRC check into the Segment Storage module.

[0008] In one embodiment of the present disclosure, the Segment Storage module comprises: a Segment Storage unit, configured to store the segmented data according to a first memory and a second memory therein, and a Linked List, configured to manage the storage location of the segmented data; the first memory and the second memory both have a head pointer and a tail pointer associated with the Linked List, the head pointer is used to write the address of the segmented data, and the tail pointer is used to read the segmented data.

[0009] In one embodiment of the present disclosure, the segmented data has an associated node identifier, and the message reordering device also includes a source selector, which is configured to interleave the node identifier based on a preset period so that the segmented data in the Segment Storage module is read into the PBC based on the interleaved node identifier.

[0010] In one embodiment of the present disclosure, the Segment Select module comprises: a lowest number acquisition unit, configured to acquire segment number information, and acquire the lowest number based on the segment number information; a time check TimerCheck unit, configured to determine whether the waiting time for the segment number exceeds a preset maximum time; a segment data sending unit, configured to read the segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the LinkedList, and send the segment data sequentially.

[0011] In one embodiment of the present disclosure, the segmented data is segmented data under a plurality of loops; the lowest number is the lowest number under the loop; and the first transmitted segmented data is the first transmitted segmented data under the loop.

[0012] In a second aspect, an embodiment of the present disclosure provides a chip, comprising the message reordering device as described in any one of the first aspects.

[0013] In a third aspect, an embodiment of the present disclosure provides a message reordering method, comprising: obtaining segmented data and segment number information, the segmented data being the segments into which the message is cut during transmission; obtaining a lowest number based on the segment number information; sequentially sending the segmented data based on the lowest number and the segment number information; determining whether the segmented data associated with the lowest number is the first segmented data transmitted, if the subsequently received segmented data are all in sequence after the first segmented data transmitted, then the segmented data associated with the lowest number is the first segmented data transmitted, otherwise the segmented data associated with the lowest number is not the first segmented data transmitted.

[0014] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory; and a processor, coupled to the memory and configured to execute the message reordering method described in the third aspect.

[0015] As described above, the message reordering device and method, chip and electronic device described in the present application have the following beneficial effects:

[0016] In the message reordering device, the segment number information and segment data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, which can ensure the initial order of messages, so that the messages can be sent sequentially. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a schematic diagram of a stacking interface according to an embodiment of the present disclosure.

[0018] Figure 2 It is a schematic diagram showing a continuous section of an embodiment of the present disclosure.

[0019] Figure 3 Shown is a structural schematic diagram of a message reordering device according to an embodiment of the present disclosure.

[0020] Figure 4 Shown is a memory representation diagram of the BurstFifo according to an embodiment of the present disclosure.

[0021] Figure 5 Shown is a structural schematic diagram of a message reordering device according to an embodiment of the present disclosure.

[0022] Figure 6 Shown is a timing diagram of a source selector according to an embodiment of the present disclosure.

[0023] Figure 7 Shown is a sample table of the lowest numbered embodiments of the present disclosure.

[0024] Figure 8 Shown is a flowchart of a message reordering method according to an embodiment of the present disclosure.

[0025] Component number description

[0026] 10 Message reordering device

[0027] 110 BurstFifo

[0028] 120 Segment Storage modules

[0029] 130 Segment Select Module

[0030] 140 Segment Check Module

[0031] Steps S11-S14 DETAILED DESCRIPTION

[0032] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0033] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present disclosure in a schematic manner, and thus the illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0034] The principles and implementation methods of the message reordering device and message reordering method of the embodiments of the present disclosure will be explained in detail below, so that those skilled in the art can understand the message reordering device and message reordering method of the embodiments of the present disclosure without creative work.

[0035] See also Figure 1 ,like Figure 1 As shown, SIF (Stack Interface) is an interface that connects incoming data to stack ports and connects stack ports to outgoing paths: SIF consists of 8 SifRacPcs (ring access controller) blocks, a SifReorder (reordering) block, a SifBcn (reverse congestion notification) block, a SifCopyTrip (copy / strip) block, an ingress queue (SifIngressFifo), and a SifRingSel (ring selection) block. Each of the 8 SifRacPcs blocks corresponds to a logical ring. The SifBcn block is used to process Bcn messages in the stack interface, the SifCopyTrip block is used to copy and strip (delete) the segments in the SifRacPcs block, the SifRingSel block is used to select the logical ring, the ingress queue is used to store local segment data, and the SifReorder block is used to reorder the segments in the SifRacPcs block. Figure 1 It also includes IQS (Ingress Queue scheduler), AQM (Active Queue Manager), Receive Serdes (received serializer / deserializer) and Transmit Seredes (transmitted serializer / deserializer). Each Rac has 4 Serdes (Serializer / Deserializer) running at 112Gbps. This makes the entire stack link set have 32 Serdes, thus achieving a bandwidth of 3.2TGbps.

[0036] Figure 1It is only used to provide an application scenario of a message reordering device (corresponding to the SifReorder block in SIF), that is, to reorder multi-ring messages in a ring stacking network. The stacking interface is not the focus of the present disclosure and will not be described in detail in this embodiment.

[0037] See also Figure 2 ,like Figure 2 As shown, in a stacking interface with several loops, when node #1 sends data to the stacking interface, the interface module does not know where it is going. Therefore, the local segmented data of node #1 can be inserted into the Rac (Ring Access Control) with the most available Credit. This means that the local segmented data from node #1 can (and will) be placed on the ring moving in the opposite direction. When the segmented data reaches node #15, it must be determined whether there is any other segmented continuous data before the segmented data can be forwarded to the PBC (Packetbuffer complex). In the stacking interface, the order of the initial messages in the interface loop needs to be guaranteed so that the messages can be sent sequentially.

[0038] See also Figure 3 ,like Figure 3 As shown, this embodiment provides a message reordering device 10, and the message reordering device 10 includes:

[0039] BurstFifo 110, Segment Storage 120, Segment Select 130 and Segment Check 140;

[0040] The BurstFifo 110 is configured to store the segmented data acquired by the message reordering device, wherein the segmented data is the segments into which the message is cut during transmission;

[0041] The Segment Storage module 120 is configured to store the segment data;

[0042] The Segment Select module 130 is configured to obtain segment number information, obtain a lowest number based on the segment number information, and sequentially send the segment data based on the lowest number and the segment number information;

[0043] The Segment Check module 140 is configured to determine whether the segmented data associated with the lowest number is the first transmitted segmented data. If the segmented data subsequently received by the message reordering device 10 are all in sequence after the first transmitted segmented data, then the segmented data associated with the lowest number is the first transmitted segmented data; otherwise, the segmented data associated with the lowest number is not the first transmitted segmented data.

[0044] Optionally, the segmented data may refer to a message being cut into multiple segments during transmission, each segment being 64 bytes long, and when the last segment of the message is less than 64 bytes, 0 is subsequently filled to make up 64 bytes. The message may include an Ethernet message and a switch management message.

[0045] Optionally, the message reordering device 10 may correspond to Figure 1 The SifReorder block in is used to reorder the segmented data provided by SifRacPcs.

[0046] Optionally, the segmented data acquired by the message reordering device 10 may be the segmented data received by the message reordering device 10, for example, Figure 1 The segmented data received by the SifRacPcs module.

[0047] Optionally, the segment number information may include the segment number of the segment data, and the lowest number refers to the lowest segment number in the segment number information.

[0048] Optionally, the segmented data is segmented data of several loops, the lowest number is the lowest number under the loop, and the first transmitted segmented data is the first transmitted segmented data under the loop.

[0049] Optionally, sending the segmented data sequentially based on the lowest number and the segment number information may include: sending the segmented data to the PBC sequentially based on the lowest number and the segment number information, and the sequential sending may refer to sending in order from small to large according to the segment numbers. For example, the segmented data may include data of segment number 1, segment number 2 and segment number 3, and the lowest number may be segment number 1. In the process of sending the segmented data to the PBC, the segmented data of segment number 1, the segmented data of segment number 2 and the segmented data of segment number 3 are sent to the PBC sequentially.

[0050] Optionally, in the Segment Check module 140, for example, the lowest number is 3, when the message reordering device 10 subsequently receives segment data with a segment number of 2, it indicates that the segment data subsequently received is before the first transmitted segment data, and when the message reordering device 10 subsequently receives segment data with a segment number of 4, it indicates that the segment data subsequently received is after the first transmitted segment data. If the segment data associated with the lowest number is not the first transmitted segment data, the data transmitted after the segment data associated with the lowest number can be discarded.

[0051] In one embodiment of the present disclosure, the BurstFifo110 can have 8-way write and 1-way read functions and be implemented in a trigger, and its elements are described in the SifRreorder BurstFifo (message reordering device burst queue) memory table. The BurstFifo110 can smooth the burstiness of the segmented data Segment Data (segmented data) storage resources (8 writes cannot be performed at a time), and the segmented data read from the BurstFifo110 is then sent to the DataCrcChecker (data cyclic redundancy check) module for segment data inspection and verification.

[0052] In one embodiment of the present disclosure, Figure 4 1 is a schematic diagram showing the memory representation of the BurstFifo 110 of the present disclosure embodiment. If the segment is a start of packet (SOP), it is checked whether the descriptor is a 32B (32-bit) descriptor. If so, it will be expanded back to 64B (64 bits) and the data will be shifted. This is in conjunction with the SIF insertion block ( Figure 1 The procedure is the opposite of the procedure performed in the data insertion block in the SifRac module in the PBC. At this time, the expanded data is written to the segmented data storage and restored to the form expected by the PBC. Figure 4 The data in it represents segment data, dataCrc represents the CRC check result, nodeId represents the node identifier, racId represents the ring access control identifier, sop represents the segment start, eop represents the segment end, segmentNumber represents the segment number, Total represents all, Wr sysClk represents the write synchronization signal, RdsysClk represents the read synchronization signal, FLOPS may refer to the number of floating-point operations that can be performed per second, and Drop Segment or CHIEF based on configuration may refer to discarding the segment or configuring it as the primary. Figure 4The Reorder Info (reorder information) in the data may refer to information for reordering the segment numbers of the segment data. For example, if the segment numbers of the segment data include 1, 5, 4 and 3, the reorder information may be information including segment numbers 1, 3, 4 and 5.

[0053] Optionally, see Figure 5 , the message reordering device also includes a data cyclic redundancy check (DataCrcChecker) module;

[0054] The DataCrcChecker module has:

[0055] A segmented data receiving unit, configured to receive the segmented data read from the BurstFifo;

[0056] A CRC (Cyclic Redundancy Check) checking unit is configured to perform a CRC check on the segmented data to obtain a CRC check result, wherein the CRC check result is a CRC check success or a CRC check failure;

[0057] A segmented data processing unit, configured to process the segmented data based on the CRC check result;

[0058] The segmented data stored in the Segment Storage module is the segmented data that has passed the CRC check.

[0059] Optionally, the segmented data processing unit is further configured to:

[0060] When the CRC check result is that the CRC check fails, the segmented data that fails the CRC check is discarded;

[0061] When the CRC check result is that the CRC check is successful, the segmented data that has successfully checked the CRC is written into the Segment Storage module.

[0062] In one embodiment of the present disclosure, the data read from the BurstFifo enters the dataCrc (data cyclic redundancy check) checker, namely the DataCrcChecker module. The Segment Data is checked to ensure that the stack link or other intermediate storage elements have not damaged it. The CRC-8 polynomial used is x8+x7+x6+x4+x2+1, which can be compared with the original Figure 1The code for generating the segmented data in the SifIngressFifo (incoming data queue) in the stack interface control is the same, and the ingoing data queue is not described in detail in this embodiment. If this CRC check fails, the segment will be discarded, or the CHIEF (main) will be set according to the SifControl.dropOnDataCrcError (discard cyclic redundancy check error data in stack interface control) bit.

[0063] Alternatively, if Figure 5 As shown, the Segment Storage module comprises: a Segment Storage unit, configured to store the second segmented data according to the first memory and the second memory therein, and a Linked List, configured to manage the storage location of the segmented data; the first memory and the second memory both have a head pointer and a tail pointer associated with the LinkedList, the head pointer is used to write the address of the segmented data, and the tail pointer is used to read the segmented data.

[0064] Optionally, the first memory and the second memory are both read once and written once within a preset cycle, for example, within any given 500 MHz cycle, each memory must be read once and written once.

[0065] Optionally, when the segmented data in one of the memories of the Segment Storage unit is being read and sent to the PBC, the writing, i.e., storage, of the segmented data will occur in another memory. For example, when the segmented data in the first memory is being read, the writing of the segmented data occurs in the second memory. When the memory in the Segment Storage unit is not being read, the writing of the segmented data occurs in the least full memory.

[0066] Optionally, the Segment Storage module is split into a first memory and a second memory, and reading is prioritized over writing, which can result in an overall depth (2*768) greater than the previously estimated 825 unfinished segments.

[0067] Alternatively, the calculation of the storage space required for reordering can be expressed as:

[0068]

[0069] Wherein, TotalSegments represents the total segments on the stack link at a given time, FixedDelay represents a fixed delay, Node represents a node, Segments represents a segment, Rac represents a ring access controller module, second represents a second, VariableSegments represents a variable segment, Nodes represents all nodes, and Racs represents all ring access controller blocks. The stack link refers to the link of the stack in the stack interface, and the stack link may refer to a linked list of the stack.

[0070] The differential time between the fastest path and the slowest path is expressed as:

[0071] WorstCaseDifferentialDelay=TotalNodes-1

[0072] Among them, WorstCaseDifferentialDelay represents the differential time between the fastest path and the slowest path, and TotalNodes represents all nodes.

[0073] The number of segments per Rac per second is given by:

[0074]

[0075] The stack bandwidth is: 112 Gbps*32 Node=3584 Gbps.

[0076] in, Indicates the number of RAC segments per second, StackBandwidth indicates the stack bandwidth, Byte indicates bytes, and Stack indicates stacks.

[0077] In one embodiment of the present disclosure, the Segment Data storage location is managed by a linked list. When segment data is written to the Segment Data Storage, i.e., the segment storage unit, a pointer is sent to the SifReorderSlice module for storage so that it can be retrieved after the segment data is read out. The head pointer is the address used to write the segment data. When the segment data is read out, the pointer returns to the end of the linked list. In the initial state of the linked list, each address points to the next location.

[0078] Writing to the Segment Data Store requires reading from the LinkedList (to find the next pointer). Reading from the Segment Data Store requires writing to the LinkedList (to link the pointer to the tail). This linked list memory is ECC (Error-Correcting Code) protected, as a failure in it would cause the LinkedList to be artificially shortened to a "1" element (itself). The linked list memory is described in the Segment Data Linked List Memory table.

[0079] There are always 4 pointers maintained in the SifReorder block. Each of the 2 Segment Data Stores has a head pointer and a tail pointer for each of the 2 Segment Data Stores. At initialization, the head pointer is equal to 0 and the tail pointer is equal to 755. The Segment Data LinkedList (segment data linked list), which is the linked list memory described above, must be initialized so that each entry points to the next (0-->1, 1-->2, ...765-->766, 766-->767). This can be achieved by setting the hardware initialization bit or software programming each entry.

[0080] Optionally, the segmented data has an associated node identifier, such as Figure 5 As shown, the message reordering device also includes a Source Selector, which is configured to interleave the node identifier based on a preset period so that the segmented data in the Segment Storage module is read into the PBC based on the interleaved node identifier. The preset period can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0081] In one embodiment of the present disclosure, the message reordering device interleaves the working NodeId (node ​​identifier) ​​every other cycle. This is because PBC cannot process back-to-back segment data from the same NodeId. The Source Selector module is responsible for switching machines back and forth between open sources (NodeId). When a NodeId no longer has valid segments ready to be sent to the PBC, the source selector will move to the next context (NodeId). The timing diagram of the source selector is shown in SifReorder source selection timing Figure 6 shown. Figure 6 The currentNodeId in it can represent the current node identification, and nodeIdDone can represent the completion of node identification.

[0082] Optionally, the Segment Select module comprises: a lowest number acquisition unit, configured to acquire segment number information, and acquire the lowest number based on the segment number information; a TimerCheck unit, configured to determine whether the waiting time for the segment number exceeds a preset maximum time; and a segment data sending unit, configured to read the second segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the Linked List, and send the second segment data sequentially.

[0083] Optionally, the segment number information may be the Reorder Info described above. The preset maximum time may be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0084] Optionally, the segment number being waited for in the TimerCheck unit may be a segment number that is missing in the segment data being sent sequentially, for example, the lowest number is 1, and segment numbers 1, 2, and 3 need to be sent sequentially. Currently, the segment data does not contain data with segment number 2, so it is necessary to wait for data with segment number 2. The TimerCheck unit refers to whether the waiting time for segment number 2 exceeds a preset time. The preset time can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0085] In one embodiment of the present disclosure, the segment selector obtains the segment number information provided by RacInfoStorage Rams (Ring Access Control Information Storage Random Access Memory) and determines the lowest segment number. Once the lowest SegmentNumber is selected, all other information in RacInfoStorage Ram is fed to the TimerCheck block. The RacInfoStorage Rams can be in the SifRacPcs module.

[0086] The Segment selection module is careful to determine the lowest SegmentNumber even if the counter rolls over. An example table of minimum segment number determinations is provided in the Minimum Segment Number Example Table. Segment numbers are counted from 0 to 4095 to help make these determinations easier (to account for wrapping effects). Since a stack link can have approximately 850 segments at any time, a minimum counter of 0-2047 is needed. It is extended to 4096 to accommodate the future.

[0087] Figure 7The segment difference of 801 is shown and how it crosses the counter boundary. At any time the difference could exceed 850, but if that happens some segments are definitely ready to be read into the PBC. The "segment selection" block relies on the fact that the segments have been stored one after another in a linked list. It guarantees that the segment selection is limited to only 8 options (one for each race, rac) and that segments arriving later that are behind previously arriving segments from the same race are guaranteed to have a segment number greater than the previously arriving segment number.

[0088] The lowest number is the lowest number under all loops. The counter is used cyclically by each Rac, so 0-4095-0-1. The minimum data is when the maximum number + the minimum number in Rac0~Rac7 is less than 4096, and the lowest is the current minimum number. When the maximum number + the minimum number in Rac0~Rac7 is greater than 4096, it means that the count has reversed a round. The minimum number at this time is the smallest of the larger numbers. Figure 7 The Seg#Rac0-7 in the figure refers to the segment number of Rac0 to Rac7, and the lowest Segement refers to the lowest number.

[0089] In one embodiment of the present disclosure, once the lowest segment number is selected, the "first transmission" is determined. Just because it appears to be the "first transmission", it may not actually be. The segment check block determines whether this segment is actually the "first transmission" or whether we need to wait longer. By storing the segment number information for each Rac, it is guaranteed that even if 50 segments are copied from the stack link, only 8 segment numbers are checked at a time. All subsequent segments copied from the stack link by a given Rac are "behind" this segment in order.

[0090] The BurstFifo described above corresponds to Figure 5 In BurstFifo, the DataCrcChecker module corresponds to Figure 5 In dataCrcCheck, the Segment Storage unit corresponds to Figure 5 The Segment Data Store in the Linked List corresponds to Figure 5 In the LinkedList, the pointer can correspond to Figure 5 In SegementDataLink, the source selector corresponds to Figure 5 Source Select in the Segment Select module corresponds to Figure 5 In SegmentSelect, the Segment Check module corresponds to Figure 5Segment Check in.

[0091] In one embodiment of the present disclosure, a chip is provided. The chip includes the message reordering device.

[0092] Figure 8 is a flow chart showing a method for reordering packets according to an embodiment of the present disclosure. Figure 8 As shown, this embodiment provides a message reordering method, including:

[0093] S11, obtaining segment data and segment number information, wherein the segment data is the segments into which the message is cut during transmission.

[0094] S12: Based on the segment number information, obtain the lowest number.

[0095] S13, sending the segment data in sequence based on the lowest number and the segment number information.

[0096] S14, determining whether the segmented data associated with the lowest number is the first segmented data transmitted. If the subsequently received segmented data are all sequentially after the first segmented data transmitted, the segmented data associated with the lowest number is the first segmented data transmitted. Otherwise, the segmented data associated with the lowest number is not the first segmented data transmitted.

[0097] Optionally, the "in order" may refer to the order of the segment numbers from small to large, and the subsequently received segmented data in order after the first transmitted segmented data may refer to the segment numbers of the subsequently received segmented data being after the segment number of the first transmitted segmented data in order from small to large. For example, if the lowest number is 2, the first transmitted segmented data refers to the segmented data with segment number 2. If the segment numbers of the subsequently received segmented data are 3, 4, 5, etc., the segmented data associated with the lowest number is the first transmitted segmented data. If the segment number of the subsequently received segmented data is 1, the segmented data associated with the lowest number is not the first transmitted segmented data.

[0098] The protection scope of the message reordering method described in the embodiment of the present disclosure is not limited to the execution order of the steps listed in the present embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present disclosure are included in the protection scope of the present disclosure.

[0099] In summary, in the message reordering device, the segment numbering information and segment data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, which can ensure the initial transmission order of the messages, so that the messages can be sent sequentially.

[0100] In the several embodiments provided in the present disclosure, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules / units is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0101] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in the various embodiments of the present disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0102] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0103] This embodiment provides an electronic device, the electronic device comprising a memory; a processor, coupled to the memory and configured to execute Figure 8 The message reordering method shown.

[0104] The present disclosure embodiment also provides a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state disk (SSD)), etc.

[0105] The embodiments of the present disclosure may also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiments of the present disclosure is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer or data center to another website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0106] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.

[0107] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0108] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.

Claims

1. A message reordering device, characterized in that: Including the burst queue BurstFifo, segment storage SegmentStorage module, segment selection Segment Select module and segment check Segment Check module: The BurstFifo is configured to store the segmented data acquired by the message reordering device, wherein the segmented data is the segments into which the message is cut during transmission; The Segment Storage module is configured to store the segment data; The Segment Select module is configured to obtain segment number information, and based on the segment number information, obtain a lowest number, and sequentially send the segment data based on the lowest number and the segment number information; The Segment Check module is configured to determine whether the segmented data associated with the lowest number is the first transmitted segmented data. If the segmented data subsequently received by the message reordering device are all after the first transmitted segmented data in sequence, then the segmented data associated with the lowest number is the first transmitted segmented data. Otherwise The segment data associated with the lowest number is not the first transmitted segment data.

2. The message reordering device according to claim 1, characterized in that: The message reordering device also includes a data cyclic redundancy check DataCrcChecker module; The DataCrcChecker module has: A segmented data receiving unit, configured to receive the segmented data read from the BurstFifo; A CRC check unit is configured to perform a CRC check on the segmented data to obtain a CRC check result, wherein the CRC check result is a CRC check success or a CRC check failure; A segmented data processing unit, configured to process the segmented data based on the CRC check result; The segmented data stored in the Segment Storage module is the segmented data that has passed the CRC check.

3. The message reordering device according to claim 2, characterized in that: The segment data processing unit is further configured to: When the CRC check result is that the CRC check fails, the segmented data that fails the CRC check is discarded; When the CRC check result is that the CRC check is successful, the segmented data that has successfully checked the CRC is written into the Segment Storage module.

4. The message reordering device according to claim 1, characterized in that: The Segment Storage module has: A Segment Storage unit is configured to store the segment data according to the first memory and the second memory therein; A linked list, configured to manage the storage location of the segmented data; The first memory and the second memory both have a head pointer and a tail pointer associated with the Linked List, the head pointer is used to write the address of the segmented data, and the tail pointer is used to read the segmented data.

5. The message reordering device according to claim 1, characterized in that: The segmented data has an associated node identifier, and the message reordering device also includes a source selector, which is configured to interleave the node identifier based on a preset period so that the segmented data in the Segment Storage module is read into the PBC based on the interleaved node identifier.

6. The message reordering device according to claim 1, characterized in that: The Segment Select module has: A lowest number obtaining unit is configured to obtain segment number information, and obtain a lowest number based on the segment number information; A time check TimerCheck unit is configured to determine whether the time for waiting for the segment number exceeds a preset maximum time; The segment data sending unit is configured to read the segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the Linked List, and send the segment data sequentially.

7. The message reordering device according to claim 6, characterized in that: The segmented data is segmented data under several loops; The lowest number is the lowest number under the loop; The first transmitted segmented data is the first transmitted segmented data under the loop.

8. A chip, characterized in that: It comprises the message reordering device as described in any one of claims 1-7.

9. A message reordering method, characterized in that: include: Acquire segment data and segment number information, wherein the segment data is the segments into which the message is cut during transmission; Based on the segment number information, obtaining the lowest number; Send the segment data sequentially based on the lowest number and the segment number information; Determine whether the segmented data associated with the lowest number is the first segmented data transmitted. If the subsequently received segmented data are all sequentially after the first segmented data transmitted, the segmented data associated with the lowest number is the first segmented data transmitted. Otherwise, the segmented data associated with the lowest number is not the first segmented data transmitted.

10. An electronic device, characterized in that: include: Memory; A processor is coupled to the memory and configured to execute the message reordering method according to claim 9.

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