Message forwarding method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a message forwarding method and device, computer equipment, a readable storage medium and a program product, and relates to the field of message processing. The method comprises the following steps: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; screening out a first memory core matched with the first hash value from a plurality of first candidate memory cores used for performing message processing on the request message; and performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object. By adopting the method, the message forwarding efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of message processing, and in particular to a message forwarding method, device, computer equipment, readable storage medium and program product. Background Art

[0002] With the development of Internet technology, various business interactions are gradually needed between networks to achieve resource interoperability. At present, an intermediate device is usually introduced between networks to process and forward traffic messages. For example, intranet devices are usually connected to SD-WAN (Software-Defined Wide Area Network) through EDGE (Edge Devices).

[0003] However, with the diversity of services, interactive resources become more and more complex, and intermediate devices will require more processor resources, which will affect the performance of intermediate devices to a certain extent, thereby affecting the forwarding efficiency of traffic packets. Summary of the invention

[0004] Based on this, it is necessary to provide a message forwarding method, apparatus, computer equipment, computer-readable storage medium and computer program product that can improve message forwarding efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a message forwarding method, including: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; screening out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.

[0006] In one of the embodiments, the method also includes: when the second object returns a response message to the first object in response to the request message, identifying the type of the response message to obtain a second message type of the response message; when the second message type is an address conversion message, obtaining a target port number of the response message; screening out a second memory core that matches the target port number from multiple first candidate memory cores; performing message processing on the response message through the second memory core to obtain a second target message, and sending the second target message to the first object.

[0007] In one of the embodiments, the method also includes: when the second message type is an encrypted message, obtaining the number of memory cores of multiple second candidate memory cores for processing the response message; based on the number of memory cores, screening out a third memory core from the multiple second candidate memory cores; decrypting the response message through the third memory core to obtain a decrypted message; hashing the target address information of the decrypted message to obtain a second hash value of the target address information; screening out a fourth memory core that matches the second hash value from multiple first candidate memory cores; processing the decrypted message through the fourth memory core to obtain a third target message, and sending the third target message to the first object.

[0008] In one of the embodiments, the request message includes at least one sub-message, and the method also includes: determining a target sub-message ranked first among each sub-message; if the target sub-message exists in a message cache list, reading the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0009] In one of the embodiments, the method also includes: performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determining a first candidate memory core quantity that matches the first business complexity and a second candidate memory core quantity that matches the second business complexity; determining a plurality of first candidate memory cores that match the first candidate memory core quantity and a plurality of second candidate memory cores that match the second candidate memory core quantity.

[0010] In one of the embodiments, a request message is processed by a first memory core to obtain a target message, including: type identification of the request message is performed by the first memory core to obtain a first message type of the request message; and based on a message processing method that matches the first message type, message processing is performed on the request message to obtain a target message.

[0011] In the second aspect, the present application also provides a message forwarding device, including: an information acquisition module, used to obtain source address information of a request message when a first object sends a request message to a second object; a hash processing module, used to perform hash processing on the source address information to obtain a first hash value of the source address information; a memory core determination module, used to screen out a first memory core that matches the first hash value from multiple first candidate memory cores for performing message processing on the request message; a message processing module, used to perform message processing on the request message through the first memory core, obtain a first target message, and forward the first target message to the second object.

[0012] In a third aspect, the present application also provides a computer device, including a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; screening out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.

[0013] In a fourth aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, which implements the following steps when the computer program is executed by a processor: when a first object sends a request message to a second object, obtain the source address information of the request message; perform hash processing on the source address information to obtain a first hash value of the source address information; screen out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.

[0014] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the following steps when executed by a processor: when a first object sends a request message to a second object, obtain the source address information of the request message; perform hash processing on the source address information to obtain a first hash value of the source address information; screen out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.

[0015] The above-mentioned message forwarding method, device, computer equipment, computer-readable storage medium and computer program product are applied to an intermediate device connected to a first object core and a second object respectively. When the first object sends a request message to the second object, the intermediate device first obtains the source address information of the request message. The source address information is hashed to obtain a first hash value of the source address information. Then, among the multiple first candidate memory cores used for message processing of the request message, a first memory core matching the first hash value is screened out, and the request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object. In other words, the present application performs hashing on the address information to screen out the memory core used for message processing. Due to the consistency of the hash function, the request message and the response message will generate the same hash value, thereby ensuring that the request message and the response message are processed by the same memory core. That is, each memory core can maintain the message session information of the core, and there is no need to perform thread synchronization with other memory cores, effectively avoiding the overhead of thread synchronization. This not only improves the performance of the intermediate device, but also enables parallel execution of message forwarding, thereby improving the efficiency of message forwarding. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] FIG1 is an application environment diagram of a message forwarding method in one embodiment;

[0018] FIG2 is a schematic diagram of a flow chart of a message forwarding method in an embodiment;

[0019] FIG3 is a schematic diagram of screening of a first memory core in one embodiment;

[0020] FIG4 is a schematic diagram of node chain forwarding in one embodiment;

[0021] FIG5 is a schematic diagram of adding a node in one embodiment;

[0022] FIG6 is a schematic diagram of a response message forwarding process in one embodiment;

[0023] FIG7 is a schematic diagram of a process of port number matching in one embodiment;

[0024] FIG8 is a schematic diagram of a process for decrypting a response message in one embodiment;

[0025] FIG9 is a schematic diagram of screening of a third memory core in one embodiment;

[0026] FIG10 is a schematic diagram of a flow chart of LAN side message scheduling in one embodiment;

[0027] FIG11 is a schematic diagram of a flow chart of message cache reading in one embodiment;

[0028] FIG12 is a schematic diagram of a process of allocating memory cores in one embodiment;

[0029] FIG13 is a schematic diagram of a flow chart of a message forwarding method in a specific embodiment;

[0030] FIG14 is a structural block diagram of a message forwarding device in one embodiment;

[0031] FIG. 15 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] The message forwarding method provided in an embodiment of the present application can be applied to the SD-WAN network environment as shown in Figure 1. Among them, the intermediate device 102 is connected to the first object 104 and the second object 106 respectively. The intermediate device can be a gateway device such as an EDGE gateway device, the first object 104 can refer to a terminal device on the LAN (Local Area Network) side, such as a network device within an enterprise, and the second object 106 can refer to a network control center on the WAN (Wide Area Network) side. The first object 104 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, and Internet of Things devices. The second object 106 can be an independent physical server, or it can be a server cluster or distributed system composed of multiple physical servers, or it can be a cloud server that provides cloud computing services.

[0034] Specifically, when the first object 104 sends a request message to the second object 106, the intermediate device 102 first obtains the source address information of the request message. The source address information is hashed to obtain a first hash value of the source address information. Among the multiple first candidate memory cores for processing the request message, the first memory core that matches the first hash value is screened out. The request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object 106.

[0035] In an exemplary embodiment, as shown in FIG. 2 , a message forwarding method is provided, which is described by taking the method applied to the intermediate device 102 in FIG. 1 as an example, including:

[0036] Step S202: when the first object sends a request message to the second object, obtain source address information of the request message.

[0037] The request message refers to a traffic message sent by the first object to the second object, or is called uplink traffic. The source address information refers to the source IP (Internet Protocol Address) address of the request message, that is, the IP address to which the first object belongs.

[0038] Exemplarily, when the first object sends a request message to the second object, the gateway device will first obtain the source IP address of the request message, that is, the IP address of the first object.

[0039] In one example, the gateway device may be a multi-core device, that is, there may be multiple memory cores in the gateway device. In this embodiment, for the first object, the gateway device may have a fixed message receiving memory core and multiple first candidate memory cores for processing the request message initiated by the first object. Similarly, for the second object, the gateway device will also have a fixed message receiving memory core and multiple second candidate memory cores for processing the response message returned by the second object. It should be noted that the message receiving memory core is only used to receive request messages or response messages, and does not participate in subsequent message processing. That is, the message receiving memory core corresponding to the first object in the gateway device will first receive the request message sent by the first object to the second object, and obtain the source IP address of the request message.

[0040] In one example, each memory core may have its own timer for releasing resources at a fixed time, such as releasing memory, so that the memory is used more efficiently and the overhead of the gateway device is reduced.

[0041] In one example, the message receiving memory core can receive messages through DPDK (Data Plane Development Kit) polling. DPDK polling means that when using DPDK for network message processing, the message receiving memory core will continuously check whether there are new messages arriving, thereby reducing the overhead caused by interrupt processing and improving the efficiency of message processing.

[0042] Step S204: perform hash processing on the source address information to obtain a first hash value of the source address information.

[0043] The hash processing is a process of transforming an input of any length into an output of a fixed length through a hash algorithm. In this embodiment, it means transforming the source address information into a value of a fixed length, that is, a first hash value, through a hash algorithm.

[0044] For example, after obtaining the source address information of the request message, the message receiving memory core of the gateway device can use a preset hash algorithm to hash the source address information to obtain a hash value, so as to facilitate subsequent traffic message scheduling based on the hash value, that is, scheduling the request message to the corresponding memory core for processing.

[0045] Step S206: select a first memory core that matches the first hash value from among a plurality of first candidate memory cores for processing the request message.

[0046] The first candidate memory core refers to a memory core that can be used to process the request message, or in other words, the first candidate memory cores are memory cores used to process each request message initiated by the first object. There can be multiple first candidate memory cores. The first memory core is the memory core that finally processes the request message.

[0047] Exemplarily, after the message receiving memory core calculates the first hash value of the request message, it can further perform memory core matching based on the first hash value to filter out a first memory core that matches the first memory core from multiple first candidate memory cores corresponding to the first object, for subsequent message processing of the request message.

[0048] FIG3 shows a schematic diagram of screening the first memory core. Among them, first_worker_index is the memory core number of the first memory core among multiple first candidate memory cores. Assuming that the memory core receiving the message is CPU1, the multiple first candidate memory cores are CPU2, CPU3...CPU11 in sequence. Then first_worker_index is the number of CPU2. It should be noted that the number of the memory core can be set by itself, and this embodiment does not limit this. Assign first_worker_index to next_worker_index. Then, the first hash value is modulo the number of threads on the LAN side len (lan_workers). In this example, the number of threads on the LAN side is 10. Finally, the value of next_worker_index is added to get the number of the first memory core to which the request message is sent. After CPU1 calculates the number, it performs traffic scheduling, that is, schedules the request message to the memory core with that number.

[0049] It should be noted that in this embodiment, a node chain forwarding mechanism can be used in the memory core to realize the forwarding of the message, that is, each operation is written as a node, such as route lookup, traffic scheduling, NAT (Network Address Translation) conversion, etc. As shown in Figure 4, the nodes in this embodiment are message reception, route lookup, NAT conversion, and message sending. In addition, a message verification node can be deployed after receiving the message to verify the MAC address of the request message to ensure that the request message needs to be forwarded by the gateway device. And the next node is determined by the field in the message. Taking NAT conversion as an example, assuming that the request message is an IPv4 message that needs NAT conversion, it will be passed to the IPv4node for processing, and then a route lookup is performed to determine the next hop address. After NAT conversion, the message is sent.

[0050] In an example, as shown in Figure 5, the request message enters the first memory core, which is the traffic enqueue. The first memory core will perform a traffic dequeue operation. At this time, a node can be added to the node chain to receive the traffic and forward it to the next node. This added node can be called a traffic shaping node. It can be configured before the route lookup.

[0051] Step S208: Process the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.

[0052] The first target message refers to a message obtained after processing the request message.

[0053] For example, after completing traffic shaping, the first memory core can perform processing operations such as route lookup, NAT conversion, and message detection on the request message to obtain a final target message. The gateway device will send the target message to the second object.

[0054] In this embodiment, when the first object sends a request message to the second object, the gateway device first obtains the source address information of the request message. The source address information is hashed to obtain the first hash value of the source address information. Then, among the multiple first candidate memory cores for message processing of the request message, the first memory core matching the first hash value is screened out, and the request message is processed by the first memory core to obtain the first target message, and the first target message is forwarded to the second object. That is, in this embodiment, the address information is hashed to screen out the memory core for message processing. Due to the consistency of the hash function, the request message and the response message will generate the same hash value, thereby ensuring that the request message and the response message are processed by the same memory core. That is, each memory core can maintain the message session information of the core, and there is no need to synchronize threads with other memory cores, effectively avoiding the overhead of thread synchronization. In this way, not only the performance of the intermediate device can be improved, but also the parallel execution of message forwarding can be realized, thereby improving the efficiency of message forwarding.

[0055] In an exemplary embodiment, as shown in FIG6 , the message forwarding method further includes:

[0056] Step S602: When the second object returns a response message to the first object in response to the request message, the response message is identified in type to obtain a second message type of the response message.

[0057] The response message refers to the message that the second object returns to the first object after receiving the request message from the first object. The response message contains the processing result of the second object on the request message, or called downlink traffic. The second message type includes address translation messages and encrypted messages. The address translation message is the NAT message, and the encrypted message is the IPsec (Internet Protocol Security) message, that is, the message after IPsec encryption.

[0058] Exemplarily, when the second object returns a response message to the first object in response to the request message, the gateway device will first identify the message type of the response message to match the corresponding message scheduling rule.

[0059] In one example, the message receiving memory core for the second object in the gateway device can continuously receive the response message sent by the second object through the DPDK polling mode, and identify the message type of the response message.

[0060] In one example, the message receiving memory core can identify the message type of the response message by the target port or message protocol number of the response message. For example, if the response message is a UDP (User Datagram Protocol) message and the destination port number is 500 or 4500, or the message protocol number of the response message is 50, then it can be considered that the response message belongs to an IPsec message. Otherwise, it belongs to a NAT message. Of course, in actual applications, other message type identification rules can also be defined, and this embodiment does not limit this.

[0061] Step S604: when the second message type is an address translation message, obtain the target port number of the response message.

[0062] Exemplarily, as shown in FIG7 , when the message receiving memory core identifies that the message type of the response message is an address translation message, that is, a NAT message, the response message can be directly dispatched to multiple first candidate memory cores for message processing, that is, NAT conversion. Considering that the IP address of the message will be converted during the NAT conversion process, that is, the target IP address in the response message is actually the public network IP address of the gateway device, not the IP address of the first object. If the memory core to be sent is determined directly based on the IP address, then all response messages will be sent to the same memory core that is processed by NAT conversion, causing the memory core to become a bottleneck. The port number will also be converted, and each message has a unique source port number and target port number. By using the port number to determine which memory core to send to, more fine-grained message forwarding can be achieved to avoid a single memory core from becoming a bottleneck.

[0063] In one example, when the first memory core performs NAT conversion on the request message, it will evenly distribute the available ports of the public IP address of the gateway device to each first candidate memory core. For example, the public IP address usually has 65535 ports (from 0 to 65535), but some of them (such as 0 to 1023) are reserved for the system or well-known services, and therefore are not used for general data transmission. The remaining ports (from 1024 to 65535) can be used for NAT conversion. In this example, these available ports are evenly distributed to each candidate memory core that processes the LAN side message. Assuming that there are 10 candidate memory cores, the number of ports that each candidate memory core can obtain is (65535 - 1024) / 10 = 6451. Each candidate memory core is assigned a specific range of ports. For example, the port range of CPU2 is 1024 + 6451*1=7475, that is, 1024 to 7475. Similarly, the port range of CPU3 is 1024 + 6451*2=13926, that is, 1025 to 13926, and so on. In this way, when the response message arrives, the message receiving memory core will determine which candidate memory core should handle the NAT reverse conversion of this message based on the destination port number. For example, if the destination port number is 12000, it falls within the port range of CPU3, so this response message will be scheduled to CPU3 for processing. Of course, in actual applications, other port range definition rules can be defined according to actual conditions, and this embodiment does not limit this.

[0064] Step S606: Filter out a second memory core that matches the target port number from the plurality of first candidate memory cores.

[0065] The second memory core refers to the memory core that matches the target port number. In one example, the memory core that performs reverse NAT conversion on the response message should be consistent with the memory core that performs NAT conversion on the request message, that is, the second memory core and the first memory core should be the same memory core.

[0066] Exemplarily, after the message receiving memory core obtains the target port number of the response message, it can perform matching among multiple first candidate memory cores to screen out a memory core that matches the target port number.

[0067] Step S608: Process the response message through the second memory core to obtain a second target message, and send the second target message to the first object.

[0068] The second target message refers to a message obtained after processing the response message, for example, it may be a message obtained after performing NAT conversion on the response message.

[0069] Exemplarily, the message receiving memory core dispatches the response message to the second memory core, and the second memory core performs message processing on the response message, such as route lookup, NAT conversion, etc., to obtain the second target message, and sends the second target message to the first object.

[0070] In this embodiment, it can be seen that the traffic message of the first object is separated from the traffic message of the second object, that is, the upstream traffic on the LAN side and the downstream traffic on the WAN side are separated, which effectively avoids the bottleneck caused by the bidirectional traffic message processing of a single memory core, thereby reducing the performance of the gateway device. Moreover, by matching the port number, it is further ensured that the response message and the request message can be processed by the same memory core, realizing symmetrical message forwarding and improving message forwarding efficiency.

[0071] In an exemplary embodiment, as shown in FIG8 , the message forwarding method further includes:

[0072] Step S802: When the second message type is an encrypted message, obtain the number of memory cores of a plurality of second candidate memory cores for performing message processing on the response message.

[0073] The second candidate memory core refers to a memory core used to process the response message returned by the second object, and the number of memory cores refers to the total number of the second candidate memory cores.

[0074] Exemplarily, when the message receiving memory core of the gateway device identifies that the response message is an encrypted message, that is, an IPsec message, it first obtains the total number of memory cores of multiple second candidate memory cores for message processing of the response message for subsequent screening of the third memory core.

[0075] Step S804: based on the number of memory cores, select a third memory core from the plurality of second candidate memory cores.

[0076] The third memory core refers to a memory core that performs decryption processing on the response message.

[0077] Exemplarily, as shown in FIG9 , the message receiving memory core will introduce a counter, namely ipsec_thread, which will automatically increase by one after each message scheduling. first_worker_index is the memory core number of the first memory core among multiple second candidate memory cores. number_of_wan is the number of memory cores that process WAN-side messages, that is, the total number of multiple second candidate memory cores. The +1 in the initialization assignment of next_worker_index ignores the message receiving memory core used to receive the response message. Finally, the counter is used to perform a modulo operation on the number of threads on the WAN side len (wan_workers), and the initialized next_worker_index is added to get the number of the next memory core to be scheduled, that is, the number of the third memory core.

[0078] Step S806: decrypt the response message through the third memory core to obtain a decrypted message.

[0079] The decrypted message refers to a message obtained after performing IPsec decryption on the response message.

[0080] Exemplarily, the message receiving memory core dispatches the response message to the third memory core, and the third memory core performs traffic scheduling, traffic shaping, and IPsec decryption processing to obtain a decrypted message.

[0081] Step S808: Perform hash processing on the target address information of the decrypted message to obtain a second hash value of the target address information.

[0082] The target address information refers to the target IP address of the decrypted message, that is, the IP address of the first object. The second hash value refers to the hash value obtained after hashing the target address information.

[0083] Exemplarily, after the decryption of the response message is completed, the message scheduling on the LAN side needs to be performed. As shown in Figure 10, since it is symmetrical with the request message, the target address information is used for hash calculation in this embodiment, so that the request message and the response message on the same data stream can be scheduled to the same memory core.

[0084] Step S810: Filter out a fourth memory core that matches the second hash value from the plurality of first candidate memory cores.

[0085] Exemplarily, the gateway device selects a fourth memory core that matches the second hash value from among the plurality of first candidate memory cores. It should be noted that the second hash value should be the same as the first hash value, so the fourth memory core should be the same as the first memory core.

[0086] Step S812: Process the decrypted message through the fourth memory core to obtain a third target message, and send the third target message to the first object.

[0087] The third target message refers to a message obtained after performing message processing on the decrypted message, such as message detection, session processing and other operations.

[0088] Exemplarily, the third memory core sends the decrypted message to the fourth memory core on the LAN side, and the fourth memory core processes the decrypted message to obtain a processed third target message, and sends the third target message to the first object.

[0089] In this embodiment, when the response message is an IPsec message, a memory core is first selected on the WAN side for decryption processing, and then a hash process based on the target IP is performed to filter out a memory core consistent with the request message on the LAN side, thereby ensuring that the request message and response message on the same data stream can be scheduled to the same memory core, thereby improving the efficiency of message forwarding.

[0090] In an exemplary embodiment, as shown in FIG11 , the message forwarding method further includes:

[0091] Step S1102, determining the target sub-message ranked first among all sub-messages.

[0092] Step S1104: if the target sub-message exists in the message cache list, read the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0093] The request message includes at least one sub-message, which can also be understood as a request message is a message array composed of multiple sub-messages, each of which can represent a request. The target sub-message refers to the first message in each sub-message. The message cache list is a list for recording cached messages, which can also be a cache area or a cache such as a cache memory.

[0094] Exemplarily, when the message receiving memory core receives the request message array, it can first extract the first sub-message in the request message array and query whether the first sub-message exists in the message cache list. If it exists, it means a cache hit, indicating that the first sub-message has been cached. Since the messages in the array are processed continuously, the messages after the first sub-message are also likely to have been cached in the message cache list. Then the message receiving memory core can directly read the target sub-message and other sub-messages from the message cache list, that is, this group of request messages will benefit from the cache hit of the first sub-message and achieve higher processing performance. If the first sub-message does not exist in the message cache list, it means a cache miss, indicating that the first sub-message has not been cached. At this time, the message receiving memory core can be preheated by the first message, that is, the data of the first sub-message is loaded into the message cache list, so that subsequent access to other messages in the array can take advantage of the acceleration effect of the message cache list. Once the first message in the message cache list is preheated, subsequent access to other messages in the array is likely to hit the cache due to the relevance or pattern of the messages in the array. In this way, the processing performance of the remaining messages in the array can directly reach the limit, thereby improving the efficiency of request message reading and thus improving the efficiency of the entire message forwarding.

[0095] In an exemplary embodiment, as shown in FIG12 , the message forwarding method further includes:

[0096] Step S1202: performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object.

[0097] The first service complexity can be used to characterize the complexity of the service that the first object, ie, the LAN side, needs to execute, and the second service complexity can be used to characterize the complexity of the service that the first object, ie, the WAN side, needs to execute.

[0098] Exemplarily, when allocating candidate memory cores to the first object and the second object, the gateway device may first perform a business complexity analysis on both, that is, analyze the complexity of the business that the first object and the second object need to execute respectively, so as to allocate an appropriate number of candidate memory cores.

[0099] Step S1204: determine the number of first candidate memory cores that matches the first business complexity level and the number of second candidate memory cores that matches the second business complexity level.

[0100] The number of first candidate memory cores refers to the number of first candidate memory cores, and the number of second candidate memory cores refers to the number of second candidate memory cores.

[0101] Exemplarily, after analyzing the business complexity of the first object and the second object, the gateway device can match the number of memory cores, that is, query the number of candidate memory cores that match the first business complexity and the number of candidate memory cores that match the second business complexity. It is understandable that a table for the mapping relationship between business complexity and the number of candidate memory cores can be pre-configured in the gateway device, so that the gateway device can determine the number of candidate memory cores configured for the first object and the second object by directly querying the table.

[0102] For example, if the first object, i.e., the LAN side, is responsible for performing route lookup, message detection, NAT conversion, etc. on request messages, and the service complexity is higher than that of the second object, i.e., the WAN side, then a larger number of candidate memory cores can be allocated to the first object. For example, when the gateway device is an 18-core device, the first object can have 11 first candidate memory cores, and the second object can have 6 second candidate memory cores.

[0103] Step S1206 , determining a plurality of first candidate memory cores that match the number of the first candidate memory cores, and a plurality of second candidate memory cores that match the number of the second candidate memory cores.

[0104] Exemplarily, after the gateway device determines the number of first candidate memory cores and the number of second candidate memory cores, a corresponding number of first candidate memory cores and second candidate memory cores may be configured.

[0105] In this embodiment, by analyzing the business complexity of the first object and the second object, the number of memory cores is determined, and then an appropriate number of memory cores are configured for the first object and the second object for message scheduling and message processing, further improving the message forwarding efficiency.

[0106] In an exemplary embodiment, a request message is processed through a first memory core to obtain a target message, including: type identification of the request message is performed through the first memory core to obtain a first message type of the request message; based on a message processing method that matches the first message type, message processing is performed on the request message to obtain a target message.

[0107] The first message type refers to the message type of the request message, including NAT message and IPsec message. The message processing method includes NAT conversion and IPsec encryption.

[0108] Exemplarily, referring to FIG2, when the first memory core processes the request message, it can first identify the message type of the request message according to the message field of the request message, such as the target IP, that is, whether the request message belongs to a NAT message or an IPsec message. When the request message belongs to a NAT message, the first memory core can perform NAT conversion on the request message and then send it out. When the request message belongs to an IPsec message, the first memory core can perform IPsec encryption on the request message and then send it out.

[0109] In this embodiment, the type of the request message is identified to determine the corresponding message processing method, thereby ensuring the accuracy of the message processing.

[0110] In a specific embodiment, as shown in FIG13 , FIG13 shows a schematic diagram of message forwarding. The EDGE gateway device is an 18-core device, that is, a device with 18 CPUs (memory cores). EDGE allocates 11 CPUs (CPU1 to CPU11) to the LAN side device and 6 CPUs (CPU12 to CPU18) to the WAN side network according to the respective service complexity of the LAN side device and the WAN side network.

[0111] When the first object, i.e., the LAN side device, sends a request message to the second object, i.e., the WAN side network, CPU1 receives the request message as the message receiving memory core, and performs hash processing on the source IP address of the request message to obtain the corresponding hash value. The hash value is used to match the next CPU scheduled by the request message, i.e., any one of CPU2 to CPU11. The CPU performs NAT conversion or IPsec encryption on the request message to obtain the target message. The CPU forwards the target message to the WAN side network.

[0112] When the WAN side network returns the corresponding response message to the LAN side device, CPU12 receives the response message as the message receiving memory core. First, identify the message type of the response message. When the response message belongs to a NAT message, perform NAT message scheduling, that is, according to the target port number, schedule the response message to CPU2 to CPU11 for NAT conversion. The CPU that processes the response message and the request message is the same CPU. When the response message belongs to an IPsec message, CPU12 will schedule the response message to any one of CPUs from CPU13 to CPU18 for IPsec decryption processing. Then schedule the decrypted message to CPU2 to CPU11 for LAN side business processing.

[0113] In this embodiment, when the LAN side device sends a request message to the WAN side network, the EDGE gateway device first obtains the source address information of the request message. The source address information is hashed to obtain the first hash value of the source address information. Then, among the multiple CPUs used to process the request message, the first CPU matching the first hash value is screened out, and the request message is processed by the first CPU to obtain the first target message, and the first target message is forwarded to the WAN side network. In other words, this embodiment performs hashing on the address information to screen out the CPU used for message processing. Due to the consistency of the hash function, the request message and the response message will generate the same hash value, thereby ensuring that the request message and the response message are processed by the same CPU. That is, each CPU can maintain the message session information of this core, and there is no need to synchronize threads with other CPUs, effectively avoiding the overhead of thread synchronization. In this way, not only can the performance of the EDGE gateway device be improved, but also the parallel execution of message forwarding can be realized, thereby improving the efficiency of message forwarding.

[0114] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0115] Based on the same inventive concept, the embodiment of the present application also provides a message forwarding device for implementing the message forwarding method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more message forwarding device embodiments provided below can refer to the limitations on the message forwarding method above, and will not be repeated here.

[0116] In an exemplary embodiment, as shown in FIG14 , a message forwarding device is provided, including: an information acquisition module 1402, used to obtain source address information of a request message when a first object sends a request message to a second object; a hash processing module 1404, used to perform hash processing on the source address information to obtain a first hash value of the source address information; a memory core determination module 1406, used to screen out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; a message processing module 1408, used to perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.

[0117] In one of the embodiments, the device is also used to: when the second object returns a response message to the first object in response to the request message, identify the type of the response message to obtain a second message type of the response message; when the second message type is an address conversion message, obtain the target port number of the response message; filter out a second memory core that matches the target port number from multiple first candidate memory cores; perform message processing on the response message through the second memory core to obtain a second target message, and send the second target message to the first object.

[0118] In one of the embodiments, the device is also used to: when the second message type is an encrypted message, obtain the number of memory cores of multiple second candidate memory cores for processing the response message; based on the number of memory cores, filter out a third memory core from the multiple second candidate memory cores; decrypt the response message through the third memory core to obtain a decrypted message; hash the target address information of the decrypted message to obtain a second hash value of the target address information; filter out a fourth memory core that matches the second hash value from multiple first candidate memory cores; process the decrypted message through the fourth memory core to obtain a third target message, and send the third target message to the first object.

[0119] In one of the embodiments, the request message includes at least one sub-message, and the device is also used to: determine the target sub-message ranked first among each sub-message; if the target sub-message exists in the message cache list, read the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0120] In one of the embodiments, the device is also used to: perform business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determine the number of first candidate memory cores that match the first business complexity and the number of second candidate memory cores that match the second business complexity; determine multiple first candidate memory cores that match the first candidate memory cores and multiple second candidate memory cores that match the second candidate memory cores.

[0121] In one embodiment, the message processing module 1408 is also used to: identify the type of the request message through the first memory core to obtain a first message type of the request message; and process the request message based on a message processing method that matches the first message type to obtain a target message.

[0122] Each module in the above-mentioned message forwarding device can be implemented in whole or in part by software, hardware and a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0123] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG15. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store message forwarding data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a message forwarding method is implemented.

[0124] Those skilled in the art will understand that the structure shown in FIG. 15 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0125] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: when a first object sends a request message to a second object, the source address information of the request message is obtained; the source address information is hashed to obtain a first hash value of the source address information; among multiple first candidate memory cores for performing message processing on the request message, a first memory core matching the first hash value is screened out; the request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object.

[0126] In one embodiment, the processor also implements the following steps when executing the computer program: when the second object returns a response message to the first object in response to the request message, the response message is type identified to obtain a second message type of the response message; when the second message type is an address conversion message, the target port number of the response message is obtained; from multiple first candidate memory cores, a second memory core that matches the target port number is screened out; through the second memory core, the response message is message processed to obtain a second target message, and the second target message is sent to the first object.

[0127] In one embodiment, the processor also implements the following steps when executing the computer program: when the second message type is an encrypted message, obtain the number of memory cores of multiple second candidate memory cores for message processing of the response message; based on the number of memory cores, screen out a third memory core from the multiple second candidate memory cores; decrypt the response message through the third memory core to obtain a decrypted message; hash the target address information of the decrypted message to obtain a second hash value of the target address information; screen out a fourth memory core that matches the second hash value from the multiple first candidate memory cores; process the decrypted message through the fourth memory core to obtain a third target message, and send the third target message to the first object.

[0128] In one embodiment, when the processor executes the computer program, the following steps are also implemented: determining the target sub-message ranked first among the sub-messages; if the target sub-message exists in the message cache list, reading the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0129] In one embodiment, when the processor executes the computer program, the following steps are also implemented: performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determining a first candidate memory core quantity that matches the first business complexity and a second candidate memory core quantity that matches the second business complexity; determining a plurality of first candidate memory cores that match the first candidate memory core quantity and a plurality of second candidate memory cores that match the second candidate memory core quantity.

[0130] In one embodiment, when the processor executes the computer program, the following steps are also implemented: through the first memory core, the type of the request message is identified to obtain the first message type of the request message; based on the message processing method matching the first message type, the request message is processed to obtain the target message.

[0131] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: when a first object sends a request message to a second object, source address information of the request message is obtained; the source address information is hashed to obtain a first hash value of the source address information; among multiple first candidate memory cores for performing message processing on the request message, a first memory core that matches the first hash value is screened out; the request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object.

[0132] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the second object returns a response message to the first object in response to the request message, the type of the response message is identified to obtain a second message type of the response message; when the second message type is an address conversion message, the target port number of the response message is obtained; from multiple first candidate memory cores, a second memory core that matches the target port number is screened out; through the second memory core, the response message is processed to obtain a second target message, and the second target message is sent to the first object.

[0133] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the second message type is an encrypted message, the number of memory cores of multiple second candidate memory cores for processing the response message is obtained; based on the number of memory cores, a third memory core is screened out from the multiple second candidate memory cores; the response message is decrypted by the third memory core to obtain a decrypted message; the target address information of the decrypted message is hashed to obtain a second hash value of the target address information; a fourth memory core that matches the second hash value is screened out from the multiple first candidate memory cores; the decrypted message is processed by the fourth memory core to obtain a third target message, and the third target message is sent to the first object.

[0134] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the target sub-message ranked first among each sub-message; if the target sub-message exists in the message cache list, reading the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0135] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determining a first candidate memory core quantity that matches the first business complexity and a second candidate memory core quantity that matches the second business complexity; determining a plurality of first candidate memory cores that match the first candidate memory core quantity and a plurality of second candidate memory cores that match the second candidate memory core quantity.

[0136] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: through the first memory core, the type of the request message is identified to obtain the first message type of the request message; based on the message processing method matching the first message type, the request message is processed to obtain the target message.

[0137] In one embodiment, a computer program product is provided, including a computer program, which implements the following steps when executed by a processor: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; screening out a first memory core that matches the first hash value from a plurality of first candidate memory cores for performing message processing on the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.

[0138] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the second object returns a response message to the first object in response to the request message, the type of the response message is identified to obtain a second message type of the response message; when the second message type is an address conversion message, the target port number of the response message is obtained; from multiple first candidate memory cores, a second memory core that matches the target port number is screened out; through the second memory core, the response message is processed to obtain a second target message, and the second target message is sent to the first object.

[0139] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the second message type is an encrypted message, the number of memory cores of multiple second candidate memory cores for processing the response message is obtained; based on the number of memory cores, a third memory core is screened out from the multiple second candidate memory cores; the response message is decrypted by the third memory core to obtain a decrypted message; the target address information of the decrypted message is hashed to obtain a second hash value of the target address information; a fourth memory core that matches the second hash value is screened out from the multiple first candidate memory cores; the decrypted message is processed by the fourth memory core to obtain a third target message, and the third target message is sent to the first object.

[0140] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the target sub-message ranked first among each sub-message; if the target sub-message exists in the message cache list, reading the target sub-message and other sub-messages except the target sub-message from the message cache list.

[0141] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determining a first candidate memory core quantity that matches the first business complexity and a second candidate memory core quantity that matches the second business complexity; determining a plurality of first candidate memory cores that match the first candidate memory core quantity and a plurality of second candidate memory cores that match the second candidate memory core quantity.

[0142] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: through the first memory core, the type of the request message is identified to obtain the first message type of the request message; based on the message processing method matching the first message type, the request message is processed to obtain the target message.

[0143] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0144] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0145] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0146] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A message forwarding method, characterized in that: The method comprises: When the first object sends a request message to the second object, obtaining source address information of the request message; Performing hash processing on the source address information to obtain a first hash value of the source address information; Screening out a first memory core that matches the first hash value from among a plurality of first candidate memory cores for processing the request message; The request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object.

2. The method according to claim 1, characterized in that The method further comprises: When the second object returns a response message to the first object in response to the request message, performing type identification on the response message to obtain a second message type of the response message; When the second message type is an address translation message, obtaining a target port number of the response message; Filtering out a second memory core matching the target port number from the plurality of first candidate memory cores; The response message is processed by the second memory core to obtain a second target message, and the second target message is sent to the first object.

3. The method according to claim 2, characterized in that The method further comprises: When the second message type is an encrypted message, obtaining the number of memory cores of a plurality of second candidate memory cores for performing message processing on the response message; Based on the number of memory cores, selecting a third memory core from the plurality of second candidate memory cores; Decrypting the response message through the third memory core to obtain a decrypted message; Performing hash processing on the target address information of the decrypted message to obtain a second hash value of the target address information; Filtering out a fourth memory core matching the second hash value from the plurality of first candidate memory cores; The decrypted message is processed by the fourth memory core to obtain a third target message, and the third target message is sent to the first object.

4. The method according to claim 1, characterized in that: The request message includes at least one sub-message, and the method further includes: Determine the target sub-message ranked first among the sub-messages; In the case that the target sub-message exists in the message cache list, the target sub-message and other sub-messages except the target sub-message are read from the message cache list.

5. The method according to claim 1, characterized in that The method further comprises: Performing business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; Determine a first candidate number of memory cores that matches the first business complexity, and a second candidate number of memory cores that matches the second business complexity; A plurality of first candidate memory cores matching the number of the first candidate memory cores and a plurality of second candidate memory cores matching the number of the second candidate memory cores are determined.

6. The method according to claim 1, characterized in that The step of performing message processing on the request message through the first memory core to obtain a target message includes: Performing type identification on the request message through the first memory core to obtain a first message type of the request message; Based on a message processing method matching the first message type, message processing is performed on the request message to obtain a target message.

7. A message forwarding device, characterized in that: The device comprises: An information acquisition module, used to acquire source address information of a request message when the first object sends a request message to the second object; A hash processing module, used to perform hash processing on the source address information to obtain a first hash value of the source address information; a memory core determination module, configured to screen out a first memory core that matches the first hash value from among a plurality of first candidate memory cores for processing the request message; A message processing module is used to perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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