Data caching method for CIS (Contact Image Sensor) linear array camera

Abstract

The invention discloses a data caching method for a CIS (Contact Image Sensor) linear array camera, belongs to the field of image acquisition and processing, and particularly designs a back-end data caching technology for a CIS linear array sensor. The main purpose is to cache segmented images collected by an ADC to an FPGA and output the segmented images to a high-speed interface. The data sequence is rearranged in the data writing stage, a row of complete images in a Z shape are written into a plurality of RAMs with the calculated number, and a fixed number of RAMs are selected in sequence in the reading stage and output to a rear-end module. Data caching and image splicing processing from ADC data to a high-speed interface are realized, and the system has the characteristics of high speed, large bandwidth, high real-time performance and high development efficiency.

Description

Technical Field

[0001] The present invention relates to the field of image acquisition and processing, and in particular to a back-end data caching method for a CIS linear array sensor. Background Art

[0002] CIS cameras usually use multiple ADCs for front-end data acquisition. The collected data needs to be cached in sequence into the FPGA on-chip RAM and then sent in parallel to high-speed interface IPs such as Coaxpress.

[0003] The data buffer module is the most important part of the entire image acquisition system. It processes the data flow from ADC to the high-speed interface. There are several cache solutions for the current CIS image acquisition system. First, write the data of each ADC channel into an independent RAM and then use high-multiple clock sampling to achieve the effect of parallel output. This method is limited by the maximum operating clock frequency and timing requirements of the FPGA device and is only suitable for low-speed transmission; second, write the data of each ADC channel into an independent RAM and then cut the data into several blocks for parallel output, and finally use software to restore the image. This solution has high requirements for computer software and poor real-time performance; in addition, FIFO can also be used for serial-to-parallel conversion for special input and output bandwidth ratios. This solution is only applicable to a small number of cameras and it is difficult to meet the data acquisition requirements of most cameras;

[0004] Purpose of the Invention

[0005] Based on the prior art, the present invention provides a new data caching solution for CIS linear array cameras, which rearranges the data order in the RAM writing stage, thereby realizing data buffering and serial-to-parallel conversion of FPGA under a single clock. For CIS camera sensors, a single-line image is cut into several parts, which are sampled in parallel by multiple ADC channels to increase the sampling speed. Each channel receives the pixels of each segment of the image sequentially. High-speed interfaces such as Coaxpress require that multiple adjacent pixels be transmitted in parallel per clock cycle. If a continuous segment of an image is stored in each RAM, read conflicts will inevitably occur during the transmission process. The present invention proposes a new data caching order to solve this problem.

[0006] The technical solution of the present invention is: a CIS linear array camera data caching method, the method comprising:

[0007] Step 1: Use FIFO to synchronize the data collected by ADC with the line and clock;

[0008] Step 2: Deserialize the synchronized data;

[0009] Step 3: Allocate the deserialized data of each Channel to the corresponding position of RAM;

[0010] Step 4: The cache system performs ping-pong operations according to external read and write control signals to ensure data integrity;

[0011] Step 5: When reading data, read the data in the RAM sequentially and output it to the high-speed interface.

[0012] Furthermore, the specific method of allocating data to the corresponding position of RAM in step 3 is:

[0013] Step 3.1: Rearrange the data order during the RAM writing phase, calculate the number of RAMs to be written as n, and these n RAMs are closely arranged;

[0014] Step 3.2: Store the first data into RAM1, the second data into RAM2, the third data into RAM3, ..., the nth data into RAMn, the n+1th data into RAM1, the n+2th data into RAM2, the n+3th data into RAM3, ...

[0015] According to the above method, write a complete row of images into the entire column of RAM in a "Z" shape;

[0016] When reading in step 5, a fixed number of RAMs are selected in sequence during the RAM reading process and merged for output.

[0017] Furthermore, the number of RAMs, the starting address and starting RAM of each channel data, and the mapping conversion period are determined by three parameters: the number of ADC channels, the bit width of the high-speed interface data port, and the single-channel data length;

[0018] ram=(ch*sensor_length)%ram_num

[0019]

[0020] Where, ch is the current channel index, sensor_length is the number of pixels in a single channel, ram_num is the required RAM quantity, ram is the starting RAM index of the current channel, and addr is the starting address of the current channel;

[0021] The number of RAMs is determined by enumeration. The initial value is determined as the maximum value of the number of channels and the pixel width of the high-speed interface. If the initial RAM index corresponding to each channel is repeated, the number of RAMs is increased by 1 until there is no conflict. % represents the remainder. The entire functional module is implemented parameterized. By modifying parameters such as the number of ADCs and the length of a single channel, the compiler automatically calculates the starting state of the RAM read and write process, the step size of the address jump, etc., and automatically generates the hardware circuit to implement the corresponding function without reprogramming.

[0022] Furthermore, the specific method of step 4 is:

[0023] Select the 3-line cache scheme for ping-pong operation, and the read and write control signals are generated by an external module; when the first write signal rises, the first line of the image is written into RAM group A; when the next write signal comes, the second line of the image is written into RAM group B; then the third line of the image is written into RAM group C... and so on; on the other hand, when the read signal rises, if the system is writing B at this time, then read A, write C read B, write A read C. Ensure that the image read is the complete image closest to the read time.

[0024] The implementation of the present invention can solve the data caching problem of almost all CIS sampling data to the high-speed interface, can well constrain the timing under a single clock, and can save computer memory overhead and improve real-time performance by completing image sorting on FPGA. By rearranging the data order in the data writing stage, a complete line of image "Z" shape is written into a calculated number of RAMs, and a fixed number of RAMs are selected in sequence to output to the back-end module in the reading stage. Data caching and image splicing processing from ADC data to the high-speed interface are realized, which has the characteristics of high speed, large bandwidth, high real-time performance and high development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the image cache.

[0026] Figure 2 This is the system block diagram of the data cache module. DETAILED DESCRIPTION

[0027] The embodiment of the present invention provides a method for data buffering of a CIS linear array camera, so that a person skilled in the art can understand and implement the present invention. The present invention is further described below. The steps are as follows:

[0028] Step 1: Select a model of CIS camera, determine its number of channels, number of pixels per channel, and high-speed interface data width; build the image front-end acquisition system except the cache module; instantiate the cache module at the top level, and modify parameters such as the number of channels, number of pixels per channel, and high-speed interface data width. After completing the system simulation verification, you can capture CIS images and transfer them to the acquisition card. Use FIFO to synchronize the data collected by ADC with lines and clocks;

[0029] Step 2: Deserialize the synchronized data;

[0030] When deserializing, a single ADC with 9 parallel acquisition channels and 10-bit accuracy is used. The first clock cycle outputs channels 1, 2, and 3 in parallel, the second clock cycle outputs channels 4, 5, and 6, the third clock cycle outputs channels 7, 8, and 9, and so on. The 3n+1th clock cycle outputs channels 1, 2, and 3, the 3n+2th clock cycle outputs channels 4, 5, and 6, the 3n+1th clock cycle outputs channels 7, 8, and 9, and so on.

[0031] In specific implementation, a state machine is used to control the ADC deserialization process. The state jumps cyclically between the 3n+1th clock cycle, the 3n+2th clock cycle, and the 3n+3th clock cycle. The state changes once in each clock cycle, n=0, 1, 2, 3...; in order to ensure the data phase synchronization of each channel, the data obtained in the 3n+1th clock cycle, the 3n+2th clock cycle, and the state will be latched in the register and finally output synchronously in the 3n+3th clock cycle.

[0032] Step 3: Allocate the deserialized data of each Channel to the corresponding position of RAM;

[0033] Step 4: The cache system performs ping-pong operations according to external read and write control signals to ensure data integrity;

[0034] According to the size of the FPGA on-chip resources, the number of cached image rows is adjusted through parameters, and a 3-row cache solution is selected; compared with the traditional 2-row cache solution, 3-row cache has more spare time during the cache process, which avoids the problem of read and write data conflicts to the greatest extent. In addition, it improves image quality when the read and write line frequencies do not match, and reduces the occurrence of image line drops. The specific implementation method of the cache system performing ping-pong operations according to external read and write control signals is as follows:

[0035] The read and write control signals are generated by an external module. When the first write signal rises, the first line of the image is written into RAM group A; when the next write signal comes, the second line of the image is written into RAM group B; then the third line of the image is written into RAM group C... and so on. On the other hand, when the read signal rises, if the system is writing B at this time, A is read, if C is written, B is read, and if A is written, C is read. This ensures that the image read is the complete image closest to the read moment.

[0036] Step 5: When reading data, read the data in the RAM sequentially and output it to the high-speed interface.

Claims

1. A CIS linear array camera data caching method, the method comprising: Step 1: Use FIFO to synchronize the data collected by ADC with the line and clock; Step 2: Deserialize the synchronized data; Step 3: Allocate the deserialized data of each Channel to the corresponding position of RAM; Step 3.1: Rearrange the data order during the RAM writing phase, calculate the number of RAMs to be written as n, and these n RAMs are closely arranged; Step 3.2: Store the first data into RAM1, the second data into RAM2, the third data into RAM3, ..., the nth data into RAMn, the n+1th data into RAM1, the n+2th data into RAM2, the n+3th data into RAM3, ... According to the above method, write a complete row of images into the entire column of RAM in a "Z" shape; Step 4: The cache system performs ping-pong operations according to external read and write control signals to ensure data integrity; Step 5: When reading data, select a fixed number of RAMs in sequence and merge them to output to the high-speed interface.

2. A CIS line array camera data caching method as claimed in claim 1, characterized in that: When deserializing in step 2, a single ADC with 9 parallel acquisition channels is used, with 10-bit accuracy. Channels 1, 2, and 3 are output in parallel in the first clock cycle, channels 4, 5, and 6 are output in the second clock cycle, channels 7, 8, and 9 are output in the third clock cycle, ..., channels 1, 2, and 3 are output in the 3n+1th clock cycle, channels 4, 5, and 6 are output in the 3n+2th clock cycle, channels 7, 8, and 9 are output in the 3n+1th clock cycle, ..., and so on. In the process of using the state machine to control ADC deserialization, the state jumps cyclically between the 3n+1th clock cycle, the 3n+2th clock cycle, and the 3n+3th clock cycle, and the state changes once in each clock cycle, n=0, 1, 2, 3...; in order to ensure the data phase synchronization of each channel, the data obtained in the state of the 3n+1th clock cycle and the 3n+2th clock cycle will be latched in the register and finally output synchronously in the state of the 3n+3th clock cycle.

3. A CIS line array camera data caching method as claimed in claim 1, characterized in that: The number of RAMs, the starting address and starting RAM of each channel data, and the mapping conversion cycle are determined by three parameters: the number of ADC channels, the bit width of the high-speed interface data port, and the single-channel data length; ram=(ch*sensor_length)%ram_num Where, ch is the current channel index, sensor_length is the number of pixels in a single channel, ram_num is the required RAM quantity, ram is the starting RAM index of the current channel, and addr is the starting address of the current channel; The number of RAMs is determined by enumeration. The initial value is determined as the maximum value of the number of channels and the pixel width of the high-speed interface. If the initial RAM index corresponding to each channel is repeated, the number of RAMs is increased by 1 until no conflict occurs. % represents the remainder operation.

4. A CIS line array camera data caching method as claimed in claim 1, characterized in that: The specific method of step 4 is: A 3-line cache scheme is selected for ping-pong operation, and the read and write control signals are generated by an external module. When the first write signal rises, the first line of the image is written into RAM group A. When the next write signal rises, the second line of the image is written into RAM group B. Then the third line of the image is written into RAM group C... and so on. On the other hand, when the read signal rises, if the system is writing B at this time, A is read, if C is written, B is read, and if A is written, C is read. This ensures that the read image is the complete image closest to the read moment.

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