Multi-channel SAR (Synthetic Aperture Radar) data recombination device in packet switching system

Abstract

The embodiment of the invention provides a multi-channel SAR data recombination device in a packet switching system, and the device comprises an SAR packet processing module which is used for serially receiving and analyzing SAR frames of N channels, writing OUDk payload data and channel numbers in the SAR frames into a multi-channel data caching module, and writing payload lengths and channel numbers into a multi-channel packet length sequence caching module; the request generation module is used for generating a reading request signal aiming at the ith channel, and sending the reading request signal and the generation moment of each reading request to the output cache module; when the output cache module detects that a read request signal queue stored in the output cache module is not empty, a ready signal is output; and the scheduling module determines a target channel, schedules a reading request signal from the output cache module corresponding to the target channel, and sends a target channel identification number and a time delay compensation value to the data reading module. Through the time division multiplexing processing, the logic resource consumption of a plurality of channels is greatly saved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a device for reassembling multi-channel SAR data in a packet switching system. Background Art

[0002] In recent years, OTN (Optical Transport Network) technology has gradually become one of the mainstream technologies in the field of optical communications.

[0003] In the traditional field of OTN, ODUk (Optical Data Unit k) is used to carry 1.25G~100G customer services, and the k value represents different rates. The characteristics of ODUk data are that the rate is fixed and the rate of the transmission code stream contains the corresponding clock information. At present, there are protocols that define the specific implementation methods of segmenting and reassembling ODUk data, so that ODUk data can be cross-transmitted in the packet switching system. This functional module is referred to as the SAR (Segmentation and Reassembly) module.

[0004] In the OTN packet switching system, the SAR module is divided into two directions: Ingress (ingress) and Egress (egress). The function of the Ingress SAR module is to convert the fixed-rate ODUk data stream into packet form and send it to the packet switching network. The function of the Egress SAR module is to process the packet format sent from the backplane packet switching network and restore it to the ODUk data stream, while recovering the clock information in the ODUk data stream.

[0005] In recent years, as the fgOTN (fine grain OTN, fine-grained optical transport network) core standard was submitted for approval by ITU-T, fgODUk (fine grain ODUk, fine-grained optical data unit k) particles for services below 1G rate were added. The rate of fgODUk particles is Nx10Mhz (N<=119), which is characterized by small bandwidth and a large number of channels. A large number of small-bandwidth fgODUk particles need to be transmitted in the packet switching backplane network, which puts forward new requirements for the processing capacity of the SAR module. If each fgODUk uses a separate SAR module, a large number of SAR modules processing fgODUk services will consume a lot of resources, resulting in a large amount of resource waste in the system, making it impossible for fgODUk particles to achieve packet switching at a low cost. Summary of the invention

[0006] The purpose of the embodiment of the present application is to provide a multi-channel SAR data reorganization device in a packet switching system, which performs time-division multiplexing on the SAR packet reorganization module, the low-pass filter module, and the export OTN module, thereby saving the logical resource consumption of multiple channels.

[0007] The specific technical solutions are as follows:

[0008] In a first aspect of the present application, a device for reassembling multi-channel SAR data in a packet switching system is provided, comprising:

[0009] A SAR packet processing module, configured to receive and parse SAR frames of N channels, write the payload data and the channel number in the SAR frame into a multi-channel data buffer module, and write the payload length and the channel number into a multi-channel packet length sequence buffer module;

[0010] N request generation modules and N output buffer modules, each channel corresponds to a request generation module and an output buffer module; the request generation module of the i-th channel is used to generate a read request signal according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module; the output buffer module outputs a ready signal when detecting that a cache queue for storing the read request signal is not empty; the payload length compensation value is calculated according to the payload length;

[0011] A scheduling module is used to detect whether the output buffer module corresponding to each channel outputs a ready signal, determine the target channel for the channel that outputs the ready signal, schedule a read request from the output buffer module corresponding to the target channel, and send the target channel identification number and delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay;

[0012] The data reading module is used to read the payload data of a preset length of the target channel from the multi-channel data buffer module according to the target channel identification number, and input the payload data and the delay compensation value into the delay compensation module;

[0013] The delay compensation module is used to perform delay compensation on the payload data according to the delay compensation value.

[0014] Optionally, the SAR packet processing module is specifically used to switch to the register state of the corresponding channel according to the channel number of the received SAR packet, and parse and process the SAR packet.

[0015] Optionally, the request generation module includes a frequency division controller circuit, the frequency division controller circuit is pre-configured with first parameters, the first parameters include an integration step parameter C, an overflow period P, and clock compensation information FB2;

[0016] The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to the first parameter.

[0017] Optionally, the frequency division controller circuit is specifically used for:

[0018] According to the rate of the reference clock signal, based on the accumulated value, the integral step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1=CNT0+C-FB+FB2, CNT0 is the accumulated value before the first operation is performed in the current round; CNT1 is the accumulated value after the first operation is performed in the current round;

[0019] When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned to P, CNT0 is assigned to 0, a high level is generated, the generation time is recorded, and the first operation is returned to execute; when it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned to 0, and the first operation is returned to execute.

[0020] Optionally, the clock compensation information FB2 is calculated using the following formula:

[0021] FB2=CLK×C / P / data bit width;

[0022] Wherein, CLK represents the rate of the reference clock signal; the data bit width is the bit width of the payload data read by the data reading module each time.

[0023] Optionally, the payload length is {B-1, B, B+1}.

[0024] Optionally, the scheduling module is specifically used to detect whether the output buffer module corresponding to each channel outputs a ready signal, and for the channel that outputs the ready signal, determine the target channel according to a preset priority order; wherein the priority order is positively correlated with the size of the channel bandwidth.

[0025] Optionally, the scheduling module is also used to input the delay compensation value and the target channel identification number into a clock compensation calculation module connected to a multi-channel packet length sequence cache module, so as to trigger the clock compensation calculation module to read the payload length sequence of the target channel from the multi-channel packet length sequence cache module, and calculate the clock compensation information based on the payload length sequence.

[0026] Optionally, the clock compensation calculation module is specifically used to average the payload length sequence of the target channel and calculate the clock compensation information according to the payload length mean.

[0027] Optionally, the SAR frames of the N channels come from a switching network, and a jitter compensation module is provided between the switching network and the SAR packet processing module, and the jitter compensation module is used to compensate for jitter and delay generated by the SAR frames in the switching network.

[0028] Beneficial effects of the embodiments of the present application:

[0029] The embodiment of the present application provides a multi-channel SAR data reorganization device in a packet switching system, a SAR packet processing module, which is used to serially receive and parse SAR frames of N channels, write the OUDk payload data and channel number in the SAR frame into a multi-channel data cache module, and write the payload length and the channel number into a multi-channel packet length sequence cache module; each channel corresponds to a request generation module and an output cache module, the request generation module of the i-th channel is used to generate a read request signal for the i-th channel according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when detecting that the read request signal queue stored in itself is not empty; the payload length is used to generate a read request signal for the i-th channel according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when detecting that the read request signal queue stored in itself is not empty; The length compensation value is calculated based on the payload length; the scheduling module detects whether the output cache module corresponding to each channel outputs a ready signal, determines the target channel for the channel that outputs the ready signal, and schedules a read request signal from the output cache module corresponding to the target channel, and sends the target channel identification number and the delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay; the data reading module reads the OUDk payload data of a preset length from the multi-channel data cache module according to the target channel identification number, and inputs the OUDk payload data and the delay compensation value into the delay compensation module; the delay compensation module is used to perform delay compensation on the OUDk payload data according to the delay compensation value.

[0030] Therefore, through time division multiplexing processing, the SAR packet reassembly module, the low-pass filter module, and the export OTN module are time-division multiplexed, thereby greatly saving the logic resource consumption of multiple channels.

[0031] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic diagram of an implementation scheme of a multi-channel SAR module in the related art;

[0034] Figure 2 A first structural diagram of a device for reassembling multi-channel SAR data in a packet switching system provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a delay compensation module provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the circuit structure of the Sigma-Detla controller provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the operation flow of the circuit of the Sigma-Detla controller provided in an embodiment of the present application;

[0038] Figure 6 A second structural diagram of a device for reassembling multi-channel SAR data in a packet switching system provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of input data and output data of a recombinant device provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of implementing time division multiplexing in a recombining device for multi-channel SAR data in a packet switching system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0042] For ease of understanding, a brief introduction to the relevant technologies is given. Figure 1 , which is a schematic diagram of an implementation scheme of a multi-channel SAR module in the related art, such as Figure 1As shown in the figure, each SAR module corresponds to one channel of ODUk data, and there are k channels of data in the figure, namely ODU0-ODUk. Multiple channels of ODUk are generated by copying and instantiating. The Ingress OTN (ingress optical transport network circuit) module splits the multiple channels of ODUk data streams and sends them to the multiple Ingress SAR (ingress segmentation circuit) modules. After generating the corresponding SAR packets, they are combined and enter the packet switching network. After passing through the packet switching network, the SAR packets of the corresponding channels are extracted from one multi-channel data stream and sent to the multiple Egress SAR (egress reassembly circuit) modules, and the clock and data streams are recovered. Then, the corresponding ODUk data is sent out, and a total of k channels of data are output, namely ODU0-ODUk. After that, they are combined through the Egress OTN module.

[0043] However, using Figure 1 In the implementation scheme shown, in the application scenario of fgODU, when there are multiple channels of ODUk and fgODUk data, the specifications are often hundreds of channels, which will require a large number of Ingress SAR modules and Egress SAR modules, resulting in a large waste of resources.

[0044] In addition, the data of multiple SAR channels are in the form of multiple channels. If multiple channels need to be mapped into one channel, additional combining and splitting adapter modules are required.

[0045] In order to solve the above technical problems, the embodiment of the present application provides a device for reassembling multi-channel SAR data in a packet switching system. Figure 2 , which is a first structural diagram of a multi-channel SAR data reorganization device in a packet switching system provided in an embodiment of the present application, the device includes: a SAR packet processing module, a multi-channel packet length sequence cache module, a request generation module, an output cache module, a scheduling module, a multi-channel data cache module, a data reading module, and a delay compensation module. Each module is introduced in detail below.

[0046] The SAR packet processing module is used to receive and parse the SAR frames of N channels, write the payload data and channel number in the SAR frames into the multi-channel data buffer module, and write the payload length and channel number into the multi-channel packet length sequence buffer module.

[0047] The reassembly device provided in the embodiment of the present application is inputted with SAR frames processed by a switching network. The SAR packet processing module receives SAR frames of N channels in a serial manner.

[0048] The SAR packet processing module processes the SAR frame, including: parsing the message header, performing parity check, packet length extraction and other operations. After checking that there are no errors, the packet length value and channel number are sent to the multi-channel packet length sequence cache module, and the payload data and channel number are sent to the multi-channel data cache module.

[0049] The packet length value is the payload data, that is, the ODUk data carried in the SAR frame, and the packet length value is the payload length, that is, the length of the ODUk data. It should be noted that the receiving rate of the SAR frame is the same, and the rate of ODUk in the frame is characterized by the payload length. The protocol specifies the length value as {B-1, B, B+1}.

[0050] In the embodiment of the present application, for N channels, the SAR packet processing module processes SAR frames in a time-division multiplexing manner. That is, the SAR packet processing module includes a register group set for each channel, so that the SAR packet processing module switches to the register state of the corresponding channel according to the channel number of the received SAR packet, and then parses and processes the SAR packet.

[0051] The data that needs to be stored in the register group is pre-specified in the protocol.

[0052] When an error occurs in the parsing, the content of the packet is discarded and corresponding replacement information and warning information are generated. This part of the processing is clearly described in the protocol and will not be described in detail.

[0053] In the embodiment of the present application, a request generation module and an output cache module are provided for each channel, that is, each channel corresponds to a request generation module and an output cache module, the processing process is the same, and the request generation modules and output cache modules of different channels are processed in parallel.

[0054] Taking the i-th channel as an example, the request generation module of the i-th channel is used to generate a read request signal according to the reference clock signal and the payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module.

[0055] Among them, the actual processing process of the request generation module is the frequency division process, that is, the frequency division is performed according to the reference clock signal. During the frequency division process, fine-tuning is performed based on the payload length compensation value of the corresponding channel, and finally the divided clock signal is obtained. Since the clock signal is used to guide the reading of ODUk data, it is called a request acquisition signal, which is specifically composed of high and low levels, and each high level corresponds to a read request.

[0056] For a specific implementation of fine-tuning the clock frequency division process according to the payload length compensation value, see below.

[0057] After generating the read request signal, the request generation module records the generation time of each read request, that is, the time when each high level is generated, which is recorded as T1. The request generation module inputs the high and low level signals representing the read request into the output buffer module, and also inputs the generation time of each high level into the output buffer module.

[0058] Taking the i-th channel as an example, a cache queue for storing a read request signal is set in the output cache module. If the cache queue is not empty, it means that there is currently ODUk data of the i-th channel that needs to be scheduled, and the output cache module will output a ready signal. The ready signal can be a high-level signal of a specific pin, which is used to inform the scheduling module that there is currently ODUk data that needs to be scheduled.

[0059] In addition, the number of high levels in the buffer queue is the same as the number of times required for scheduling. For example, if the buffer queue of the output buffer module of the i-th channel contains two high level signals, it means that the ODUk data of the i-th channel needs to be scheduled twice.

[0060] In the reorganization device provided in the embodiment of the present application, the scheduling module also performs scheduling based on time division multiplexing for N channels.

[0061] Specifically, the scheduling module is connected to the output buffer modules of N channels at the same time. The scheduling module detects in real time whether the output buffer module corresponding to each channel outputs a ready signal, and determines the target channel from the channel that outputs the ready signal, that is, the ODUk data of the target channel needs to be read currently.

[0062] After the target channel is determined, a read request needs to be scheduled from the output buffer module corresponding to the target channel, so that the number of high levels representing the read request in the output buffer module is reduced by one.

[0063] In one embodiment of the present application, priority orders can be preconfigured for different channels, and the scheduling module performs scheduling according to the priority order. For example, when the scheduling module detects that the output buffer modules of multiple channels all output ready signals, a channel is determined as the target channel according to the priority order.

[0064] As an example, the bandwidth values ​​of various channels are inconsistent. In order to schedule data with large bandwidth first, the priority order can be configured to be positively correlated with the channel bandwidth.

[0065] For example, the order of the incoming Ready (ready signal) is rearranged so that the existing Ready signal group arranged by channel number (Readyn, Readym, ····, Ready0) becomes a Ready signal group arranged from small to large according to bandwidth (Ready (Bmax), Readyn, Ready0, ····, ReadyB (min)), which is convenient for scheduling by the scheduling module. Ready (Bmin) indicates the ready signal generated by the output buffer module corresponding to the channel with the largest bandwidth, and ReadyB (min) indicates the ready signal generated by the output buffer module corresponding to the channel with the smallest bandwidth.

[0066] It should be noted that since the scheduling module performs scheduling based on time division multiplexing, the generated read request cannot be scheduled immediately, but is temporarily stored in the output cache module for a period of time before scheduling, which will cause a delay. That is, the delay can be understood as the delay caused by scheduling data from other channels through time division multiplexing. Therefore, the scheduling module needs to calculate the delay compensation value for subsequent compensation of the delay.

[0067] Specifically, the scheduling module needs to input the target channel identification number into the data reading module so that the data reading module reads data from the corresponding channel.

[0068] When the scheduling module sends the data to be output to the export, the current time T2 is recorded, which is the time when the scheduling is completed. The delay compensation value Tc can be calculated according to the following formula:

[0069] Tc=T2-T1-Td

[0070] Among them, Td represents the data processing delay of the scheduling module, which is the time required for the scheduling module to process data and is a fixed value. If the scheduling module does not perform time division multiplexing, but processes the read request at the first time, then T2-T1=Td, but due to the delay caused by scheduling the data of other channels through time division multiplexing, T2 is further delayed, so T2-T1-Td is the delay that needs to be compensated.

[0071] The scheduling module sends the target channel identification number and the delay compensation value to the data reading module. The data reading module reads the payload data of the preset length of the corresponding channel from the multi-channel data buffer module, and then inputs the payload data and the delay compensation value into the delay compensation module.

[0072] The delay compensation module is used to perform delay compensation on the payload data based on the delay compensation value.

[0073] In one embodiment of the present application, the delay compensation module may be a variable delay FIFO (First Input First Output) module. The FIFO has a maximum delay Tn, and the delay can be controlled to be Tn-Tc by inputting Tc, thereby offsetting the delay of this module. Figure 3 As shown, Figure 3 A structural diagram of a delay compensation module provided in an embodiment of the present application. Among them, the variable delay FIFO module is used to compensate for the delay of the OUDk payload data according to the delay compensation value, input data at the data input time, and the corresponding data input Tc is 2. As shown in the figure, the data output time is advanced, and the advance output time is advanced by Tc=2 units compared to the normal input time, thereby realizing compensation for the delay.

[0074] That is to say, for each channel, each read ODUk data needs to pass through the variable delay FIFO module, each piece of data corresponds to a delay compensation value, and the delay is compensated by the variable delay FIFO module to ensure that the ODUk data output from the variable delay FIFO module is continuous.

[0075] As can be seen from the above, the multi-channel SAR data reorganization device in the packet switching system provided by the embodiment of the present application, the SAR packet processing module, is used to serially receive and parse the SAR frames of N channels, write the OUDk payload data and the channel number in the SAR frame into the multi-channel data cache module, and write the payload length and the channel number into the multi-channel packet length sequence cache module; each channel corresponds to a request generation module and an output cache module, the request generation module of the i-th channel is used to generate a read request signal for the i-th channel according to the reference clock signal and the payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when it detects that the read request signal queue stored in itself is not empty; The payload length compensation value is calculated based on the payload length; the scheduling module detects whether the output cache module corresponding to each channel outputs a ready signal, determines the target channel for the channel that outputs the ready signal, and schedules a read request signal from the output cache module corresponding to the target channel, and sends the target channel identification number and the delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay; the data reading module reads the OUDk payload data of a preset length from the multi-channel data cache module according to the target channel identification number, and inputs the OUDk payload data and the delay compensation value into the delay compensation module; the delay compensation module is used to perform delay compensation on the OUDk payload data according to the delay compensation value.

[0076] Therefore, through time division multiplexing processing, the SAR packet reassembly module, the low-pass filter module, and the export OTN module are time-division multiplexed, thereby greatly saving the logic resource consumption of multiple channels.

[0077] In addition, when the SAR packets in the Egress direction are reassembled, it is necessary to generate multiple ODUk clock envelopes. In the solution provided in the embodiment of the present application, a reference clock signal as a reference clock can generate multiple ODUk rate request signals, that is, generate multiple ODUk clock envelopes. And the embodiment of the present application has the function of adjusting the request rate.

[0078] Furthermore, one channel of data obtained by synthesizing data from multiple channels carries a delay jitter compensation value caused by the synthesis, thereby retaining the clock accuracy of the original data.

[0079] In one embodiment of the present application, the request generation module includes a frequency division controller circuit, the frequency division controller circuit is pre-configured with first parameters, the first parameters include an integration step parameter C, an overflow period P, and clock compensation information FB2;

[0080] The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to a first parameter.

[0081] It should be noted that there are many ways to implement the frequency division controller circuit, which is not limited in the embodiments of the present application.

[0082] In one embodiment of the present application, the frequency division controller circuit is configured as a Sigma-Detla controller circuit. The Sigma-Detla controller circuit has a simple structure, is easy to implement, and has a frequency division accuracy that fully meets the requirements of the present solution.

[0083] Those skilled in the art can understand that the rate of the ODUk transmission code stream includes the corresponding clock information. The rate of the ODUk signal not only reflects the data transmission speed, but also includes the clock information related thereto. This design ensures the stability and synchronization of the ODUk signal during the transmission process, which is crucial to ensuring the quality and reliability of data transmission.

[0084] In OTN networks, the rate and clock information of ODUk signals are crucial to ensure the correct transmission and processing of signals. By accurately controlling the rate and clock information of ODUk signals, data traffic in the network can be effectively managed to avoid data loss or delay, thereby improving the performance and efficiency of the entire network.

[0085] In one embodiment of the present application, the Sigma-Detla controller circuit is actually used to generate a clock signal, which is obtained by dividing the reference clock signal, and in the process of frequency division, the rate of the transmission code stream is taken into account, thereby generating a clock signal that matches the rate of the ODUk data transmission code rate of each channel.

[0086] Specifically, the rate of the ODUk data transmission code rate of each channel can be pre-configured, and the k in the ODUk data is used for the rate, which is specified in the protocol. Therefore, for different channels, when the reference clock signal is the same, different integration step parameters C and overflow period P are selected, and frequency division is performed on the basis of the reference clock signal to obtain a clock signal that matches the rate of the ODUk data transmission code rate adapted to the channel.

[0087] Taking a single channel as an example, the parameters of the Sigma-Detla controller circuit are configured in advance, including the integral step parameter C, the overflow period P, and the clock compensation information FB2.

[0088] During operation, the Sigma-Detla controller circuit generates a frequency-divided signal of the reference clock signal according to the configured parameters. In this process, the clock compensation information FB2 represents the controller adjustment value corresponding to different payload lengths in the SAR frame. The protocol stipulates that the payload length is {B-1, B, B+1}.

[0089] Specifically, although the ODUk data transmission code rate of each channel is pre-configured, it is difficult to ensure that the actual transmission code rate is equal to the pre-configured transmission code rate. Therefore, the protocol stipulates that in the Ingress SAR, the payload length of the SAR packet is set according to the deviation between the actual transmission code rate and the pre-configured transmission code rate.

[0090] When there is no deviation, the payload length is set to B; when there is a deviation, the payload length is set to B-1 or B+1, so that the deviation of the transmission code rate is represented by the payload length in the SAR packet.

[0091] The above settings have been clearly defined in the protocol. In the Engress SAR provided in the embodiment of the present application, the payload length is applied to the process of the Sigma-Detla controller circuit generating the frequency division clock to fine-tune the frequency division clock based on the payload length. As described above, the frequency division clock represents the signal read request signal, and fine-tuning the frequency division clock is equivalent to fine-tuning the read request signal, so that the final data reading rate matches the transmission bit rate at the input channel.

[0092] In one embodiment of the present application, the calculation formula of the clock compensation information FB2 is CLK×C / P / data bit width.

[0093] Specifically, the Sigma-Detla controller circuit specifically performs the following operations:

[0094] According to the rate of the reference clock signal, based on the accumulated value, the integral step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1=CNT0+C-FB+FB2, CNT0 is the accumulated value before the first operation is performed in the current round; CNT1 is the accumulated value after the first operation is performed in the current round;

[0095] When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned to P, CNT0 is assigned to 0, a high level is generated, the generation time is recorded, and the first operation is returned to execute; when it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned to 0, and the first operation is returned to execute.

[0096] See Figure 4 and Figure 5 , Figure 4 A schematic diagram of the circuit structure of the Sigma-Detla controller provided in an embodiment of the present application is shown in FIG. Figure 5 A schematic diagram of the operation flow of the circuit of the Sigma-Detla controller provided in an embodiment of the present application.

[0097] like Figure 4 As shown, the circuit of the Sigma-Detla controller specifically includes an integrator circuit counter, a D flip-flop, and a decision device. The two ports of the D flip-flop are the D terminal and the Q terminal. The pre-configured parameters include the integration step size C, the overflow period P, and the clock rate of the reference clock signal CLK. The decision device outputs a quantized output OUT and a feedback signal FB, and the feedback signal is input to the integrator circuit counter. The input of the integrator circuit counter also includes clock compensation information FB2.

[0098] See also Figure 5 After configuring the current channel parameters: integration step length C, overflow period P, initialize the configuration CNT0 = 0. Within one clock cycle of the reference clock signal, the integrator CNT accumulates the integration step length parameter C once, that is, the following operation is performed:

[0099] CNT1= CNT0+C-FB+FB2.

[0100] Then, it is determined whether the overflow cycle is exceeded, that is, whether the updated CNT is greater than P. If so, the valid signal OUT=1 is output, and the feedback signal FB=P is set. When OUT=1, the T1 time is recorded and the next operation is returned. The OUT signal is a high level in the frequency division signal. If not, the feedback signal FB=0 is set, and the valid signal OUT=0 is output.

[0101] It can be seen that frequency division based on the reference clock signal is achieved through a simple circuit structure, and different integration step parameters C and overflow period P are pre-configured for different channels, so that the frequency division signal is adapted to the transmission code rate of OUDk of the channel.

[0102] like Figure 4 As shown, in the process of frequency division realized by the Sigma-Detla controller circuit, FB2 is used to characterize the influence of the payload length in the SAR packet on the accumulation process. As mentioned above, the protocol stipulates that the payload length is {B-1, B, B+1}. When the payload length is B, it means that the actual transmission rate of the ODUk data of the channel is equal to the preset transmission rate, and there is no need to fine-tune the frequency division clock. At this time, the FB2 value is 0; when the payload length is B+1, it means that the transmission rate is faster than the preset transmission rate, so it is necessary to generate a high level representing the read request at a faster rate, thereby improving the accumulation speed of the Sigma-Detla controller circuit, that is, the FB2 value is a positive value. According to CNT1= From the formula CNT0+C-FB+FB2, it can be seen that when FB2 is a positive value, CNT1 will accumulate to the overflow period P faster, thereby generating a read request faster to match the transmission rate of ODUk; correspondingly, when the payload length is B-1, it means that the transmission rate at this time is slower than the preset transmission rate, so it is necessary to generate a high level representing the read request at a slower rate, thereby reducing the accumulation speed of the Sigma-Detla controller circuit, that is, the FB2 value is a negative value. According to the formula CNT1= CNT0+C-FB+FB2, when FB2 is a negative value, CNT1 will accumulate to the overflow period P more slowly, thereby generating a read request more slowly to match the transmission rate of ODUk.

[0103] It can be seen that in the reassembly device provided in the embodiment of the present application, the Sigma-Detla controller circuit is used to divide the reference clock signal to obtain the ODUk data request envelope adapted to different channels and different rates. In addition, the clock compensation information FB2 is generated according to the payload length, and the divided clock is fine-tuned to achieve matching between the input rate and the output rate of the reassembly device.

[0104] In one embodiment of the present application, the operation on the clock compensation information FB2 is performed by a clock compensation calculation module, and the clock compensation calculation module may also work in a time division multiplexing manner.

[0105] Specifically, when the scheduling module outputs the target channel identification number, the target channel identification number may be additionally output to the clock compensation calculation module to trigger the clock compensation calculation module to calculate FB2.

[0106] After receiving the target channel identification number, the clock compensation calculation module averages the payload length sequence of the target channel and calculates the clock compensation information according to the payload length mean.

[0107] Therefore, only one clock compensation calculation module needs to be provided to perform clock compensation for ODUk data of different rates, so as to generate a read request signal adapted to the ODUk data rate.

[0108] For ease of understanding, the following Figure 6 The multi-channel SAR data reorganization device in the packet switching system provided in the embodiment of the present application is further described.

[0109] See also Figure 6 , which is a second structural diagram of a multi-channel SAR data reassembly device in a packet switching system provided in an embodiment of the present application. As shown in the figure, the SAR packets of N channels come from a switching network, and a jitter compensation module is provided between the switching network and the SAR packet processing module. The jitter compensation module is used to compensate for the jitter and delay generated by the SAR frame in the switching network according to the input real-time time. This part is clearly stipulated in the protocol, and this application will not elaborate on it.

[0110] The SAR packet processing module serially receives the SAR packets and channel numbers of N channels. After receiving the SAR packet of a certain channel, it switches to the register state of the current channel, then parses and processes the SAR packet, writes the payload length and channel number into the multi-channel packet length sequence buffer module, and writes the payload data (ODUk data and channel number) into the multi-channel data buffer module.

[0111] Each channel corresponds to an ODUk envelope request generation module, which specifically includes a Sigma-Detla controller circuit and an output buffer module. According to the clock rate of the reference clock signal CLK, based on the pre-configured integration step parameter C and overflow period P, operations are performed to obtain a frequency-divided signal, and the frequency-divided signal is written into the output buffer module as a read request signal, and the generation time T1 of each read signal (i.e., the high level in the frequency-divided signal) is written into the output buffer module, wherein the generation time is based on the time information T2 generated by the local time generation module.

[0112] The output buffer module outputs a ready signal when detecting that the buffer queue for storing the read request signal is not empty.

[0113] The priority scheduling module is pre-configured with the scheduling priority of each channel, and the module specifically includes a scheduling module, a request generation monitoring module, and a delay compensation calculation module. The specific implementation is: the request generation monitoring module reads whether the output cache module corresponding to each channel outputs a ready signal. After reading the ready signal, the scheduling module selects a high-priority channel for scheduling based on the pre-configured priority, that is, the delay compensation calculation module reads a data output from the output cache module corresponding to the channel, that is, a high-level signal, and the generation time T1 of the high-level signal. Then the delay compensation calculation module calculates the delay compensation value Tc.

[0114] The priority scheduling module sends the channel number identifier to the clock compensation calculation module, which triggers the clock compensation calculation module to read the corresponding payload length sequence from the multi-channel packet length sequence cache module according to the channel number identifier, and then calculates the clock compensation information FB2. FB2 is input into the Sigma-Detla controller circuit and acts on the frequency division process to fine-tune the frequency division signal according to the payload length.

[0115] On the other hand, the priority scheduling module synchronously sends the channel number identifier and the delay compensation value Tc to the egress OTN functional module, triggering the egress OTN functional module to read the ODUk data from the multi-channel data buffer module, and the delay compensation module performs delay compensation on the ODUk data according to the delay compensation value Tc, and outputs the read ODUk data serially.

[0116] The signal envelope maintenance module included in the export OTN functional module is used to ensure that the sent ODUk data is continuous. Specifically, when the signal envelope maintenance module sends a read request and channel number data reading to the multi-channel data cache module, if the SAR packet is parsed successfully, the SAR packet processing module will write the ODUk data to the multi-channel data cache module, and the signal envelope maintenance module will obtain the ODUk data from the multi-channel data cache module and output it externally. However, if the SAR packet is parsed incorrectly, the SAR packet processing module cannot write the ODUk data to the multi-channel data cache module. Therefore, when the signal envelope maintenance module detects that the data cache of the corresponding channel is empty, indicating that the ODUk data is lost, the signal envelope maintenance module will generate a clock cycle replacement signal to maintain the continuity of the ODUk data. At the same time, an alarm message will be output.

[0117] See also Figure 7 , which is a schematic diagram of input data and output data of the recombination device provided in an embodiment of the present application, such as Figure 7 As shown, as the time value increases, the reorganization device inputs the SAR packets of multiple channels in series and the corresponding channel numbers, specifically including the SAR packet of channel 0, the SAR packet of channel a, and the like.

[0118] When the reassembly module outputs, according to ODUk and channel number, it outputs the payload data of channel 0, the payload data of channel a, the payload data of channel b, and the payload data of channel n in sequence, and the payload data is delayed according to the delay compensation Tc.

[0119] After being processed by the reassembly module provided in the embodiment of the present application, the ODUk data in the SAR packets of the multiple channels are extracted, and the ODUk data of the multiple channels are reintegrated into one channel for output.

[0120] It can be seen that the multi-channel SAR data reassembly device in the packet switching system provided by the embodiment of the present application generates a plurality of ODUk rate request signals through a reference clock, and has the function of adjusting the request rate. The data of multiple channels have been synthesized into one channel for output, and carry the delay jitter compensation value caused by the combination, retaining the accuracy of the original data clock.

[0121] Moreover, through time division multiplexing, the consumption of logic resources of multiple channels is greatly saved.

[0122] See Figure 8 , a schematic diagram of a multi-channel SAR data reorganization device in a packet switching system provided by an embodiment of the present application to implement time division multiplexing. In the multi-channel SAR data reorganization device in a packet switching system provided by an embodiment of the present application, the SAR packet reorganization module, the clock compensation calculation module and the export OTN functional module are all time-division multiplexed. The SAR packet reorganization module receives the SAR frame and the channel number N. The export OTN module outputs ODUk data + channel number N + Tc time compensation value. A register circuit for each channel can be set in the above modules as a multi-channel multiplexing information state storage circuit, from which the state of channel N is obtained, and after processing, the state of channel N is filled into the multi-channel multiplexing information state storage circuit. The multi-channel multiplexing information state storage circuit stores the SAR reorganization state cache, clock compensation state cache, and export OTN module state cache of channels 0-channel n respectively. When processing a certain channel, switch to the register state corresponding to the channel, and through time division multiplexing, a large amount of logic resources are saved in the scenario with a large number of channels.

[0123] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0124] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0125] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0126] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A device for reassembling multi-channel SAR data in a packet switching system, characterized in that: include: A segmentation and reassembly SAR packet processing module, used for receiving and parsing SAR frames of N channels, writing payload data and channel numbers in the SAR frames into a multi-channel data buffer module, and writing payload length and the channel number into a multi-channel packet length sequence buffer module; N request generation modules and N output buffer modules, each channel corresponds to a request generation module and an output buffer module; The request generation module of the i-th channel is used to generate a read request signal according to the reference clock signal and the payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module; The output cache module outputs a ready signal when detecting that the cache queue for storing the read request signal is not empty; the payload length compensation value is calculated according to the payload length; A scheduling module is used to detect whether the output buffer module corresponding to each channel outputs a ready signal, determine the target channel for the channel that outputs the ready signal, schedule a read request from the output buffer module corresponding to the target channel, and send the target channel identification number and delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay; The data reading module is used to read the payload data of a preset length of the target channel from the multi-channel data buffer module according to the target channel identification number, and input the payload data and the delay compensation value into the delay compensation module; The delay compensation module is used to perform delay compensation on the payload data according to the delay compensation value.

2. The device according to claim 1, characterized in that The SAR packet processing module is specifically used to switch to the register state of the corresponding channel according to the channel number of the received SAR packet, and parse and process the SAR packet.

3. The device according to claim 1, characterized in that The request generation module includes a frequency division controller circuit, and the frequency division controller circuit is pre-configured with first parameters, and the first parameters include an integration step parameter C, an overflow period P, and clock compensation information FB2; The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to the first parameter.

4. The device according to claim 3, characterized in that The frequency division controller circuit is specifically used for: According to the rate of the reference clock signal, based on the accumulated value, the integral step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1=CNT0+C-FB+FB2, CNT0 is the accumulated value before the first operation is performed in the current round; CNT1 is the accumulated value after the first operation is performed in the current round; When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned a value of P, CNT0 is assigned a value of 0, a high level is generated, the generation time is recorded, and the first operation is returned to execute; When it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned a value of 0, and the first operation is executed again.

5. The device according to claim 4, characterized in that The clock compensation information FB2 is calculated using the following formula: FB2=CLK×C / P / data bit width; Wherein, CLK represents the rate of the reference clock signal; the data bit width is the bit width of the payload data read by the data reading module each time.

6. The device according to any one of claims 1 to 5, characterized in that: The payload length is {B-1, B, B+1}.

7. The device according to claim 1, characterized in that The scheduling module is specifically used to detect whether the output buffer module corresponding to each channel outputs a ready signal, and for the channel that outputs the ready signal, determine the target channel according to a preset priority order; The priority order is positively correlated with the channel bandwidth.

8. The device according to claim 2, characterized in that The scheduling module is also used to input the delay compensation value and the target channel identification number into a clock compensation calculation module connected to a multi-channel packet length sequence cache module, so as to trigger the clock compensation calculation module to read the payload length sequence of the target channel from the multi-channel packet length sequence cache module, and calculate the clock compensation information based on the payload length sequence.

9. The device according to claim 8, characterized in that The clock compensation calculation module is specifically used to average the payload length sequence of the target channel and calculate the clock compensation information according to the payload length mean.

10. The device according to claim 1, characterized in that The SAR frames of N channels come from a switching network. A jitter compensation module is provided between the switching network and the SAR packet processing module. The jitter compensation module is used to compensate for jitter and delay generated by the SAR frames in the switching network.

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