A multi-channel SAR data reassembly device in a packet switching system

Abstract

An embodiment of the present application provides a multi-channel SAR data reassembly device in a packet switching system, comprising: a SAR packet processing module for serially receiving and parsing SAR frames from N channels, writing the OUDk payload data and channel number in the SAR frames to a multi-channel data cache module, and writing the payload length and channel number to a multi-channel packet length sequence cache module; a request generation module for generating a read request signal for the i-th channel, and sending the read request signal and the generation time of each read request to an output cache module; the output cache module outputs a ready signal when detecting that the read request signal queue stored in the output cache module is not empty; and a scheduling module for determining a target channel, scheduling a read request signal from the output cache module corresponding to the target channel, and sending the target channel identification number and delay compensation value to the data reading module. Through time-division multiplexing processing, the logical resource consumption of multiple channels is significantly reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a device for reassembling multi-channel SAR data in a packet switching system. Background Art

[0002] In recent years, Optical Transport Network (OTN) technology has gradually become one of the mainstream technologies in the field of optical communications.

[0003] In traditional OTN, Optical Data Unit k (ODUk) carries 1.25G to 100G customer services, with the k value representing different data rates. ODUk data is characterized by a fixed rate, and the transmission rate of the bit stream includes corresponding clock information. Currently, protocols define specific methods for segmenting and reassembling ODUk data, enabling cross-transmission of ODUk data across packet switching systems. This functional module is referred to as the Segmentation and Reassembly (SAR) module.

[0004] In an OTN packet switching system, SAR modules are used for both ingress and egress. The ingress SAR module converts fixed-rate ODUk data streams into packets and sends them to the packet switching network. The egress SAR module converts packets sent from the backplane packet switching network back into ODUk data streams and recovers the clock information in the ODUk data streams.

[0005] In recent years, with the approval of the fgOTN (fine-grain OTN) core standard by the ITU-T, the fgODUk (fine-grain ODUk) granularity has been added for services with sub-1G rates. The fgODUk granularity has a rate of N x 10 MHz (N <= 119), characterized by low bandwidth and a large number of channels. The need to transmit a large number of these low-bandwidth fgODUk granularities across a packet-switched backplane network places new demands on the processing capabilities of the SAR module. If each fgODUk channel uses a separate SAR module, the large number of SAR modules processing fgODUk services would consume a significant amount of resources, resulting in significant system resource waste and making it impossible to implement packet switching of fgODUk granularity at low cost. Summary of the Invention

[0006] The purpose of the embodiment of the present application is to provide a device for reassembling multi-channel SAR data in a packet switching system, which uses time-division multiplexing to time-division multiplex the SAR packet reassembly module, the low-pass filter module, and the egress OTN module, thereby saving the logical resource consumption of multiple channels.

[0007] The specific technical solutions are as follows:

[0008] In a first aspect of the present application, a device for reassembling multi-channel SAR data in a packet switching system is provided, comprising:

[0009] A SAR packet processing module is configured to receive and parse SAR frames of N channels, write the payload data and channel number in the SAR frames into a multi-channel data buffer module, and write the payload length and the channel number into a multi-channel packet length sequence buffer module;

[0010] N request generation modules and N output buffer modules, one request generation module and one output buffer module corresponding to each channel; the request generation module of the i-th channel is used to generate a read request signal based on a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module; the output buffer module outputs a ready signal when detecting that a cache queue for storing the read request signal is not empty; the payload length compensation value is calculated based on the payload length;

[0011] The scheduling module is configured to detect whether the output buffer module corresponding to each channel outputs a ready signal, determine the target channel for the channel that outputs the ready signal, schedule a read request from the output buffer module corresponding to the target channel, and send the target channel identification number and delay compensation value to the data reading module, where the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1, and the processing delay;

[0012] The data reading module is configured to read the payload data of a preset length of the target channel from the multi-channel data buffer module according to the target channel identification number, and input the payload data and the delay compensation value into the delay compensation module;

[0013] The delay compensation module is configured to perform delay compensation on the payload data according to the delay compensation value.

[0014] Optionally, the SAR packet processing module is specifically used to switch to the register state of the corresponding channel according to the channel number of the received SAR packet, and parse and process the SAR packet.

[0015] Optionally, the request generating module includes a frequency division controller circuit, the frequency division controller circuit is pre-configured with first parameters, the first parameters including an integration step parameter C, an overflow period P, and clock compensation information FB2;

[0016] The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to the first parameter.

[0017] Optionally, the frequency division controller circuit is specifically used for:

[0018] According to the rate of the reference clock signal, based on the accumulated value, the integration step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1 = CNT0 + C-FB + FB2, where CNT0 is the accumulated value before the first operation in the current round; CNT1 is the accumulated value after the first operation in the current round;

[0019] When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned to P, CNT0 is assigned to 0, a high level is generated, the generation time is recorded, and the first operation is executed again. When it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned to 0, and the first operation is executed again.

[0020] Optionally, the clock compensation information FB2 is calculated using the following formula:

[0021] FB2=CLK×C / P / data bit width;

[0022] Wherein, CLK represents the rate of the reference clock signal; the data bit width is the bit width of the payload data read by the data reading module each time.

[0023] Optionally, the payload length is {B-1, B, B+1}.

[0024] Optionally, the scheduling module is specifically used to detect whether the output buffer module corresponding to each channel outputs a ready signal, and for the channel that outputs the ready signal, determine the target channel according to a preset priority order; wherein the priority order is positively correlated with the size of the channel bandwidth.

[0025] Optionally, the scheduling module is also used to input the delay compensation value and the target channel identification number into a clock compensation calculation module connected to a multi-channel packet length sequence cache module, so as to trigger the clock compensation calculation module to read the payload length sequence of the target channel from the multi-channel packet length sequence cache module, and calculate the clock compensation information based on the payload length sequence.

[0026] Optionally, the clock compensation calculation module is specifically configured to average the payload length sequences of the target channel and calculate the clock compensation information according to the payload length mean.

[0027] Optionally, the SAR frames of the N channels come from a switching network, and a jitter compensation module is provided between the switching network and the SAR packet processing module, and the jitter compensation module is used to compensate for jitter and delay generated by the SAR frames in the switching network.

[0028] Beneficial effects of the embodiments of the present application:

[0029] The embodiment of the present application provides a device for reassembling multi-channel SAR data in a packet switching system, a SAR packet processing module, which is used to serially receive and parse SAR frames of N channels, write the OUDk payload data and channel number in the SAR frame into a multi-channel data cache module, and write the payload length and the channel number into a multi-channel packet length sequence cache module; each channel corresponds to a request generation module and an output cache module, the request generation module of the i-th channel is used to generate a read request signal for the i-th channel according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when detecting that the read request signal queue stored in itself is not empty; the payload length is used to generate a read request signal for the i-th channel according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when detecting that the read request signal queue stored in itself is not empty; The length compensation value is calculated based on the payload length; the scheduling module detects whether the output cache module corresponding to each channel outputs a ready signal, determines the target channel for the channel that outputs the ready signal, and schedules a read request signal from the output cache module corresponding to the target channel, and sends the target channel identification number and delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay; the data reading module reads the OUDk payload data of a preset length from the multi-channel data cache module according to the target channel identification number, and inputs the OUDk payload data and the delay compensation value into the delay compensation module; the delay compensation module is used to perform delay compensation on the OUDk payload data according to the delay compensation value.

[0030] Therefore, through time division multiplexing processing, the SAR packet reassembly module, low-pass filter module, and egress OTN module are time-division multiplexed, thereby significantly saving the logic resource consumption of multiple channels.

[0031] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0033] Figure 1 Schematic diagram of an implementation scheme of a multi-channel SAR module in the related art;

[0034] Figure 2 A schematic diagram of a first structure of a device for reassembling multi-channel SAR data in a packet switching system provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a delay compensation module provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the circuit structure of the Sigma-Detla controller provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the operation flow of the circuit of the Sigma-Detla controller provided in an embodiment of the present application;

[0038] Figure 6 A second structural diagram of the device for reassembling multi-channel SAR data in a packet switching system provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of input data and output data of a recombinant device provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of a device for reassembling multi-channel SAR data in a packet switching system according to an embodiment of the present application for implementing time division multiplexing. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0042] For ease of understanding, a brief introduction to related technologies is given. Figure 1 , which is a schematic diagram of an implementation scheme of a multi-channel SAR module in related technology, such as Figure 1As shown in the figure, each SAR module corresponds to one channel of ODUk data, for a total of k channels, designated ODU0 through ODUk. Multiple ODUk channels are generated through replication and instantiation. The Ingress OTN (Ingress Optical Transport Network) module splits the multiple ODUk data streams and sends them to the multi-channel Ingress SAR (Ingress Segmentation) module. After generating the corresponding SAR packets, they are combined and sent to the packet switching network. After passing through the packet switching network, the SAR packets corresponding to the channel are extracted from the multi-channel data stream and sent to the multi-channel Egress SAR (Egress Reassembly) module for clock and data recovery. The corresponding ODUk data is then sent out, for a total of k channels, designated ODU0 through ODUk. The Egress OTN module then combines the packets.

[0043] However, the use of Figure 1 In the implementation scheme shown in the fgODU application scenario, when there are multiple channels of ODUk and fgODUk data, the specifications may reach hundreds of channels, requiring a large number of ingress SAR modules and egress SAR modules, resulting in a large waste of resources.

[0044] In addition, the data of multiple SAR channels are in the form of multiple channels. If multiple channels need to be mapped into one channel, additional combining and splitting adaptation modules are required.

[0045] In order to solve the above technical problems, the embodiment of the present application provides a multi-channel SAR data reassembly device in a packet switching system. Figure 2 , which is a first structural diagram of a multi-channel SAR data reassembly device in a packet switching system provided in an embodiment of the present application. The device includes: a SAR packet processing module, a multi-channel packet length sequence buffer module, a request generation module, an output buffer module, a scheduling module, a multi-channel data buffer module, a data reading module, and a delay compensation module. Each module is introduced in detail below.

[0046] The SAR packet processing module is used to receive and parse the SAR frames of N channels, write the payload data and channel number in the SAR frames into the multi-channel data buffer module, and write the payload length and channel number into the multi-channel packet length sequence buffer module.

[0047] The reassembly device provided in the embodiment of the present application is inputted with SAR frames processed by a switching network. The SAR packet processing module receives SAR frames of N channels in a serial manner.

[0048] The SAR packet processing module processes the SAR frame, specifically including: parsing the message header, performing parity check, packet length extraction and other operations. After checking that there are no errors, the packet length value and channel number are sent to the multi-channel packet length sequence cache module, and the payload data and channel number are sent to the multi-channel data cache module.

[0049] The packet length value is the payload data, i.e., the ODUk data carried in the SAR frame, and the packet length value is the payload length, i.e., the length of the ODUk data. It should be noted that the receive rate of SAR frames is the same, and the ODUk rate in the frame is represented by the payload length, which the protocol specifies as {B-1, B, B+1}.

[0050] In this embodiment of the present application, the SAR packet processing module processes SAR frames for N channels in a time-division multiplexing manner. Specifically, the SAR packet processing module includes a register set for each channel. Thus, based on the channel number of a received SAR packet, the SAR packet processing module switches to the register state corresponding to the channel and then parses and processes the SAR packet.

[0051] The data that needs to be stored in the register group is pre-specified in the protocol.

[0052] When an error occurs in the parsing, the packet content is discarded and corresponding replacement information and warning information are generated. This part of the processing is clearly described in the protocol and will not be described in detail.

[0053] In the embodiment of the present application, a request generation module and an output cache module are provided for each channel, that is, each channel corresponds to a request generation module and an output cache module, the processing process is the same, and the request generation modules and output cache modules of different channels are processed in parallel.

[0054] Taking the i-th channel as an example, the request generation module of the i-th channel is used to generate a read request signal according to the reference clock signal and the payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module.

[0055] The actual processing process of the request generation module is the frequency division process, that is, the frequency is divided according to the reference clock signal. During the frequency division process, fine-tuning is performed based on the payload length compensation value of the corresponding channel to finally obtain the divided clock signal. Since this clock signal is used to guide the reading of ODUk data, it is called the request acquisition signal. Specifically, it consists of high and low levels, and each high level corresponds to a read request.

[0056] The specific implementation of fine-tuning the clock frequency division process according to the payload length compensation value is described below.

[0057] After generating a read request signal, the request generation module records the time each read request is generated, that is, the time each high level is generated, recorded as T1. The request generation module inputs the high and low level signals representing the read request into the output buffer module, and also inputs the time each high level is generated into the output buffer module.

[0058] Taking the i-th channel as an example, the output buffer module is equipped with a buffer queue for storing read request signals. If the buffer queue is not empty, it indicates that there is ODUk data for the i-th channel that needs to be scheduled. The output buffer module will then output a ready signal. This ready signal can be a high-level signal on a specific pin, used to inform the scheduling module that there is ODUk data that needs to be scheduled.

[0059] In addition, the number of high-level signals in the buffer queue is the same as the number of times scheduling is required. For example, if the buffer queue of the output buffer module of the i-th channel contains two high-level signals, it means that the ODUk data of the i-th channel needs to be scheduled twice.

[0060] In the recombining device provided in the embodiment of the present application, the scheduling module also performs scheduling based on time division multiplexing for N channels.

[0061] Specifically, the scheduling module is connected to the output buffer modules of N channels at the same time. The scheduling module detects in real time whether the output buffer module corresponding to each channel outputs a ready signal. For the channel that outputs the ready signal, the target channel is determined, that is, the ODUk data of the target channel needs to be read.

[0062] After the target channel is determined, a read request needs to be scheduled from the output buffer module corresponding to the target channel, so that the number of high levels representing the read request in the output buffer module is reduced by one.

[0063] In one embodiment of the present application, priority orders can be preconfigured for different channels, and the scheduling module performs scheduling based on the priority order. For example, when the scheduling module detects that the output buffer modules of multiple channels all output ready signals, it determines a channel as the target channel based on the priority order.

[0064] As an example, the bandwidth values ​​of various channels are inconsistent. In order to prioritize the scheduling of data with larger bandwidth, the priority order can be configured to be positively correlated with the channel bandwidth.

[0065] For example, the order of incoming Ready signals is reordered, so that the existing Ready signal group, which was arranged by channel number (Readyn, Readym, ..., Ready0), becomes a Ready signal group arranged by bandwidth from smallest to largest (Ready (Bmax), Readyn, Ready0, ..., ReadyB (min)). This facilitates scheduling by the scheduling module. Ready (Bmin) indicates the ready signal generated by the output buffer module corresponding to the channel with the largest bandwidth, while ReadyB (min) indicates the ready signal generated by the output buffer module corresponding to the channel with the smallest bandwidth.

[0066] It's important to note that because the scheduling module uses time-division multiplexing (TDM) for scheduling, generated read requests aren't immediately dispatched. Instead, they're temporarily stored in the output buffer module for a period of time before being scheduled, resulting in a delay. This delay can be understood as the delay incurred by scheduling data from other channels through TDM. Therefore, the scheduling module needs to calculate a delay compensation value to compensate for this delay.

[0067] Specifically, the scheduling module needs to input the target channel identification number into the data reading module so that the data reading module reads data from the corresponding channel.

[0068] When the scheduling module sends the data to be output to the export, the current time T2 is recorded, which is the time when the scheduling is completed. The delay compensation value Tc can be calculated according to the following formula:

[0069] Tc=T2-T1-Td

[0070] Td represents the data processing delay of the scheduling module, which is a fixed value and represents the time required for the scheduling module to process data. If the scheduling module does not perform time division multiplexing and processes read requests immediately, then T2 - T1 = Td. However, due to the delay in scheduling data from other channels through time division multiplexing, T2 is further delayed. Therefore, T2 - T1 - Td is the delay that needs to be compensated.

[0071] The scheduling module sends the target channel identification number and delay compensation value to the data reading module. The data reading module reads the payload data of the preset length of the corresponding channel from the multi-channel data buffer module, and then inputs the payload data and delay compensation value into the delay compensation module.

[0072] The delay compensation module is used to perform delay compensation on the payload data based on the delay compensation value.

[0073] In one embodiment of the present application, the delay compensation module can be a variable delay FIFO (First Input First Output) module. The FIFO has a maximum delay Tn and can control the delay to be Tn-Tc by inputting Tc, thereby offsetting the delay of this module. Figure 3 As shown, Figure 3 A schematic diagram of the structure of a delay compensation module provided in an embodiment of the present application. The variable delay FIFO module is used to compensate for the delay of the OUDk payload data based on the delay compensation value. If data is input at the data input time and the corresponding data input Tc is 2, as shown in the figure, the data output time is advanced by Tc = 2 units compared to the normal input time, thereby achieving delay compensation.

[0074] That is to say, for each channel, each read ODUk data needs to pass through the variable delay FIFO module. Each piece of data corresponds to a delay compensation value. The delay is compensated by the variable delay FIFO module to ensure that the ODUk data output from the variable delay FIFO module is continuous.

[0075] As can be seen from the above, the embodiment of the present application provides a multi-channel SAR data reassembly device in a packet switching system, a SAR packet processing module, which is used to serially receive and parse SAR frames of N channels, write the OUDk payload data and channel number in the SAR frame into a multi-channel data cache module, and write the payload length and the channel number into a multi-channel packet length sequence cache module; each channel corresponds to a request generation module and an output cache module, the request generation module of the i-th channel is used to generate a read request signal for the i-th channel according to a reference clock signal and a payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output cache module; the output cache module outputs a ready signal when it detects that the read request signal queue stored in itself is not empty; The payload length compensation value is calculated based on the payload length; the scheduling module detects whether the output cache module corresponding to each channel outputs a ready signal, determines the target channel for the channel that outputs the ready signal, and schedules a read request signal from the output cache module corresponding to the target channel, and sends the target channel identification number and the delay compensation value to the data reading module, wherein the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1 and the processing delay; the data reading module reads the OUDk payload data of a preset length from the multi-channel data cache module according to the target channel identification number, and inputs the OUDk payload data and the delay compensation value into the delay compensation module; the delay compensation module is used to perform delay compensation on the OUDk payload data according to the delay compensation value.

[0076] Therefore, through time division multiplexing processing, the SAR packet reassembly module, low-pass filter module, and egress OTN module are time-division multiplexed, thereby significantly saving the logic resource consumption of multiple channels.

[0077] Furthermore, when SAR packets are reassembled in the egress direction, multiple ODUk clock envelopes need to be generated. The solution provided in this embodiment of the application uses a reference clock signal to generate request signals for multiple ODUk rates, thereby generating multiple ODUk clock envelopes. This embodiment also includes a request rate adjustment function.

[0078] Furthermore, the data obtained by synthesizing the data of multiple channels carries the delay jitter compensation value caused by the combination, thereby retaining the clock accuracy of the original data.

[0079] In one embodiment of the present application, the request generation module includes a frequency division controller circuit, which is pre-configured with first parameters, the first parameters including an integration step parameter C, an overflow period P, and clock compensation information FB2;

[0080] The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to a first parameter.

[0081] It should be noted that there are many ways to implement the frequency division controller circuit, which is not limited in the embodiments of the present application.

[0082] In one embodiment of the present application, the frequency division controller circuit is configured as a Sigma-Detla controller circuit. The Sigma-Detla controller circuit has a simple structure, is easy to implement, and its frequency division accuracy fully meets the requirements of this solution.

[0083] Those skilled in the art will appreciate that the ODUk transmission stream rate includes corresponding clock information. The ODUk signal rate not only reflects the data transmission speed but also includes related clock information. This design ensures the stability and synchronization of the ODUk signal during transmission, which is crucial for ensuring the quality and reliability of data transmission.

[0084] In OTN networks, the rate and clock information of ODUk signals are crucial to ensuring correct signal transmission and processing. By precisely controlling the rate and clock information of ODUk signals, data traffic in the network can be effectively managed, avoiding data loss or delay, thereby improving the performance and efficiency of the entire network.

[0085] In one embodiment of the present application, the Sigma-Detla controller circuit is actually used to generate a clock signal, which is obtained by dividing the reference clock signal. In addition, during the division process, the rate of the transmission code stream is taken into account, thereby generating a clock signal that matches the rate of the ODUk data transmission code rate of each channel.

[0086] Specifically, the ODUk data transmission rate for each channel can be preconfigured. The k in the ODUk data is used for this rate and is specified in the protocol. Therefore, for different channels, while the reference clock signal is the same, different integration step parameters C and overflow period P are selected. Frequency division is performed on the reference clock signal to obtain a clock signal that matches the ODUk data transmission rate for that channel.

[0087] Taking a single channel as an example, the parameters of the Sigma-Detla controller circuit are configured in advance, including the integration step parameter C, the overflow period P, and the clock compensation information FB2.

[0088] During operation, the Sigma-Detla controller circuit generates a frequency-divided signal of the reference clock signal according to the configured parameters. During this process, the clock compensation information FB2 represents the controller adjustment value corresponding to different payload lengths in the SAR frame. The protocol stipulates that the payload length is {B-1, B, B+1}.

[0089] Specifically, although the ODUk data transmission code rate of each channel is pre-configured, it is difficult to ensure that the actual transmission code rate is equal to the pre-configured transmission code rate. Therefore, the protocol stipulates that in the ingress SAR, the payload length of the SAR packet is set according to the deviation between the actual transmission code rate and the pre-configured transmission code rate.

[0090] When there is no deviation, the payload length is set to B; when there is a deviation, the payload length is set to B-1 or B+1, so that the deviation of the transmission code rate is represented by the payload length in the SAR packet.

[0091] The above settings are clearly defined in the protocol. In the Engress SAR provided in the embodiments of this application, the payload length is applied to the Sigma-Detla controller circuit during the frequency division clock generation process to fine-tune the frequency division clock based on the payload length. As described above, the frequency division clock represents the read request signal. Fine-tuning the frequency division clock is equivalent to fine-tuning the read request signal, so that the final data read rate matches the transmission bit rate of the input channel.

[0092] In one embodiment of the present application, the calculation formula of the clock compensation information FB2 is CLK×C / P / data bit width.

[0093] Specifically, the Sigma-Detla controller circuit performs the following operations:

[0094] Based on the rate of the reference clock signal, the accumulated value, the integration step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1 = CNT0 + C-FB + FB2, where CNT0 is the accumulated value before the first operation in the current round; CNT1 is the accumulated value after the first operation in the current round.

[0095] When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned to P, CNT0 is assigned to 0, a high level is generated, the generation time is recorded, and the first operation is executed again. When it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned to 0, and the first operation is executed again.

[0096] See Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the circuit structure of the Sigma-Detla controller provided in an embodiment of the present application. Figure 5 Schematic diagram of the operation flow of the circuit of the Sigma-Detla controller provided in an embodiment of the present application.

[0097] like Figure 4 As shown, the Sigma-Detla controller circuit specifically includes an integrator counter, a D flip-flop, and a decision circuit. The D flip-flop has two terminals, D and Q. Preconfigured parameters include the integration step size C, the overflow period P, and the clock rate of the reference clock signal CLK. The decision circuit outputs a quantized output OUT and a feedback signal FB, which is input to the integrator counter. The integrator counter also includes clock compensation information FB2.

[0098] See also Figure 5 After configuring the current channel parameters: integration step C, overflow period P, initialize the configuration CNT0 = 0. Within one clock cycle of the reference clock signal, the integrator CNT accumulates the integration step parameter C once, that is, the following operation is performed:

[0099] CNT1= CNT0+C-FB+FB2.

[0100] Next, a determination is made as to whether the overflow period has been exceeded—that is, whether the updated CNT is greater than P. If so, a valid signal OUT = 1 is output, and the feedback signal FB = P. When OUT = 1, the time T1 is recorded and the next operation is returned. The OUT signal is a high level in the divided signal. If not, the feedback signal FB = 0, and a valid signal OUT = 0 is output.

[0101] It can be seen that frequency division based on the reference clock signal is achieved through a simple circuit structure, and different integration step parameters C and overflow period P are pre-configured for different channels, so that the frequency-divided signal is adapted to the transmission code rate of the OUDk of the channel.

[0102] like Figure 4 As shown in the figure, in the process of frequency division implemented by the Sigma-Detla controller circuit, FB2 is used to characterize the influence of the payload length in the SAR packet on the accumulation process. As mentioned above, the protocol stipulates that the payload length is {B-1, B, B+1}. When the payload length is B, it means that the actual transmission rate of the ODUk data of the channel is equal to the preset transmission rate, and there is no need to fine-tune the frequency division clock. At this time, the FB2 value is 0; when the payload length is B+1, it means that the transmission rate is faster than the preset transmission rate. Therefore, it is necessary to generate a high level representing the read request at a faster rate, thereby improving the accumulation speed of the Sigma-Detla controller circuit, that is, the FB2 value is positive. According to CNT1= From the formula CNT0+C-FB+FB2, it can be seen that when FB2 is a positive value, CNT1 accumulates to the overflow period P more quickly, thereby generating a read request more quickly to match the ODUk transmission rate. Correspondingly, when the payload length is B-1, it indicates that the transmission rate is slower than the preset transmission rate. Therefore, a high level representing a read request needs to be generated at a slower rate. Therefore, the accumulation speed of the Sigma-Detla controller circuit is reduced, that is, the FB2 value becomes negative. According to the formula CNT1= CNT0+C-FB+FB2, when FB2 is a negative value, CNT1 accumulates to the overflow period P more slowly, thereby generating a read request more slowly to match the ODUk transmission rate.

[0103] As can be seen, the reassembly device provided in this embodiment of the present application uses a Sigma-Detla controller circuit to divide the reference clock signal to obtain ODUk data request envelopes adapted to different channels and rates. Furthermore, clock compensation information FB2 is generated based on the payload length, and the divided clock is fine-tuned to achieve matching between the input and output rates of the reassembly device.

[0104] In one embodiment of the present application, the operation on the clock compensation information FB2 is performed by a clock compensation calculation module, and the clock compensation calculation module may also operate in a time division multiplexing manner.

[0105] Specifically, when the scheduling module outputs the target channel identification number, the target channel identification number may be additionally output to the clock compensation calculation module to trigger the clock compensation calculation module to calculate FB2.

[0106] After receiving the target channel identification number, the clock compensation calculation module averages the payload length sequence of the target channel and calculates the clock compensation information according to the average value of the payload length.

[0107] Therefore, only one clock compensation calculation module needs to be provided to perform clock compensation for ODUk data of different rates, so as to generate a read request signal adapted to the ODUk data rate.

[0108] For ease of understanding, the following Figure 6 The multi-channel SAR data reassembly device in the packet switching system provided in the embodiment of the present application is further described.

[0109] See also Figure 6 This is a schematic diagram of the second structure of a multi-channel SAR data reassembly device in a packet switching system provided by an embodiment of the present application. As shown, SAR packets from N channels originate from a switching network. A jitter compensation module is provided between the switching network and the SAR packet processing module. This module compensates for jitter and delay incurred by SAR frames in the switching network based on the input real-time time. This section is clearly defined in the protocol and will not be elaborated upon in this application.

[0110] The SAR packet processing module serially receives SAR packets and channel numbers of N channels. After receiving the SAR packet of a certain channel, it switches to the register state of the current channel, then parses the SAR packet, writes the payload length and channel number into the multi-channel packet length sequence buffer module, and writes the payload data (ODUk data and channel number) into the multi-channel data buffer module.

[0111] Each channel corresponds to an ODUk envelope request generation module, which specifically includes a Sigma-Detla controller circuit and an output buffer module. Based on the clock rate of the reference clock signal CLK, it performs calculations based on the pre-configured integration step parameter C and overflow period P to obtain a frequency-divided signal. The frequency-divided signal is written into the output buffer module as a read request signal. The generation time T1 of each read signal (i.e., the high level in the frequency-divided signal) is also written into the output buffer module. The generation time is based on the time information T2 generated by the local time generation module.

[0112] The output buffer module outputs a ready signal when detecting that the buffer queue for storing the read request signal is not empty.

[0113] The priority scheduling module is preconfigured with the scheduling priority of each channel. It specifically includes a scheduling module, a request generation monitoring module, and a delay compensation calculation module. Specifically, the request generation monitoring module checks whether the output buffer module corresponding to each channel has output a ready signal. Upon receiving a ready signal, the scheduling module selects the highest-priority channel for scheduling based on the preconfigured priority. Specifically, the delay compensation calculation module reads a data output (i.e., a high-level signal) from the output buffer module corresponding to that channel, along with the time T1 at which this high-level signal was generated. The delay compensation calculation module then calculates the delay compensation value, Tc.

[0114] The priority scheduling module sends the channel number identifier to the clock compensation calculation module, which triggers the clock compensation calculation module to read the corresponding payload length sequence from the multi-channel packet length sequence cache module according to the channel number identifier, and then calculates the clock compensation information FB2. FB2 is input into the Sigma-Detla controller circuit and acts on the frequency division process to fine-tune the frequency division signal according to the payload length.

[0115] On the other hand, the priority scheduling module synchronously sends the channel number identifier and the delay compensation value Tc to the egress OTN functional module, triggering the egress OTN functional module to read the ODUk data from the multi-channel data buffer module, and the delay compensation module performs delay compensation on the ODUk data according to the delay compensation value Tc, and outputs the read ODUk data serially.

[0116] The signal envelope maintenance module included in the egress OTN functional module is used to ensure that the transmitted ODUk data is continuous. Specifically, when the signal envelope maintenance module sends a read request and channel number data reading to the multi-channel data cache module, if the SAR packet is parsed successfully, the SAR packet processing module will write the ODUk data to the multi-channel data cache module, and the signal envelope maintenance module will obtain the ODUk data from the multi-channel data cache module and output it externally. However, if the SAR packet parsing error occurs, the SAR packet processing module cannot write the ODUk data to the multi-channel data cache module. Therefore, when the signal envelope maintenance module detects that the data cache of the corresponding channel is empty, indicating that the ODUk data is lost, the signal envelope maintenance module will generate a clock cycle replacement signal to maintain the continuity of the ODUk data. At the same time, an alarm message will be output.

[0117] See also Figure 7 , which is a schematic diagram of input data and output data of the recombinant device provided in an embodiment of the present application, such as Figure 7 As shown, as the time value increases, the reassembly device inputs the SAR packets of multiple channels in series and the corresponding channel numbers, specifically including the SAR packet of channel 0, the SAR packet of channel a, and the like.

[0118] The reassembly module outputs the payload data of channel 0, channel a, channel b, and channel n in sequence based on the ODUk and channel number. The payload data is also delayed based on the delay compensation Tc.

[0119] After being processed by the reassembly module provided in the embodiment of the present application, the ODUk data in the SAR packets of the multiple channels are extracted, and the ODUk data of the multiple channels are re-integrated into one channel for output.

[0120] As can be seen, the multi-channel SAR data reassembly device in a packet switching system, provided by the embodiments of the present application, generates request signals for multiple ODUk rates using a single reference clock, while also providing the ability to adjust the requested rate. Data from multiple channels is combined into a single output, including the delay and jitter compensation value caused by the combining process, preserving the accuracy of the original data clock.

[0121] Moreover, through time division multiplexing, the logic resource consumption of multiple channels is greatly saved.

[0122] See Figure 8 , a schematic diagram illustrating time division multiplexing implemented by the multi-channel SAR data reassembly device in the packet switching system provided in an embodiment of the present application. In the multi-channel SAR data reassembly device in the packet switching system provided in an embodiment of the present application, the SAR packet reassembly module, the clock compensation calculation module, and the egress OTN functional module all implement time division multiplexing. The SAR packet reassembly module receives the SAR frame and channel number N. The egress OTN module outputs the ODUk data, channel number N, and Tc time compensation value. Each of the above modules can be configured with a register circuit for each channel, serving as a multi-channel multiplexing information status storage circuit. The status of channel N is obtained from the register circuit and, after processing, the status of channel N is entered into the multi-channel multiplexing information status storage circuit. The multi-channel multiplexing information status storage circuit stores the SAR reassembly status cache, clock compensation status cache, and egress OTN module status cache for channels 0 through n, respectively. When processing a particular channel, the register state corresponding to the channel is switched to. Through time division multiplexing, a significant amount of logic resources is saved in scenarios with a large number of channels.

[0123] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, hard disk, tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0124] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0125] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0126] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A device for reassembling multi-channel SAR data in a packet switching system, characterized in that: include: A segmentation and reassembly SAR packet processing module is configured to receive and parse SAR frames of N channels, write payload data and channel numbers in the SAR frames into a multi-channel data buffer module, and write payload length and the channel number into a multi-channel packet length sequence buffer module; N request generation modules and N output buffer modules, each channel corresponds to a request generation module and an output buffer module; The request generation module of the i-th channel is used to generate a read request signal according to the reference clock signal and the payload length compensation value of the i-th channel, and send the read request signal and the generation time T1 of each read request to the output buffer module; The output buffer module outputs a ready signal when detecting that the buffer queue for storing the read request signal is not empty; the payload length compensation value is calculated according to the payload length; The scheduling module is configured to detect whether the output buffer module corresponding to each channel outputs a ready signal, determine the target channel for the channel that outputs the ready signal, schedule a read request from the output buffer module corresponding to the target channel, and send the target channel identification number and delay compensation value to the data reading module, where the delay compensation value is calculated based on the scheduling completion time T2, the generation time T1, and the processing delay; The data reading module is configured to read the payload data of a preset length of the target channel from the multi-channel data buffer module according to the target channel identification number, and input the payload data and the delay compensation value into the delay compensation module; The delay compensation module is configured to perform delay compensation on the payload data according to the delay compensation value.

2. The device according to claim 1, characterized in that The SAR packet processing module is specifically configured to switch to a register state of a corresponding channel according to a channel number of a received SAR packet, and perform parsing processing on the SAR packet.

3. The device according to claim 1, characterized in that The request generation module includes a frequency division controller circuit, and the frequency division controller circuit is pre-configured with first parameters, wherein the first parameters include an integration step parameter C, an overflow period P, and clock compensation information FB2; The frequency division controller circuit is used to generate a frequency division signal of the reference clock signal according to the first parameter.

4. The device according to claim 3, characterized in that The frequency division controller circuit is specifically used for: According to the rate of the reference clock signal, based on the accumulated value, the integration step parameter C, the overflow period P, the feedback signal FB, and the clock compensation information FB2, the following first operation is performed: CNT1 = CNT0 + C-FB + FB2, where CNT0 is the accumulated value before the first operation in the current round; CNT1 is the accumulated value after the first operation in the current round; When it is determined that CNT1 exceeds the overflow period P, the feedback signal FB is assigned to P, CNT0 is assigned to 0, a high level is generated, the generation time is recorded, and the first operation is executed again. When it is determined that CNT1 does not exceed the overflow period P, the feedback signal is assigned a value of 0, and the process returns to execute the first operation.

5. The device according to claim 4, characterized in that The clock compensation information FB2 is calculated using the following formula: FB2=CLK×C / P / data bit width; Wherein, CLK represents the rate of the reference clock signal; the data bit width is the bit width of the payload data read by the data reading module each time.

6. The device according to any one of claims 1 to 5, characterized in that The payload length is {B-1, B, B+1}.

7. The device according to claim 1, characterized in that The scheduling module is specifically used to detect whether the output buffer module corresponding to each channel outputs a ready signal, and for the channel that outputs the ready signal, determine the target channel according to a preset priority order; The priority order is positively correlated with the channel bandwidth.

8. The device according to claim 2, characterized in that The scheduling module is further configured to input the delay compensation value and the target channel identification number into a clock compensation calculation module connected to a multi-channel packet length sequence cache module, so as to trigger the clock compensation calculation module to read the payload length sequence of the target channel from the multi-channel packet length sequence cache module and calculate clock compensation information based on the payload length sequence.

9. The device according to claim 8, characterized in that The clock compensation calculation module is specifically configured to average the payload length sequences of the target channel and calculate the clock compensation information according to the average of the payload lengths.

10. The device according to claim 1, characterized in that The SAR frames of N channels come from a switching network. A jitter compensation module is provided between the switching network and the SAR packet processing module. The jitter compensation module is used to compensate for jitter and delay generated by the SAR frames in the switching network.

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