An LED open-circuit protection control system and its control method

Abstract

This invention discloses an LED open-circuit protection control system and its control method, comprising a logic control module, a constant on-time module, a drive module, NMOS transistors MN1 and MN2, an inductor L, a current sampling resistor Rsense, a capacitor C2, an operational amplifier OP2, an error amplifier EA, a comparator CMP1, a loop compensation network, a switch S1, a filter network, a selector MUX, operational amplifier OP1, a PMOS transistor MP1, a minimum off-time detection circuit, an output overvoltage detection circuit, an AND gate AND1, and an inverter INV1. This invention clamps the output voltage of the error amplifier EA to a suitable voltage value required for normal system operation when the output LED is open-circuited, thereby solving the inductor current spike problem in traditional technologies when the fault is cleared and improving the reliability of the system.

Description

Technical Field

[0001] This invention relates to a control system and its control method, particularly an LED open-circuit protection control system and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Buck-type LED drivers are widely used in automotive matrix headlights. Traditional Buck-type LED drivers, when the output LEDs are open-circuited, detect that the output current at the LED string terminals is zero, which is less than the loop's set reference current value. This causes the error amplifier in the loop to reach its maximum voltage clamping value. When the open-circuit fault is cleared, because the error amplifier's output voltage is still at its maximum clamping value, it causes a large current spike in the system inductor current, affecting system reliability. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an LED open circuit protection control system and its control method to solve the problem of inductor current spike when the LED open circuit fault is cleared.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] An LED open-circuit protection control system includes a logic control module, a constant on-time module, a driver module, NMOS transistors MN1 and MN2, an inductor L, a current sampling resistor Rsense, a capacitor C2, an operational amplifier OP2, an error amplifier EA, a comparator CMP1, a loop compensation network, a switch S1, a filter network, a selector MUX, an operational amplifier OP1, a PMOS transistor MP1, a minimum off-time detection circuit, an output overvoltage detection circuit, an AND gate AND1, and an inverter INV1. The output of the constant on-time module is connected to the second input of the logic control module to generate a control signal TON. The output of the logic control module is connected to the input of the driver module to generate a control signal PWM. The first output terminal of the driver module is connected to the gate of NMOS transistor MN1 and generates a control signal HG. The second output terminal of the driver module is connected to the gate of NMOS transistor MN2 and generates a control signal LG. The drain of NMOS transistor MN1 is connected to the power supply VIN. The source of NMOS transistor MN1 is connected to the drain of NMOS transistor MN2 and one end of inductor L and generates a control signal SW. The source of NMOS transistor MN2 is grounded. The other end of inductor L is connected to one end of current sampling resistor Rsense and the non-inverting input terminal of operational amplifier OP2. The other end of current sampling resistor Rsense is connected to the inverting input terminal of operational amplifier OP2, one end of capacitor C2, and LED and generates output voltage VOUT and output current IOUT. The other end of capacitor C2 is grounded. The output of operational amplifier OP2 is connected to the inverting input of error amplifier EA and one end of switch S1 to generate a sampling voltage FB. The non-inverting input of error amplifier EA is connected to the reference voltage VREF. The other end of switch S1 is connected to the input of the filter network. The output of the filter network is connected to the first input of selector MUX to generate a voltage signal VCLP_dyn. The second input of selector MUX is connected to the reference voltage VCLP_max. The output of selector MUX is connected to the non-inverting input of operational amplifier OP1. The output of operational amplifier OP1 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP1 is grounded. The source of PMOS transistor MP1 is connected to the gate of operational amplifier OP2. The inverting input of amplifier OP1, the output of error amplifier EA, the input of the loop compensation network, and the non-inverting input of comparator CMP1 are connected to generate a voltage signal COMP. The inverting input of comparator CMP1 is connected to the sampled voltage FB. The output of comparator CMP1 is connected to the first input of the logic control module to generate a control signal CMPOUT. The first input of the minimum turn-off time detection circuit is connected to the control signal CMPOUT. The second input of the minimum turn-off time detection circuit is connected to the control signal PWM. The output of the minimum turn-off time detection circuit is connected to the first input of AND gate AND1 to generate a control signal MINOFF_det. The input of the output overvoltage detection circuit is connected to the output voltage VOUT.The output of the overvoltage detection circuit is connected to the second input of AND gate AND1 to generate the control signal VOUT_ovp. The output of AND gate AND1 is connected to the input of inverter INV1 and the control terminal of selector MUX to generate the control signal OPEN. The output of inverter INV1 is connected to the control terminal of switch S1 to generate the control signal OPEN_b.

[0006] Furthermore, the loop compensation network includes a resistor Rcomp and a capacitor Ccomp. One end of the capacitor Ccomp serves as the input terminal of the loop compensation network and is connected to the control signal OPEN. The other end of the capacitor Ccomp is connected to one end of the resistor Rcomp, and the other end of Rcomp is grounded.

[0007] Furthermore, the filter network includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the filter network, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the filter network to generate a voltage signal VCLP_dyn. The other end of the capacitor C1 is grounded.

[0008] Furthermore, the minimum turn-off time detection circuit includes a PMOS transistor MP2, a resistor R2, an NMOS transistor MN3, a capacitor C3, and a D flip-flop DFF1. The source of the PMOS transistor MP2 is connected to the power supply VIN. The gate of the PMOS transistor MP2 is connected to the gate of the NMOS transistor MN3 and serves as the second input terminal of the minimum turn-off time detection circuit, connected to the control signal PWM. The drain of the PMOS transistor MP2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the drain of the NMOS transistor MN3, one end of the capacitor C3, and the CLK terminal of the D flip-flop DFF1. The source of the NMOS transistor MN3 and the other end of the capacitor C3 are grounded. The D terminal of the D flip-flop DFF1 serves as the first input terminal of the minimum turn-off time detection circuit, connected to the control signal CMPOUT. The Q terminal of the D flip-flop DFF1 serves as the output terminal of the minimum turn-off time detection circuit, generating the control signal MINOFF_det.

[0009] Furthermore, the output overvoltage detection circuit includes a comparator CMP2. The non-inverting input of the comparator CMP2 serves as the input of the output overvoltage detection circuit and is connected to the output voltage VOUT. The inverting input of the comparator CMP2 is connected to the reference voltage VREF_OVP. The output of the comparator CMP2 serves as the output of the output overvoltage detection circuit and generates a control signal VOUT_ovp.

[0010] A control method for an LED open-circuit protection control system includes the following steps:

[0011] Operational amplifier OP2 amplifies the voltage difference across the current sampling resistor Rsense to obtain the feedback voltage FB related to the inductor current. The feedback voltage FB and the reference voltage VREF are used to generate the voltage signal COMP through error amplifier EA. The voltage signal COMP is then compared with the feedback voltage FB to obtain the control signal CMPOUT.

[0012] The constant on-time module generates a control signal TON. The control signal TON and the control signal CMPOUT are processed by the logic control module to generate a control signal PWM. The control signal PWM is processed by the drive module to generate control signals HG and LG to control the upper and lower Buck transistors.

[0013] The voltage signal MINOFF_det, indicating that the upper transistor's turn-off time has reached its minimum, is obtained by detecting the PWM control signal. The voltage signal VOUT_ovp is obtained by detecting the output voltage VOUT. The MINOFF_det and VOUT_ovp signals are ANDed to obtain the OPEN voltage signal. The inverted signal of OPEN is the control signal OPEN_b. OPEN_b samples the feedback voltage FB through control switch S1 and then generates the voltage signal VCLP_dyn through a filter network. The value of VCLP_dyn is equal to the voltage value corresponding to the average value of the inductor current IL sampled under non-open-circuit conditions. The OPEN control selector MUX determines whether to input either the reference voltage VCLP_max or the VCLP_dyn to the non-inverting input of operational amplifier OP1. Operational amplifier OP1 and PMOS transistor MP1 form a clamping circuit. When the COMP voltage signal is greater than the voltage at the non-inverting input of operational amplifier OP1, the clamping circuit clamps the maximum value of COMP at the voltage value at the non-inverting input of operational amplifier OP1.

[0014] When the output LED is open-circuited, the output current IOUT becomes zero; the voltage signal COMP gradually increases, and the output voltage VOUT begins to rise. When it rises to the OVP voltage point, the voltage signal VOUT_ovp becomes high; when the output voltage VOUT approaches the power supply VIN, the NMOS transistor MN1's turn-off time reaches its minimum, and the voltage signal MINOFF_det becomes high. Then, the voltage signal OPEN becomes high, and the voltage signal COMP is clamped to the voltage signal VCLP_dy. Since the value of the voltage signal VCLP_dyn is the voltage value corresponding to the average value of the inductor current IL sampled in the non-open-circuit state, the voltage signal VCLP_dyn is equal to the voltage value required by the voltage signal COMP when the system is working normally; when the LED fault is cleared, the voltage signal COMP has been clamped to the voltage value required for normal operation, so there is no spike in the inductor current value.

[0015] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an LED open circuit protection control system and its control method. When the output LED is open circuit, the output voltage of the error amplifier EA is clamped to a suitable voltage value required when the system is working normally. This voltage value is approximately equal to the required output voltage value of EA under normal working conditions. Moreover, this voltage value can be obtained by filtering the voltage obtained by dynamically sampling the inductor current, thereby solving the problem of inductor current spike when the fault is cleared in the traditional technology and improving the reliability of the system. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an LED open-circuit protection control system according to the present invention.

[0017] Figure 2 This is a circuit diagram of the minimum shutdown time detection circuit of the present invention.

[0018] Figure 3 This is a circuit diagram of the output overvoltage detection circuit of the present invention.

[0019] Figure 4 This is a waveform diagram of the LED open-circuit protection control system of the present invention. Detailed Implementation

[0020] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0021] like Figure 1As shown, an LED open-circuit protection control system of the present invention includes a logic control module, a constant on-time module, a drive module, NMOS transistors MN1 and MN2, an inductor L, a current sampling resistor Rsense, a capacitor C2, an operational amplifier OP2, an error amplifier EA, a comparator CMP1, a loop compensation network, a switch S1, a filter network, a selector MUX, operational amplifier OP1, a PMOS transistor MP1, a minimum off-time detection circuit, an output overvoltage detection circuit, an AND gate AND1, and an inverter INV1. The output terminal of the constant on-time module is connected to the second input terminal of the logic control module and generates a control signal TON. The output terminal of the logic control module is connected to the input terminal of the drive module. The module generates a PWM control signal. The first output of the driver module is connected to the gate of NMOS transistor MN1 and generates a control signal HG. The second output of the driver module is connected to the gate of NMOS transistor MN2 and generates a control signal LG. The drain of NMOS transistor MN1 is connected to the power supply VIN. The source of NMOS transistor MN1 is connected to the drain of NMOS transistor MN2 and one end of inductor L, generating a control signal SW. The source of NMOS transistor MN2 is grounded. The other end of inductor L is connected to one end of the current sampling resistor Rsense and the non-inverting input of operational amplifier OP2. The other end of the current sampling resistor Rsense is connected to the inverting input of operational amplifier OP2, one end of capacitor C2, and an LED, generating an output signal SW. The output voltage VOUT and output current IOUT are connected. The other end of capacitor C2 is grounded. The output of operational amplifier OP2 is connected to the inverting input of error amplifier EA and one end of switch S1 to generate sampling voltage FB. The non-inverting input of error amplifier EA is connected to reference voltage VREF. The other end of switch S1 is connected to the input of filter network. The output of filter network is connected to the first input of selector MUX to generate voltage signal VCLP_dyn. The second input of selector MUX is connected to reference voltage VCLP_max. The output of selector MUX is connected to the non-inverting input of operational amplifier OP1. The output of operational amplifier OP1 is connected to the gate of PMOS transistor MP1. With the drain grounded, the source of PMOS transistor MP1 is connected to the inverting input of operational amplifier OP1, the output of error amplifier EA, the input of the loop compensation network, and the non-inverting input of comparator CMP1 to generate a voltage signal COMP. The inverting input of comparator CMP1 is connected to the sampled voltage FB. The output of comparator CMP1 is connected to the first input of the logic control module to generate a control signal CMPOUT. The first input of the minimum turn-off time detection circuit is connected to the control signal CMPOUT, the second input of the minimum turn-off time detection circuit is connected to the control signal PWM, and the output of the minimum turn-off time detection circuit is connected to the first input of AND gate AND1 to generate a control signal MINOFF_det.The input terminal of the output overvoltage detection circuit is connected to the output voltage VOUT. The output terminal of the output overvoltage detection circuit is connected to the second input terminal of AND gate AND1 to generate the control signal VOUT_ovp. The output terminal of AND gate AND1 is connected to the input terminal of inverter INV1 and the control terminal of selector MUX to generate the control signal OPEN. The output terminal of inverter INV1 is connected to the control terminal of switch S1 to generate the control signal OPEN_b.

[0022] The loop compensation network includes a resistor Rcomp and a capacitor Ccomp. One end of the capacitor Ccomp serves as the input terminal of the loop compensation network and is connected to the control signal OPEN. The other end of the capacitor Ccomp is connected to one end of the resistor Rcomp, and the other end of Rcomp is grounded.

[0023] The filter network includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the filter network, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the filter network to generate a voltage signal VCLP_dyn. The other end of the capacitor C1 is grounded.

[0024] like Figure 2 As shown, the minimum turn-off time detection circuit includes a PMOS transistor MP2, a resistor R2, an NMOS transistor MN3, a capacitor C3, and a D flip-flop DFF1. The source of PMOS transistor MP2 is connected to the power supply VIN. The gate of PMOS transistor MP2 is connected to the gate of NMOS transistor MN3 and serves as the second input terminal of the minimum turn-off time detection circuit, connected to the control signal PWM. The drain of PMOS transistor MP2 is connected to one end of resistor R2. The other end of resistor R2 is connected to the drain of NMOS transistor MN3, one end of capacitor C3, and the CLK terminal of D flip-flop DFF1. The source of NMOS transistor MN3 and the other end of capacitor C3 are grounded. The D terminal of D flip-flop DFF1 serves as the first input terminal of the minimum turn-off time detection circuit, connected to the control signal CMPOUT. The Q terminal of D flip-flop DFF1 serves as the output terminal of the minimum turn-off time detection circuit, generating the control signal MINOFF_det.

[0025] like Figure 3 As shown, the output overvoltage detection circuit includes a comparator CMP2. The non-inverting input of the comparator CMP2 is used as the input of the output overvoltage detection circuit and connected to the output voltage VOUT. The inverting input of the comparator CMP2 is connected to the reference voltage VREF_OVP. The output of the comparator CMP2 is used as the output of the output overvoltage detection circuit and generates the control signal VOUT_ovp.

[0026] like Figure 4 As shown, a control method for an LED open-circuit protection control system includes the following steps:

[0027] Operational amplifier OP2 amplifies the voltage difference across the current sampling resistor Rsense to obtain the feedback voltage FB related to the inductor current. The feedback voltage FB and the reference voltage VREF are used to generate the voltage signal COMP through error amplifier EA. The voltage signal COMP is then compared with the feedback voltage FB to obtain the control signal CMPOUT.

[0028] The constant on-time module generates a control signal TON. The control signal TON and the control signal CMPOUT are processed by the logic control module to generate a control signal PWM. The control signal PWM is then processed by the drive module to generate control signals HG and LG to control the upper and lower Buck transistors.

[0029] The voltage signal MINOFF_det, indicating the minimum turn-off time of the upper transistor, is obtained by detecting the PWM control signal. The voltage signal VOUT_ovp is obtained by detecting the output voltage VOUT. The voltage signals MINOFF_det and VOUT_ovp are ANDed to obtain the voltage signal OPEN. The inverted signal of OPEN is the control signal OPEN_b. The control signal OPEN_b samples the feedback voltage FB through the control switch S1 and then generates the voltage signal VCLP_dyn through the filter network. The value of the voltage signal VCLP_dyn is equal to the voltage value corresponding to the average value of the inductor current IL sampled in the non-open circuit state. The voltage signal OPEN control selector MUX determines whether to input the reference voltage VCLP_max or the voltage signal VCLP_dyn to the non-inverting input of the operational amplifier OP1. The operational amplifier OP1 and the PMOS transistor MP1 form a clamping circuit. When the voltage signal COMP is greater than the voltage at the non-inverting input of the operational amplifier OP1, the clamping circuit clamps the maximum value of the voltage signal COMP at the voltage value at the non-inverting input of the operational amplifier OP1.

[0030] When the output LED is open-circuited, the output current IOUT becomes zero; the voltage signal COMP gradually increases, and the output voltage VOUT begins to rise. When it rises to the OVP voltage point, the voltage signal VOUT_ovp becomes high; when the output voltage VOUT approaches the power supply VIN, the NMOS transistor MN1's turn-off time reaches its minimum, the voltage signal MINOFF_det becomes high, and the voltage signal OPEN becomes high. The voltage signal COMP is clamped to the voltage signal VCLP_dy. Since the value of the voltage signal VCLP_dyn is the voltage value corresponding to the average value of the inductor current IL sampled in the non-open-circuit state, the voltage signal VCLP_dyn is equal to the voltage value required by the voltage signal COMP when the system is working normally; when the LED fault is cleared, the voltage signal COMP has been clamped to the voltage value required for normal operation, so there is no spike in the inductor current value, which solves the problem of inductor current spike when the fault is cleared in traditional technology and improves the reliability of the system.

[0031] This invention provides an LED open-circuit protection control system and its control method. When the output LED is open-circuited, the output voltage of the error amplifier EA is clamped to a suitable voltage value required for normal system operation. This voltage value is approximately equal to the required output voltage value of EA under normal operating conditions. Moreover, this voltage value can be obtained by dynamically sampling the voltage converted from the inductor current and then filtering it, thereby solving the problem of inductor current spikes when the fault is cleared in traditional technology and improving the reliability of the system.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An LED open-circuit protection control system, characterized in that: The system includes a logic control module, a constant on-time module, a driver module, NMOS transistors MN1 and MN2, inductor L, current sampling resistor Rsense, capacitor C2, operational amplifier OP2, error amplifier EA, comparator CMP1, loop compensation network, switch S1, filter network, selector MUX, operational amplifier OP1, PMOS transistor MP1, minimum off-time detection circuit, output overvoltage detection circuit, AND gate AND1, and inverter INV1. The output of the constant on-time module is connected to the second input of the logic control module to generate a control signal TON. The output of the logic control module is connected to the input of the driver module to generate a control signal PWM. The first output of the driver module is connected to... The gate of NMOS transistor MN1 is connected to and generates a control signal HG. The second output terminal of the driver module is connected to the gate of NMOS transistor MN2 and generates a control signal LG. The drain of NMOS transistor MN1 is connected to the power supply VIN. The source of NMOS transistor MN1 is connected to the drain of NMOS transistor MN2 and one end of inductor L and generates a control signal SW. The source of NMOS transistor MN2 is grounded. The other end of inductor L is connected to one end of current sampling resistor Rsense and the non-inverting input terminal of operational amplifier OP2. The other end of current sampling resistor Rsense is connected to the inverting input terminal of operational amplifier OP2, one end of capacitor C2, and LED and generates output voltage VOUT and output current IOUT. The other end of capacitor C2... The operational amplifier OP2 is grounded. Its output is connected to the inverting input of error amplifier EA and one end of switch S1 to generate a sampling voltage FB. The non-inverting input of error amplifier EA is connected to the reference voltage VREF. The other end of switch S1 is connected to the input of the filter network. The output of the filter network is connected to the first input of selector MUX to generate a voltage signal VCLP_dyn. The second input of selector MUX is connected to the reference voltage VCLP_max. The output of selector MUX is connected to the non-inverting input of operational amplifier OP1. The output of operational amplifier OP1 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP1 is grounded. The source of PMOS transistor MP1 is connected to the operational amplifier... The inverting input of OP1, the output of error amplifier EA, the input of the loop compensation network, and the non-inverting input of comparator CMP1 are connected to generate the voltage signal COMP. The inverting input of comparator CMP1 is connected to the sampled voltage FB. The output of comparator CMP1 is connected to the first input of the logic control module to generate the control signal CMPOUT. The first input of the minimum turn-off time detection circuit is connected to the control signal CMPOUT. The second input of the minimum turn-off time detection circuit is connected to the control signal PWM. The output of the minimum turn-off time detection circuit is connected to the first input of AND gate AND1 to generate the control signal MINOFF_det. The input of the output overvoltage detection circuit is connected to the output voltage VOUT.The output of the overvoltage detection circuit is connected to the second input of AND gate AND1 to generate the control signal VOUT_ovp. The output of AND gate AND1 is connected to the input of inverter INV1 and the control terminal of selector MUX to generate the control signal OPEN. The output of inverter INV1 is connected to the control terminal of switch S1 to generate the control signal OPEN_b.

2. The LED open-circuit protection control system according to claim 1, characterized in that: The loop compensation network includes a resistor Rcomp and a capacitor Ccomp. One end of the capacitor Ccomp serves as the input terminal of the loop compensation network and is connected to the control signal OPEN. The other end of the capacitor Ccomp is connected to one end of the resistor Rcomp, and the other end of Rcomp is grounded.

3. The LED open-circuit protection control system according to claim 1, characterized in that: The filter network includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the filter network, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the filter network to generate a voltage signal VCLP_dyn. The other end of the capacitor C1 is grounded.

4. The LED open-circuit protection control system according to claim 1, characterized in that: The minimum turn-off time detection circuit includes a PMOS transistor MP2, a resistor R2, an NMOS transistor MN3, a capacitor C3, and a D flip-flop DFF1. The source of PMOS transistor MP2 is connected to the power supply VIN. The gate of PMOS transistor MP2 is connected to the gate of NMOS transistor MN3 and serves as the second input terminal of the minimum turn-off time detection circuit, connected to the control signal PWM. The drain of PMOS transistor MP2 is connected to one end of resistor R2. The other end of resistor R2 is connected to the drain of NMOS transistor MN3, one end of capacitor C3, and the CLK terminal of D flip-flop DFF1. The source of NMOS transistor MN3 and the other end of capacitor C3 are grounded. The D terminal of D flip-flop DFF1 serves as the first input terminal of the minimum turn-off time detection circuit, connected to the control signal CMPOUT. The Q terminal of D flip-flop DFF1 serves as the output terminal of the minimum turn-off time detection circuit, generating the control signal MINOFF_det.

5. The LED open-circuit protection control system according to claim 1, characterized in that: The output overvoltage detection circuit includes a comparator CMP2. The non-inverting input of the comparator CMP2 is used as the input of the output overvoltage detection circuit and connected to the output voltage VOUT. The inverting input of the comparator CMP2 is connected to the reference voltage VREF_OVP. The output of the comparator CMP2 is used as the output of the output overvoltage detection circuit and generates a control signal VOUT_ovp.

6. A control method for an LED open-circuit protection control system according to any one of claims 1-5, characterized in that... Includes the following steps: Operational amplifier OP2 amplifies the voltage difference across the current sampling resistor Rsense to obtain the feedback voltage FB related to the inductor current. The feedback voltage FB and the reference voltage VREF are used to generate the voltage signal COMP through error amplifier EA. The voltage signal COMP is then compared with the feedback voltage FB to obtain the control signal CMPOUT. The constant on-time module generates a control signal TON. The control signal TON and the control signal CMPOUT are processed by the logic control module to generate a control signal PWM. The control signal PWM is processed by the drive module to generate control signals HG and LG to control the upper and lower Buck transistors. The voltage signal MINOFF_det, indicating that the upper transistor's turn-off time has reached its minimum, is obtained by detecting the PWM control signal. The voltage signal VOUT_ovp is obtained by detecting the output voltage VOUT. The MINOFF_det and VOUT_ovp signals are ANDed to obtain the OPEN voltage signal. The inverted signal of OPEN is the control signal OPEN_b. OPEN_b samples the feedback voltage FB through control switch S1 and then generates the voltage signal VCLP_dyn through a filter network. The value of VCLP_dyn is equal to the voltage value corresponding to the average value of the inductor current IL sampled under non-open-circuit conditions. The OPEN control selector MUX determines whether to input either the reference voltage VCLP_max or the VCLP_dyn to the non-inverting input of operational amplifier OP1. Operational amplifier OP1 and PMOS transistor MP1 form a clamping circuit. When the COMP voltage signal is greater than the voltage at the non-inverting input of operational amplifier OP1, the clamping circuit clamps the maximum value of COMP at the voltage value at the non-inverting input of operational amplifier OP1. When the output LED is open-circuited, the output current IOUT becomes zero; the voltage signal COMP gradually increases, and the output voltage VOUT begins to rise. When it rises to the OVP voltage point, the voltage signal VOUT_ovp becomes high; when the output voltage VOUT approaches the power supply VIN, the NMOS transistor MN1's turn-off time reaches its minimum, and the voltage signal MINOFF_det becomes high. Then, the voltage signal OPEN becomes high, and the voltage signal COMP is clamped to the voltage signal VCLP_dy. Since the value of the voltage signal VCLP_dyn is the voltage value corresponding to the average value of the inductor current IL sampled in the non-open-circuit state, the voltage signal VCLP_dyn is equal to the voltage value required by the voltage signal COMP when the system is working normally; when the LED fault is cleared, the voltage signal COMP has been clamped to the voltage value required for normal operation, so there is no spike in the inductor current value.

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