Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of transistors stacked along a vertical substrate direction, a word line extending along the vertical substrate direction through the different layers; the semiconductor layer comprising a first part in contact with the first electrode or the second electrode, and a second part not in contact with the first electrode or the second electrode, the first part extending only in a direction perpendicular to the substrate direction; the second part comprising a first extension extending in a direction perpendicular to the substrate direction and a second extension extending from the first extension away from the sidewall of the word line and parallel to the substrate direction; a plurality of semiconductor layers are arranged in a broken manner. The scheme provided by the embodiment of the disclosure has the advantages that the structure of the semiconductor device is simple, and the manufacturing process is simple.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, device design and manufacturing in the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non- ROM) in terms of application.

[0003] In order to reduce the cost of memory products as much as possible, people want to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device, which can eliminate parasitic MOS tubes and simplify the process.

[0006] The embodiment of the present disclosure provides a semiconductor device, comprising:

[0007] A plurality of transistors distributed in different layers stacked along a vertical substrate direction;

[0008] A word line extending along the vertical substrate direction through the different layers;

[0009] The transistor comprises a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the semiconductor layer comprises a first part in contact with the first electrode or the second electrode, and a second part not in contact with the first electrode or the second electrode, the first part extending only in a direction perpendicular to the substrate; the second part comprises a first extension extending in a direction perpendicular to the substrate, and a second extension extending away from the sidewall of the word line and parallel to the substrate;

[0010] The plurality of semiconductor layers of the plurality of transistors are physically disconnected, and the plurality of semiconductor layers are distributed in different regions of the sidewall of the word line.

[0011] In some embodiments, the cross section of the semiconductor layer in a direction perpendicular to the substrate and perpendicular to the arrangement direction of the first electrode and the second electrode is U-shaped, and the opening of the U-shaped is directed away from the sidewall of the word line.

[0012] In some embodiments, the word line comprises a vertical portion extending along a direction perpendicular to the substrate and a plurality of protruding portions extending from sidewalls of the vertical portion, the protruding portions being located between adjacent semiconductor layers along a direction perpendicular to the substrate.

[0013] In some embodiments, the transistor further comprises a gate insulating layer;

[0014] The semiconductor device further comprises:

[0015] a second insulating layer and a conductive layer alternately arranged along a direction perpendicular to the substrate; and a via hole extending through each of the second insulating layer and each of the conductive layer;

[0016] The via hole comprises, from inside to outside, the word line, the gate insulating layer surrounding sidewalls of the word line, and the plurality of semiconductor layers surrounding different regions of sidewalls of the gate insulating layer.

[0017] The first electrode and the second electrode are arranged to be electrically connected to the conductive layer and the semiconductor layer.

[0018] In some embodiments, a film layer of the same material as the insulating layer is filled in the opening of the U-shaped semiconductor layer.

[0019] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, the semiconductor device comprising a plurality of transistors stacked along a direction perpendicular to a substrate, a word line extending through different layers along a direction perpendicular to the substrate, the transistor comprising a first electrode and a second electrode, the manufacturing method of the semiconductor device comprising:

[0020] providing a substrate, depositing a sacrificial layer film and a conductive film alternately on the substrate, and patterning to form a plurality of stacked structures, each of the stacked structures comprising a plurality of sacrificial layers and a plurality of conductive layers arranged alternately and forming a predetermined pattern, and a first insulating layer forming a complementary pattern to the predetermined pattern of each of the sacrificial layers and each of the conductive layers; the predetermined pattern of the conductive layer comprising a first electrode and a second electrode of the transistor to be formed;

[0021] forming a via hole extending through each of the sacrificial layers and each of the conductive layers of the stacked structure simultaneously in a direction perpendicular to the substrate, the via hole comprising a plurality of first sub-holes located in the sacrificial layers and a plurality of second sub-holes located in the conductive layers respectively, and the sacrificial layers only exposing sidewalls in the first sub-holes, the conductive layers only exposing sidewalls in the second sub-holes, the first insulating layer exposing sidewalls and a surface extending along a direction parallel to the substrate in the first sub-holes, and the first insulating layer only exposing sidewalls in the second sub-holes; and the second sub-holes disconnecting the first electrode and the second electrode in the conductive layer;

[0022] depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film in the via in sequence to form a semiconductor layer and a gate insulating layer of the transistor and a word line, wherein the semiconductor layer is connected with the first electrode and the second electrode of the transistor of each layer;

[0023] etching the first insulating layer and each of the sacrificial layers outside the via to expose the semiconductor layer located in each of the first sub-via;

[0024] etching to remove the semiconductor layer located in the first sub-via so that the semiconductor layers of the transistors of different layers are disconnected.

[0025] In some embodiments, the via formed through each of the sacrificial layers and each of the conductive layers of the stack structure in a direction perpendicular to the substrate comprises:

[0026] forming an initial via through the stack structure in a direction perpendicular to the substrate by dry etching the stack structure in one process, the initial via located in a conductive layer being completely surrounded by the conductive layer;

[0027] increasing the aperture of the initial via in the sacrificial layer by wet etching the sacrificial layer in the initial via with the conductive layer as a barrier until the first insulating layer is exposed;

[0028] increasing the aperture of the region corresponding to the first insulating layer by wet etching the exposed first insulating layer with the conductive layer and the sacrificial layer as a barrier to obtain a via located in the sacrificial layer;

[0029] increasing the aperture of the initial via of the conductive layer by wet etching the conductive layer to disconnect the conductive layer into two parts to obtain a via located in the conductive layer.

[0030] In some embodiments, the etching the first insulating layer and the sacrificial layer to expose the semiconductor layer located in the first sub-via comprises:

[0031] dry etching the first insulating layer outside the via to expose the sidewall of each of the sacrificial layers connected with the first insulating layer and the semiconductor layer located in the first sub-via connected with the first insulating layer;

[0032] wet etching to remove all the sacrificial layers to expose the semiconductor layer located in the first sub-via connected with the sacrificial layer.

[0033] In some embodiments, after etching to remove the semiconductor layer located in the first sub-via so that the semiconductor layers of the transistors of different layers are disconnected, the method further comprises:

[0034] An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

[0035] In some embodiments, the sacrificial layer thin film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0036] An embodiment of the present disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments.

[0037] The embodiments of the present disclosure include a semiconductor device, a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a word line extending through the different layers in a direction perpendicular to the substrate; the semiconductor layer includes a first portion in contact with the first electrode or the second electrode, and a second portion not in contact with the first electrode or the second electrode, the first portion extending only in a direction perpendicular to the substrate; the second portion includes a first extension extending in a direction perpendicular to the substrate and a second extension extending from the first extension away from the word line sidewall and parallel to the substrate; the plurality of semiconductor layers of the plurality of transistors are physically disconnected, and the plurality of semiconductor layers are distributed in different regions of the word line sidewall. In the semiconductor device provided by the embodiments of the present disclosure, the plurality of semiconductor layers of the plurality of transistors are spaced apart to eliminate parasitic MOS tubes between layers. The structure is simple and easy to manufacture.

[0038] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0039] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0041] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment;

[0042] Figure 1B For the Figure 1A Schematic diagram of the aa' direction;

[0043] Figure 1C For the Figure 1Aschematic view in the direction of bb';

[0044] Figure 1D for along Figure 1A schematic view in the direction of cc';

[0045] Figure 1E for along Figure 1A schematic view in the direction of dd';

[0046] Figure 2 schematic view in the direction of aa' of a cross section of a stack structure provided for an exemplary embodiment;

[0047] Figure 3A schematic view in the direction of aa' of a cross section of a stack structure provided for an exemplary embodiment;

[0048] Figure 3B schematic view in the direction of aa' of a cross section of a stack structure provided for an exemplary embodiment;

[0049] Figure 3C schematic view in the direction of bb' of a cross section of a stack structure provided for an exemplary embodiment;

[0050] Figure 3D schematic view in the direction of cc' of a cross section of a stack structure provided for an exemplary embodiment;

[0051] Figure 3E schematic view in the direction of dd' of a cross section of a stack structure provided for an exemplary embodiment;

[0052] Figure 4A schematic view in the direction of aa' of a cross section of a stack structure provided for an exemplary embodiment;

[0053] Figure 4B schematic view in the direction of bb' of a cross section of a stack structure provided for an exemplary embodiment;

[0054] Figure 4C schematic view in the direction of cc' of a cross section of a stack structure provided for an exemplary embodiment;

[0055] Figure 4D schematic view in the direction of dd' of a cross section of a stack structure provided for an exemplary embodiment;

[0056] Figure 5A schematic view in the direction of aa' of a cross section of a stack structure provided for an exemplary embodiment;

[0057] Figure 5B schematic view in the direction of bb' of a cross section of a stack structure provided for an exemplary embodiment;

[0058] Figure 5CA cross-sectional view along the direction of cc' of the formation of the initial via for an exemplary embodiment;

[0059] Figure 6A A cross-sectional view along the direction of aa' of the lateral etching of the sacrificial layer for an exemplary embodiment;

[0060] Figure 6B A cross-sectional view along the direction of bb' of the lateral etching of the sacrificial layer for an exemplary embodiment;

[0061] Figure 6C A cross-sectional view along the direction of cc' of the lateral etching of the sacrificial layer for an exemplary embodiment;

[0062] Figure 7A A cross-sectional view along the direction of aa' of the lateral etching of the first and fourth insulating layers for an exemplary embodiment;

[0063] Figure 7B A cross-sectional view along the direction of bb' of the lateral etching of the first and fourth insulating layers for an exemplary embodiment;

[0064] Figure 7C A cross-sectional view along the direction of cc' of the lateral etching of the first and fourth insulating layers for an exemplary embodiment;

[0065] Figure 8A A cross-sectional view along the direction of aa' of the lateral etching of the conductive layer for an exemplary embodiment;

[0066] Figure 8B A cross-sectional view along the direction of bb' of the lateral etching of the conductive layer for an exemplary embodiment;

[0067] Figure 8C A cross-sectional view along the direction of cc' of the lateral etching of the conductive layer for an exemplary embodiment

[0068] Figure 9A A cross-sectional view along the direction of aa' of the formation of the semiconductor layer, the gate insulating layer and the word line for an exemplary embodiment;

[0069] Figure 9B A cross-sectional view along the direction of bb' of the formation of the semiconductor layer, the gate insulating layer and the word line for an exemplary embodiment;

[0070] Figure 9C A cross-sectional view along the direction of cc' of the formation of the semiconductor layer, the gate insulating layer and the word line for an exemplary embodiment;

[0071] FIG. 10A is a plan view of a mask pattern for forming the fifth trench for an exemplary embodiment;

[0072] Figure 10BA cross-sectional view of the fifth trench in the direction of aa' is provided for an exemplary embodiment.

[0073] Figure 10C A cross-sectional view of the fifth trench in the direction of bb' is provided for an exemplary embodiment.

[0074] Figure 10D A cross-sectional view of the fifth trench in the direction of cc' is provided for an exemplary embodiment.

[0075] Figure 11A A cross-sectional view of the etching of the sacrificial layer in the direction of aa' is provided for an exemplary embodiment.

[0076] Figure 11B A cross-sectional view of the etching of the sacrificial layer in the direction of bb' is provided for an exemplary embodiment.

[0077] Figure 11C A cross-sectional view of the etching of the sacrificial layer 9 in the direction of cc' is provided for an exemplary embodiment.

[0078] Figure 12A A cross-sectional view of the etching of the semiconductor layer in the first sub-hole in the direction of aa' is provided for an exemplary embodiment.

[0079] Figure 12B A cross-sectional view of the etching of the semiconductor layer in the first sub-hole in the direction of bb' is provided for an exemplary embodiment.

[0080] Figure 12C A cross-sectional view of the etching of the semiconductor layer in the first sub-hole in the direction of cc' is provided for an exemplary embodiment.

[0081] Figure 13A A cross-sectional view of the forming of the second insulating layer in the direction of aa' is provided for an exemplary embodiment.

[0082] Figure 13B A cross-sectional view of the forming of the second insulating layer in the direction of bb' is provided for an exemplary embodiment.

[0083] Figure 13C A cross-sectional view of the forming of the second insulating layer in the direction of cc' is provided for an exemplary embodiment. DETAILED DESCRIPTION

[0084] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0085] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings thereof by those having ordinary skills in the art to which the present disclosure belongs.

[0086] Embodiments of the present disclosure are not necessarily limited by the size of the components shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect real proportions. Furthermore, the drawings schematically show ideal examples, and embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0087] In the present disclosure, ordinal numbers such as "first", "second", "third" and the like are provided in order to avoid confusion of components, and do not indicate any order, number, or importance.

[0088] In the present disclosure, words indicating directions or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used for the purpose of convenience in order to describe the positional relationships of components with reference to the drawings, and are only for the purpose of facilitating the description of the present specification and simplifying the description, and thus cannot be construed to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as a limitation on the present disclosure. The positional relationships of the components are appropriately changed according to the directions in which each component is described. Therefore, the words explained in the disclosure are not limited, and can be appropriately replaced according to the situation.

[0089] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0090] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0091] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using transistors with opposite polarities, or in the case of changing the direction of current in the operation of a circuit, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0092] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0093] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0094] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0095] In the embodiment of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A.

[0096] The development of 3D memory array stacking structures has led to various problems. As the number of stacking layers increases, the array becomes larger, and the unit devices become closer together, the presence of parasitic MOS transistors between different layers can significantly impact the retention of capacitor charge and the overall stability of the device. This application proposes a semiconductor device and a method for removing parasitic MOS transistors from a semiconductor device. The semiconductor device has a simple structure, a simple process, and reduces costs.

[0097] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment, Figure 1B For the Figure 1A Schematic diagram of the aa' direction, Figure 1C For the Figure 1A Schematic diagram of the bb' direction, Figure 1D For the Figure 1A Schematic diagram of the cc' direction, Figure 1E For the Figure 1A Schematic diagram of the dd' direction. Figure 1AOnly the structure of the active region 300 where the transistors are located is shown, and the structure of the capacitor region 200 is not shown. The semiconductor device can be a transistor, or a memory cell containing a transistor, or a memory cell array containing memory cells, or a 3D stacked structure containing a memory cell array, or a memory containing a transistor or a memory cell array, etc.

[0098] As shown in Figures 1A to 1E The semiconductor device provided by the embodiment of the present disclosure comprises:

[0099] A plurality of transistors are stacked along the vertical substrate 1 direction in different layers.

[0100] A word line 40 extends along the vertical substrate 1 direction through the different layers.

[0101] The transistor can comprise a first electrode 51, a second electrode 52, and a semiconductor layer 23 surrounding the sidewall of the word line 40; the semiconductor layer 23 comprises a first part in contact with the first electrode 51 or the second electrode 51, and a second part not in contact with the first electrode 51 or the second electrode 52, the first part only extends along the direction perpendicular to the substrate 1 direction; the second part comprises a first extension part extending along the direction perpendicular to the substrate 1 direction, and a second extension part extending away from the sidewall of the word line 40 and parallel to the substrate 1 direction from the first extension part.

[0102] The plurality of semiconductor layers 23 of the plurality of transistors are physically disconnected, and the plurality of semiconductor layers 23 are distributed in different regions of the sidewall of the word line 40.

[0103] The plurality of semiconductor layers of the plurality of transistors are physically disconnected, which can eliminate the parasitic MOS tube between layers, reduce the leakage current, and improve the stability of the device. Moreover, the structure can be realized through the following process characteristics, and is easy to manufacture.

[0104] The structure corresponding to the process manufacturing does not need to make a dummy word line, and does not need to make a dummy spacer in the conductor layer, but fills a first insulating layer outside the hole, etches the first insulating layer outside the hole to expand the hole diameter, forms two grooves on the first insulating layer, forms the semiconductor layer of the parasitic MOS tube in the grooves and the end part of the sacrificial layer, removes the sacrificial layer by opening the hole outside the hole, and exposes the semiconductor layer of the parasitic MOS tube by the first insulating layer.

[0105] The arrangement direction of the first electrode 51 and the second electrode 52 is a direction from the first electrode 51 to the second electrode 52, or a direction from the contact surface between the first electrode 51 and the semiconductor layer 23 to the contact surface between the second electrode 52 and the semiconductor layer 23. The arrangement direction perpendicular to the substrate 1 and perpendicular to the first electrode 51 and the second electrode 52 may be, for example, the cc' direction, and the arrangement direction perpendicular to the substrate 1 and parallel to the first electrode 51 and the second electrode 52 may be, for example, the aa' direction.

[0106] In some embodiments, the cross-section of the semiconductor layer 23 may be U-shaped along a direction perpendicular to the substrate 1 and perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52, with the opening of the U-shape facing away from the sidewall of the word line 40. The sidewall of the word line 40 is a surface formed along the extension direction of the word line 40.

[0107] In some embodiments, the semiconductor device may further include a gate electrode 26. The gate electrodes 26 of transistors in different layers may be part of the word line 40. It is understood that before or after the word line 40 is formed, it is not necessary to separately form the gate electrode 26. After the word line 40 is formed, a portion of the word line 40 functions as the gate electrode 26.

[0108] In some embodiments, the word line 40 is filled in the through hole, and its shape is adapted to the through hole. For example, the word line 40 may include a vertical portion extending in a direction perpendicular to the substrate 1 and a plurality of raised portions extending from the sidewalls of the vertical portion, and the raised portions extend in a direction parallel to the substrate 1 and perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52. The raised portions may be located between adjacent semiconductor layers 23 in a direction perpendicular to the substrate. The semiconductor layer 23 may be distributed on the opposite surfaces of two adjacent raised portions and on the sidewalls of the vertical portion defined between the two raised portions. That is, distributed on the lower surface of one raised portion (the surface facing the substrate 1 side) and the upper surface of the other raised portion (the surface away from the substrate 1 side), as well as on the sidewalls of the vertical portion between the two raised portions.

[0109] In some embodiments, on a plane perpendicular to the substrate 1, the orthographic projections of the protrusion and the first and second electrodes 51, 52 do not overlap. That is, in the vertical direction, the protrusion and the first and second electrodes 51, 52 are at different distances from the substrate and are film layers at different heights.

[0110] In some embodiments, the first electrode 51 and the second electrode 52 can be located in the same conductive film layer along the direction perpendicular to the substrate 1. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 can be located in different conductive film layers.

[0111] In an exemplary embodiment, the first electrode 51 or the second electrode 52 of the transistors of different layers can be located in different conductive film layers distributed in the vertical direction and isolated by insulating film layers and the like.

[0112] In some embodiments, the transistor can further include a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23, and the gate insulating layer 24 can surround the sidewall of the word line 40.

[0113] In some embodiments, the gate insulating layers 24 of the plurality of transistors of different layers are integrated structures. In the present embodiment, the gate insulating layers 24 of the transistors can be deposited on the inner sidewall of the via by one process, and subsequent processes do not need to be cut off, thereby simplifying the process. However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layers 24 of the plurality of transistors of different layers can be disconnected.

[0114] In some embodiments, the semiconductor device can further include:

[0115] The second insulating layer 11 and the conductive layer are alternately distributed in sequence along the direction perpendicular to the substrate 1; and the via penetrates each of the second insulating layer 11 and each of the conductive layer;

[0116] The word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 surrounding different regions of the sidewall of the gate insulating layer 24 are sequentially distributed from the inside to the outside with reference to the center of the hole in the via;

[0117] The first electrode 51 and the second electrode 52 of the same transistor are disposed in one of the conductive layers and are electrically connected to the semiconductor layer 23.

[0118] In the present embodiment, the transistors of different layers are stacked and share the hole where the word line 40 is located, and the gate electrode 26, the gate insulating layer 24, and the semiconductor layer 23 of the stacked transistors are formed by one process in the hole, which can simplify the process.

[0119] In some embodiments, a plurality of the second insulating layers 11 distributed between different conductive layers are connected to form an integrated structure, the integrated structure includes a lateral extension arranged between adjacent conductive layers and a longitudinal extension extending in a direction perpendicular to the substrate 1, the longitudinal extension is provided with protrusions towards the sidewalls of the word lines 40 between adjacent conductive layers, as shown in Figure 1D The longitudinal extension of the second insulating layer 11 includes a plurality of protrusions corresponding to the protrusions of the word lines 40, which protrude towards the sidewalls of the word lines 40. When manufacturing the semiconductor layer, after etching the semiconductor layer outside the hole to remove the parasitic MOS, the insulating film layer is filled to form the protrusions of the longitudinal extension.

[0120] The second insulating layer not only fills between the stacked adjacent conductive layers but also fills in the U-shaped opening, and the second insulating layer can be a silicon oxide film layer.

[0121] In some embodiments, the semiconductor device further includes a first insulating layer 10 arranged between the longitudinal extension of the second insulating layer 11 and the semiconductor layer 23, and filling the U-shaped opening of the semiconductor layer 23. In some embodiments, the semiconductor device can be a storage cell array, which includes a plurality of storage cells including transistors. As shown in Figure 1A The transistors in the same layer form a storage cell array respectively distributed along a first direction X and a second direction Y, and each layer can further include a bit line 30 connected to the second electrode 52 of the transistors in the same column in the layer. Figure 1A Each layer includes four rows and two columns of storage cells as shown in the figure, but the embodiments of the present disclosure are not limited thereto, and each layer can include storage cells with other numbers of rows and columns, for example, it can only include one storage cell.

[0122] In some embodiments, the second electrodes 52 of the transistors of the storage cells in two adjacent columns are connected to the same bit line 30.

[0123] In some embodiments, the second electrode 52 of the transistor can be part of the bit line 30 to which the second electrode 52 is connected. For example, the bit line 30 is a straight line, the sidewalls of the straight line extending direction are connected to the semiconductor layer 23, or the bit line 30 has a branch with an integrated design, the branch is connected to the semiconductor layer 23, and the extension direction of the branch intersects, such as approximately perpendicular to, the extension direction of the bit line 30.

[0124] The branch can be a plurality of branches on one sidewall of the bit line, or a plurality of branches on both sidewalls at the same time, each branch corresponds to a transistor or a storage cell to be formed.

[0125] In some embodiments, the bit line 30 can extend along a second direction Y, and the first electrode 51 and the second electrode 52 can extend along a first direction X respectively, and the first electrode 51 and the second electrode 52 are arranged along the first direction X in sequence.

[0126] The above-mentioned stacked transistors can be applied in a plurality of memory cell scenarios, such as conventional 1T, 2T memory cells, with or without capacitors, in a DRAM scenario. Alternatively, the stacked transistors can be applied in a 4T or 6T memory cell scenario in an SRAM.

[0127] In some embodiments, the semiconductor device can further include a data storage element of a memory.

[0128] In some embodiments, the data storage element is, for example, a capacitor, i.e., a 1T1C memory structure. However, embodiments of the present disclosure are not limited thereto, and can be combined with other transistors to form a 2T0C memory structure, etc.

[0129] In some embodiments, the capacitor can include a first pole 41 and a second pole 42, and the first pole 41 is connected to the first electrode 51.

[0130] In some embodiments, the first pole 41 and the first electrode 51 can be connected as an integral structure, or share an electrode, which can be a wire extending laterally in a direction parallel to the substrate 1.

[0131] In some embodiments, the first electrode 41 can include a first end surface facing a side of the word line 40 and a second end surface facing away from the side of the word line 40, and a side surface connecting the first end surface and the second end surface, the first electrode 51 serving as the first pole 41 of the capacitor, and the second pole 42 surrounding the side surface of the first electrode 51.

[0132] In some embodiments, the semiconductor device can further include a support layer 45 extending in a direction perpendicular to the substrate 1, and the support layer 45 is connected to the second end surface of each first electrode 51. The support layer 45 forms a plate-shaped film layer extending in a direction perpendicular to the substrate 1, and can be formed before the capacitor is manufactured, to provide support for the subsequent manufacturing process of the capacitor.

[0133] In some embodiments, the support layer 45 can wrap the second end surface of each first electrode 51, and contact a region of the side surface of the first electrode 51 close to the second end surface, to play a supporting role for the first electrode 51. In this scheme, the support layer 45 can be partially arranged on the upper surface of the first electrode 51, to enhance the supporting performance of the support layer 45.

[0134] In some embodiments, the stacks of transistors arranged along the direction perpendicular to the substrate 1 are periodically arranged along the direction perpendicular to the substrate 1.

[0135] The technical solution of the present embodiment is further described below through the manufacturing process of the semiconductor device of the present embodiment. The "patterning process" in the present embodiment includes deposition of a film, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like. The "photolithography process" in the present embodiment includes coating of a film, mask exposure, and development. The deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, and the like, the coating can use known coating processes, and the etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "film" refers to a film formed by deposition or coating of a certain material. If the "film" does not need to be subjected to a patterning process or a photolithography process during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be subjected to a patterning process or a photolithography process during the entire manufacturing process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process includes at least one "pattern".

[0136] In an exemplary embodiment, the method for manufacturing the semiconductor device includes:

[0137] 1) Depositing a sacrificial layer film and a first conductive film on the substrate 1 in sequence to form a stack structure including alternately arranged sacrificial layers 9 and conductive layers 12, as shown in Figure 2 Figure 2 The cross-sectional schematic view of the stack structure along the aa' direction is provided for an exemplary embodiment, and the cross-sectional schematic views of the bb' direction, the cc' direction, and the dd' direction are similar, and thus are omitted. In some embodiments, the sacrificial layer 9 is arranged on the topmost conductive layer 12, and the bottommost sacrificial layer 9 can serve as a stop layer in subsequent etching operations.

[0138] In some embodiments, the sacrificial layer film can be an insulating material having a large etching selectivity ratio with the conductive layer and the isolation layer, including but not limited to aluminum oxide (Al2O3) and the like.

[0139] In some embodiments, the first conductive film can be a conductive material as follows:

[0140] For example, it can contain tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, and the like; it can be a metal alloy containing the aforementioned metals;

[0141] ​Or, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials;

[0142] Or, it can be a polysilicon material, a doped semiconductor material, etc., such as doped silicon, doped germanium, doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0143] Figure 2 The stack structure shown in the middle includes four layers of sacrificial layers 9 and three layers of conductive layers 12, which are only examples, and in other embodiments, the stack structure can include more or fewer film layers.

[0144] 2) Patterning the stack structure so that the stack structure forms a predetermined pattern;

[0145] The patterning of the stack structure can include:

[0146] Using a mask containing a predetermined pattern, the stack structure is etched from the top layer to the bottom layer (excluding the substrate 1) using dry etching, so that the conductive layer 12 and the sacrificial layer 9 both form a predetermined pattern, which defines a transistor electrode pattern and a bit line pattern. The mask pattern is as shown in Figure 3A As shown in the middle of the stack structure, the mask blocks part of it and removes the unblocked part, and the removed area forms a first trench. The first trench extends along the X direction, and the area between the first trenches is a strip-shaped area extending along the X direction.

[0147] The predetermined pattern of the conductive layer 12 can include a plurality of first conductive portions 121 and second conductive portions 122, wherein the first conductive portions 121 can extend along a first direction X, and the second conductive portions 122 can extend along a second direction Y;

[0148] A first insulating film is deposited to form a first insulating layer 10 that fills the first trench and covers the stack structure; as Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E As shown in Figure 3A is a cross-sectional view of the conductive layer 12 along a direction parallel to the substrate 1, Figure 3B is a cross-sectional view along the aa' direction after the predetermined pattern is formed, Figure 3C is a cross-sectional view along the bb' direction after the predetermined pattern is formed, Figure 3D is a cross-sectional view along the cc' direction after the predetermined pattern is formed, Figure 3ETo form a cross-sectional view of the preset pattern along the direction dd'. The preset pattern and the pattern of the plurality of first grooves are complementary, that is, the combination of the pattern of the preset pattern and the pattern of the first grooves is the shape of the conductive layer 12 in step 1). The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0149] The first conductive part 121 can subsequently form the first electrode 51 of the transistor, the second conductive part 122 can form the second electrode 52 of the transistor, and the bit line 30.

[0150] Alternatively, the first conductive part 121 can subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive part 122 can form the bit line 30.

[0151] In some embodiments, the first insulating film can include, but is not limited to, an oxide of silicon, such as silicon dioxide (SiO2).

[0152] Figure 3A The preset pattern shown is only an example, and the preset pattern can be other shapes.

[0153] 3) Forming a capacitor;

[0154] The forming of the capacitor can include:

[0155] Using dry etching to etch the stack structure from the top layer to the bottom layer in the support area 100 to form a second groove, exposing the end surface of the first conductive part 121 away from the second conductive part 122; the support area 100 is located on the side of the first conductive part 121 away from the second conductive part 122.

[0156] Depositing a support layer film in the second groove to form a support layer 45, the support layer 45 filling the second groove; the support layer 45 can be a plate-shaped film layer extending in the direction perpendicular to the substrate and parallel to the cc' direction.

[0157] Exposing the first conductive part 121 located in the capacitor area 200;

[0158] Sequentially depositing a dielectric film and a conductor material to form a dielectric layer 43 and a second electrode 42, respectively, the dielectric layer 43 covering the exposed area of the first conductive layer 121;

[0159] Depositing a second conductive film to form a second conductive layer 7 covering the second electrode 42 and filling the third groove; the second conductive layer 7 is connected to the second electrode 42, and the second conductive layer 7 can be grounded, thereby realizing capacitor grounding;

[0160] The second conductive layer 7 is polished, a third insulating thin film is deposited to form a third insulating layer 13 covering the second conductive layer 7;

[0161] A fourth insulating thin film is deposited in the active region 300 and polished to form a fourth insulating layer 14 filling the fourth trench;

[0162] A fifth insulating thin film is deposited on the substrate with the above structure to form a fifth insulating layer 15 covering the third and fourth insulating layers 13 and 14. The fifth insulating layer 15 serves as a stop layer when the subsequent word line 40 is polished, as shown in Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D wherein, Figure 4A is a cross-sectional view of the capacitor formed in the aa' direction, Figure 4B is a cross-sectional view of the capacitor formed in the bb' direction, Figure 4C is a cross-sectional view of the capacitor formed in the cc' direction, Figure 4D is a cross-sectional view of the capacitor formed in the dd' direction. The cross-sectional view in the dd' direction remains unchanged in subsequent steps, and the cross-sectional view in the dd' direction is no longer provided.

[0163] In some embodiments, the support layer thin film can be an insulating film layer different from the second insulating thin film eventually filled between the transistors, including but not limited to silicon nitride (SiN).

[0164] In some embodiments, the medium thin film can be a High-K medium material, i.e., a medium material with a dielectric constant K≥3.9. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, such as, can include but not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. high-K material.

[0165] In some embodiments, the conductor material includes but not limited to at least one of the following: metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer.

[0166] In some embodiments, the second conductive thin film includes but not limited to at least one of the following: metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as Poly-GiSe, etc.

[0167] The second pole 42 can surround the sidewall of the first conductive part 121, and the second pole 42 is insulated from the first conductive part 121 by the medium layer 43.

[0168] In some embodiments, the third insulating thin film includes, but is not limited to, silicon nitride (SiN).

[0169] In some embodiments, the fourth insulating thin film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc.

[0170] In some embodiments, the fifth insulating thin film includes, but is not limited to, SiN.

[0171] 4) Forming an initial via K0;

[0172] The forming of the initial via K0 can include: etching the stack structure by dry etching to form a plurality of initial vias K0 penetrating through the stack structure, the sidewall of the initial via K0 exposing each of the conductive layers 12 and the sacrificial layer 9, and the aperture size of the initial via K0 at different layers being substantially uniform, and along the cc' direction, the size of the initial via K0 being smaller than the size of the first conductive part 121, the initial via K0 not breaking the conductive layer 12, and the entire area of the conductive layer 12 remaining connected, as shown in Figure 5A , Figure 5B and Figure 5C wherein, Figure 5A is a cross-sectional view along the aa' direction after forming the initial via K0, Figure 5B is a cross-sectional view along the bb' direction after forming the initial via K0, Figure 5C is a cross-sectional view along the cc' direction after forming the initial via K0.

[0173] 5) Lateral etching of the sacrificial layer 9;

[0174] The lateral etching of the sacrificial layer 9 can include: laterally etching the sacrificial layer 9 within the initial via K0, and stopping when etching to the first insulating layer 10, i.e., along the cc' direction, the sacrificial layer 9 is etched through, and the sidewall of the initial via K0 exposes the first insulating layer 10, at this time, along the aa' direction, the aperture size d2 of the first sub-hole of the initial via K0 located in the sacrificial layer 9 is greater than the aperture size d1 of the second sub-hole of the initial via K0 located in the conductive layer 12, along the cc' direction, the aperture size d4 of the first sub-hole of the initial via K0 located in the sacrificial layer 9 is greater than the aperture size d3 of the second sub-hole of the initial via K0 located in the conductive layer 12, and along the cc' direction, the aperture size d4 of the first sub-hole of the initial via K0 located in the sacrificial layer 9 is consistent with the size of the sacrificial layer 9 along the cc' direction, as shown in Figure 6A , Figure 6B and Figure 6C wherein, Figure 6A is a cross-sectional view along the aa' direction, Figure 6B is a cross-sectional view along the bb' direction, Figure 6C is a cross-sectional view along the cc' direction.

[0175] 6) Laterally etching the first insulating layer 10 and the fourth insulating layer 14;

[0176] The lateral etching of the first insulating layer 10 and the fourth insulating layer 14 may include: lateral etching of the first insulating layer 10 and the fourth insulating layer 14 in the initial through hole K0, etching the first insulating layer 10 to a preset thickness h, for example, 5 nm to 15 nm, and the etched thickness is less than the thickness of the first insulating layer along the cc' direction, so as to avoid the same initial through hole K0 from being connected, resulting in the connection of the film layers of adjacent transistors, such as Figure 7A 、 Figure 7B and Figure 7C As shown, Figure 7A is the cross-sectional view along the aa' direction, Figure 7B is the cross-sectional view along the bb' direction, Figure 7C It is a cross-sectional view along the cc' direction.

[0177] At this point, the diameter d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction is further expanded, that is, expanded by twice the thickness of the etched first insulating layer 10, that is, h*2. The diameter d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the aa' direction remains unchanged. The diameters d1 and d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 remain unchanged.

[0178] 7) Laterally etching the conductive layer 12;

[0179] The laterally etching the conductive layer 12 may include: laterally etching the conductive layer 12 so that the first conductive portion 121 is disconnected from the second conductive portion 122. Figure 8A 、 Figure 8B and Figure 8C As shown, Figure 8A is a cross-sectional view along the aa' direction after the conductive layer 12 is laterally etched. Figure 8B is a cross-sectional view along the bb' direction after the conductive layer 12 is laterally etched. Figure 8C It is a cross-sectional view along the cc' direction after the conductive layer 12 is laterally etched.

[0180] like Figure 8C As shown, at this time, there is no conductive layer 12 on the cross section in the cc' direction, that is, in the cc' direction, the aperture d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 is consistent with the size of the first conductive part 121 along the cc' direction, but is still smaller than the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction; in the aa' direction, the aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 can be equal to the aperture d1 of the second sub-hole of the initial through hole K0 located in the conductive layer 12.

[0181] At this point, the etching of the initial via hole K0 is completed, and the via hole K0 is referred to as a via hole K1; in the aa' direction, the second sub-hole of the via hole K1 in the conductive layer 12 can be overlapped with the first sub-hole of the via hole K1 in the substrate 1; in the cc' direction, the second sub-hole in the substrate 1 falls into the first sub-hole in the substrate 1, that is, in the cc' direction, there is a hole diameter gap between the sub-holes of the conductive layer 12 and the sacrificial layer 9, which facilitates the subsequent exposure of the semiconductor layer located in the first sub-hole.

[0182] 8) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0183] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 can include:

[0184] In the via hole K1, a semiconductor thin film, a gate insulating thin film and a gate electrode thin film are sequentially deposited and polished to form a semiconductor layer 23, a gate insulating layer 24 and a word line 40, and the gate electrode thin film fills the via hole K1, as shown in Figure 9A 、 Figure 9B and Figure 9C wherein, Figure 9A is a cross-sectional view along the aa' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40, Figure 9B is a cross-sectional view along the bb' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40, Figure 9C is a cross-sectional view along the cc' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40.

[0185] In some embodiments, the semiconductor thin film, the gate insulating thin film and the gate electrode thin film can be deposited by an ALD method.

[0186] In the exemplary embodiments of the present disclosure, the material of the semiconductor layer 23 can be a material such as silicon or polycrystalline silicon with a band gap less than 2eV, or can be a wide band gap material such as a metal oxide material with a band gap greater than 2eV.

[0187] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0188] In some embodiments, the material of the metal-oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor can meet the requirements, and the specific material can be adjusted according to the actual situation.

[0189] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0190] The material of the metal-oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0191] In the exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric material. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like can be included. For example, at least one of the following high-K materials can be included, such as but not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), titanium oxide (TiO2), and the like.

[0192] In some embodiments, the gate electrode thin film can be one or more of the following different types of materials:

[0193] For example, it can contain tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, and the like; it can be a metal alloy containing one of the aforementioned metals;

[0194] Or, it can be metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (AZO) and other high-conductivity metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0195] Or, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0196] 9) Forming a fifth trench T5;

[0197] The exposure of the sacrificial layer 9 and the exposure of the part of the semiconductor layer 23 located in the first sub-hole can include: etching the stack structure from top to bottom (excluding the substrate 1) using dry etching to form a plurality of fifth trenches T5, exposing the sidewall of the sacrificial layer 9 and exposing the part of the semiconductor layer 23 located in the first sub-hole, as shown in FIG. 10A, Figure 10B 、 Figure 10C and Figure 10D , wherein FIG. 10A is a plan view of a mask pattern for forming the fifth trench T5, Figure 10B is a cross-sectional view along the aa' direction after forming the fifth trench T5, Figure 10C is a cross-sectional view along the bb' direction after forming the fifth trench T5, Figure 10D is a cross-sectional view along the cc' direction after forming the fifth trench T5. The mask pattern includes a first region 101, a second region 102, a third region 103, and a fourth region 104. The first region 101 corresponds to the capacitor region, and the second region 102 corresponds to the region where the bit line 30 is located. Both the capacitor region and the region where the bit line 30 is located are covered to avoid being etched. The third region 103 corresponds to the region where the word line 40 and the gate insulating layer 40, and the semiconductor layer 23 located in the second sub-hole are located. The fourth region 104 corresponds to the region where the first electrode 51 is located. The width s1 of the fourth region 104 can be the size of the first electrode 51 along the cc' direction. The width s2 of the third region 103 can be the aperture d4 of the via K1 in the first sub-hole of the sacrificial layer 9 along the cc' direction. The length s3 can be the size of the semiconductor layer 23 located in the first sub-hole along the aa' direction, so that the semiconductor layer 23 located in the first sub-hole and parallel to the aa' direction can be completely exposed.

[0198] 10) Etching the sacrificial layer 9;

[0199] The etching of the sacrificial layer 9 can include removing the remaining sacrificial layer 9 by wet etching to expose the semiconductor layer 23 located in the first sub-hole and parallel to the cc' direction, so that the semiconductor layer 23 located in the first sub-hole has been exposed, facilitating the subsequent removal of the semiconductor layer 23 located in the first sub-hole, as shown in Figure 11A 、 Figure 11B and Figure 11C , wherein Figure 11A is a cross-sectional view along the aa' direction after the etching of the sacrificial layer 9, Figure 11B is a cross-sectional view along the bb' direction after the etching of the sacrificial layer 9, Figure 11C is a cross-sectional view along the cc' direction after the etching of the sacrificial layer 9.

[0200] 11) etching the semiconductor layer 23 located in the first sub-hole;

[0201] The etching of the semiconductor layer 23 located in the first sub-hole can include removing the exposed semiconductor layer 23 located in the first sub-hole by wet etching, as shown in Figure 12A 、 Figure 12B and Figure 12C , wherein Figure 12A is a cross-sectional view along the aa' direction after the etching of the semiconductor layer 23 located in the first sub-hole, Figure 12B is a cross-sectional view along the bb' direction after the etching of the semiconductor layer 23 located in the first sub-hole, Figure 12C is a cross-sectional view along the cc' direction after the etching of the semiconductor layer 23 located in the first sub-hole. It can be seen that the semiconductor layers 23 of different transistors have been disconnected, so that the parasitic MOS tubes between layers can be eliminated.

[0202] 12) forming a second insulating layer 11;

[0203] The forming of the second insulating layer 11 can include depositing a second insulating film on the substrate forming the foregoing structure, forming a fifth insulating layer 16 filling the area where the sacrificial layer 9 is located and the area where the semiconductor layer 23 is etched away, as shown in Figure 13A 、 Figure 13B and Figure 13C , wherein Figure 13A is a cross-sectional view along the aa' direction after the forming of the second insulating layer 11, Figure 13B is a cross-sectional view along the bb' direction after the forming of the second insulating layer 11, Figure 13C is a cross-sectional view along the cc' direction after the forming of the second insulating layer 11.

[0204] In some embodiments, the second insulating film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0205] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of transistors stacked in a direction perpendicular to a substrate, word lines extending in the direction perpendicular to the substrate through different layers, the transistors comprising a first electrode and a second electrode, the method comprising:

[0206] providing a substrate, depositing a plurality of thin films of a sacrificial layer and a plurality of thin films of a conductive layer on the substrate in sequence and alternately, patterning to form a plurality of stack structures, each of the stack structures comprising a plurality of the sacrificial layers and a plurality of the conductive layers arranged alternately and stacked in a predetermined pattern, and a first insulating layer arranged in a complementary pattern to the predetermined pattern of each of the sacrificial layers and each of the conductive layers, the predetermined pattern of the conductive layers comprising a first electrode and a second electrode of the transistors to be formed;

[0207] forming a via hole through each of the sacrificial layers and each of the conductive layers of the stack structures in the direction perpendicular to the substrate, the via hole comprising a plurality of first sub-holes in the sacrificial layers and a plurality of second sub-holes in the conductive layers, the sacrificial layers exposing only sidewalls in the first sub-holes, the conductive layers exposing only sidewalls in the second sub-holes, the first insulating layer exposing sidewalls and a surface extending in a direction parallel to the substrate in the first sub-holes, and the first insulating layer exposing only sidewalls in the second sub-holes, and the second sub-holes disconnecting the first electrode and the second electrode in the conductive layers;

[0208] depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film in the via hole in sequence to form a semiconductor layer and a gate insulating layer of the transistors and the word lines, wherein the semiconductor layer is connected to the first electrode and the second electrode of each layer of the transistors;

[0209] etching the first insulating layer and each of the sacrificial layers outside the via hole to expose the semiconductor layer in each of the first sub-holes;

[0210] etching and removing the semiconductor layer in the first sub-holes to disconnect the semiconductor layers of the transistors of different layers.

[0211] In some embodiments, the via hole through each of the sacrificial layers and each of the conductive layers of the stack structures in the direction perpendicular to the substrate comprises:

[0212] forming an initial via hole through the stack structures in the direction perpendicular to the substrate by dry etching the stack structures in one process, the initial via hole in the conductive layer being completely surrounded by the conductive layer;

[0213] wet-etching the sacrificial layer in the initial via with the conductive layer as a barrier layer to increase the aperture of the initial via in the sacrificial layer until the first insulating layer is exposed;

[0214] wet-etching the exposed first insulating layer with the conductive layer and the sacrificial layer as barrier layers to increase the aperture of the corresponding region of the first insulating layer, to obtain a via in the sacrificial layer;

[0215] wet-etching the conductive layer to increase the aperture of the initial via of the conductive layer, and disconnecting the conductive layer into two parts, to obtain a via in the conductive layer.

[0216] In some embodiments, the etching the first insulating layer and the sacrificial layer to expose the semiconductor layer in the first sub-via includes:

[0217] dry-etching the first insulating layer outside the via to expose the sidewall of each of the sacrificial layer connected with the first insulating layer and the semiconductor layer in the first sub-via connected with the first insulating layer;

[0218] wet-etching to remove all the sacrificial layer to expose the semiconductor layer in the first sub-via connected with the sacrificial layer.

[0219] In some embodiments, after the semiconductor layer of different layers of transistors is disconnected by etching the semiconductor layer in the first sub-via, the method further includes:

[0220] depositing an insulating film to form a second insulating layer to fill the region where the etched sacrificial layer and the first insulating layer are located.

[0221] In some embodiments, the sacrificial layer film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0222] The embodiments of the present disclosure also provide an electronic device including the semiconductor device of the foregoing embodiments, or including a semiconductor device formed by using the manufacturing method of any one of the foregoing semiconductor devices. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0223] Although the present application has been described with reference to the above embodiments, the contents described are merely employed embodiments for facilitating the understanding of the present application, and are not intended to limit the present application. Any modification and change in the form and details can be made by any person skilled in the art without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of transistors stacked along a vertical substrate direction; a word line extending along the vertical substrate direction through different layers; the transistor comprises a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the semiconductor layer comprises a first part in contact with the first electrode and the second electrode, and a second part not in contact with the first electrode and the second electrode, the first part extending only in a direction perpendicular to the substrate; the second part comprises a first extension extending in a direction perpendicular to the substrate and a second extension extending away from the sidewall of the word line and parallel to the substrate; a plurality of semiconductor layers of the plurality of transistors are physically separated, and the plurality of semiconductor layers are distributed in different regions of the sidewall of the word line.

2. The semiconductor device according to claim 1, wherein In a direction perpendicular to the substrate and perpendicular to the arrangement direction of the first electrode and the second electrode, the cross section of the semiconductor layer is U-shaped, and the opening of the U-shaped semiconductor layer is directed away from the sidewall of the word line.

3. The semiconductor device of claim 1, wherein The word line comprises a vertical part extending in a direction perpendicular to the substrate and a plurality of protruding parts extending from the sidewall of the vertical part, the protruding parts being located between the semiconductor layers adjacent in a direction perpendicular to the substrate.

4. The semiconductor device of claim 2, wherein The transistor further comprises a gate insulating layer; The semiconductor device further comprises: insulating layers and conductive layers alternately arranged along a vertical substrate direction; a via extending through each of the insulating layers and each of the conductive layers; the via sequentially comprises the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer from inside to outside; the first electrode and the second electrode are arranged to electrically connect the conductive layer and the semiconductor layer.

5. The semiconductor device of claim 4, wherein, The opening of the U-shaped semiconductor layer is filled with a film layer of the same material as the insulating layer.

6. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises a plurality of transistors stacked along a vertical substrate direction, a word line extending along the vertical substrate direction through different layers, the transistor comprising a first electrode and a second electrode, and a manufacturing method of the semiconductor device comprises: providing a substrate, sequentially depositing a sacrificial layer film and a conductive film on the substrate, and patterning to form a plurality of stacked structures, each of the stacked structures comprising a plurality of sacrificial layers and a plurality of conductive layers arranged alternately and stacked to form a predetermined pattern, and a first insulating layer forming a complementary pattern with the predetermined pattern of each of the sacrificial layers and each of the conductive layers; the predetermined pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed; a via formed in a direction perpendicular to the substrate and penetrating through each of the sacrificial layers and each of the conductive layers of the stack structure, the via including a plurality of first sub-vias in the sacrificial layers and a plurality of second sub-vias in the conductive layers, and the sacrificial layers exposing only sidewalls in the first sub-vias, the conductive layers exposing only sidewalls in the second sub-vias, the first insulating layers exposing sidewalls and surfaces extending in a direction parallel to the substrate in the first sub-vias, and the first insulating layers exposing only sidewalls in the second sub-vias, and the second sub-vias disconnecting the first electrodes and the second electrodes in the conductive layers; depositing a semiconductor film, a gate insulating film and a gate electrode film in the via in sequence to form a semiconductor layer and a gate insulating layer of the transistors and a word line, wherein the semiconductor layer is connected to the first electrodes and the second electrodes of the transistors in each layer; etching the first insulating layers and the sacrificial layers outside the via to expose the semiconductor layers in the first sub-vias; removing the semiconductor layers in the first sub-vias by etching to disconnect the semiconductor layers of the transistors in different layers.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the via formed in a direction perpendicular to the substrate and penetrating through each of the sacrificial layers and each of the conductive layers of the stack structure includes: forming an initial via in a direction perpendicular to the substrate and penetrating through the stack structure by dry etching the stack structure in one process, and the initial via in the conductive layers being completely surrounded by the conductive layers; increasing the aperture of the initial via in the sacrificial layers by wet etching the sacrificial layers in the initial via with the conductive layers as a barrier until the first insulating layers are exposed; increasing the aperture of the first insulating layers in the corresponding regions by wet etching the exposed first insulating layers with the conductive layers and the sacrificial layers as a barrier to obtain the via in the sacrificial layers; increasing the aperture of the initial via in the conductive layers by wet etching the conductive layers to disconnect the conductive layers into two parts to obtain the via in the conductive layers.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching the first insulating layers and the sacrificial layers to expose the semiconductor layers in the first sub-vias includes: dry etching the first insulating layers outside the via to expose the sidewalls of each of the sacrificial layers connected to the first insulating layers and the semiconductor layers in the first sub-vias connected to the first insulating layers; wet etching to remove all the sacrificial layers to expose the semiconductor layers in the first sub-vias connected to the sacrificial layers.

9. The method of manufacturing a semiconductor device according to claim 8, wherein after the etching to remove the semiconductor layers in the first sub-vias to disconnect the semiconductor layers of the transistors in different layers, further including: depositing an insulating film to form a second insulating layer filling the regions of the etched sacrificial layers and the first insulating layers.

10. The method of manufacturing a semiconductor device according to Claim 9, wherein the sacrificial layers include silicon nitride or aluminum oxide, and the first insulating layers and the second insulating layers include silicon oxide.

11. An electronic device, comprising: a semiconductor device as claimed in any one of claims 1 to 5, or a semiconductor device formed by the manufacturing method as claimed in any one of claims 6 to 10.

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