Semiconductor device and method for manufacturing semiconductor device

Abstract

The application discloses a semiconductor device based on a BJT structure and a manufacturing method of the semiconductor device. The semiconductor device can reduce the beta gain of a parasitic transistor in the device, improve the breakdown voltage between a collector C and an emitter E, and keep the breakdown voltage between the emitter E and a base B as much as possible, and the breakdown voltage between the collector C and the base B is unchanged, so that the circuit performance is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device of BJT structure and a manufacturing method of semiconductor device. BACKGROUND

[0002] In the existing semiconductor device of BJT structure, there is a high Gummel lateral parasitic NPN structure, as shown in the following reference Figure 1 Figure 1 The NPN transistor 100 in the cross-sectional structure diagram of the existing semiconductor device of BJT structure is the lateral parasitic NPN structure in the device. The β gain of the lateral parasitic NPN transistor 100 is particularly large, which affects the performance of the device. Figure 1

[0003] In the prior art, the current of the base can be increased by surrounding a high-doped wide P-type ring, so as to reduce the parasitic gain. However, this method needs to occupy an additional device area, and thus when it is desired to save the device area, this method is not desirable.

[0004] The information disclosed in this section of background art is only intended to increase the understanding of the overall background of the present application, and should not be considered as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY

[0005] The present application aims to provide a semiconductor device of BJT structure and a manufacturing method of semiconductor device, which can reduce the β gain of the parasitic transistor in the device, improve the breakdown voltage between the collector C and the emitter E, while maintaining the breakdown voltage between the emitter E and the base B as much as possible, and the breakdown voltage between the collector C and the base B unchanged, and improve the circuit performance.

[0006] In order to achieve the above-mentioned purpose, the technical scheme provided by an embodiment of the present application is as follows:

[0007] A semiconductor device, comprising:

[0008] a semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer;

[0009] a first trench extending from a top surface of the epitaxial layer into the buried layer, the first trench having a first conductive material having the second doping type disposed therein, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer;

[0010] ​​a first drift region disposed in the epitaxial layer and located within a range surrounded by the first trench, the first drift region having a second doping type;

[0011] a first well region disposed in the epitaxial layer and located between the first trench and the first drift region, the first well region having a first doping type or a second doping type or a non-doping type;

[0012] a second well region disposed in the epitaxial layer and located below the first well region, the second well region having a second doping type;

[0013] a third well region disposed in the epitaxial layer, the third well region including a first third sub-well region interposed between the first well region and the first trench, and a second third sub-well region interposed between the first well region and the first drift region, the third well region having a first doping type;

[0014] wherein,

[0015] when the first well region has the second doping type, a doping concentration of the second well region is greater than a doping concentration of the first well region;

[0016] when the first well region has the first doping type, a doping concentration of the third well region is greater than a doping concentration of the first well region.

[0017] In one or more embodiments of the present application, a sum of depths of the first well region and the second well region is greater than a depth of the third well region; and / or,

[0018] a depth of the first well region is equal to a depth of the third well region; and / or,

[0019] a depth of the second well region is less than a depth of the third well region.

[0020] In one or more embodiments of the present application, the first third sub-well region and the second third sub-well region are respectively disposed adjacent to the first well region, and the second well region is disposed adjacent to the first well region.

[0021] In one or more embodiments of the present application, the first well region has a first region where the first well region is located, the second well region has a second region where the second well region is located, and the third well region has a third region where the third well region is located;

[0022] forming a third well region in the third region and doping the first region with the first doping type by ion implantation of the first doping type in the first region and the third region, and counter-doping the first region with the second doping type by ion implantation of the second doping type in the first region and the second region, forming a first well region in the first region and a second well region in the second region; or

[0023] forming a second well region in the second region and doping the first region with the second doping type by ion implantation of the second doping type in the first region and the second region, and counter-doping the first region with the first doping type by ion implantation of the first doping type in the first region and the third region, forming a first well region in the first region and a third well region in the third region.

[0024] In one or more embodiments of the present application, the semiconductor device further comprises a first isolation structure disposed between the first trench and the third well region, the first isolation structure extending from a top surface of the epitaxial layer into the buried layer.

[0025] In one or more embodiments of the present application, the semiconductor device further comprises a second isolation structure disposed between the third well region and the first drift region, the second isolation structure extending from a top surface of the epitaxial layer into the epitaxial layer with a predetermined distance from the buried layer.

[0026] In one or more embodiments of the present application, the first well region comprises a plurality of first well region units arranged in intervals, and the second well region comprises a plurality of second well region units arranged in intervals, the plurality of first well region units and the plurality of second well region units being arranged in one-to-one correspondence.

[0027] In one or more embodiments of the present application, the third well region comprises third third sub-well region units interposed between adjacent first well region units and between adjacent second well region units, the third third sub-well region units being adjacent to the first third sub-well region and the second third sub-well region, respectively.

[0028] In one or more embodiments of the present application, the second third sub-well region comprises a plurality of second third sub-well region units arranged in intervals, adjacent second third sub-well region units being separated by the epitaxial layer.

[0029] The first trench and the third well region, and the third well region and the first drift region are separated by the epitaxial layer.

[0030] A method of fabricating a semiconductor device, comprising:

[0031] providing a semiconductor body comprising a substrate of a first doping type, a buried layer of a second doping type disposed on the substrate, and an epitaxial layer of the first doping type disposed on the buried layer;

[0032] forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer into the buried layer, the first trench having a first conductive material of the second doping type disposed therein, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer;

[0033] forming a first drift region of the second doping type in the semiconductor body and disposed within a region enclosed by the first trench, and a first doped region of the first doping type in the epitaxial layer and disposed between the first trench and the first drift region;

[0034] counter-doping a portion of the first doped region with the second doping type to form a second well region below the first doped region, a first well region within the first doped region, and a third well region formed by the portion of the first doped region that is not counter-doped.

[0035] A semiconductor device, comprising:

[0036] a semiconductor body comprising a substrate of a first doping type, a buried layer of a second doping type disposed on the substrate, and an epitaxial layer of the first doping type disposed on the buried layer;

[0037] a first trench extending from a top surface of the epitaxial layer into the buried layer, the first trench having a first conductive material of the second doping type disposed therein, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer;

[0038] a first drift region disposed in the epitaxial layer and within a region enclosed by the first trench, the first drift region having the second doping type;

[0039] a fourth well region disposed in the epitaxial layer and between the first trench and the first drift region, the fourth well region having the second doping type, the fourth well region comprising a plurality of spaced-apart fourth well region units;

[0040] a third well region disposed in the epitaxial layer, the third well region including a first third sub-well region interposed between the fourth well region and the first trench, a second third sub-well region interposed between the fourth well region and the first drift region, and a third third sub-well region unit interposed between adjacent fourth well region units, the third third sub-well region unit being contiguous to the first third sub-well region and the second third sub-well region respectively, the third well region having the first doping type.

[0041] In one or more embodiments of the present application, the fourth well region has a depth greater than a depth of the third well region.

[0042] In one or more embodiments of the present application, the semiconductor device further includes a first isolation structure disposed between the first trench and the third well region, the first isolation structure extending from a top surface of the epitaxial layer into the buried layer.

[0043] In one or more embodiments of the present application, the semiconductor device further includes a second isolation structure disposed between the third well region and the first drift region, the second isolation structure extending from a top surface of the epitaxial layer into the epitaxial layer with a preset distance from the buried layer.

[0044] In one or more embodiments of the present application, the second third sub-well region includes a plurality of spaced-apart second third sub-well region units, adjacent second third sub-well region units being separated by the epitaxial layer.

[0045] A semiconductor device, comprising:

[0046] a semiconductor body including a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer;

[0047] a first trench extending from a top surface of the epitaxial layer into the buried layer, the first trench having a first conductive material having the second doping type disposed therein, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer;

[0048] a first drift region disposed in the epitaxial layer within a range enclosed by the first trench, the first drift region having the second doping type;

[0049] a fourth well region disposed in the epitaxial layer between the first trench and the first drift region, the fourth well region having the second doping type;

[0050] a third well region disposed in the epitaxial layer, the third well region including a first third sub-well region interposed between the fourth well region and the first trench, and a second third sub-well region interposed between the fourth well region and the first drift region, the third well region having a first doping type;

[0051] a first isolation structure disposed between the first trench and the third well region, the first isolation structure extending from a top surface of the epitaxial layer into the buried layer.

[0052] In one or more embodiments of the present application, the semiconductor device further includes a second isolation structure disposed between the third well region and the first drift region, the second isolation structure extending from a top surface of the epitaxial layer into the epitaxial layer and having a predetermined distance from the buried layer.

[0053] In one or more embodiments of the present application, the second third sub-well region includes a plurality of spaced apart second third sub-well region units, adjacent ones of the second third sub-well region units being separated by the epitaxial layer.

[0054] Compared with the prior art, the semiconductor device and the method for manufacturing the semiconductor device can reduce the beta gain of the parasitic transistor in the device, improve the breakdown voltage between the collector C and the emitter E, and maintain the breakdown voltage between the emitter E and the base B as much as possible, and the breakdown voltage between the collector C and the base B is unchanged, thereby improving the circuit performance.

[0055] The semiconductor device and the method for manufacturing the semiconductor device are compatible with the existing MTI / DTI basic process, do not increase the additional mask cost, reduce the parasitic NPN transistor gain of the BJT structure semiconductor device, and improve the circuit performance. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0057] Figure 1 a cross-sectional view of a semiconductor device based on a BJT structure in the prior art;

[0058] Figure 2 a cross-sectional view of a semiconductor device based on a BJT structure in an embodiment;

[0059] Figure 3Cross-sectional schematic view of a semiconductor device based on a BJT structure in Example 1.

[0060] Figure 4 Top view of a semiconductor device based on a BJT structure in Example 1.

[0061] Figure 5 Cross-sectional schematic view of a semiconductor device based on a BJT structure in Example 2.

[0062] Figure 6 Top view of a semiconductor device based on a BJT structure in Example 2.

[0063] Figure 7 Top view of a semiconductor device based on a BJT structure in Example 3.

[0064] Figure 8 Top view of a semiconductor device based on a BJT structure in Example 4.

[0065] Figure 9 Top view of a semiconductor device based on a BJT structure in Example 5.

[0066] Figure 10 Top view of a semiconductor device based on a BJT structure in Example 6.

[0067] Figure 11 Top view of a semiconductor device based on a BJT structure in Example 7.

[0068] Figure 12 Cross-sectional schematic view of a semiconductor device based on a BJT structure in Example 7.

[0069] Figure 13 Top view of a semiconductor device based on a BJT structure in Example 8.

[0070] Figure 14 Cross-sectional schematic view of a semiconductor device based on a BJT structure in Example 8.

[0071] Figure 15 Top view of a semiconductor device based on a BJT structure in Example 9.

[0072] Figure 16 Top view of a semiconductor device based on a BJT structure in Example 10.

[0073] Figure 17 Top view of a semiconductor device based on a BJT structure in Example 11. DETAILED DESCRIPTION

[0074] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0075] As mentioned in the background, in order to solve the problem of high Gummel of the lateral parasitic NPN transistor 100 in the semiconductor device of the BJT structure in the prior art, a high-doped wide P-type ring is arranged to increase the current of the base, but this method needs to occupy an additional device area.

[0076] Therefore, how to solve the problem of high Gummel of the lateral parasitic NPN structure in the semiconductor device of the BJT structure while keeping the device area unchanged is a problem worth considering.

[0077] It is found that by adding an embedded N-type doped region in the P-type well and shorting both to the base metal connection, a new lateral parasitic NPN transistor 200 is formed between the emitter E and the base B of the device, thereby increasing the total current of the base B of the original lateral parasitic NPN transistor 100 and reducing the Gummel. Figure 2 As shown, Figure 2 is a cross-sectional structure schematic diagram of the semiconductor device of the BJT structure in an embodiment, Figure 2 The NPN transistor 200 in the above is another newly added lateral parasitic NPN structure in the device.

[0078] Therefore, by adding an embedded N-type doped region in the P-type well, a new lateral parasitic NPN structure is constructed between the emitter E and the base B, which can greatly improve the breakdown voltage between the collector C and the emitter E.

[0079] However, this method brings great defects while bringing benefits. This method will reduce the breakdown voltage between the emitter E and the base B, from about 80V to 30V; at the same time, it will also reduce the breakdown voltage between the collector C and the base B, from about 100V to 50V, resulting in unbalanced overall performance of the device.

[0080] Therefore, in order to solve the high Gummel problem of the lateral parasitic NPN structure in the semiconductor device of the BJT structure while keeping the device area unchanged and the overall performance of the device balanced and stable, the application provides a semiconductor device based on a BJT structure and a manufacturing method of the semiconductor device, which can reduce the beta gain of the parasitic transistor in the device, improve the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B as much as possible, and the breakdown voltage between the collector C and the base B unchanged, thereby improving the circuit performance.

[0081] The semiconductor device of the application comprises a semiconductor body, a first trench, a first drift region, a first well region, a second well region and a third well region.

[0082] The semiconductor body comprises a substrate with a first doping type, a buried layer with a second doping type arranged on the substrate, and an epitaxial layer with the first doping type arranged on the buried layer. The first doping type can be P-type, and the second doping type can be N-type. Alternatively, the first doping type is N-type, and the second doping type is P-type.

[0083] The first trench extends from the top surface of the epitaxial layer into the buried layer, and a first conductive material with the second doping type is arranged in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. The first conductive material can serve as the collector C of the semiconductor device due to the communication with the buried layer. The first trench is arranged in a ring shape, and the first trench is the device region.

[0084] The first drift region is arranged in the epitaxial layer and within the range surrounded by the first trench. A spacing space is formed between the first drift region and the first trench. The first drift region has the second doping type. The first drift region can serve as the emitter E of the semiconductor device.

[0085] The first well region is arranged in the epitaxial layer and within the spacing space between the first trench and the first drift region. The first well region has the first doping type or the second doping type or a non-doping type, and the first well region is also arranged in a ring shape.

[0086] The second well region is arranged below the first well region in the epitaxial layer, and the second well region is arranged adjacent to the first well region. The second well region has the second doping type. The second well region is also arranged in a ring shape. The depth of the second well region is less than the depth of the first well region.

[0087] The third well region is arranged in the epitaxial layer, and the third well region includes a first third sub-well region interposed between the first well region and the first trench, and a second third sub-well region interposed between the first well region and the first drift region, and the first third sub-well region and the second third sub-well region are respectively arranged adjacent to the first well region. The third well region is also arranged in a ring shape. The third well region has the first doping type. The depth of the third well region is less than the sum of the depths of the first well region and the second well region, and the depth of the third well region is equal to the depth of the first well region.

[0088] When the first well region has the second doping type, the doping concentration of the second well region is greater than the doping concentration of the first well region; when the first well region has the first doping type, the doping concentration of the third well region is greater than the doping concentration of the first well region.

[0089] In the above technical solution, the first well region, the second well region and the third well region can be formed in the following manner. Specifically, the first well region has a first region, the second well region has a second region, and the third well region has a third region, and the sum of the first region and the third region is a first doped region. First, ion implantation of the first doping type is performed in the first region and the third region (the first doped region) to form the third well region in the third region and make the first region have the first doping type; then, ion implantation of the second doping type is performed in the first region and the second region to counter-dope the first region having the first doping type to form the first well region in the first region, and at the same time, to form the second well region in the second region. Alternatively, first, ion implantation of the second doping type is performed in the first region and the second region to form the second well region in the second region and make the first region have the second doping type; then, ion implantation of the first doping type is performed in the first region and the third region (the first doped region) to counter-dope the first region having the second doping type to form the first well region in the first region, and at the same time, to form the third well region in the third region.

[0090] It can be understood that the above technical solution is based on the existing MTI / DTI (middle trench isolation / deep trench isolation) basic process, and a first doped region of the first doping type is first formed, and then doping of the second doping type is performed in the region, the doping of the second doping type partially overlaps the original first doped region in the lateral direction, and the depth of the doping of the second doping type is greater than the depth of the first doping type in the prior art, so that there is still a region having the second doping type, i.e., the second well region 42, at the bottom of the base, but the upper part of the base will be counter-doped by the first doping type, thereby forming the first well region 41.

[0091] The first region is doped by controlling the ion implantation dose of the first doping type and the ion implantation dose of the second doping type, so that the first well region presents the second doping type with weak doping or the first doping type with weak doping or presents a non-doped type.

[0092] It can be understood that the first trench formed in the semiconductor body and the method of ion implantation to the semiconductor body are existing processes, and the present application does not make detailed description thereof.

[0093] In the above technical solution, the doping type of the first well region has no specific requirement, only the second well region presents a doping type different from the third well region, and the second well region slightly protrudes from the lower surface of the third well region (the side surface away from the top surface of the epitaxial layer).

[0094] The second well region forms a new lateral parasitic NPN (based on the first doping type being P type and the second doping type being N type) or PNP (based on the first doping type being N type and the second doping type being P type) in the semiconductor device. The newly generated lateral parasitic NPN or PNP provides current to the original lateral parasitic transistor base region, thereby reducing the β gain of the original lateral parasitic transistor in the device and increasing the breakdown voltage between the collector C and the emitter E. Figure 2 The second well region is not completely formed through the third well region, so the current provided to the original lateral parasitic transistor base region is small, which reduces the β gain without causing great adverse effects on the breakdown voltage between the emitter E and the base B and the breakdown voltage between the collector C and the base B of the semiconductor device.

[0095] In a preferred embodiment, the semiconductor device can further include a first isolation structure. The first isolation structure is disposed between the first trench and the third well region. The first isolation structure extends from the top surface of the epitaxial layer to the buried layer. The width of the first isolation structure ranges from 0.5 μm to 0.7 μm, and the depth ranges from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0096] The semiconductor device further includes a second isolation structure. The second isolation structure is disposed between the third well region and the first drift region. The second isolation structure extends from the top surface of the epitaxial layer to the epitaxial layer and has a predetermined distance from the buried layer. The width of the second isolation structure ranges from 0.35 μm to 0.5 μm, and the depth ranges from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0097] In the above technical solution, the first isolation structure can improve the breakdown voltage between the collector C and the base B. The second isolation structure can improve the breakdown voltage between the emitter E and the base B.

[0098] In another preferred embodiment, the first well region includes a plurality of first well region units arranged at intervals, and the plurality of first well region units are arranged in a ring shape. The second well region includes a plurality of second well region units arranged at intervals, and the plurality of second well region units are arranged in a ring shape. The plurality of first well region units and the plurality of second well region units are arranged one-to-one. The third well region further includes third third sub-well region units interposed between adjacent first well region units and adjacent second well region units, and the third third sub-well region units are respectively adjacent to the first third sub-well region and the second third sub-well region. The third third sub-well region units are respectively adjacent to the adjacent first well region units and the second well region units.

[0099] By changing the area of the second well region in the device region, the influence on the breakdown voltage between the emitter E and the base B and the breakdown voltage between the collector C and the base B can be further reduced.

[0100] In the above embodiment, the semiconductor device can also include the first isolation structure and / or the second isolation structure. The first isolation structure is arranged between the first trench and the third well region. The second isolation structure is arranged between the third well region and the first drift region.

[0101] In still another preferred embodiment, the second third sub-well region includes a plurality of second third sub-well region units arranged at intervals, and the plurality of second third sub-well region units are arranged in a ring shape, and adjacent second third sub-well region units are separated by an epitaxial layer.

[0102] In addition, the application also provides a semiconductor device, which includes a semiconductor body, a first trench, a first drift region, a fourth well region, and a third well region.

[0103] The semiconductor body includes a substrate with a first doping type, a buried layer with a second doping type arranged on the substrate, and an epitaxial layer with the first doping type arranged on the buried layer. The first doping type can be P-type, and the second doping type can be N-type. Alternatively, the first doping type is N-type, and the second doping type is P-type.

[0104] The first trench extends from a top surface of the epitaxial layer into the buried layer, and a first conductive material with the second doping type is arranged in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. The first conductive material can serve as the collector C of the semiconductor device due to the communication with the buried layer. The first trench is arranged in a ring shape, and the first trench is the device region.

[0105] A first drift region is disposed in the epitaxial layer and is located within the region enclosed by the first trench. A separation space is formed between the first drift region and the first trench. The first drift region has a second doping type and can serve as an emitter E of the semiconductor device.

[0106] The fourth well region is disposed in the epitaxial layer and is located between the first trench and the first drift region. The fourth well region has the second doping type and includes a plurality of spaced fourth well region units. The plurality of fourth well region units are arranged in a ring shape.

[0107] The third well region is disposed in the epitaxial layer. The third well region includes a first third sub-well region interposed between the fourth well region and the first trench, a second third sub-well region interposed between the fourth well region and the first drift region, and a third third sub-well region unit interposed between adjacent fourth well region units. The third third sub-well region unit is adjacent to the first third sub-well region and the second third sub-well region, respectively. The depth of the third well region is less than the depth of the fourth well region. The third well region has a first doping type.

[0108] In the above technical solution, the breakdown voltage between the emitter E and the base B of the semiconductor device and the breakdown voltage between the collector C and the base B are kept unchanged by setting the intervals of the fourth well region units.

[0109] In a preferred embodiment, the semiconductor device may further include a first isolation structure disposed between the first trench and the third well region. The first isolation structure extends from the top surface of the epitaxial layer into the buried layer. The first isolation structure has a width ranging from 0.5 μm to 0.7 μm and a depth ranging from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0110] The semiconductor device may further include a second isolation structure disposed between the third well region and the first drift region. The second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and is spaced a predetermined distance from the buried layer. The second isolation structure has a width ranging from 0.35 μm to 0.5 μm and a depth ranging from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0111] In another preferred embodiment, the second and third sub-well regions include a plurality of spaced second and third sub-well region units, the plurality of second and third sub-well region units are arranged in a ring shape, and adjacent second and third sub-well region units are separated by an epitaxial layer.

[0112] In the technical solution, the interval of the second and third sub-well region units can narrow the punch through breakdown path of the emitter E and the base B, and the width of the interval region between the adjacent second and third sub-well region units can be adjusted, so that the breakdown voltage between the emitter E and the base B of the semiconductor device and the breakdown voltage between the collector C and the base B are not greatly affected while the beta gain is reduced.

[0113] Further, the application also provides a semiconductor device, which comprises a semiconductor body, a first trench, a first drift region, a fourth well region, a third well region and a first isolation structure.

[0114] The semiconductor body comprises a substrate with a first doping type, a buried layer with a second doping type arranged on the substrate, and an epitaxial layer with the first doping type arranged on the buried layer. The first doping type can be P type, and the second doping type can be N type. Alternatively, the first doping type is N type, and the second doping type is P type.

[0115] The first trench extends from the top surface of the epitaxial layer into the buried layer, and a first conductive material with the second doping type is arranged in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. The first conductive material can serve as the collector C of the semiconductor device because it is in communication with the buried layer. The first trench is arranged in a ring shape, and the device region is in the first trench.

[0116] The first drift region is arranged in the epitaxial layer and located within the range surrounded by the first trench. A spacing is formed between the first drift region and the first trench. The first drift region has the second doping type, and can serve as the emitter E of the semiconductor device.

[0117] The fourth well region is arranged in the epitaxial layer and located between the first trench and the first drift region, and has the second doping type.

[0118] The third well region is arranged in the epitaxial layer, and comprises a first third sub-well region interposed between the fourth well region and the first trench, and a second third sub-well region interposed between the fourth well region and the first drift region. The second third sub-well region and the first third sub-well region are respectively adjacent to the fourth well region. The third well region has the first doping type.

[0119] The first isolation structure is arranged between the first trench and the third well region, and extends from the top surface of the epitaxial layer into the buried layer. The width of the first isolation structure ranges from 0.5 μm to 0.7 μm, and the depth ranges from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0120] In a preferred embodiment, the semiconductor device further includes a second isolation structure disposed between the third well region and the first drift region. The second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and is spaced a predetermined distance from the buried layer. The second isolation structure has a width ranging from 0.35 μm to 0.5 μm and a depth ranging from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0121] In another preferred embodiment, the second and third sub-well regions include a plurality of spaced second and third sub-well region units, the plurality of second and third sub-well region units are arranged in a ring shape, and adjacent second and third sub-well region units are separated by an epitaxial layer.

[0122] The semiconductor device of the present invention can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and simultaneously keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving circuit performance.

[0123] The semiconductor device of the present invention is described in detail below through several specific embodiments in combination with the accompanying drawings to facilitate understanding of the technical solution of the present invention.

[0124] Example 1:

[0125] like Figure 3 and Figure 4 As shown, the semiconductor device in the first embodiment of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a first well region 41 , a second well region 42 and a third well region 50 .

[0126] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 disposed on the substrate 11, and a P-type doped epitaxial layer 13 disposed on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0127] A first trench 20 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The first trench 20 is arranged in a ring shape, defining the device area within the device. A barrier layer 22 is provided on the sidewalls of the first trench 20. The first trench 20 is filled with a first P-type doped conductive material 21—polysilicon. The first conductive material 21 communicates with the buried layer 12, electrically connecting the buried layer 12 to the top surface of the epitaxial layer 13.

[0128] Since the first conductive material 21 is connected to the buried layer 12 , the first conductive material 21 can serve as a collector C of the semiconductor device.

[0129] The first drift region 30 is arranged in the epitaxial layer 13 and located in the range surrounded by the first trench 20. A spacing space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of the semiconductor device.

[0130] The first well region 41 is arranged in the epitaxial layer 13 and located in the spacing space between the first trench 20 and the first drift region 30. The first well region 41 is a weak P-type well region. The first well region 41 is also arranged in a ring shape.

[0131] The second well region 42 is arranged in the epitaxial layer 13 and located below the first well region 41, and the second well region 42 is arranged adjacent to the first well region 41. The second well region 42 is an N-type well region. The second well region 42 is also arranged in a ring shape. The depth of the second well region 42 is less than the depth of the first well region 41.

[0132] The third well region 50 is arranged in the epitaxial layer 13, and the third well region 50 includes a first third sub-well region 51 interposed between the first well region 41 and the first trench 20, and a second third sub-well region 52 interposed between the first well region 41 and the first drift region 30, and the first third sub-well region 51 and the second third sub-well region 52 are arranged adjacent to the first well region 41, respectively. The third well region 50 is also arranged in a ring shape, and the depth of the third well region 50 is equal to the depth of the first well region 41.

[0133] The third well region 50 is a P-type well region, and the doping concentration of the third well region 50 is greater than the doping concentration of the first well region 41.

[0134] The third well region 50 can serve as a base B of the semiconductor device.

[0135] In the above technical solution, the first well region 41, the second well region 42 and the third well region 50 can be formed in the following manner.

[0136] Specifically, the first well region 41 has a first region, the second well region 42 has a second region, and the third well region 50 has a third region.

[0137] First, P-doping is performed in the first region and the third region (first doped region) to form the third well region 50 in the third region and make the first region have a P-type doping type; and then N-type doping is performed in the first region and the second region to counter-dope the P-doped first region, form the first well region 41 in the first region, and form the second well region 42 in the second region.

[0138] The semiconductor device in the embodiment 1 of the present application can further include a second trench 70 and a third trench 80.

[0139] A second trench 70 is located at the periphery of the first trench 20, the second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11, and a second trench structure 71 is arranged in the second trench 70, the second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13.

[0140] A third trench 80 is located between the first trench 20 and the second trench 70, the third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and the depth of the third trench 80 is less than that of the second trench 70. A third trench isolation structure 81 is arranged in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 and the second trench 70 and improve the breakdown voltage between them.

[0141] It should be noted that, Figure 4 The second trench 70 and the third trench 80 in Figure 3 are not shown.

[0142] Embodiment 2:

[0143] Referring to Figure 5 and Figure 6 , the difference between this embodiment 2 and embodiment 1 is that in this embodiment 2, a first isolation structure 61 is further arranged between the first trench 20 and the third well region 50. A second isolation structure 62 is further arranged between the third well region 50 and the first drift region 30.

[0144] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a predetermined distance from the buried layer 12. The first isolation structure 61 and the second isolation structure 62 are both formed by sidewall thermal oxidation and / or oxide deposition.

[0145] It should be noted that, Figure 6 The second trench 70 and the third trench 80 in Figure 5 are not shown.

[0146] Embodiment 3:

[0147] Referring to Figure 7 , the difference between this embodiment 3 and embodiment 1 is that in this embodiment 3, the second third sub-well region 52 includes a plurality of second third sub-well region units 521 arranged at intervals, the plurality of second third sub-well region units 521 are arranged in a ring shape, and adjacent second third sub-well region units 521 are separated by an epitaxial layer.

[0148] Embodiment 4:

[0149] Referring to Figure 8As shown, the difference between the present embodiment 4 and the embodiment 1 is that, in the present embodiment 4, the first well region 41 comprises a plurality of first well region units 411 arranged at intervals, and the plurality of first well region units 411 are arranged in a ring shape.

[0150] The second well region 42 comprises a plurality of second well region units 421 arranged at intervals, and the plurality of second well region units 421 are arranged in a ring shape. The plurality of first well region units 411 and the plurality of second well region units 421 are arranged one by one.

[0151] The third well region 50 further comprises a third third sub-well region unit 531 interposed between adjacent first well region units 411 and adjacent second well region units 421, the third third sub-well region unit 531 is adjacent to the first third sub-well region 51 and the second third sub-well region 52 respectively, and the third third sub-well region unit 531 is adjacent to the adjacent first well region unit 411 and the second well region unit 421 respectively.

[0152] Embodiment 5:

[0153] Reference Figure 9 As shown, the difference between the present embodiment 5 and the embodiment 4 is that, in the present embodiment 5, the first trench 20 and the third well region 50 are further provided with a first isolation structure 61. The third well region 50 and the first drift region 30 are further provided with a second isolation structure 62.

[0154] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a predetermined distance from the buried layer 12. The first isolation structure 61 and the second isolation structure 62 are both formed by sidewall thermal oxidation and / or oxide deposition.

[0155] Embodiment 6:

[0156] Reference Figure 10 As shown, the difference between the present embodiment 6 and the embodiment 4 is that, in the present embodiment 6, the second third sub-well region 52 comprises a plurality of second third sub-well region units 521 arranged at intervals, and the plurality of second third sub-well region units 521 are arranged in a ring shape. Each second third sub-well region unit 521 is arranged one by one and adjacent to the third third sub-well region unit 531. The adjacent second third sub-well region units 521 are separated by an epitaxial layer.

[0157] Embodiment 7:

[0158] Reference Figure 11 And Figure 12 As shown, the semiconductor device in the present embodiment 7 comprises a semiconductor body 10, a first trench 20, a first drift region 30, a fourth well region 43 and a third well region 50.

[0159] The semiconductor body 10 comprises a P-doped substrate 11, an N-doped buried layer 12 arranged on the substrate 11, and a P-doped epitaxial layer 13 arranged on the buried layer 12. The depth of the epitaxial layer is 13 μm, and the depth of the buried layer 12 is 8 μm.

[0160] The first trench 20 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The first trench 20 is arranged in a ring shape and divides a device region in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-doped first conductive material 21 - polysilicon. The first conductive material 21 is in communication with the buried layer 12 and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0161] Since the first conductive material 21 is in communication with the buried layer 12, the first conductive material 21 can serve as a collector C of the semiconductor device.

[0162] The first drift region 30 is arranged in the epitaxial layer 13 and within the range enclosed by the first trench 20. A spacing is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of the semiconductor device.

[0163] The fourth well region 43 is arranged in the epitaxial layer 13 and between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 comprises a plurality of fourth well region units 431 arranged in a spaced-apart manner. The plurality of fourth well region units 431 are arranged in a ring shape.

[0164] Reference is made to Fig. 1, which shows a semiconductor device according to an embodiment of the present application. The semiconductor device comprises a semiconductor body 10, a first trench 20, a first drift region 30, a fourth well region 43, and a third well region 50. Figure 11 As shown in Fig. 1, the third well region 50 is arranged in the epitaxial layer 13, and the third well region 50 comprises a first third sub-well region 51 interposed between the fourth well region 43 and the first trench 20, a second third sub-well region 52 interposed between the fourth well region 43 and the first drift region 30, and a third third sub-well region unit 531 interposed between adjacent fourth well region units 431. The first third sub-well region 51 and the second third sub-well region 52 are respectively arranged adjacent to the fourth well region 43. The third third sub-well region unit 531 is arranged adjacent to the adjacent fourth well region unit 431. The third third sub-well region unit 531 is respectively arranged adjacent to the first third sub-well region 51 and the second third sub-well region 52.

[0165] The third well region 50 is also arranged in a ring shape, and the depth of the third well region 50 is less than the depth of the fourth well region 43. The third well region 50 is a P-type well region and can serve as a base B of the semiconductor device.

[0166] The semiconductor device in the embodiment 7 of the present application can further comprise a second trench 70 and a third trench 80.

[0167] The second trench 70 is located at the periphery of the first trench 20 . The second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11 . A second trench structure 71 is provided in the second trench 70 . The second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13 .

[0168] The third trench 80 is located between the first trench 20 and the second trench 70. The third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a depth less than that of the second trench 70. A third trench isolation structure 81 is disposed in the third trench 80. The third trench structure 81 is used to isolate the first trench 20 from the second trench 70 and improve the breakdown voltage therebetween.

[0169] Example 8:

[0170] refer to Figure 13 and Figure 14 As shown, the difference between the eighth embodiment and the seventh embodiment is that, in the eighth embodiment, a first isolation structure 61 is further provided between the first trench 20 and the third well region 50 , and a second isolation structure 62 is further provided between the third well region 50 and the first drift region 30 .

[0171] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a predetermined distance from the buried layer 12. Both the first isolation structure 61 and the second isolation structure 62 are formed by sidewall thermal oxidation and / or oxide deposition.

[0172] Example 9:

[0173] refer to Figure 15 As shown, the difference between this embodiment 9 and embodiment 7 is that in this embodiment 9, the second and third sub-well regions 52 include a plurality of spaced second and third sub-well region units 521, each second and third sub-well region unit 521 corresponding one-to-one to and adjacent to a third and third sub-well region unit 531. The plurality of second and third sub-well region units 521 are arranged in a ring, and adjacent second and third sub-well region units 521 are separated by an epitaxial layer.

[0174] Example 10:

[0175] refer to Figure 16 As shown, the semiconductor device in embodiment 10 of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a fourth well region 43 , a third well region 50 , a first isolation structure 61 and a second isolation structure 62 .

[0176] The semiconductor body 10 comprises a P-doped substrate 11, an N-doped buried layer 12 arranged on the substrate 11, and a P-doped epitaxial layer 13 arranged on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0177] The first trench 20 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The first trench 20 is arranged in a ring shape and divides a device region in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-doped first conductive material 21 - polysilicon. The first conductive material 21 is in communication with the buried layer 12 and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0178] Since the first conductive material 21 is in communication with the buried layer 12, the first conductive material 21 can serve as a collector C of the semiconductor device.

[0179] The first drift region 30 is arranged in the epitaxial layer 13 and within the range enclosed by the first trench 20. A spacing is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of the semiconductor device.

[0180] The fourth well region 43 is arranged in the epitaxial layer 13 and between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 is arranged in a ring shape.

[0181] The third well region 50 is arranged in the epitaxial layer 13. The third well region 50 comprises a first third sub-well region 51 interposed between the fourth well region 43 and the first trench 20, and a second third sub-well region 52 interposed between the fourth well region 43 and the first drift region 30. The first third sub-well region 51 and the second third sub-well region 52 are respectively arranged adjacent to the fourth well region 43.

[0182] The third well region 50 is also arranged in a ring shape and has a depth smaller than that of the fourth well region 43. The third well region 50 is a P-type well region and can serve as a base B of the semiconductor device.

[0183] The first isolation structure 61 is arranged between the first trench 20 and the third well region 50. The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12.

[0184] The second isolation structure 62 is arranged between the third well region 50 and the first drift region 30. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a predetermined distance from the buried layer 12.

[0185] The first isolation structure 61 and the second isolation structure 62 are both formed by sidewall thermal oxidation and / or oxide deposition.

[0186] The semiconductor device in the embodiment 10 of the present application can further include a second trench 70 and a third trench 80.

[0187] The second trench 70 is located outside the first trench 20, and the second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11. A second trench structure 71 is arranged in the second trench 70, and the second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13.

[0188] The third trench 80 is located between the first trench 20 and the second trench 70, and the third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and the depth of the third trench 80 is less than that of the second trench 70. A third trench isolation structure 81 is arranged in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 and the second trench 70, and to improve the breakdown voltage between them.

[0189] Embodiment 11:

[0190] Reference Figure 17 As shown in the figure, the semiconductor device in the embodiment 11 of the present application includes a semiconductor body 10, a first trench 20, a first drift region 30, a fourth well region 43, and a third well region 50.

[0191] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 arranged on the substrate 11, and a P-type doped epitaxial layer 13 arranged on the buried layer 12. The depth of the epitaxial layer is 13 μm, and the depth of the buried layer 12 is 8 μm.

[0192] The first trench 20 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The first trench 20 is arranged in a ring shape, and divides a device region in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-type doped first conductive material 21 - polysilicon. The first conductive material 21 is in communication with the buried layer 12, and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0193] Since the first conductive material 21 is in communication with the buried layer 12, the first conductive material 21 can be used as the collector C of the semiconductor device.

[0194] The first drift region 30 is arranged in the epitaxial layer 13 and located within the range surrounded by the first trench 20. A spacing space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region, and can be used as the emitter E of the semiconductor device.

[0195] The fourth well region 43 is arranged in the epitaxial layer 13 and located between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 is arranged in a ring shape.

[0196] The third well region 50 is arranged in the epitaxial layer 13, and the third well region 50 includes a first third sub-well region 51 interposed between the fourth well region 43 and the first trench 20, and a second third sub-well region 52 interposed between the fourth well region 43 and the first drift region 30. The first third sub-well region 51 and the second third sub-well region 52 are respectively arranged adjacent to the fourth well region 43. The second third sub-well region 52 includes a plurality of spaced-apart second third sub-well region units 521, and the plurality of second third sub-well region units 521 are arranged in a ring shape, and adjacent second third sub-well region units 521 are separated by the epitaxial layer.

[0197] The third well region 50 is also arranged in a ring shape, and the depth of the third well region 50 is less than the depth of the fourth well region 43. The third well region 50 is a P-type well region. The third well region 50 can serve as a base B of the semiconductor device.

[0198] The semiconductor device in the embodiment 11 of the present application can further include a second trench 70 and a third trench 80.

[0199] The second trench 70 is located at the periphery of the first trench 20, and the second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11. The second trench 70 is provided with a second trench structure 71, and the second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13.

[0200] The third trench 80 is located between the first trench 20 and the second trench 70, and the third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and the depth of the third trench 80 is less than the depth of the second trench 70. The third trench 80 is provided with a third trench isolation structure 81, and the third trench structure 81 is used to isolate the first trench 20 and the second trench 70, and improve the breakdown voltage therebetween.

[0201] Compared with the prior art, the semiconductor device of the present application can reduce the beta gain of the parasitic transistor in the device, improve the breakdown voltage between the collector C and the emitter E, and at the same time, try to maintain the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B is unchanged, and improve the circuit performance.

[0202] The semiconductor device of the present application is compatible with the existing MTI / DTI basic process, does not increase the additional mask cost, reduces the parasitic NPN transistor gain of the BJT structure semiconductor device, and improves the circuit performance.

[0203] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0204] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; a first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is provided in the epitaxial layer and is located within a range surrounded by the first trench, the first drift region having a second doping type; A first well region (41) is provided in the epitaxial layer and located between the first trench and the first drift region, the first well region having a first doping type, a second doping type, or a non-doping type; a second well region (42) disposed in the epitaxial layer and located below the first well region, the second well region having a second doping type; a third well region (50) disposed in the epitaxial layer, the third well region comprising a first third sub-well region (51) interposed between the first well region and the first trench, and a second third sub-well region (52) interposed between the first well region and the first drift region, the third well region having a first doping type; in, When the first well region has a second doping type, the doping concentration of the second well region is greater than the doping concentration of the first well region; When the first well region has a first doping type, the doping concentration of the third well region is greater than the doping concentration of the first well region.

2. The semiconductor device according to claim 1, wherein The sum of the depths of the first well region and the second well region is greater than the depth of the third well region; and / or, The depth of the first well region is equal to the depth of the third well region; and / or, The depth of the second well region is smaller than that of the third well region.

3. The semiconductor device according to claim 1, wherein The first third sub-well region and the second third sub-well region are respectively arranged adjacent to the first well region, and the second well region is arranged adjacent to the first well region.

4. The semiconductor device according to claim 3, wherein The first well region has a first area, the second well region has a second area, and the third well region has a third area; Performing ion implantation of a first doping type in the first region and the third region to form a third well region in the third region, and causing the first region to have the first doping type; performing ion implantation of a second doping type in the first region and the second region to counter-dope the first region having the first doping type, thereby forming a first well region in the first region, and simultaneously forming a second well region in the second region; or, By performing ion implantation of the second doping type in the first region and the second region, a second well region is formed in the second region, and the first region has the second doping type. By performing ion implantation of the first doping type in the first region and the third region, the first region having the second doping type is counter-doped to form a first well region in the first region. At the same time, a third well region is formed in the third region.

5. The semiconductor device according to claim 1, wherein The invention also includes a first isolation structure (61), which is arranged between the first trench and the third well region, and extends from the top surface of the epitaxial layer into the buried layer. The semiconductor device according to claim 1 , wherein: The invention also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

7. The semiconductor device according to claim 1, wherein The first well region includes a plurality of first well region units (411) arranged at intervals, and the second well region includes a plurality of second well region units (421) arranged at intervals, wherein the plurality of first well region units and the plurality of second well region units are arranged in a one-to-one correspondence.

8. The semiconductor device according to claim 7, wherein: The third well region includes a third sub-well region unit (531) inserted between adjacent first well region units and between adjacent second well region units, and the third sub-well region unit is adjacent to the first sub-well region and the second sub-well region respectively.

9. The semiconductor device according to claim 1, wherein The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

10. The semiconductor device according to claim 1, wherein The first trench and the third well region, and the third well region and the first drift region are separated by the epitaxial layer.

11. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; forming a first trench (20) in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the buried layer, a first conductive material (21) having a second doping type being disposed in the first trench, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer; forming a first drift region (30) having a second doping type and a first doping region having a first doping type in the semiconductor body, wherein the first drift region is arranged in the epitaxial layer and is located within a range surrounded by the first trench, and the first doping region is arranged in the epitaxial layer and is located between the first trench and the first drift region; Counter-doping of a second doping type is performed on a portion of the first doping region to form a second well region (42) below the first doping region, forming a first well region (41) within the first doping region, and forming a third well region (50) on a portion of the first doping region that is not counter-doped.

12. A semiconductor device, characterized in that: include: A semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; a first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is provided in the epitaxial layer and is located within a range surrounded by the first trench, the first drift region having a second doping type; a fourth well region (43) disposed in the epitaxial layer and located between the first trench and the first drift region, the fourth well region having a second doping type and comprising a plurality of fourth well region units (431) disposed at intervals; A third well region (50) is arranged in the epitaxial layer, the third well region comprising a first third sub-well region (51) inserted between the fourth well region and the first trench, a second third sub-well region (52) inserted between the fourth well region and the first drift region, and a third third sub-well region unit (531) inserted between adjacent fourth well region units, the third third sub-well region unit being adjacent to the first third sub-well region and the second third sub-well region, respectively, and the third well region having a first doping type.

13. The semiconductor device according to claim 12, wherein: The depth of the fourth well region is greater than the depth of the third well region.

14. The semiconductor device according to claim 12, wherein: The invention also includes a first isolation structure (61), which is arranged between the first trench and the third well region, and extends from the top surface of the epitaxial layer into the buried layer.

15. The semiconductor device according to claim 12, wherein The invention also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

16. The semiconductor device according to claim 12, wherein: The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

17. A semiconductor device, characterized in that: include: A semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; a first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is provided in the epitaxial layer and is located within a range surrounded by the first trench, the first drift region having a second doping type; a fourth well region (43) disposed in the epitaxial layer and located between the first trench and the first drift region, the fourth well region having a second doping type; a third well region (50) disposed in the epitaxial layer, the third well region comprising a first third sub-well region (51) interposed between the fourth well region and the first trench, and a second third sub-well region (52) interposed between the fourth well region and the first drift region, the third well region having a first doping type; A first isolation structure (61) is provided between the first trench and the third well region, and the first isolation structure extends from the top surface of the epitaxial layer into the buried layer.

18. The semiconductor device according to claim 17, wherein: The invention also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

19. The semiconductor device according to claim 17, wherein The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

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