Semiconductor structure and preparation method thereof

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes: providing an initial structure including a stack of a dielectric layer and a conductive layer, the conductive layer including a plurality of conductive strips, a first hole penetrating through the dielectric layer and the conductive strips in a first direction, and the first hole of the conductive strips being divided into two parts; laterally thinning the conductive strips to form a first gap; forming a first indium gallium zinc oxide in the first gap; laterally thinning the dielectric layer to expose part of the first indium gallium zinc oxide and form a second gap; forming a second indium gallium zinc oxide on the surface of the exposed first indium gallium zinc oxide, and the concentration of indium in the first indium gallium zinc oxide being greater than the concentration of indium in the second indium gallium zinc oxide; and forming a gate structure in the first hole and the second gap. The above technical solution forms the first indium gallium zinc oxide with a higher concentration of indium between the second indium gallium zinc oxide and the conductive strips, thereby reducing the contact resistance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In dynamic random access memory (DRAM) manufacturing, buried bit lines are often used. As semiconductor process sizes continue to shrink, existing fabrication techniques are increasingly unable to meet these demands. Currently, 3D DRAM based on indium gallium zinc oxide (IGZO) has become a key research area within the industry due to its excellent leakage resistance, low cost, and relatively simple manufacturing process.

[0003] However, the contact resistance between IGZO and metal electrodes is relatively high, which affects the performance of the device. Therefore, how to reduce the contact resistance between IGZO and metal electrodes and improve device performance is a problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present disclosure is to reduce the contact resistance between IGZO and metal electrodes, improve device performance, and provide a semiconductor structure and a preparation method thereof.

[0005] To address the above-mentioned problems, the present disclosure provides a method for fabricating a semiconductor structure, comprising: providing an initial structure, the initial structure comprising a dielectric layer and a conductive layer stacked sequentially along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and spaced apart along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being separated into two independent portions by the first hole in the second direction; laterally thinning the conductive strips along the second direction to form a first gap between two adjacent dielectric layers; forming a first indium gallium zinc oxide within the first gap; laterally thinning the dielectric layer along the second direction to expose a portion of the first indium gallium zinc oxide and form a second gap between two adjacent first indium gallium zinc oxides; forming a second indium gallium zinc oxide on a surface of the exposed first indium gallium zinc oxide, wherein the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; and forming a gate structure within the first hole and the second gap.

[0006] In some embodiments, after the step of laterally thinning the dielectric layer along the second direction, the method further includes the following step: performing plasma treatment on the exposed first indium gallium zinc oxide to form oxygen vacancies in the first indium gallium zinc oxide.

[0007] In some embodiments, during the plasma treatment of the exposed first indium gallium zinc oxide, the plasma concentration decreases with the treatment time.

[0008] In some embodiments, in the step of laterally thinning the dielectric layer in the second direction, the dielectric layer is thinned in the second direction in multiple times to partially expose the first indium gallium zinc oxide; and the exposed first indium gallium zinc oxide is treated after each time of thinning the dielectric layer in the second direction to form oxygen vacancies in the first indium gallium zinc oxide.

[0009] In some embodiments, in the step of treating the exposed first indium gallium zinc oxide after each time of thinning the dielectric layer in the second direction, the exposed first indium gallium zinc oxide is subjected to plasma treatment after each time of thinning the dielectric layer in the second direction, and the plasma concentration decreases with the increase of the number of times of thinning the dielectric layer in the second direction to form a gradient of oxygen vacancy concentration in the first indium gallium zinc oxide.

[0010] In some embodiments, the step of treating the first indium gallium zinc oxide after the plasma treatment further comprises annealing the first indium gallium zinc oxide.

[0011] In some embodiments, the molar component ratio of indium, gallium and zinc in the first indium gallium zinc oxide is (9-10): 1: 1.

[0012] To solve the above problems, the present disclosure further provides a semiconductor structure, comprising: an initial structure, the initial structure comprising a dielectric layer and a conductive layer stacked in a first direction, the conductive layer comprising a plurality of conductive strips extending in a second direction and spaced apart in a third direction, in the second direction, the conductive strips are divided into first parts and second parts independent of each other, and the opposite ends of the first parts and the second parts are recessed in the dielectric layer; a first indium gallium zinc oxide arranged at the opposite ends of the first parts and the second parts of the conductive strips, respectively, and the ends of the first indium gallium zinc oxide protrude from the dielectric layer; a second indium gallium zinc oxide covering the surface of the region where the first indium gallium zinc oxide protrudes from the dielectric layer, and the concentration of indium in the first indium gallium zinc oxide is greater than that in the second indium gallium zinc oxide; and a gate structure covering the second indium gallium zinc oxide.

[0013] In some embodiments, the oxygen vacancy concentration of the first indium gallium zinc oxide near one end of the second indium gallium zinc oxide is greater than that far from the other end of the second indium gallium zinc oxide.

[0014] In some embodiments, the oxygen vacancy concentration of the first indium gallium zinc oxide decreases in a gradient.

[0015] The preparation method of the semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by forming the first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is conducive to further reducing the contact resistance between the second indium gallium zinc oxide and the conductive strip. Further, the oxygen vacancy concentration gradient is formed in the first indium gallium zinc oxide, which can prevent the transistor from leaking and reduce the power consumption of the device. In addition, annealing the first indium gallium zinc oxide can improve the damage to the surface of the first indium gallium zinc oxide and improve its electrical properties, such as conductivity, carrier concentration, and mobility.

[0016] The semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by setting the first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is conducive to further reducing the contact resistance between the second indium gallium zinc oxide and the conductive strip.

[0017] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. Techniques, methods and devices known to those skilled in the relevant art can not be discussed in detail, but should be considered as part of the authorized description under appropriate circumstances. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present disclosure, the drawings needed in the specific embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some specific embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0019] Figure 1 It is a structural schematic diagram of the semiconductor structure in the prior art.

[0020] Figure 2 It is a step flow chart of an embodiment of the semiconductor structure preparation method of the present disclosure.

[0021] Figures 3A to 3H It is a process flow chart of an embodiment of the semiconductor structure preparation method of the present disclosure.

[0022] Figures 4A to 4D It is a process flow chart of another embodiment of the semiconductor structure preparation method of the present disclosure. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, and not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0024] See also Figure 1 , which is a schematic diagram of the structure of a semiconductor structure in the prior art. Figure 1 As shown, the semiconductor structure includes: a silicon dioxide layer 11, a metal electrode 12, an annular channel 13, a gate dielectric layer 14, and a gate 15. The multiple silicon dioxide layers 11 are stacked in sequence, and the metal electrode 12 is located inside the stacked silicon dioxide layers 11. The metal electrode 12 is divided into two parts, located on both sides of the annular channel 13, and the annular channel 13 is located on the surface of the part of the metal electrode 12 protruding from the silicon dioxide layer 11. The gate dielectric layer 14 and the gate 15 are located in the silicon dioxide layer 11 and between the two parts of the metal electrode 12, and are located on the surface of the annular channel 13. The material of the metal electrode 12 of the semiconductor structure is metal tungsten, and the material of the annular channel 13 is indium gallium zinc oxide. The contact resistance between metal tungsten and indium gallium zinc oxide is large, which greatly affects the performance of the device.

[0025] In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure. Figure 2 as well as Figures 3A to 3H ,in, Figure 2 A flowchart of one embodiment of a method for preparing a semiconductor structure disclosed herein; Figures 3A to 3H FIG. 1 is a process flow chart of an embodiment of the method for preparing a semiconductor structure disclosed herein. Figure 2 As shown, the method for preparing a semiconductor structure includes: step S21, providing an initial structure, the initial structure including a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer including a plurality of conductive strips extending along a second direction and spaced apart along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being separated into two independent parts by the first hole in the second direction; step S22, laterally thinning the conductive strips along the second direction to form a first gap between two adjacent dielectric layers; step S23, forming a first indium gallium zinc oxide in the first gap; step S24, laterally thinning the dielectric layer along the second direction to expose a portion of the first indium gallium zinc oxide and form a second gap between two adjacent first indium gallium zinc oxides; step S25, forming a second indium gallium zinc oxide on a surface of the exposed first indium gallium zinc oxide, wherein the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; step S26, forming a gate structure in the first hole and the second gap.

[0026] See also Figure 3A And step S21 provides an initial structure. The initial structure includes a dielectric layer 31 and a conductive layer 32 stacked in sequence along a first direction D1. The conductive layer 32 includes a plurality of conductive strips 320 extending along a second direction D2 and spaced apart along a third direction D3. A first hole 391 penetrates the dielectric layer 31 and the conductive strips 320 along the first direction D1. The conductive strips 320 are separated into two independent portions in the second direction D2 by the first hole 391. As shown in the figure, the two independent conductive strip portions are a first portion 321 and a second portion 322. In some embodiments, the dielectric layer 31 is made of silicon oxide, and the conductive strips 320 are made of a metal, such as tungsten.

[0027] The first direction D1 is a direction perpendicular to the initial structure surface, the second direction D2 and the third direction D3 are directions parallel to the initial structure surface, and the second direction D2 is perpendicular to the third direction D3. In this embodiment, the first direction D1 is the Z direction in the Cartesian coordinate system, the second direction D2 is the X direction in the Cartesian coordinate system, and the third direction is the Y direction in the Cartesian coordinate system.

[0028] See also Figure 3B And step S22, laterally thinning the conductive strip 320 along the second direction D2 to form a first gap 381 between two adjacent dielectric layers 31. In some embodiments, the conductive strip 320 is laterally thinned along the second direction D2 by an etching process on the sidewalls of the first hole 391. The portion of the conductive strip 320 exposed by the sidewalls of the first hole 391 is removed to form the first gap 381.

[0029] See also Figure 3D And step S23, forming the first indium gallium zinc oxide 331 in the first gap 381. In some embodiments, the step of forming the first indium gallium zinc oxide 331 in the first gap 381 further includes the following steps:

[0030] like Figure 3C As shown, in the first hole 391 and the first gap 381 (shown in Figure 3B ). In some embodiments, the molar ratio of indium, gallium, and zinc in the first indium, gallium, and zinc oxide material layer 371 is (9-10):1:1, forming a material layer with a high indium-gallium ratio. In this embodiment, the first indium, gallium, and zinc oxide layer 371 can be deposited in the first hole 391 and the first gap 381 using an atomic layer deposition process, and the ratio of indium to gallium can be controlled by adjusting the flow rate of the precursor gas.

[0031] like Figure 3D As shown, the first indium gallium zinc oxide material layer 371 in the first hole 391 is removed, and the first gap 381 (shown in FIG. Figure 3B) is used as the first InGaZnO material layer 371 in the first hole 391. In this embodiment, the first InGaZnO material layer 371 in the first hole 391 is removed by dry etching.

[0032] After completing the above steps, the first gap 381 (shown in FIG) can be obtained. Figure 3B ) within the first indium gallium zinc oxide 331.

[0033] In some embodiments, the molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide 331 is (9-10):1:1, that is, the first indium gallium zinc oxide 331 has a high-indium structure.

[0034] See also Figure 3E And step S24, the dielectric layer 31 is laterally thinned along the second direction D2, exposing portions of the first indium gallium zinc oxides 331 and forming second gaps 382 between adjacent first indium gallium zinc oxides 331. In some embodiments, the dielectric layer 31 can be laterally thinned along the second direction D2 by an etching process on the sidewalls of the first hole 391, with the removed areas of the dielectric layer 31 forming the second gaps 382.

[0035] like Figure 3F As shown, in some embodiments, after the step of laterally thinning the dielectric layer 31 along the second direction D2, the following step is further included: performing a plasma treatment on the exposed first indium gallium zinc oxide 331 to form oxygen vacancies 34 in the first indium gallium zinc oxide 331. The formation of oxygen vacancies 34 in the first indium gallium zinc oxide 331 can prevent leakage of the semiconductor structure and reduce device power consumption.

[0036] In some embodiments, plasma treatment includes, but is not limited to, methods for increasing the concentration of oxygen vacancies, such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, hydrogen ion plasma treatment is used to treat the first indium gallium zinc oxide 331. The hydrogen ions bombard the metal-oxygen bonds, breaking them and forming oxygen vacancies in the first indium gallium zinc oxide.

[0037] In this embodiment, during the plasma treatment of the exposed first indium gallium zinc oxide 331, the plasma concentration decreases over time. This decrease in plasma concentration over time also forms an oxygen vacancy concentration gradient within the first indium gallium zinc oxide 331, thereby preventing transistor leakage and reducing device power consumption.

[0038] After the plasma treatment of the first InGaZn oxide 331, the method further includes annealing the first InGaZn oxide 331. The annealing process can reduce damage to the first InGaZn oxide 331 caused by the plasma treatment and improve its electrical properties, such as conductivity, carrier concentration, and mobility.

[0039] In the above embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment after the dielectric layer 31 is thinned in the second direction D2. In other embodiments, the dielectric layer 31 can be thinned in the second direction D2 in multiple times to partially expose the first indium gallium zinc oxide 331 in the step of thinning the dielectric layer 31 in the second direction D2, and the exposed first indium gallium zinc oxide 331 is subjected to treatment after each time the dielectric layer 31 is thinned in the second direction D2 to form the oxygen vacancy 34 in the first indium gallium zinc oxide 331. Forming the oxygen vacancy 34 in the first indium gallium zinc oxide 331 can prevent leakage of the transistor and reduce power consumption of the device. Please refer to Figures 4A to 4D which is a process flow diagram of another embodiment of the plasma treatment of the first indium gallium zinc oxide 331.

[0040] Please refer to the embodiment shown in Figures 4A to 4D

[0041] As shown in Figure 4A , the dielectric layer 31 is thinned in the second direction D2 to expose the first indium gallium zinc oxide 331. For example, the dielectric layer 31 is thinned in the second direction D2 by an etching process.

[0042] As shown in Figure 4B , the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form the oxygen vacancy 34 in the first indium gallium zinc oxide 331. In some embodiments, the plasma treatment includes but is not limited to methods of increasing the oxygen vacancy concentration such as hydrogen ion plasma treatment, indium ion doping, argon ion plasma treatment, etc. In this embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment by a hydrogen ion plasma treatment process.

[0043] As shown in Figure 4C , the dielectric layer 31 is continuously thinned in the second direction D2 to expose the first indium gallium zinc oxide 331 to a target position and form a second gap 382 between the two adjacent first indium gallium zinc oxides 331.

[0044] As shown in Figure 4D , the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form the oxygen vacancy 34 in the first indium gallium zinc oxide 331. In some embodiments, the plasma treatment includes but is not limited to methods of increasing the oxygen vacancy concentration such as hydrogen ion plasma treatment, indium ion doping, argon ion plasma treatment, etc. In this embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment by a hydrogen ion plasma treatment process.

[0045] ​In this step, all exposed areas of the first indium gallium zinc oxide 331 are plasma treated. The oxygen vacancy concentrations of the areas that have been plasma treated previously are superimposed, and the oxygen vacancy concentration of the areas that are plasma treated for the first time in this step is the oxygen vacancy concentration formed by the current plasma treatment, thereby forming an oxygen vacancy concentration gradient in the exposed areas of the first indium gallium zinc oxide 331.

[0046] In some embodiments, during the step of treating the exposed first indium gallium zinc oxide 331 after each lateral thinning of the dielectric layer 31, the exposed first indium gallium zinc oxide 331 is subjected to a plasma treatment, and the plasma concentration decreases as the number of lateral thinnings of the dielectric layer 31 increases, thereby further forming an oxygen vacancy concentration gradient in the first indium gallium zinc oxide 331. Forming an oxygen vacancy concentration gradient in the first indium gallium zinc oxide 331 can further enhance electrical conductivity and reduce contact resistance.

[0047] In an embodiment where the dielectric layer 31 is thinned in stages and the exposed first indium gallium zinc oxide 331 is plasma treated after each thinning step along the second direction D2, an annealing process is performed after all thinning and plasma treatment steps are completed. The annealing process can mitigate damage to the first indium gallium zinc oxide 331 caused by the plasma treatment and improve its electrical properties, such as conductivity, carrier concentration, and mobility.

[0048] In the above embodiment, the dielectric layer 31 is laterally thinned twice and plasma treatment is performed twice. In other embodiments, the dielectric layer 31 may be laterally thinned multiple times and plasma treatment may be performed multiple times, for example, three times or more.

[0049] Please continue reading Figure 2 、 Figure 3G And in step S25, a second indium gallium zinc oxide 332 is formed on the exposed surface of the first indium gallium zinc oxide 331, wherein the indium concentration in the first indium gallium zinc oxide 331 is greater than the indium concentration in the second indium gallium zinc oxide 332. The second indium gallium zinc oxide 332 covers the exposed surface of the first indium gallium zinc oxide 331 and can be electrically connected to the conductive strip 320 through the first indium gallium zinc oxide 331. By forming the first indium gallium zinc oxide 331 with a higher indium concentration between the second indium gallium zinc oxide 332 and the conductive strip 320, the disclosed semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide 332 and the conductive strip 320. In some embodiments, the second indium gallium zinc oxide 332 can be deposited using an atomic layer deposition process.

[0050] In this step, the second InGaZnO 332 only covers the exposed surface of the first InGaZnO 331 , the surface of the dielectric layer 31 is not covered by the second InGaZnO 332 , and the second gap 382 is not filled by the second InGaZnO 332 .

[0051] In addition, in the embodiment in which the dielectric layer 31 is laterally thinned multiple times and the plasma treatment is performed twice, the second indium gallium zinc oxide 332 formed in step S25 is the same as that in the present embodiment.

[0052] See also Figure 1 、 Figure 3H And step S26, forming a gate structure 35 within the first hole 391 and the second gap 382. Methods for forming the gate structure 35 include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. The gate structure 35 further includes a gate 351 and a gate dielectric layer 352. The gate dielectric layer 352 is disposed at least between the gate 351 and the second indium gallium zinc oxide 332 to insulate the gate 351 from the second indium gallium zinc oxide 332.

[0053] In addition, in the embodiment where the dielectric layer 31 is thinned laterally multiple times and the plasma treatment is performed twice (ie Figures 4A to 4D The gate structure 35 formed in step S26 is the same as that of this embodiment. The above technical solution reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by forming a first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. Furthermore, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which further reduces the contact resistance. Furthermore, an oxygen vacancy concentration gradient is formed within the first indium gallium zinc oxide, which can prevent transistor leakage and reduce device power consumption. Furthermore, annealing the first indium gallium zinc oxide can reduce surface damage on the first indium gallium zinc oxide and improve its electrical properties, such as conductivity, carrier concentration, and mobility.

[0054] Based on the same inventive concept, an embodiment of the present disclosure further provides a semiconductor structure.

[0055] See also Figure 3H , which is a schematic structural diagram of an embodiment of the semiconductor structure disclosed in the present invention. Figure 3HAs shown, the semiconductor structure includes an initial structure, a first indium gallium zinc oxide 331, a second indium gallium zinc oxide 332, and a gate structure 35. The initial structure includes a dielectric layer 31 and a conductive layer 32 stacked in sequence along a first direction D1. The conductive layer 32 includes a plurality of conductive strips 320 extending along a second direction D2 and spaced apart along a third direction D3. In the second direction D2, the conductive strips 320 are separated into independent first and second portions 321, 322, with the opposing ends of the first and second portions 321, 322 recessed into the dielectric layer 31. The first indium gallium zinc oxide 331 is disposed at the opposing ends of the first and second portions 321, 322 of the conductive strips 320, respectively, with the ends of the first indium gallium zinc oxide 331 protruding from the dielectric layer 31. The second indium gallium zinc oxide 332 covers the surface of the first indium gallium zinc oxide 331 protruding from the dielectric layer 31. The indium concentration in the first indium gallium zinc oxide 331 is greater than that in the second indium gallium zinc oxide 332. The gate structure 15 covers the second InGaZnO 332 .

[0056] The above technical solution reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by placing a first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. Furthermore, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first and second indium gallium zinc oxides, further reducing the contact resistance between the second indium gallium zinc oxide and the conductive strip.

[0057] The gate structure, the second InGaZnO 332 , the first InGaZnO 331 and the conductive strip constitute a transistor. The first portion of the conductive strip can serve as a source region of the transistor, and the second portion of the conductive strip can serve as a drain region of the transistor.

[0058] In some embodiments, the molar ratio of indium gallium zinc in the first indium gallium zinc oxide 331 is (9-10): 1: 1. The first indium gallium zinc oxide 331 with a high indium gallium ratio can reduce the contact resistance between the second indium gallium zinc oxide 332 and the conductive strip.

[0059] In some embodiments, oxygen vacancies 34 are formed in the first indium gallium zinc oxide 331, which can prevent transistor leakage and reduce device power consumption. Figure 3H The embodiment shown differs in that Figure 4D In the embodiment shown, the concentration of oxygen vacancies 34 at the end of the first indium gallium zinc oxide 331 close to the second indium gallium zinc oxide 332 is greater than the concentration of oxygen vacancies 34 at the end away from the second indium gallium zinc oxide 332. Figure 4DIn the shown embodiment, the concentration of oxygen vacancies 34 in the first indium gallium zinc oxide 331 decreases in a gradient. Forming a concentration gradient of oxygen vacancies in the first indium gallium zinc oxide 331 can further improve the conductive effect and reduce the contact resistance between the second indium gallium zinc oxide and the conductive strip.

[0060] It should be noted that reference to "an embodiment", "one embodiment", "an example embodiment", "some embodiments", etc., in the specification indicates that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0061] Generally, the scope of a term is to be understood commensurate with the term's context and use. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as "a", "an", or "the", again, depending at least in part upon context, can be understood to take either the singular or plural connotation, allowing for either the singular or plural structures, or combinations thereof. Further, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but, instead, can also allow for consideration of other factors not necessarily explicitly described or not otherwise readily apparent. It will also be noted that "connected" or "coupled" as used herein can be used broadly and encompass both direct and indirect coupling or connection, and can further include one or more intermediate coupled or connected entities.

[0062] It should be noted that the terms "comprises", "comprising", "includes", "including", "has", "having" and variants thereof in the documents of the present disclosure are intended to cover both the case where one or more features, structures, or characteristics are included and the case where one or more features, structures, or characteristics are not included. The terms "first", "second", and the like, do not denote any order, quantity, combination, or otherwise, but are used to identify one feature from another, and a person of ordinary skill in the art will understand that the data thus identified can be interchanged with other data as appropriate. Also, the embodiments and features of the disclosure can be combined with each other as much as possible unless they conflict with each other. Furthermore, in the above description, descriptions of well-known components and techniques have been omitted to avoid unnecessarily obscuring the concept of the disclosure. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between the embodiments are referred to each other.

[0063] The above merely preferred embodiments of the present disclosure, it should be noted that for those skilled in the art, without departing from the principles of the present disclosure, can also make several improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing an initial structure, the initial structure comprising a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and spaced apart along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being separated into two independent parts by the first hole in the second direction; Laterally thinning the conductive strip along a second direction to form a first gap between two adjacent dielectric layers; forming a first indium gallium zinc oxide in the first gap; Laterally thinning the dielectric layer along a second direction to expose a portion of the first indium gallium zinc oxide and forming a second gap between two adjacent first indium gallium zinc oxides; forming a second indium gallium zinc oxide on the exposed surface of the first indium gallium zinc oxide, wherein the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; A gate structure is formed in the first hole and the second gap.

2. The method according to claim 1, characterized in that After the step of laterally thinning the dielectric layer along the second direction, the method further includes the following step: performing plasma treatment on the exposed first indium gallium zinc oxide to form oxygen vacancies in the first indium gallium zinc oxide.

3. The method according to claim 2, characterized in that During the process of performing plasma treatment on the exposed first indium gallium zinc oxide, the plasma concentration decreases with the treatment time.

4. The method according to claim 1, wherein In the step of laterally thinning the dielectric layer along the second direction, the dielectric layer is laterally thinned along the second direction in multiple steps to partially expose the first indium gallium zinc oxide; After each time the dielectric layer is laterally thinned along the second direction, the exposed first indium gallium zinc oxide is treated to form oxygen vacancies in the first indium gallium zinc oxide; wherein the exposed first indium gallium zinc oxide is subjected to plasma treatment.

5. The method according to claim 4, characterized in that In the step of treating the exposed first indium gallium zinc oxide after each laterally thinning the dielectric layer along the second direction, the plasma concentration decreases as the number of times the dielectric layer is laterally thinned increases, so as to form an oxygen vacancy concentration gradient in the first indium gallium zinc oxide.

6. The method according to claim 2, 3 or 5, characterized in that After the first indium gallium zinc oxide is subjected to plasma treatment, the method further includes: annealing the first indium gallium zinc oxide.

7. The method according to claim 1, characterized in that The molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:

1.

8. A semiconductor structure, characterized in that include: an initial structure comprising a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and spaced apart along a third direction, wherein in the second direction, the conductive strips are separated into a first portion and a second portion that are independent of each other, and opposite ends of the first portion and the second portion are recessed into the dielectric layer; a first indium gallium zinc oxide, disposed at opposite ends of the first portion and the second portion of the conductive strip, and the ends of the first indium gallium zinc oxide both protrude from the dielectric layer; a second indium gallium zinc oxide covering a surface of a region of the first indium gallium zinc oxide protruding from the dielectric layer, wherein a concentration of indium in the first indium gallium zinc oxide is greater than a concentration of indium in the second indium gallium zinc oxide; A gate structure covers the second indium gallium zinc oxide.

9. The semiconductor structure according to claim 8, wherein: The oxygen vacancy concentration at one end of the first indium gallium zinc oxide close to the second indium gallium zinc oxide is greater than the oxygen vacancy concentration at a side away from the second indium gallium zinc oxide.

10. The semiconductor structure according to claim 9, wherein: The concentration of oxygen vacancies in the first indium gallium zinc oxide decreases gradually.

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