A semiconductor device terminal structure and preparation method thereof, and a semiconductor device

Abstract

The present invention provides a semiconductor device terminal structure, a preparation method thereof, and a semiconductor device, belonging to the technical field of semiconductor devices. The semiconductor device terminal structure has a recessed structure etched in the middle of a drift layer, and a first doped region is provided on the sidewalls and corners of the recessed structure near the main junction region, and a second doped region is provided on the sidewalls and corners near the cutting path region. A third doped region is provided in the drift layer of the main junction region. A terminal structure is provided at the bottom of the recessed structure. A buried layer is provided in the drift layer at a position higher than the terminal structure. A field plate is provided within the recessed structure. By directly connecting the first doped region and the second doped region to the terminal structure, and by directly connecting the first doped region to the third doped region, the function of the field plate and the buried layer is coordinated, so that the terminal structure of the semiconductor device has the functions of preventing premature breakdown of the main junction, preventing premature breakdown of the cutting path region, blocking the cathode potential, and blocking leakage current.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device terminal structure and a preparation method thereof, as well as a semiconductor device comprising the semiconductor device terminal structure. Background Art

[0002] When in the blocking state, a semiconductor device primarily carries voltage through the depletion region formed by the pn junction (main junction) under reverse bias. According to Poisson's equation, the peak electric field intensity in the depletion region is located near the pn junction; when the peak electric field intensity reaches the critical breakdown electric field intensity of the semiconductor material, the device will breakdown. In the actual fabrication process, cylindrical and spherical junctions form at the edges and corners of the pn junction. Due to the curvature effect, the electric field near these junctions is more concentrated, and the electric field intensity is much greater than that of the parallel plane junction in the middle region. Consequently, the edges and corners will breakdown before the parallel plane junction, resulting in a device breakdown voltage far lower than the ideal value.

[0003] To alleviate the problem of premature breakdown at the edges and corners of the pn junction, where curvature reduces device blocking capability, the industry often adds termination structures around the pn junction. These structures disperse the electric field that originally gathered at the main junction edge, reducing the field strength there and bringing the device's breakdown voltage closer to the ideal value for a parallel-plane junction.

[0004] Current junction termination technology is relatively mature for silicon materials. However, for third-generation wide-bandgap semiconductor materials, such as silicon carbide, firstly, due to the extremely low diffusion coefficient of impurities in silicon carbide materials, the doping of silicon carbide materials is often performed through high-temperature ion implantation to form a shallow pn junction, resulting in a smaller radius of curvature of the pn junction of silicon carbide power devices, making it easier for the electric field to concentrate, and further reducing the blocking capability of the device and the protection capability of the junction terminal. Secondly, in a high-voltage, high-temperature, and high-humidity environment, charge accumulation, moisture corrosion, and ion migration will occur at the terminal, and the electrode on the front of the device and the cutting path may be short-circuited. At this time, the cutting path and the back electrode, as well as the main junction and the back electrode, need to withstand the blocking voltage of the device. The traditional terminal structure only protects the main junction and ignores the protection of the cutting path area, resulting in increased leakage current in the cutting path area or premature breakdown in the cutting path area, and the breakdown voltage of the device is lower than the ideal value. Third, on the outside of the junction terminal and at the outermost edge of the device (i.e., the cutting path area of ​​the device), when the device is in the blocking state, the potential of the cutting path area is equal to the bus voltage, while the potential of the electrode in the middle of the front of the device is 0V, which means that there is a huge potential difference between the electrode and the cutting path. Air breakdown may occur between the front electrode and the cutting path, causing the device to burn. Summary of the Invention

[0005] Based on the above technical problems, the present invention provides a semiconductor device terminal structure that has the functions of increasing the device breakdown voltage, preventing premature breakdown of the main junction and the cutting path area, blocking cathode potential, and blocking leakage current.

[0006] Specifically, in order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0007] A semiconductor device terminal structure comprises a substrate and a drift layer located on the substrate; the middle portion of the drift layer is recessed toward the substrate to form a recessed structure; the recessed structure has a first sidewall and a second sidewall; a first doped region is provided on the first sidewall and at a corner where the first sidewall is connected to the bottom of the recessed structure; a second doped region is provided on the second sidewall and at a corner where the second sidewall is connected to the bottom of the recessed structure; a buried layer is provided in the drift layer around the recessed structure; the first doped region and the second doped region are both in direct contact with the buried layer; in the direction from the substrate to the drift layer, the height of the buried layer is higher than the height of the bottom of the recessed structure; the interior of the recessed structure is filled with an insulating dielectric layer; the first doped region and the second doped region are in direct contact with the buried layer; Field plates are provided on the inner sides of one side wall and the second side wall; the field plates are separated from the first doping region and the second doping region by the insulating dielectric layer; a terminal structure is provided at the bottom of the recessed structure; the first doping region and the second doping region are in direct contact with the terminal structure; a third doping region is provided on the upper layer of the drift layer in the main junction area of ​​the semiconductor device, and the height of the third doping region is higher than the height of the buried layer along the direction from the substrate to the drift layer; the first doping region is in direct contact with the third doping region; the doping types of the substrate and the drift layer are both the first doping type; the doping types of the first doping region, the second doping region, the third doping region, the buried layer and the terminal structure are all the second doping type.

[0008] In a preferred embodiment, the recessed structure is a groove whose bottom surface is parallel to the substrate.

[0009] In a preferred solution, the terminal structure is a field limiting ring, a junction terminal extension structure, a field plate, or a combination of these.

[0010] In a preferred embodiment, the substrate is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate; or / and the material of the field plate is a metal material or a semiconductor material.

[0011] The present invention further provides a method for preparing the semiconductor device terminal structure described in any of the above solutions, comprising the following steps:

[0012] S1. growing a drift layer on a substrate; forming a buried layer in the drift layer;

[0013] S2, forming a concave structure in the middle of the drift layer;

[0014] S3, forming a first doped region on a first sidewall of the recessed structure near the main junction region, and forming a second doped region on a second sidewall near the cutting street region; forming a terminal structure at the bottom of the recessed structure; and forming a third doped region in an upper layer of the drift layer of the main junction region;

[0015] S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewalls and bottom of the recessed structure;

[0016] S5. forming a field plate in the recessed structure;

[0017] S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

[0018] In a preferred embodiment, step S1 includes the following steps: growing a first drift layer on the substrate, forming the buried layer on the upper surface of the first drift layer, and forming a second drift layer on the upper surface of the buried layer; the second drift layer and the first drift layer have the same doping type.

[0019] The present invention also provides a semiconductor device comprising the semiconductor device terminal structure.

[0020] In a preferred embodiment, a fourth doping region is provided on the upper layer of the drift layer located in the cutting zone area of ​​the semiconductor device; the height of the fourth doping region is higher than the height of the buried layer along the direction from the substrate to the drift layer; the doping type of the fourth doping region is the same as the doping type of the first doping region.

[0021] In a preferred solution, the drift layer includes a first drift layer and a second drift layer, the first drift layer is located between the substrate and the buried layer, the second drift layer is located above the buried layer, and the second drift layer and the first drift layer have the same doping type.

[0022] In a preferred embodiment, an anode is deposited on the upper surface of the drift layer located in the main junction region of the semiconductor device, the insulating dielectric layer extends from the inside of the recessed structure to the upper surface of the drift layer, and the field plate extends from the inner side of the first side wall to the upper surface of the insulating dielectric layer located in the main junction region until it contacts the anode.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] (1) In the terminal structure of the semiconductor device provided in the present invention, a recessed structure deeper than the buried layer (deeper than the third doped region located in the main junction region) is etched in the middle of the drift layer, and a first doped region is provided at the sidewall and corner of the recessed structure close to the main junction region. A terminal structure directly connected to the first doped region is provided at the bottom of the recessed structure, thereby preventing the main junction from being broken down prematurely.

[0025] (2) By setting a grounded or floating field plate inside the recessed structure, the electric field distribution inside the device is modulated, thereby alleviating the electric field concentration near the corners of the main junction and the first doped region, and further alleviating the problem of reduced device breakdown voltage.

[0026] (3) By setting a second doping region on the sidewalls and corners of the recessed structure close to the cutting path area, setting a terminal structure directly connected to the second doping region at the bottom of the recessed structure, and coordinating with a grounded or floating field plate set inside the recessed structure, the problem of premature breakdown of the cutting path area caused by a short circuit between the cutting path surface and the anode metal is solved.

[0027] (4) The buried layer set in the main junction area and the cutting channel area can isolate the cathode potential and block the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the structure prepared in step S1 of Example 3 of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure prepared in step S2 of Example 3 of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure prepared in step S3 of Example 3 of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure prepared in step S4 of Example 3 of the present invention;

[0032] Figure 5 This is a schematic diagram of the structure prepared in step S5 of Example 3 of the present invention;

[0033] Figure 6 A schematic diagram of a semiconductor device terminal structure prepared in step S6 of Example 3 of the present invention;

[0034] Figure 7 A schematic structural diagram of a semiconductor device provided by the present invention;

[0035] Figure 8 A schematic structural diagram of another semiconductor device provided by the present invention;

[0036] Figure 9A schematic structural diagram of another semiconductor device provided by the present invention;

[0037] Figure 10 A schematic structural diagram of another semiconductor device provided by the present invention;

[0038] Figure 11 A schematic structural diagram of another semiconductor device provided by the present invention;

[0039] Figure 12 A schematic structural diagram of another semiconductor device provided by the present invention;

[0040] Figure 13 A schematic structural diagram of another semiconductor device provided by the present invention;

[0041] Figure 14 A schematic structural diagram of another semiconductor device provided by the present invention;

[0042] Figure 15 This is a schematic structural diagram of another semiconductor device provided by the present invention.

[0043] In the figure: 1. substrate; 2. drift layer; 21. first drift layer; 22. second drift layer; 31. first doped region; 32. second doped region; 33. third doped region; 34. fourth doped region; 4. buried layer; 5. insulating dielectric layer; 6. field plate; 7. terminal structure; 8. cathode; 9. anode; A. main junction region; B. terminal region; C. cutting path region. DETAILED DESCRIPTION

[0044] The following content clearly and completely describes the technical solution of the present application in conjunction with the embodiments so that those skilled in the art can fully understand the present application. Obviously, the embodiments described are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made by those of ordinary skill in the art to the following embodiments without creative work falls within the scope of protection of the present application.

[0045] Directional terms used in this application, such as "upper," "lower," "inner," "outer," "bottom," and "upper surface," indicate positions or locations based on the figures in the specification or the positions or locations in which the product of this application is typically placed when in use. These terms are intended solely to facilitate description and understanding of the product structure of this application. Therefore, these directional terms should not be construed as limiting this application. In this application, unless otherwise expressly defined, expressions such as "upper," "above," "above," and "upper surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediate medium; that the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is at a higher level than the second feature. Expressions such as "lower," "below," "below," and "lower surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediate medium; that the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is at a lower level than the second feature. The ordinal numbers used in this application, such as "first" and "second," are used solely for descriptive purposes to distinguish similar objects and are not to be construed as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. Methods not described in detail in the following examples are conventional methods well known to those skilled in the art.

[0046] Example 1

[0047] Reference Figures 5 and 6A semiconductor device terminal structure includes a substrate 1 and a drift layer 2 located on the substrate 1. The center of the drift layer 2 is recessed toward the substrate 1, forming a recessed structure. The recessed structure has a first sidewall and a second sidewall. A first doped region 31 is disposed on the first sidewall and at the corner where the first sidewall connects to the bottom of the recessed structure. A second doped region 32 is disposed on the second sidewall and at the corner where the second sidewall connects to the bottom of the recessed structure. A buried layer 4 is disposed in the drift layer 2 surrounding the recessed structure. The first doped region 31 is in direct contact with the buried layer 4 located in the main junction region of the semiconductor device. The second doped region 32 is in direct contact with the buried layer 4 located in the saw street region of the semiconductor device. When current flows from the substrate 1 to the drift layer 2, the height of the buried layer 4 is higher than the height of the bottom of the recessed structure. The interior of the recessed structure is filled with an insulating dielectric layer 5. Field plates 6 are disposed on the inner sides of both the first and second sidewalls. The field plates 6 and the first doped region 31, and the field plates 6 and the second doped region 32 are both isolated by the insulating dielectric layer 5. A terminal structure 7 is provided at the bottom of the recessed structure. Both the first doped region 31 and the second doped region 32 are in direct contact with the terminal structure 7. A third doped region 33 is provided above the drift layer 2 located in the main junction region of the semiconductor device. Along the direction from the substrate 1 to the drift layer 2, the height of the third doped region 33 is higher than that of the buried layer 4. The third doped region 33 is in direct contact with the first doped region 31. The substrate 1 and the drift layer 2 are both doped with the first doping type; the first doped region 31, the second doped region 32, the third doped region 33, the buried layer 4, and the terminal structure 7 are all doped with the second doping type.

[0048] As an example, the substrate 1 is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate.

[0049] As an example, in some embodiments, the recessed structure is a groove whose bottom surface is parallel to the substrate. In other embodiments, the shape of the recessed structure is not limited.

[0050] As an example, the field plate 6 is made of a metal material (such as aluminum, copper, nickel, etc.) or a semiconductor material (such as polysilicon).

[0051] As an example, the terminal structure 7 is one or a combination of a field limiting ring (FLR), a junction termination extension (JTE), and a field plate (FP). Figure 6 、 Figure 7 As shown, the terminal structure 7 is a field limiting ring. Figure 8 As shown, the terminal structure 7 is a junction terminal extension structure. Figure 9 As shown, the terminal structure 7 is a combination of a field limiting ring and a junction terminal extension structure. Figure 10 As shown, the terminal structure 7 is a combination of a junction terminal extension structure and a floating field plate 6. Figure 11 As shown, the terminal structure 7 directly in contact with the first doped region 31 is a field limiting ring, and the terminal structure 7 directly in contact with the second doped region 32 is a junction terminal extension structure; that is, the terminal structure close to the main junction area of ​​the semiconductor device and the terminal structure close to the cutting street area can be the same or different.

[0052] As an example, the doping type of the substrate 1 and the drift layer 2 is n-type, and the doping type of the first doping region 31, the second doping region 32, the third doping region 33, the buried layer 4, and the terminal structure 7 is p-type. Alternatively, the doping type of the substrate 1 and the drift layer 2 is p-type, and the doping type of the first doping region 31, the second doping region 32, the third doping region 33, the buried layer 4, and the terminal structure 7 is n-type.

[0053] Example 2

[0054] Reference Figures 7 to 12 A semiconductor device is divided into a main junction region A, a terminal region B and a cutting street region C. The terminal region B includes the terminal structure of the semiconductor device in Example 1. A cathode 8 is deposited on the surface of the substrate 1 facing away from the drift layer 2. An anode 9 is deposited on the upper surface of the third doped region 33 (or the drift layer 2) located in the main junction region A. Figure 12 A fourth doping region 34 is provided on the upper layer of the drift layer 2 in the scribe line region C. The doping type of the fourth doping region 34 is the same as that of the first doping region 31. The fourth doping region 34 can further reduce the risk of breakdown in the scribe line region C.

[0055] As an example, the doping depth of the third doping region 33 in the direction from the drift layer 2 to the substrate 1 can be adjusted. For example, the doping depth of the third doping region 33 makes the third doping region 33 directly contact the buried layer 4 (e.g. Figure 13 shown).

[0056] As an example, the doping depth of the fourth doping region 34 in the direction from the drift layer 2 to the substrate 1 can be adjusted. For example, the doping depth of the fourth doping region 34 makes the fourth doping region 34 directly contact the buried layer 4 (e.g. Figure 14 shown).

[0057] As an example, the drift layer 2 is divided into a first drift layer 21 and a second drift layer 22. The first drift layer 21 is located between the substrate 1 and the buried layer 4, and the second drift layer 22 is located above the buried layer 4. The second drift layer 22 and the first drift layer 21 have the same doping type but different doping concentrations. The doping depth of the third doping region 33 is such that the third doping region 33 does not directly contact the buried layer 4 (e.g., Figures 7 to 12As shown), at this time, the second drift layer 22 of the main junction region A serves as a current diffusion layer, which can enhance the conduction capability of the device.

[0058] As an example, the drift layer 2 is divided into a first drift layer 21 and a second drift layer 22. The first drift layer 21 is located between the substrate 1 and the buried layer 4, and the second drift layer 22 is located above the buried layer 4. The second drift layer 22 and the first drift layer 21 have the same doping type but different doping concentrations. The doping depth of the fourth doping region 34 is such that the fourth doping region 34 does not directly contact the buried layer 4 (e.g., Figure 12 As shown), at this time, the second drift layer 22 in the cutting channel region C serves as a current diffusion layer, which can enhance the conduction capability of the device.

[0059] As an example, the insulating dielectric layer 5 extends from the inside of the recess structure to the upper surface of the drift layer 2. The field plate 6 extends from the inner side of the first sidewall of the recess structure to the upper surface of the insulating dielectric layer 5 located in the main junction region A, and periodically contacts the anode 9 in three-dimensional space (e.g., Figure 15 As shown, Figure 15 For the convenience of observation, the interior of the recessed structure is not completely filled with an insulating dielectric layer to achieve the purpose of grounding.

[0060] Example 3

[0061] Reference Figures 1 to 6 A method for preparing a semiconductor device terminal structure comprises the following steps:

[0062] S1. growing a drift layer on a substrate; forming a buried layer in the drift layer;

[0063] S2, forming a concave structure in the middle of the drift layer;

[0064] S3, forming a first doped region on a first sidewall of the recessed structure near the main junction region, and forming a second doped region on a second sidewall near the cutting street region; forming a terminal structure at the bottom of the recessed structure; and forming a third doped region in an upper layer of the drift layer of the main junction region;

[0065] S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewalls and bottom of the recessed structure;

[0066] S5. Depositing a field plate material in the recessed structure and etching to form a field plate;

[0067] S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

[0068] As an example, the method of forming the buried layer in the drift layer in step S1 is ion implantation, molecular beam epitaxy, or chemical vapor deposition.

[0069] As an example, step S1 includes the following steps: growing a first drift layer on a substrate, growing a buried layer on the upper surface of the first drift layer by molecular beam epitaxy, and forming a second drift layer on the upper surface of the buried layer by secondary epitaxy. The first drift layer and the second drift layer are collectively referred to as drift layers. The second drift layer and the first drift layer have the same doping type but different doping concentrations.

[0070] As an example, the etching method in step S2 is dry etching or wet etching.

[0071] As an example, the method for forming the first doping region, the second doping region, and the third doping region in step S3 is ion implantation or secondary epitaxy; the method for forming the terminal structure is ion implantation.

[0072] As an example, the method for depositing the insulating medium in step S4 is chemical vapor deposition, and the method for etching the insulating medium is dry etching or wet etching. Step S6 adopts the same method as step S4.

[0073] As an example, the method for depositing the field plate material in step S5 is chemical vapor deposition. When etching the deposited field plate material, only the field plate structure of the sidewall of the recessed structure (such as Figure 9 As shown), it is also possible to retain the field plate structure on the sidewall and bottom of the recessed structure (as shown Figure 10 shown).

[0074] As an example, in step S5, a field plate is formed on the surface of the insulating dielectric layer on the sidewall of the recessed structure. In step S6, the insulating dielectric layer on the upper surface of the drift layer is etched away.

[0075] Example 4

[0076] A method for preparing a semiconductor device, comprising the method of steps S1 to S6 in embodiment 3, further comprising the following steps:

[0077] S7. Depositing an anode metal on the upper surface of the structure obtained in step S6 by chemical deposition, and performing wet etching to obtain an anode; and depositing a cathode metal on the lower surface of the substrate by chemical deposition to obtain a cathode.

[0078] In a further preferred embodiment, step S3 further includes forming a fourth doping region in the upper layer of the drift layer in the scribe line region. As an example, the fourth doping region is formed by ion implantation or secondary epitaxy.

[0079] In a further preferred embodiment, a field plate located above the drift layer in the main junction region is retained during etching in step S5, and the field plate extends from the surface of the insulating dielectric layer on the side wall of the recessed structure to the upper surface of the insulating dielectric layer in the main junction region (the insulating dielectric layer in the main junction region is located on the upper surface of the drift layer and is the dielectric layer that is not etched during etching in step S4).

[0080] The embodiments described above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various modifications and variations. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A semiconductor device terminal structure, characterized in that: The invention comprises a substrate and a drift layer located on the substrate; the middle portion of the drift layer is recessed toward the substrate to form a recessed structure; the recessed structure has a first sidewall and a second sidewall; a first doped region is provided on the first sidewall and at a corner where the first sidewall is connected to the bottom of the recessed structure; a second doped region is provided on the second sidewall and at a corner where the second sidewall is connected to the bottom of the recessed structure; a buried layer is provided in the drift layer around the recessed structure; the first doped region and the second doped region are both in direct contact with the buried layer; in a direction from the substrate to the drift layer, the height of the buried layer is higher than the height of the bottom of the recessed structure; the recessed structure The interior of the structure is filled with an insulating dielectric layer; field plates are provided on the inner sides of the first sidewall and the second sidewall; the field plates are isolated from the first doped region and the second doped region by the insulating dielectric layer; a terminal structure is provided at the bottom of the recessed structure; the first doped region and the second doped region are both in direct contact with the terminal structure, the terminal structure in direct contact with the first doped region is a field limiting ring, and the terminal structure in direct contact with the second doped region is a junction terminal extension structure; a third doped region is provided on the upper layer of the drift layer in the main junction region of the semiconductor device, and the height of the third doped region is higher than the height of the buried layer along the direction from the substrate to the drift layer; The first doping region is in direct contact with the third doping region; the doping types of the substrate and the drift layer are both the first doping type; the doping types of the first doping region, the second doping region, the third doping region, the buried layer, and the terminal structure are all the second doping type.

2. The semiconductor device terminal structure according to claim 1, wherein: The recessed structure is a groove whose bottom surface is parallel to the substrate.

3. The semiconductor device terminal structure according to claim 1, wherein: The substrate is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate; or / and the material of the field plate is a metal material or a semiconductor material.

4. The method for preparing a semiconductor device terminal structure according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1. growing a drift layer on a substrate; forming a buried layer in the drift layer; S2, forming a concave structure in the middle of the drift layer; S3, forming a first doped region on a first sidewall of the recessed structure near the main junction region, and forming a second doped region on a second sidewall near the cutting street region; forming a terminal structure at the bottom of the recessed structure; and forming a third doped region in an upper layer of the drift layer of the main junction region; S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewalls and bottom of the recessed structure; S5. forming a field plate in the recessed structure; S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

5. The preparation method according to claim 4, characterized in that Step S1 includes the following steps: growing a first drift layer on the substrate, forming the buried layer on the upper surface of the first drift layer, and forming a second drift layer on the upper surface of the buried layer; the second drift layer and the first drift layer have the same doping type.

6. A semiconductor device, characterized in that: A semiconductor device terminal structure comprising the semiconductor device terminal structure according to any one of claims 1 to 3.

7. The semiconductor device according to claim 6, wherein: A fourth doping region is provided on the upper layer of the drift layer located in the cutting street area of ​​the semiconductor device; along the direction from the substrate to the drift layer, the height of the fourth doping region is higher than the height of the buried layer; the doping type of the fourth doping region is the same as the doping type of the first doping region.

8. The semiconductor device according to claim 7, wherein: The drift layer includes a first drift layer and a second drift layer. The first drift layer is located between the substrate and the buried layer. The second drift layer is located above the buried layer. The second drift layer and the first drift layer have the same doping type.

9. The semiconductor device according to claim 6, wherein: An anode is deposited on the upper surface of the drift layer located in the main junction area of ​​the semiconductor device, the insulating dielectric layer extends from the inside of the recessed structure to the upper surface of the drift layer, and the field plate extends from the inner side of the first side wall to the upper surface of the insulating dielectric layer located in the main junction area until it contacts the anode.

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