An SOI-LIGBT device incorporating deep trench and self-biased PMOS

Abstract

The application relates to an SOI-LIGBT device introducing a deep trench and a self-biased PMOS, and belongs to the technical field of semiconductor devices. The device comprises a cathode P+ region, a cathode P-well region, a cathode N+ region, a drift region, a P-buried region, an anode N-buffer region, an anode P+ region, a main gate oxide layer, a polycrystalline silicon main gate, a deep trench oxide layer, a deep trench oxide layer, a polycrystalline silicon auxiliary gate, a silicon dioxide buried oxygen layer and a substrate. The device integrates a self-biased PMOS at the cathode, provides an extraction channel of excess carriers in the off state, improves the working frequency of the device in the application process, reduces the saturation current when the device is forwardly conducted, increases the short-circuit safe working time of the device, and improves the reliability and safety of the device. The PMOS integrated at the cathode does not need to be controlled by an additional circuit, the feasibility of the device in the actual application process is improved, and the design difficulty of a driving circuit is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a SOI-LIGBT device with a deep trench and a self-biased PMOS. Background Art

[0002] The insulated-gate bipolar transistor (IGBT) is a power semiconductor device that plays a key role in modern power electronics. As power electronics technology evolves toward high voltage, high current, and high frequency, traditional power transistors (such as bipolar junction transistors (BJTs)) and power field-effect transistors (MOSFETs) are gradually exposing limitations in some applications. BJTs, for example, suffer from high drive currents and slow switching speeds, while MOSFETs exhibit high on-resistance in high-voltage, high-current applications. This technological advancement led to the emergence of the IGBT, which combines the advantages of the MOSFET's high input impedance and voltage-controlled drive with the BJT's low on-state voltage drop. It emerged in the 1980s and has since rapidly developed.

[0003] In the industrial sector, with the increasing degree of automated production, applications such as motor speed regulation and inverter power supplies require more efficient power control components, and IGBTs are well-suited to meet these needs. In the energy sector, IGBTs play a vital role in power conversion in traditional thermal and hydropower generation, as well as in inverters and other devices in emerging renewable energy power generation systems such as solar and wind power. Furthermore, in the transportation sector, such as in electric vehicle motor drives and charging systems, the high performance of IGBTs is crucial for improving energy efficiency and vehicle performance. In short, the emergence of IGBTs has met the power electronics industry's urgent need for high-performance power devices and has driven technological innovation and development in numerous fields.

[0004] Due to the bipolar conductive characteristics of IGBT, although IGBT has good conduction advantages, it also brings a series of reliability problems such as low switching frequency and high saturation current that are prone to latch-up. Solving these problems can broaden the application scenarios of IGBT, which is of great significance to IGBT. Summary of the Invention

[0005] In view of this, the present invention aims to provide a SOI-LIGBT device that introduces deep trenches and self-biased PMOS to improve reliability. By introducing a deep trench oxide layer and self-biased PMOS into the structure of a traditional IGBT device, a hole carrier extraction channel is provided when the device is turned off. This allows excess hole carriers in the drift region to be quickly extracted during shutdown, enabling rapid device shutdown. This structure improves the IGBT's turn-off speed while also reducing its saturation current, thereby increasing the device's short-circuit safe operating area and latch-up resistance, thereby enhancing device reliability.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A SOI-LIGBT device with a deep trench and self-biased PMOS is disclosed, comprising:

[0008] substrate;

[0009] a buried silicon dioxide layer located on the surface of the substrate;

[0010] a drift region located on the surface of the silicon dioxide buried layer;

[0011] a main gate oxide layer located on the surface of the silicon dioxide buried layer and adjacent to the drift region;

[0012] a polysilicon main gate located in the main gate oxide layer and wrapped by the main gate oxide layer;

[0013] a P-buried region located in the middle region of the drift region;

[0014] a deep trench oxide layer located in the P-buried region and extending upwardly out of the P-buried region;

[0015] a polysilicon auxiliary gate located in the deep trench oxide layer and wrapped by the deep trench oxide layer;

[0016] a cathode P-well region located on the surface of the drift region and distributed on one side of the deep trench oxide layer;

[0017] A cathode P+ region and a cathode N+ region located on the surface of the cathode P-well region and between the deep trench oxide layer and the silicon dioxide buried layer;

[0018] an anode N-buffer region located on the surface of the drift region and distributed on the other side of the deep trench oxide layer;

[0019] an anode P+ region located in the anode N-buffer region and surrounded by the anode N-buffer region;

[0020] an emitter electrode located on the surface of the cathode N+ region, cathode P+ region and polysilicon auxiliary gate; and

[0021] A collector electrode is located on the surface of the anode P+ region.

[0022] The anode P+ region, anode N-buffer region, drift region and cathode P-well region constitute the first anode region PNP transistor of the device. When the device is forward-conducted, the first anode region PNP transistor is used to provide holes.

[0023] In the first anode region PNP transistor, the emitter is the anode P+ region, the base is the anode N-buffer region and the drift region, and the collector is the cathode P-well region.

[0024] The anode P+ region, anode N-buffer region, drift region and low-doped P-buried region constitute the second anode region PNP transistor of the device. When the device is forward-conducting, the second anode region PNP transistor is used to provide holes.

[0025] In the second anode region PNP transistor, the emitter is the anode P+ region, the base is the anode N-buffer region and the drift region, and the collector is the low-doped P-buried region.

[0026] The P-buried region, drift region, cathode P-well region, cathode P+ region, deep trench oxide layer, and polysilicon auxiliary gate constitute the self-biased PMOS cathode of the device. The deep trench oxide layer serves as the gate oxide layer of the self-biased PMOS, the P-buried region serves as the source of the self-biased PMOS, the drift region serves as the substrate of the self-biased PMOS, the cathode P-well region and cathode P+ region serve as the drain of the self-biased PMOS, and the polysilicon auxiliary gate serves as the gate of the self-biased PMOS.

[0027] Furthermore, a self-biased PMOS is used to control the on and off of the device and provide an additional hole channel to reduce energy loss when the device is turned off and reduce the saturation current to improve the short-circuit safe operating area and anti-latch capability of the device.

[0028] The beneficial effects of the present invention are as follows: based on the traditional LIGBT device, the present invention introduces a deep trench oxide layer, so that the carriers no longer simply migrate from left to right or from right to left, thereby increasing the carrier path without increasing the chip area, further saving silicon wafer area, and also allowing the structure to have a higher power density. The breakdown voltage is greatly improved compared with the traditional structure, and the voltage resistance performance is improved by 51.1% compared with the traditional LIGBT device.

[0029] At the same time, the present invention also introduces a self-biased PMOS. When the device is turned off or the forward voltage is large, the potential of the source of the self-biased PMOS will become high, and the gate of the self-biased PMOS is short-circuited with the emitter of the device and grounded. When the difference between the gate potential and the source potential of the self-biased PMOS is less than the threshold voltage of the PMOS, the PMOS turns on to extract holes, providing an additional channel for hole carriers. This not only reduces the energy loss of the device when it is turned off, but also reduces the saturation current, improving the short-circuit safe operating area and anti-latch capability of the device. Among them, the short-circuit safe operating time of the present invention is approximately 3.2 times that of traditional devices.

[0030] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings, in which:

[0032] Figure 1 A schematic structural diagram of a PDP-LIGBT device provided in Example 1 of the present invention;

[0033] Figure 2 for Figure 1 Equivalent circuit diagram of the device shown;

[0034] Figure 3 Optimization diagram of breakdown voltage of Example 1 of the present invention, CONV-LIGBT (traditional SOI-LIGBT) and DOT-LIGBT (SOI-LIGBT with only deep trench oxide layer introduced);

[0035] Figure 4 1 is a comparison diagram of forward blocking curves of Example 1 of the present invention, CONV-LIGBT, and DOT-LIGBT;

[0036] Figure 5 1 is a comparison chart of forward conduction performance of Example 1 of the present invention, CONV-LIGBT, and DOT-LIGBT;

[0037] Figure 6 This is a comparison chart of the short-circuit safety performance of Example 1 of the present invention, CONV-LIGBT, and DOT-LIGBT;

[0038] Figure 7 1 is a comparison diagram of the turn-off curves of Example 1 of the present invention, CONV-LIGBT, and DOT-LIGBT;

[0039] Figure numerals: cathode P+ region 1, cathode N+ region 2, cathode P-well region 3, polysilicon main gate 4, main gate oxide layer 5, drift region 6, silicon dioxide buried oxide layer 7, P-type substrate 8, low-doped P-buried region 9, deep trench oxide layer 10, anode buffer layer 11, anode P+ region 12, polysilicon auxiliary gate 13. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0042] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0043] Example 1:

[0044] like Figure 1As shown, this embodiment improves the traditional SOI-LIGBT device to obtain a SOI-LIGBT device with deep trench and self-biased PMOS. The device includes a cathode P+ region 1, a cathode N+ region 2, a cathode P-well region 3, a polysilicon main gate 4, a main gate oxide layer 5, a drift region 6, a silicon dioxide buried oxide layer 7, a P-type substrate 8, a low-doped P-buried region 9, a deep trench oxide layer 10, an anode buffer layer 11, an anode P+ region 12, and a polysilicon auxiliary gate 13.

[0045] The device's standard MOS region consists of the cathode P+ region 1, cathode N+ region 2, cathode P-well region 3, drift region 6, busbar oxide layer 5, and polysilicon busbar 4. The cathode P+ region 1 is adjacent to the cathode N+ region 2 and is located above the cathode P-well region 3. Below the cathode P-well region 3 is the drift region 6. The busbar oxide layer 5 is adjacent to the cathode P-well region 3, drift region 6, and cathode N+ region 2. The busbar oxide layer 5 completely surrounds the bottom, left, and right sides of the main polysilicon gate 4.

[0046] The anode P+ region 12, anode N-buffer region 11, drift region 6, and cathode P-well region 3 form the device's first anode region PNP transistor. The anode P+ region 12 is completely surrounded by the anode N-buffer region 11, and the lower side of the anode N-buffer region 11 is surrounded by the drift region 6; the lower side of the cathode P-well region 3 is surrounded by the drift region 6. During forward conduction, this first anode region PNP transistor primarily provides holes.

[0047] Among them, the anode P+ region 12 serves as the emitter of the first anode region PNP transistor, the anode N-buffer region 11 and the drift region 6 serve as the base of the first anode region PNP transistor, and the cathode P-well3 region serves as the collector of the first anode region PNP transistor.

[0048] The device's second anode region, a PNP transistor, is comprised of anode P+ region 12, anode N-buffer region 11, drift region 6, and low-doped P-buried region 9. Low-doped P-buried region 9 is located in the center of drift region 6. During forward conduction, this second anode region, a PNP transistor, primarily provides holes.

[0049] The anode P+ region 12 serves as the emitter of the second anode region PNP transistor, the anode N-buffer region 11 and the drift region 6 serve as the base of the second anode region PNP transistor, and the P-buried region serves as the collector of the second anode region PNP transistor.

[0050] The device's cathode self-biased PMOS is comprised of a low-doped P-buried region 9, a drift region 6, a cathode P-well region 3, a cathode P+ region 1, a deep trench oxide layer 10, and a polysilicon auxiliary gate 13. The deep trench oxide layer 10 serves as the PMOS's gate oxide, the low-doped P-buried region 9 serves as the PMOS's source, the drift region 6 serves as the PMOS's substrate, and the cathode P-well region 3 and cathode P+ region 1 serve as the PMOS's drain. The polysilicon auxiliary gate 13 serves as the self-biased PMOS's gate and is short-circuited to the emitter of the IGBT.

[0051] When the device is operating in forward conduction, the device operates similarly to a conventional IGBT, with the gate voltage of the cathode MOS gradually increasing, initiating electron injection into the drift region. As the anode voltage increases, the device's integrated self-biased PMOS gradually turns on, providing an additional hole path for the IGBT during forward conduction or short-circuit operation. This reduces the device's saturation current and improves its reliability. When the device is turned off, it extracts excess hole carriers from the drift region, enhancing its high-frequency characteristics.

[0052] Example 2

[0053] This example uses SENTAURUS simulation software to simulate and analyze the performance of the SOI-LIGBT device described in Example 1, analyze its mechanism, and perform electrical simulations. During the simulations, the device in Example 1 shared the same simulation parameters as the conventional device and the DOT-LIGBT, including a carrier lifetime of 10 μs and an ambient temperature of 300 K.

[0054] like Figure 2 The figure shows an equivalent circuit diagram of the device of Example 1, in which the IGBT is equivalent to a PNP transistor controlled by an NMOS. On this basis, Example 1 integrates a self-biased P-type MOS tube and an additional PNP triode, and does not require additional electrical signal control, so in actual application, no additional control circuit is required.

[0055] like Figure 3 The figure shows a comparison of the breakdown voltage of the device of Example 1 when the total length is 16 μm as the doping concentration of the drift region changes. It can be seen that under the same chip size, the device of Example 1 greatly improves the device's voltage resistance and drift region doping, thereby improving the device's reliability and application range.

[0056] like Figure 4 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3Comparing the breakdown voltage curve below with that of DOT-LIGBT and traditional SOI-LIGBT, it can be seen that the breakdown voltage of this device is increased by 51.1% compared with traditional SOI-LIGBT devices.

[0057] like Figure 5 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 The forward conduction performance of Example 1 is compared with that of DOT-LIGBT and traditional SOI-LIGBT. It can be clearly seen from the forward conduction curve that the saturation current of Example 1 has a great advantage over traditional SOI-LIGBT and DOT-LIGBT, and it can be seen that the current at this time has two paths, one is the traditional IGBT path, and the other is the self-bias PMOS path. The self-bias PMOS integrated in Example 1 plays a good shunting role.

[0058] like Figure 6 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 By comparing the short-circuit safety performance of the device with that of DOT-LIGBT and traditional SOI-LIGBT, it can be seen that the self-biased PMOS of the device in Example 1 has an obvious shunting effect. The short-circuit safety working time of the device is about 3.2 times that of the traditional device, which greatly improves the reliability of the device.

[0059] like Figure 7 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 Comparing the turn-off curves below with those of a DOT-LIGBT and a traditional SOI-LIGBT, the device in Example 1 significantly reduces its turn-off time compared to a DOT-LIGBT due to the carrier extraction effect of the self-biased PMOS, but its turn-off time is longer than that of a traditional SOI-LIGBT. This is because the carrier path of traditional devices is shorter and the amount of excess carriers is smaller. However, traditional IGBT devices have poor reliability and low breakdown voltage, which can cause reliability issues.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. A SOI-LIGBT device with deep trench and self-biased PMOS, characterized in that: The device includes: substrate; a buried silicon dioxide layer located on the surface of the substrate; a drift region located on the surface of the silicon dioxide buried layer; a main gate oxide layer located on the surface of the silicon dioxide buried layer and adjacent to the drift region; a polysilicon main gate located in the main gate oxide layer and wrapped by the main gate oxide layer; a P-buried region located in the middle region of the drift region; a deep trench oxide layer located in the P-buried region and extending upwardly out of the P-buried region; a polysilicon auxiliary gate located in the deep trench oxide layer and wrapped by the deep trench oxide layer; a cathode P-well region located on the surface of the drift region and distributed on one side of the deep trench oxide layer; A cathode P+ region and a cathode N+ region located on the surface of the cathode P-well region and between the deep trench oxide layer and the silicon dioxide buried layer; an anode N-buffer region located on the surface of the drift region and distributed on the other side of the deep trench oxide layer; an anode P+ region located in the anode N-buffer region and surrounded by the anode N-buffer region; an emitter electrode located on the surface of the cathode N+ region, cathode P+ region and polysilicon auxiliary gate; and A collector electrode is located on the surface of the anode P+ region.

2. The SOI-LIGBT device according to claim 1, characterized in that: The anode P+ region, the anode N-buffer region, the drift region and the cathode P-well region constitute the first anode region PNP transistor of the device. When the device is forward-conducting, the first anode region PNP transistor is used to provide holes.

3. The SOI-LIGBT device according to claim 1, wherein: The anode P+ region, anode N-buffer region, drift region and low-doped P-buried region constitute the second anode region PNP transistor of the device. When the device is forward-conducted, the second anode region PNP transistor is used to provide holes.

4. The SOI-LIGBT device according to claim 1, wherein: The P-buried region, drift region, cathode P-well region, cathode P+ region, deep trench oxide layer and polysilicon auxiliary gate constitute the self-biased PMOS at the cathode of the device, wherein the deep trench oxide layer is the gate oxide layer of the self-biased PMOS, the P-buried region is the source of the self-biased PMOS, the drift region is the substrate of the self-biased PMOS, the cathode P-well region and cathode P+ region are the drain of the self-biased PMOS, and the polysilicon auxiliary gate is the gate of the self-biased PMOS; the self-biased PMOS is used to control the opening and closing of the device and provides an additional hole channel to reduce energy loss when the device is turned off.

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