Chip packaging structure and light-emitting device

Abstract

The invention relates to a chip packaging structure and a light-emitting device. The chip packaging structure comprises a packaging body, a chip body and a through hole penetrating through the chip body, the packaging body comprises a packaging assembly, a first electrode layer and a second electrode layer, the first electrode layer comprises a first positive electrode and a first negative electrode, and the second electrode layer comprises a second positive electrode and a second negative electrode. The chip body comprises an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflecting layer which are stacked in sequence, the first conductive layer and the second conductive layer are arranged on the chip body, the through holes comprise a first through hole and a second through hole, a conductive path is formed between the N-type semiconductor and the first conductive layer through the through holes, and light is emitted on the light-emitting layer based on the conductive path. The first current and the second current conducted through different through holes are different in magnitude. By adopting the structure, the through holes with different current conduction capabilities are formed in the chip packaging structure, so that the light-emitting intensities of different light-emitting areas are different, and the light-emitting flexibility of the LED chip is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a light-emitting device. Background Art

[0002] With the continuous development of science and technology, LED (Light Emitting Diode) chip packaging technology is in constant iteration, and LED light-emitting devices based on LED chip packaging structure have also been widely used in various industries, such as automotive headlights, commercial lighting, street lighting, stage lighting, projectors and mobile lighting.

[0003] At present, the traditional LED chip packaging structure is mainly composed of two components, a P-type semiconductor and an N-type semiconductor. Among them, the P-type semiconductor has a high hole concentration and the N-type semiconductor has a high electron concentration. When the P-type semiconductor and the N-type semiconductor are in close contact, a PN junction will be formed between the P-type semiconductor and the N-type semiconductor, and then the carrier migration on the P-type semiconductor and the N-type semiconductor will cause light to be generated near the PN junction. However, due to the uniform design of the LED chip packaging structure, the current in the LED chip structure is uniformly distributed during the transmission process, which makes it difficult to focus the light and the light intensity is low. Therefore, the current LED chip has poor light-emitting flexibility. Summary of the invention

[0004] Based on this, it is necessary to provide a chip packaging structure and a light-emitting device that can improve the light-emitting flexibility of the LED chip by setting through holes with different current conduction capabilities in the chip packaging structure to make the light-emitting intensities of different light-emitting areas different.

[0005] In a first aspect, the present application provides a chip packaging structure, the chip packaging structure comprising a packaging body, a chip body and a through hole penetrating the chip body, wherein the packaging body comprises a packaging component, a first electrode layer located on the backlight side of the chip body and a second electrode layer located on the opposite side of the backlight side of the chip body, the first electrode layer comprises a first positive electrode and a first negative electrode, the second electrode layer comprises a second positive electrode and a second negative electrode, the chip body comprises an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflective layer stacked in sequence, a first conductive layer not adjacent to the N-type semiconductor and a second conductive layer adjacent to the P-type semiconductor are arranged on the chip body, the through hole comprises a first through hole penetrating a first area of ​​the reflective layer and a second through hole penetrating a second area of ​​the reflective layer; wherein,

[0006] The packaging components are electrically connected to the second electrode layer and the power supply, respectively, the first positive electrode is electrically connected to the second positive electrode and the first conductive layer, respectively, the first negative electrode is electrically connected to the second negative electrode and the second conductive layer, and a conductive path is formed between the N-type semiconductor and the first conductive layer through the through hole, and light is emitted from the light-emitting layer based on the conductive path, wherein a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the first current and the second current have different current sizes.

[0007] In one embodiment, the first conductive layer and the reflective layer are located at different depths of the chip body, the second conductive layer is disposed on the reflective layer, and the area ratio of the first region to the second region is between a first preset ratio and a second preset ratio, wherein the first preset ratio is smaller than the second preset ratio, and the area of ​​the first region is smaller than that of the second region at the first preset ratio, and the area of ​​the first region is larger than that of the second region at the second preset ratio.

[0008] In one embodiment, the chip packaging structure includes one of the following:

[0009] The hole density of the first through holes is greater than the hole density of the second through holes; the number of the first through holes is greater than the number of the second through holes; the number of the first through holes is the same as the number of the second through holes, and the aperture of the first through hole is greater than the aperture of the second through hole.

[0010] In one embodiment, the reflective layer further includes a first sub-region, a second sub-region, a third sub-region and a fourth sub-region, the first sub-region, the second sub-region, the third sub-region and the fourth sub-region together constitute a discretely distributed third region, and the second conductive layer is located in the third region.

[0011] In one embodiment, the package body further includes a metal dam, the metal dam and the first electrode layer are located on the same layer, the package assembly includes a package base and a welding base, and the first electrode layer, the package base, the second electrode layer and the welding base are stacked and welded in sequence in a first preset direction.

[0012] In one embodiment, the first positive electrode is located in the first conductive region of the first electrode layer, the first negative electrode is located in the second conductive region of the first electrode layer, the second positive electrode is located in the third conductive region of the second electrode layer, and the second negative electrode is located in the fourth conductive region of the second electrode layer, the first conductive region and the third conductive region satisfy a preset position distribution relationship, and the second conductive region and the fourth conductive region satisfy the preset position distribution relationship, wherein the second conductive region is the central region within the first conductive region, and the third conductive region and the fourth conductive region are different conductive regions.

[0013] In one embodiment, the chip body also includes a metal bonding layer and a chip base, the chip base is electrically connected to the first electrode layer, and the first conductive layer is arranged on the metal bonding layer, wherein the N-type semiconductor, the light-emitting layer, the P-type semiconductor, the reflective layer, the second conductive layer and the metal bonding layer are sequentially stacked in a second preset direction and bonded to the chip base through the metal bonding layer, and the bottom surface area of ​​the first electrode layer is larger than the bottom surface area of ​​the chip base.

[0014] In one of the embodiments, the packaging component further includes a fluorescent layer, the fluorescent layer includes uniformly distributed fluorescent substances, the fluorescent layer is coated on the surface of the N-type semiconductor, and the fluorescent layer and the N-type semiconductor are stacked in sequence in the second preset direction.

[0015] In one embodiment, the chip body further includes an insulating layer, wherein the insulating layer is disposed between the reflective layer and the metal bonding layer, and the insulating layer is used to isolate the current between the first conductive layer and the second conductive layer.

[0016] In a second aspect, the present application further provides a method for preparing a chip packaging structure, which is used to manufacture the chip packaging structure as described in the first aspect above, the method comprising: arranging a packaging component, a first electrode layer located on the backlight side of the chip body, and a second electrode layer located on the opposite side of the backlight side of the chip body in a packaging body, wherein the first electrode layer comprises a first positive electrode and a first negative electrode, and the second electrode layer comprises a second positive electrode and a second negative electrode, the chip body comprises an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflective layer stacked in sequence, and a through hole is arranged in the chip body to penetrate the chip body, wherein a first conductive layer not adjacent to the N-type semiconductor and a second conductive layer adjacent to the P-type semiconductor are arranged on the chip body, and the through hole comprises a through hole that penetrates the reflective layer. A first through hole in a first area of ​​the layer and a second through hole in a second area of ​​the reflective layer; wherein the packaging components are electrically connected to the second electrode layer and the power supply, respectively, the first positive electrode is electrically connected to the second positive electrode and the first conductive layer, respectively, and the first negative electrode is electrically connected to the second negative electrode and the second conductive layer, respectively, and a chip packaging structure is formed by packaging the packaging body and the chip body, so that a conductive path is formed between the N-type semiconductor and the first conductive layer through the through hole, and light is emitted from the light-emitting layer based on the conductive path, wherein a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the first current and the second current have different current sizes.

[0017] In a third aspect, the present application further provides a light-emitting device, comprising the chip packaging structure as described in the first aspect above.

[0018] The above chip packaging structure and light-emitting device are composed of a packaging body, a chip body and a through hole penetrating the chip body, wherein the packaging body is composed of three parts: a packaging component, a first electrode layer located on the backlight side of the chip body, and a second electrode layer located on the opposite side of the backlight side of the chip body, that is, different electrode layers are arranged on different sides of the backlight side of the chip body, and different electrode layers of the packaging body have positive and negative poles, and the chip body is sequentially stacked with an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflective layer, and a first conductive layer not adjacent to the N-type semiconductor and a second conductive layer adjacent to the P-type semiconductor are arranged on the chip body, wherein The packaging component is respectively connected to the second electrode layer and the power supply, and the first positive electrode is respectively electrically connected to the second positive electrode and the first conductive layer, and the first negative electrode is respectively electrically connected to the second negative electrode and the second conductive layer, thereby ensuring that a conductive path is formed between the non-adjacent N-type semiconductor and the first conductive layer through the through holes, wherein the through holes include a first through hole penetrating the first area of ​​the reflective layer and a second through hole penetrating the second area of ​​the reflective layer, and a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the current magnitudes of the first current and the second current are different, that is, the current of the conductive path passes through The through hole that penetrates the chip body transmits between the N-type semiconductor, the light-emitting layer, the P-type semiconductor and the reflective layer of the chip body. Specifically, the first current and the second current of the conductive path flow through the second positive electrode, the first positive electrode, the second conductive layer, the P-type semiconductor, the light-emitting layer and the N-type semiconductor in sequence, and then flow through the first through hole and the second through hole to the first negative electrode and the second negative electrode, thereby allowing the current of the conductive path to pass through different current channels provided by the first through hole and the second through hole to achieve uneven current distribution on the entire chip body. At the same time, different electrode layers are arranged on different sides of the backlight side of the chip body, which can also effectively avoid the current congestion problem of the conductive path. Therefore, by arranging through holes with different current conduction capabilities in the chip packaging structure and transmitting different currents of the conductive path through different through holes, the luminous intensity of different luminous areas of the LED light-emitting device can be differentiated, while the non-LED light-emitting device can only emit light uniformly. Therefore, the uniform design of the LED chip packaging structure overcomes the technical defects that the current in the LED chip structure is uniformly distributed during the transmission process, thereby making it difficult to focus the light and the light intensity is low. Therefore, the light-emitting flexibility of the LED chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a chip packaging structure in one embodiment;

[0021] Figure 2 is a general schematic diagram of a chip packaging structure in one embodiment;

[0022] Figure 3 A schematic diagram of a reflective layer after a through hole penetrates the reflective layer in one embodiment;

[0023] Figure 4 is a schematic diagram of a second conductive layer distributed in a third area in an embodiment;

[0024] Figure 5 A schematic diagram of electrode distribution of a first electrode layer and a second electrode layer in one embodiment;

[0025] Figure 6 FIG. 1 is an exploded schematic diagram of a chip packaging structure in an embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] First of all, it should be understood that LED light-emitting devices using LED chip packaging technology have been widely used in solid-state lighting, display, and mobile lighting due to their advantages of high luminous efficiency, long service life, and high environmental protection. Traditional LED chip packaging technologies mainly include DIP (Dual In-line Package), SMD (Surface Mounted Device), and COB (Chip On Board). It can be understood that no matter how the chip is packaged, it contains a variety of packaging materials, and different packaging materials have differences in electrical conductivity and thermal conductivity, which makes the current flow uneven in the chip body. Taking the chip packaging structure packaged by flip chip packaging technology as an example, this packaging structure usually includes multiple functional areas such as circuit layer, interconnection layer, and insulation layer. The above layers are stacked together through vertical connection technology to achieve highly integrated and complex functions. Among them, the current flow path inside the chip is as follows: the current first enters the chip through the solder bumps on the top layer of the chip. Inside the chip body, the current flows from one layer to another through the PN junction. At this time, the current crowding effect is easily triggered, causing the current to flow concentratedly in certain areas inside the LED chip and less in other areas, ultimately causing the LED chip to have uneven light intensity distribution, large light loss and poor light efficiency. At the same time, by evenly arranging through holes on the LED chip packaging structure to ensure that the current in the LED chip structure is evenly distributed during the transmission process, the differentiated light-emitting needs of the LED chip cannot be met. For example, the current chip cannot increase the light-emitting intensity of the central area and reduce the light-emitting intensity of the edge area. That is, the current LED chip has poor light-emitting flexibility. Therefore, there is an urgent need for a chip packaging structure that can improve the light-emitting flexibility of the LED chip.

[0028] In one embodiment, Figure 1As shown, a chip packaging structure is provided, which includes a chip body 10, a packaging body 20 and a through hole 30 penetrating the chip body 10, wherein the packaging body 20 includes a first electrode layer 22 located on the backlight side of the chip body and a second electrode layer 23 located on the opposite side of the backlight side of the chip body, the first electrode layer 22 includes a first positive electrode and a first negative electrode, the second electrode layer 23 includes a second positive electrode and a second negative electrode, the chip body 10 includes an N-type semiconductor 102, a light-emitting layer 103, a P-type semiconductor 104 and a reflective layer 105 stacked in sequence, a first conductive layer 107 not adjacent to the N-type semiconductor and a second conductive layer 1051 adjacent to the P-type semiconductor are arranged on the chip body, and the through hole 30 penetrates the chip body 10. 0 includes a first through hole 31 penetrating through a first area of ​​the reflective layer 105 and a second through hole 32 penetrating through a second area of ​​the reflective layer 105; wherein the packaging component is electrically connected to the second electrode layer 23 and the power supply respectively, the first positive electrode is electrically connected to the second positive electrode and the first conductive layer 107 respectively, the first negative electrode is electrically connected to the second negative electrode and the second conductive layer 1051 respectively, a conductive path is formed between the N-type semiconductor 102 and the first conductive layer 107 through the through hole 30, and light is emitted in the light-emitting layer 103 based on the conductive path, wherein a first current of the conductive path is conducted through the first through hole 31, and a second current of the conductive path is conducted through the second through hole 32, and the current magnitudes of the first current and the second current are different.

[0029] In one practicable manner, the first through hole 31 and the second through hole 32 penetrating the chip body 10 penetrate the reflective layer 105, the P-type semiconductor 104 and the light-emitting layer 103 from bottom to top, and penetrate half of the N-type semiconductor 102 located at the top layer to ensure that current efficiently flows through the various components of the chip packaging structure, wherein the first conductive layer 107 and the second conductive layer 1051 can both be arranged on the reflective layer 105.

[0030] It should be noted that the main function of the chip packaging structure is, on the one hand, to provide physical protection conditions for the LED chip, thereby extending the service life of the LED chip in the working state, and on the other hand, to improve the chip's integration, maintainability and scalability. It can be understood that the PN junction formed by the P-type semiconductor and the N-type semiconductor is the essential reason why the LED chip can emit light. When the power supply applies a forward voltage to both ends of the PN junction through the conductive path, the current in the conductive path will flow through the second positive electrode, the first positive electrode, the second conductive layer, the P-type semiconductor, the light-emitting layer and the N-type semiconductor in sequence, and then flow through the evenly distributed through holes to the first negative electrode and the second negative electrode, thereby Positive carriers and negative carriers recombine near the PN junction, and the excess energy in the recombination process is emitted into the external space in the form of photons, ultimately achieving luminescence. In addition to being able to avoid environmental interference with the LED chip, the overall chip packaging structure can also provide a specific conductive path design and light propagation path design. However, the current chip packaging structure that relies on traditional LED chip packaging technology is prone to consistent luminous intensity in different luminous areas of the LED chip due to the evenly distributed through-hole design, resulting in large light loss of the LED chip, easy heat generation or poor luminous efficiency. Based on this, the embodiment of the present application proposes the above-mentioned chip packaging structure.

[0031] It should be noted that the package is a module with specific functions formed by packaging the LED chip and its necessary circuits. In the traditional chip packaging structure, the electrodes are usually arranged directly on the light-emitting surface, which makes the light-emitting layer emit light at different emission angles. Part of the light will be blocked due to the emission angle, resulting in light loss. Therefore, in this embodiment, the electrode is divided into a first electrode layer and a second electrode layer, wherein the first electrode layer is arranged on the backlight side of the chip body, and the second electrode layer is arranged on the opposite side of the backlight side of the chip body. On the one hand, it can avoid the current crowding inside the chip, and on the other hand, the light path is optimized by adjusting the position of the electrode layer, so that the scattering and reflection loss of light inside the chip can be reduced. The ultimate goal of improving the light output efficiency of the chip body is achieved. The packaging component is used to support the integration of the LED chip and its necessary components. For example, in one implementable method, the first electrode layer is the upper electrode layer, the second electrode layer is the lower electrode layer, the packaging component is the supporting weldment, the upper electrode layer, the packaging component and the lower electrode layer are stacked in sequence from top to bottom, and the supporting weldment is welded on the circuit board, so that the chip package can be applied to various light-emitting devices, wherein the first positive electrode of the first electrode layer and the second positive electrode of the second electrode layer are correspondingly distributed, and the first positive electrode and the second positive electrode are connected through a metal connecting hole, and the first negative electrode of the first electrode layer and the second negative electrode of the second electrode layer are correspondingly distributed, and the first negative electrode and the second negative electrode are connected through a metal connecting hole.

[0032] It should be noted that the chip body is a carrier of an integrated circuit. It is understandable that a plurality of chip layers are stacked in the chip body due to different preparation processes. With the reduction of chip size and the increase of chip integration requirements, the wire bonding technology in the traditional chip packaging structure is obviously difficult to meet the high-density and high-speed connection requirements. In order to achieve the connection requirements between different chip layers, holes are punched in the chip body and filled with metal to obtain through holes that penetrate the chip body. It is understandable that the N-type semiconductor of the chip body and the first conductive layer are guided through the first through hole and the second through hole, wherein the first current flowing through the first through hole can be greater than the second current flowing through the second through hole, and the first current flowing through the first through hole can also be less than the second current flowing through the second through hole. In addition, the number and deployment positions of the first through hole and the second through hole are not specifically limited in this embodiment. For example, in an operative manner, the through holes are arranged in an array according to a preset spacing on each chip layer of the chip body. It is understandable that the properties and deployment positions of the first through hole and the second through hole are different, and this differentiated setting enables the first through hole and the second through hole to have different current conduction capabilities.

[0033] It can be understood that the structure of the light-emitting layer can be specifically a quantum well, a single heterojunction and a double heterojunction, the first conductive layer can be specifically an N-electrode layer, and the second conductive layer can be specifically a P-electrode layer. By setting any one of the first conductive layer and the second conductive layer on the reflective layer, the photons that could originally escape or be absorbed on the reflective layer are reflected back to the photoelectric conversion area, thereby improving the absorption of the light generated by the light-emitting layer in the photoelectric material, and thus the photoelectric conversion efficiency of the LED chip can be improved. For example, in one feasible method, the P-electrode layer adjacent to the P-type semiconductor is set on the reflective layer, and the N-electrode layer and the reflective layer that are not adjacent to the N-type semiconductor are located at different depths of the chip body, that is, the N-electrode layer and the P-electrode layer are divided in the spatial position of the chip body, which helps to reduce the conflict and congestion of the current inside the chip. At the same time, it also avoids unnecessary lateral flow of the current inside the chip, and ultimately improves the photoelectric conversion efficiency.

[0034] As an example, an N-type semiconductor, a quantum well, a P-type semiconductor, a reflective layer (a P electrode is provided on the reflective layer), an N electrode, an upper electrode layer, a packaging component and a lower electrode layer are stacked in sequence from top to bottom in the vertical direction, wherein the N-type semiconductor, the quantum well, the P-type semiconductor, the reflective layer and the N electrode together constitute a chip body, the upper electrode layer, the packaging component and the lower electrode layer together constitute a packaging body, and the chip body, the packaging body and a through hole that penetrates the chip body together constitute a chip packaging structure, wherein the through hole includes a first through hole that penetrates a first area of ​​the reflective layer and a second through hole that penetrates a second area of ​​the reflective layer, the packaging component is connected to a power supply through a first pin, the packaging component is connected to the second electrode layer through a second pin, the first positive electrode is electrically connected to the second positive electrode and the N electrode layer, respectively, the first negative electrode is electrically connected to the second negative electrode and the second conductive layer, respectively, a conductive path is formed between the N-type semiconductor and the first conductive layer through the through hole, and light is emitted in the quantum well based on the conductive path, a first current of the conductive path is conducted through the first through hole, a second current of the conductive path is conducted through the second through hole, and the current magnitudes of the first current and the second current are different.

[0035] In this embodiment, a first through hole and a second through hole are provided to penetrate the chip body, and a P electrode layer adjacent to the P-type semiconductor and an N electrode layer not adjacent to the N-type semiconductor are provided on the reflective layer, wherein, since the packaging component is respectively connected to the lower electrode layer and the power supply, and the first positive electrode is respectively electrically connected to the second positive electrode and the first conductive layer, and the first negative electrode is respectively electrically connected to the second negative electrode and the second conductive layer, it is ensured that a conductive path is formed between the non-adjacent N-type semiconductor and the N electrode layer through the through holes, wherein the through holes include a first through hole penetrating a first region of the reflective layer and a second through hole penetrating a second region of the reflective layer, and a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the current magnitudes of the first current and the second current are different, that is, the current of the conductive path is transmitted between the N-type semiconductor, the light-emitting layer, the P-type semiconductor and the reflective layer of the chip body through the first through hole and the second through hole penetrating the chip body, and specifically, the first current and the second current of the conductive path flow in sequence. Through the second positive electrode, the first positive electrode, the second conductive layer, the P-type semiconductor, the light-emitting layer and the N-type semiconductor, and then through the first through hole and the second through hole to the first negative electrode and the second negative electrode, the current in the conductive path can be allowed to pass through the different current channels provided by the first through hole and the second through hole, so as to realize the uneven distribution of current on the entire chip body. At the same time, the upper and lower electrode layers are respectively arranged on different sides of the backlight side of the chip body, which can also effectively avoid the current congestion problem of the conductive path. Therefore, by arranging through holes with different current conduction capabilities in the chip packaging structure, and transmitting different currents of the conductive path through different through holes, the luminous intensity of different luminous areas of the LED light-emitting device can be differentiated, while the non-LED light-emitting device can only emit light uniformly. Therefore, the uniform design of the LED chip packaging structure is overcome, which causes the current in the LED chip structure to be uniformly distributed during the transmission process, thereby making it difficult to focus the light and the light intensity is low. Therefore, the light-emitting flexibility of the LED chip is improved.

[0036] In one practicable manner, referring to Figure 2 , Figure 2 The schematic diagram is a general diagram showing a chip packaging structure, wherein the chip packaging structure includes a chip body and a packaging body.

[0037] In one embodiment, Figure 3 As shown, Figure 3A schematic diagram showing a reflective layer after a through hole penetrates the reflective layer, wherein the first conductive layer and the reflective layer are located at different depths of a chip body, the second conductive layer is disposed on the reflective layer, and after the reflective layer is divided into a first region and a second region, the first through hole is used to penetrate the first region, and the second through hole is used to penetrate the second region, wherein an area ratio of the first region to the second region can be set between a first preset ratio and a second preset ratio, wherein the first preset ratio is smaller than the second preset ratio, the area of ​​the first region is smaller than the area of ​​the second region under the first preset ratio, and the area of ​​the first region is larger than the area of ​​the second region under the second preset ratio.

[0038] In one practicable manner, after the second conductive layer adjacent to the P-type semiconductor is disposed on the reflective layer, the first conductive layer not adjacent to the N-type semiconductor can be disposed on the upper layer of the reflective layer to ensure that the first conductive layer and the second conductive layer are located at different depths of the chip body.

[0039] It should be noted that setting through holes in different chip layers of the chip body will affect the transmission of light to a certain extent due to the area. However, the uniform distribution of current in this process can increase the light intensity. Therefore, there is a regional area ratio that has a positive effect on the light conversion efficiency of the chip packaging structure, wherein the first preset ratio is greater than the second preset ratio, the first preset ratio can be 0.7, 0.8 or 0.9, etc., the second preset ratio can specifically be 1.3, 1.5 or 2, etc., the first area is smaller than the second area under the first preset ratio, that is, the first preset ratio is less than 1, and the second area is larger than the second area under the second preset ratio, wherein the first area has The body may be the central area of ​​the emission layer, and the second area may specifically be the edge area of ​​the emission layer, that is, by limiting the area relationship between the first area and the second area, the luminous abilities of different areas are different, so that the light is more concentrated in the central area, thereby further improving the luminous effect of the chip packaging structure. For example, in an implementable manner, assuming that the first preset ratio is 0.8 and the second preset ratio is 1.3, the area ratio of the first area to the second area is between 1:0.8 and 1:1.3; assuming that the first preset ratio is 0.9 and the second preset ratio is 1.5, the area ratio of the first area to the second area is between 1:0.9 and 1:1.5.

[0040] In one embodiment, the chip packaging structure includes one of the following items: the hole density of the first through-hole is greater than the hole density of the second through-hole; the number of the first through-holes is greater than the number of the second through-holes; the number of the first through-holes is the same as the number of the second through-holes, and the hole diameter of the first through-hole is greater than the hole diameter of the second through-hole.

[0041] It should be noted that by further increasing the hole density of the first through holes in the first area and reducing the hole density of the second through holes in the second area, the luminous effects of different areas of the chip packaging structure can be optimized in a targeted manner. For example, in one feasible method, setting the hole density of the first through holes in the central area to be greater than the hole density of the second through holes in the edge area can make the light conversion efficiency higher and the luminous flux larger, thereby improving the floodlight effect of the chip packaging structure. Setting the number of through holes in the central area to be greater than the number of through holes in the edge area can make the light intensity more concentrated in the central area, thereby achieving the purpose of increasing the light intensity and improving the irradiation distance of the chip packaging structure. At the same time, due to the concentration of light intensity in the central area, the heating temperature of the central area of ​​the reflective layer is higher, while the heating temperature of the edge area is lower due to the weaker light intensity. Therefore, temperature transfer will occur on the chip body of the chip packaging structure, that is, the edge area with lower temperature assists the central area with higher temperature to dissipate heat.

[0042] For example, in an practicable manner, the central area of ​​the reflective layer can be set as the first area, and the edge area of ​​the reflective layer can be set as the second area. After the above-mentioned first through hole in the central area and the through hole in the edge area are set in a targeted manner, it can be ensured that the current of the chip packaging structure is transmitted more concentratedly from the central area, and the current transmitted from the edge area is reduced, that is, by sacrificing the current density of the edge area of ​​the chip packaging structure, a higher current density can be provided for the central area of ​​the chip packaging structure, so that the central area of ​​the chip packaging structure has a greater luminous intensity than the edge area, and finally applied to the LED light-emitting device, it can provide the technical advantage of high light intensity in the central area, so that the light-emitting flexibility of the LED chip is further improved. At the same time, the chip packaging structure can also bear part of the heat of the high current density parameter in the central area when the regional current density is low, that is, by reducing the current transmitted from the edge area, the edge area at low temperature can assist the central area at high temperature to dissipate heat, so while further improving the light-emitting flexibility of the LED chip, the heat dissipation performance of the chip packaging structure can also be improved.

[0043] In one embodiment, the reflective layer further includes a first sub-region, a second sub-region, a third sub-region and a fourth sub-region, which together constitute a discretely distributed third region, and the second conductive layer is located in the third region.

[0044] It should be noted that the second conductive layer disposed on the reflective layer can be disposed in different forms. For example, in one practicable manner, assuming that the second conductive layer is a P-electrode layer, the P-electrode layer is continuously distributed on any side of the reflective layer. In order to reduce the shielding of the light by the second conductive layer, thereby increasing the transmittance of the light, the second conductive layer can be discretely distributed on the reflective layer, wherein the first sub-region, the second sub-region, the third sub-region and the fourth sub-region are four sub-regions at different positions on the reflective layer, with reference to Figure 4 , Figure 4 This is a schematic diagram showing the distribution of the second conductive layer in the third area. The first area is the central area 1053, the second area is the edge area 1052, 111 is the first sub-area, 112 is the second sub-area, 113 is the third sub-area, and 114 is the fourth sub-area, that is, the P electrodes are discretely distributed in the four corners of the reflective layer.

[0045] Since the second conductive layer is discretely distributed in different sub-areas of the reflective layer, the position difference of the second conductive layer can reduce the shielding of the light emitted by the light-emitting layer by the second conductive layer, thereby improving the transmittance of the light in the reflective layer. Therefore, by discretely distributing the second conductive layer in the second conductive layer, the light conversion efficiency can be improved, that is, the effect of the LED chip is further improved.

[0046] In one embodiment, the package body also includes a metal dam, the metal dam and the first electrode layer are located on the same layer, the package assembly includes a package base and a welding base, and the first electrode layer, the package base, the second electrode layer and the welding base are stacked and welded in sequence in a first preset direction.

[0047] It should be noted that, in order to facilitate the carrying of different components in the package body, the package assembly can specifically be provided with a package base and a welding base, wherein the package base is used to provide a fixed platform for the components in the package body so that the chip package base will not shift during the packaging process, and the welding base is used to weld the chip packaging structure and the external circuit board. Considering the contact between the package body and the external environment, a metal dam is also provided in the package body, wherein the metal dam is used to improve the stability of the package body. It can be understood that an electrical transmission path for electrical connection of the conductive path is provided inside the package base and the welding base. For example, in an implementable method, assuming that the first electrode layer is the upper electrode layer and the second electrode layer is the lower electrode layer, the first preset direction is the vertical direction perpendicular to the horizontal plane, and the package body is stacked from top to bottom with an upper electrode layer, a package base, a lower electrode layer and a welding base, wherein the metal dam and the upper electrode layer are located on the same layer, and the welding base is welded to the external circuit board.

[0048] Since the package body is composed of the first electrode layer, the second electrode layer, the package base, the welding base and the metal dam, the stability of the chip package structure during the packaging process can be ensured.

[0049] In one embodiment, the first positive electrode is located in the first conductive region of the first electrode layer, the first negative electrode is located in the second conductive region of the first electrode layer, the second positive electrode is located in the third conductive region of the second electrode layer, and the second negative electrode is located in the fourth conductive region of the second electrode layer. The first conductive region and the third conductive region satisfy a preset position distribution relationship, and the second conductive region and the fourth conductive region satisfy a preset position distribution relationship, wherein the second conductive region is the central region within the first conductive region, and the third conductive region and the fourth conductive region are different conductive regions.

[0050] It should be noted that, in order to ensure the stability of the forward voltage of the chip packaging structure, the positions of the first electrode layer and the second electrode layer can be set according to a preset position distribution relationship. For example, in one practicable manner, referring to Figure 5 , Figure 5 The diagram is a schematic diagram showing the electrode distribution of the first electrode layer and the second electrode layer, wherein the first positive electrode is the upper positive electrode 2011, the first negative electrode is the upper negative electrode 2012, the second positive electrode is the upper positive electrode 2043, and the second negative electrode is the lower negative electrode 2041. Assuming that the first electrode layer is the upper electrode layer and the second electrode layer is the lower electrode layer, for the upper electrode layer, since it is connected to the chip body, it is necessary to set the first negative electrode of the upper electrode layer in the second conductive region of the upper electrode layer, and the first positive electrode in the first conductive region of the upper electrode layer, wherein the second conductive region is the central region within the first conductive region, that is, the first positive electrode of the upper electrode layer is set around the first negative electrode of the upper electrode layer. Since the first positive electrode is located around the first negative electrode, it is ensured that the first positive electrode can diffuse more evenly to the surface of the first negative electrode after releasing carriers, thereby further improving the luminous efficiency of the LED chip through uniform current distribution.

[0051] It should be noted that, for the second electrode layer, since it is connected to the packaging component, it is sufficient to ensure that the current flowing through it can be transmitted evenly. For example, in one feasible method, assuming that the second electrode layer is the lower electrode layer, the second positive electrode and the second negative electrode can be symmetrically arranged based on the lower electrode base. It can be understood that the second positive electrode and the second negative electrode are arranged in the third conductive region and the fourth conductive region symmetrically arranged based on the lower electrode base. Considering the packaging difficulty of the package body, the position distribution relationship can be pre-set for the first conductive region and the third conductive region, the second conductive region and the fourth conductive region, respectively. The first setting position of the first positive electrode of the first conductive layer and the second setting position of the second positive electrode of the second conductive layer can be aligned in the axial direction, and the third setting position of the first negative electrode of the first conductive layer and the fourth setting position of the second negative electrode of the second conductive layer can be aligned in the axial direction.

[0052] In one embodiment, the chip body also includes a metal bonding layer and a chip base, the chip base is electrically connected to the first electrode layer, and the first conductive layer is arranged on the metal bonding layer, wherein the N-type semiconductor, the light-emitting layer, the P-type semiconductor, the reflective layer, the second conductive layer and the metal bonding layer are sequentially stacked in a second preset direction and bonded to the chip base through the metal bonding layer, and the bottom surface area of ​​the first electrode layer is larger than the bottom surface area of ​​the chip base.

[0053] It should be noted that, since the current in the conductive path is transmitted between the chip bodies through the through holes, in order to increase the light intensity, a metal bonding layer can be used to converge the current flowing through different through holes, wherein the metal bonding layer can specifically be copper and its alloys or silver and its alloys. It can be understood that after a metal bonding layer is added to the chip packaging structure, the first conductive layer can be disposed on the metal bonding layer, so that the first conductive layer can be electrically connected to the metal conductive layer, wherein the first electrode layer is connected to the chip base. Since welding is required between the first electrode layer and the chip base, the bottom surface area of ​​the first electrode layer can be set larger than the bottom surface area of ​​the chip base, thereby facilitating the connection and welding of the circuit.

[0054] For example, in one implementable method, assuming that the first electrode layer is the upper electrode layer, the first conductive layer is the N electrode layer, and the second conductive layer is the P electrode layer, then in the chip packaging structure of this embodiment, the N electrode layer is arranged on the metal bonding layer, and the P electrode layer is arranged on the reflective layer, then the N-type semiconductor, the light-emitting layer, the P-type semiconductor, the reflective layer including the P electrode layer, and the metal bonding layer including the N electrode layer of the chip body are stacked in sequence from top to bottom in a second preset direction, wherein the second preset direction and the first preset direction may be the same and may both be vertical directions perpendicular to the horizontal plane.

[0055] In one embodiment, the packaging component further includes a fluorescent layer, the fluorescent layer includes uniformly distributed fluorescent substances, the fluorescent layer is coated on the surface of the N-type semiconductor, and the fluorescent layer and the N-type semiconductor are stacked in sequence in a second preset direction.

[0056] It should be noted that after the chip packaging structure is placed in different light-emitting devices, ordinary white light may not meet the user's usage requirements, and a fluorescent layer may be set on the outermost layer of the chip packaging structure, and the fluorescent layer is used to absorb the light emitted by the light-emitting layer, wherein the fluorescent layer includes a uniformly distributed fluorescent substance, and the fluorescent layer is coated on the surface of the N-type semiconductor. The fluorescent layer and the N-type semiconductor are stacked in sequence in a second preset direction. It can be understood that the fluorescent substance uniformly distributed in the fluorescent layer can specifically be fluorescein isothiocyanate, tetraethyl rhodamine, tetramethyl rhodamine isothiocyanate or phycoerythrin, etc.

[0057] In one embodiment, the chip body further includes an insulating layer, which is disposed between the reflective layer and the metal bonding layer, and is used to isolate the current between the first conductive layer and the second conductive layer.

[0058] It should be noted that, in the design process of the chip body, in order to prevent electrical interference between the first conductive layer and the second conductive layer, thereby improving the stability and reliability of the chip packaging structure, it is understandable that the insulating layer is composed of , and For example, in one practicable manner, an insulating layer is disposed between the metal bonding layer and the reflective layer to avoid a short circuit between the P-type semiconductor and the N-type semiconductor.

[0059] In one practicable manner, referring to Figure 6 , Figure 6 The exploded schematic diagram of the chip packaging structure, wherein 101 is a fluorescent layer, 102 is an N-type semiconductor, 103 is a quantum well, 104 is a P-type semiconductor, 105 is a reflective layer, wherein the P-electrode layer is arranged with the reflective layer 105, 106 is an insulating layer, 107 is an N-electrode layer, 108 is a metal bonding layer, 109 is a chip base, 201 is an upper electrode layer, 202 is a metal dam, 203 is a packaging base, 204 is a lower electrode layer, 205 is a welding base, and the fluorescent layer The chip body composed of the N-type semiconductor 101, the quantum well 103, the P-type semiconductor 104, the reflective layer 105, the insulating layer 106, the N-electrode layer 107, the metal bonding layer 108 and the chip base 109 is provided with a through hole, and the through hole penetrates the chip body. The specific penetration form can be: penetrate the quantum well 103, the P-type semiconductor 104, the reflective layer 105, the insulating layer 106, the N-electrode layer 107 and the metal bonding layer 108, and partially penetrate the N-type semiconductor 102, wherein the through hole can be specifically an N-via hole, the chip packaging structure is a chip packaging with uneven light emission, which has a first area (central area) and a second area (edge ​​area), the area ratio of the first area to the second area is between 1:0.8 and 1:2, the N-type semiconductor of the chip packaging structure is electrically connected through the N-electrode layer and the metal bonding layer, the N-type semiconductor is electrically connected to the N-electrode layer, the N-electrode layer is electrically connected to the metal bonding layer, the P-type semiconductor is electrically connected to the reflective layer, the package body is provided with an upper electrode layer (first electrode layer) and a lower electrode layer (second electrode layer), the first positive electrode of the upper electrode layer is electrically connected to the second positive electrode of the lower electrode layer, the first negative electrode of the upper electrode layer is electrically connected to the second negative electrode of the lower electrode layer, the first positive electrode is also electrically connected to the reflective layer of the chip packaging structure, the first negative electrode is also electrically connected to the metal bonding layer of the chip packaging structure, the first positive electrode, the first negative electrode, the second positive electrode and the second negative electrode satisfy a preset position distribution relationship, and the bottom surface area of ​​the upper electrode layer is larger than the bottom surface area of ​​the chip base.

[0060] Since the packaging components are respectively connected to the second electrode layer and the power source, the first positive electrode is respectively electrically connected to the second positive electrode and the first conductive layer, and the first negative electrode is respectively electrically connected to the second negative electrode and the first conductive layer, it can be ensured that a conductive path is formed between the N-type semiconductor and the first conductive layer through the first through hole and the second through hole, wherein the through hole includes a first through hole penetrating the first area of ​​the reflective layer and a second through hole penetrating the second area of ​​the reflective layer, and a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the current magnitudes of the first current and the second current are different, that is, the current of the conductive path is transmitted between the N-type semiconductor, the light-emitting layer, the P-type semiconductor and the reflective layer of the chip body through the through hole penetrating the chip body. Specifically, the first current and the second current of the conductive path flow through the second positive electrode, the first positive electrode, the second conductive layer, the P-type semiconductor, the light-emitting layer and the N-type semiconductor in sequence, and then through The first through hole and the second through hole flow through to the first negative electrode and the second negative electrode, thereby allowing the current in the conductive path to pass through different current channels provided by the first through hole and the second through hole, thereby realizing uneven current distribution on the entire chip body. At the same time, different electrode layers are arranged on different sides of the backlight side of the chip body, which can also effectively avoid the current congestion problem of the conductive path. Therefore, by arranging through holes with different current conduction capabilities in the chip packaging structure and transmitting different currents of the conductive path through different through holes, the luminous intensity of different luminous areas of the LED light-emitting device can be differentiated, while the non-LED light-emitting device can only emit light uniformly. Therefore, the uniform design of the LED chip packaging structure overcomes the technical defects that the current in the LED chip structure is uniformly distributed during the transmission process, thereby making it difficult to focus the light and the light intensity is low. Therefore, the light-emitting flexibility of the LED chip is improved.

[0061] This embodiment provides a light-emitting device, which includes an LED package provided in the embodiment of the present invention. The light-emitting device provided in this embodiment includes but is not limited to a lighting device, a light signal indicating device, a fill light device or a backlight device.

[0062] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0063] Those skilled in the art will understand that Figure 6 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the light-emitting device to which the scheme of the present application is applied. The specific light-emitting device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0064] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0065] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure includes a packaging body, a chip body and a through hole penetrating the chip body, wherein the packaging body includes a packaging component, a first electrode layer located on the backlight side of the chip body and a second electrode layer located on the opposite side of the backlight side of the chip body, the first electrode layer includes a first positive electrode and a first negative electrode, the second electrode layer includes a second positive electrode and a second negative electrode, the chip body includes an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflective layer stacked in sequence, a first conductive layer not adjacent to the N-type semiconductor and a second conductive layer adjacent to the P-type semiconductor are arranged on the chip body, and the through hole includes a first through hole penetrating a first area of ​​the reflective layer and a second through hole penetrating a second area of ​​the reflective layer; wherein, The packaging components are electrically connected to the second electrode layer and the power supply, respectively, the first positive electrode is electrically connected to the second positive electrode and the first conductive layer, respectively, the first negative electrode is electrically connected to the second negative electrode and the second conductive layer, and a conductive path is formed between the N-type semiconductor and the first conductive layer through the through hole, and light is emitted from the light-emitting layer based on the conductive path, wherein a first current of the conductive path is conducted through the first through hole, and a second current of the conductive path is conducted through the second through hole, and the first current and the second current have different current sizes.

2. The chip packaging structure according to claim 1, characterized in that: The first conductive layer and the reflective layer are located at different depths of the chip body, the second conductive layer is arranged on the reflective layer, and the area ratio of the first region to the second region is between a first preset ratio and a second preset ratio, wherein the first preset ratio is smaller than the second preset ratio, and the area of ​​the first region is smaller than that of the second region under the first preset ratio, and the area of ​​the first region is larger than that of the second region under the second preset ratio.

3. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure includes one of the following: The hole density of the first through-holes is greater than the hole density of the second through-holes; The number of the first through holes is greater than the number of the second through holes; The number of the first through holes is the same as the number of the second through holes, and the diameter of the first through holes is larger than the diameter of the second through holes.

4. The chip packaging structure according to claim 1, characterized in that: The reflective layer further includes a first sub-region, a second sub-region, a third sub-region and a fourth sub-region, the first sub-region, the second sub-region, the third sub-region and the fourth sub-region together constitute a discretely distributed third region, and the second conductive layer is located in the third region.

5. The chip packaging structure according to claim 1, characterized in that: The package body also includes a metal dam, the metal dam and the first electrode layer are located on the same layer, the package assembly includes a package base and a welding base, the first electrode layer, the package base, the second electrode layer and the welding base are stacked and welded in sequence in a first preset direction.

6. The chip packaging structure according to claim 1, characterized in that: The first positive electrode is located in the first conductive region of the first electrode layer, the first negative electrode is located in the second conductive region of the first electrode layer, the second positive electrode is located in the third conductive region of the second electrode layer, the second negative electrode is located in the fourth conductive region of the second electrode layer, the first conductive region and the third conductive region satisfy a preset position distribution relationship, the second conductive region and the fourth conductive region satisfy the preset position distribution relationship, wherein the second conductive region is the central region within the first conductive region, and the third conductive region and the fourth conductive region are different conductive regions.

7. The chip packaging structure according to claim 6, characterized in that: The chip body also includes a metal bonding layer and a chip base, the chip base is electrically connected to the first electrode layer, and the first conductive layer is arranged on the metal bonding layer, wherein the N-type semiconductor, the light-emitting layer, the P-type semiconductor, the reflective layer, the second conductive layer and the metal bonding layer are sequentially stacked in a second preset direction and bonded to the chip base through the metal bonding layer, and the bottom surface area of ​​the first electrode layer is larger than the bottom surface area of ​​the chip base.

8. The chip packaging structure according to claim 7, characterized in that: The packaging component further includes a fluorescent layer, which includes uniformly distributed fluorescent substances. The fluorescent layer is coated on the surface of the N-type semiconductor. The fluorescent layer and the N-type semiconductor are sequentially stacked in the second preset direction.

9. The chip packaging structure according to claim 8, characterized in that: The chip body further includes an insulating layer, which is disposed between the reflective layer and the metal bonding layer, and is used to isolate the current between the first conductive layer and the second conductive layer.

10. A light emitting device, characterized in that: The light emitting device comprises the chip packaging structure according to any one of claims 1 to 9.

Images