Systems, methods, and apparatus for responsive power control in processor

Abstract

Systems, methods, and apparatus for responsive power control in a processor are described. In one example, an apparatus includes a first intellectual property (IP) circuit to perform an operation on data and a power controller. The power controller is to: receive a boost value based at least in part on one or more characteristics of the power source; determining a boosted maximum power level based at least in part on the boosted value and a conventional maximum power level; and providing a boosted maximum power budget for the first IP circuit based at least in part on the boosted maximum power level. In response to the input voltage violation signal, the first IP circuit is to responsively reduce power consumption to be equal to or lower than a conventional maximum power budget for the first IP circuit that is lower than the boosted maximum power budget. Other embodiments are described and claimed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 519,628, filed on August 15, 2023, entitled “SYSTEM, METHOD AND APPARATUS FOR REACTIVE POWER CONTROL IN A PROCESSOR.” Background Art

[0002] In computing systems, the main power source has a limited peak power delivery capability. Whether the main power source is an AC power source or a battery, exceeding the power output capability may cause the output voltage to drop, which may cause system failure. And battery-powered systems have an output power capability that varies with the charge level of the battery, because as the battery charge level decreases, the peak power delivery capability also decreases. The peak output power capability also varies with the battery configuration.

[0003] In existing platforms, these peak power delivery constraints can directly impact performance capabilities. Since peak power delivery capability violations can result in system failures in tens of microseconds (μs) or faster, these constraints are actively managed, meaning that the system is designed and operated to prevent power consumption from exceeding the power delivery limit. Historically, peak power delivery constraints have been managed by limiting the maximum frequency of high-power circuitry within the processor to ensure that peak power consumption remains below the platform peak power delivery capability. The nature of a constraint that is actively and predictively managed is that it is conservative, meaning that performance is constrained until the physical limits of the platform are reached. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of a computing system according to an embodiment.

[0005] Figure 2 is a block diagram of a system on chip according to an embodiment.

[0006] Figure 3 is a flow chart of a method according to an embodiment.

[0007] Figure 4 is a graphical illustration of the relationship between allowable response time and available boost credits.

[0008] Figure 5 An example computing system is illustrated.

[0009] Figure 6 A block diagram of an example processor is illustrated in accordance with an embodiment. DETAILED DESCRIPTION

[0010] In various embodiments, the processor is configured to provide higher performance capabilities for a given peak power delivery capability. This arrangement is achieved by a protection mechanism that allows the peak power delivery capability to be managed responsively rather than actively. In practice, this means that performance is constrained only when the instantaneous power consumption reaches the peak power delivery limit, rather than actively reducing the operating frequency limit. In an embodiment, this reactive power control occurs at least in part based on detecting power consumption at a threshold, combined with the ability of various high power consumption circuits to reduce power consumption back below the threshold almost instantly (e.g., within a few microseconds).

[0011] With embodiments, a programmable boost increase may be added to the existing (legacy) maximum power delivery capability of a given system. Thus, at least some circuitry may be allowed to operate at higher power consumption levels. This is so because such circuitry may be provided with control circuitry for ensuring that any boosted power consumption is reduced to below the legacy power consumption almost instantaneously (e.g., within about 1-10 μs) when signaled that the power consumption is to be reduced.

[0012] With this arrangement, certain high power consumption circuit systems can be operated at operating frequencies above the limit defined by the peak power delivery capability of the power supply network, thereby providing higher performance without violating the power delivery requirements. The result is that the maximum possible power consumed by the load is increased, resulting in better performance.

[0013] Embodiments may achieve this reduction by immediately forcing at least some (or all) highly loaded IP circuits to power throttle, which significantly reduces IP power consumption. Although different techniques are possible, in some cases, a circuit may throttle power consumption by immediately reducing the clock frequency of the IP circuit. Another approach may be to invoke a microarchitectural mechanism to immediately constrain the throughput of the IP circuit, such as by reducing the number of instructions that a core can execute or retire in any given clock cycle. Other approaches may include duty cycling, such as by cutting off clock edges or performing another technique to reduce power consumption.

[0014] Reference now Figure 1 , which is a block diagram of a platform according to an embodiment. Figure 1 As shown in , computing platform 100 can be any type of computing device, ranging from relatively small devices (such as smart phones) to larger devices (including laptop computers, desktop computers, server computers, etc.). Figure 1At a high level as shown, the platform 100 includes a processor implemented as a SoC 110, although other processor implementations are possible. As shown, the processor SoC 110 is coupled to a memory 160, which is a system memory (e.g., a dynamic random access memory (DRAM)) and a non-volatile memory 170, which can be implemented as flash memory, a disk drive, etc. in different embodiments. It should be understood that the term "system on chip" or "SoC" should be broadly interpreted to mean an integrated circuit having one or more semiconductor dies that are implemented in a package, whether a single die, multiple dies on a common substrate, or multiple dies with at least some of the dies in a stacked relationship. Therefore, as used herein, such a SoC is conceived to include separate chiplets, dielets, and / or slices, and the terms "system in package" and "SiP" are interchangeable with system on chip and SoC.

[0015] Regarding SoC 110, included are a plurality of cores. In the particular embodiment shown, there are two different core types, namely first cores 1120-112 n (so-called efficiency core (E-core)) and the second core 114 0-n (So-called performance cores (P-cores)). It will be appreciated that the various cores may include many different types of execution units, intellectual property (IP) circuits (one of which is shown as IP circuit 1150 within P-core 1140), and other circuitry. Although only a single IP circuit is shown, it will be appreciated that SoC 110 may include many different IP circuits present in one or more of cores 112, 113, GPU 120, and / or as independent processing circuits. As further shown, SoC 110 includes a graphics processing unit (GPU) 120 that includes a plurality of execution units (EUs) 122. 0-n In one or more embodiments, the first core 112 and the second core 114 and / or the GPU 120 may be implemented on separate dies.

[0016] These various computing elements are coupled to additional components of the SoC 110, including a shared cache memory 125, which in an embodiment may be a last level cache (LLC) having a distributed architecture. In addition, a memory controller 130 is present along with a power controller 140, which may be implemented as a hardware control circuit, which may be a dedicated microcontroller for executing instructions (e.g., firmware instructions) stored, for example, on a non-transitory storage medium. In other cases, the power controller 140 may have different portions distributed across one or more of the available cores.

[0017] Still refer to Figure 1 , power controller 140 includes various component circuit systems. Power controller 140 includes power budget circuit 142. In an embodiment, power budget circuit 142 is configured to receive the boost value and determine the boosted power budget for various high-power IP circuits within SoC 110. Such IP circuits may include cores, graphics processing units, vector processing engines, memory subsystems, cache memories, and fabrics (and / or any portion of any of these items), as well as other high-power IP circuits. Power budget circuit 142 can send these boosted power budgets to the IP circuits so that they can operate at this higher power consumption level.

[0018] The power controller 140 also includes a dynamic voltage and frequency scaling (DVFS) circuit 144. The DVFS circuit 144 may be configured to dynamically adjust the voltage and / or frequency of the cores 112, 114, and / or GPU 120 depending on environmental conditions, including temperature, power budget, etc. Note that the DVFS circuit 144 may perform such power management operations at a slower frequency (e.g., within a millisecond responsiveness) than the instantaneous (within about 1-10 μs) power throttling that a single IP circuit independently and autonomously performs in response to receipt of an input voltage violation signal.

[0019] like Figure 1As further shown in FIG. 1 , SoC 110 is powered by an operating voltage received from voltage regulator 150. Voltage regulator 150, in turn, receives power from a power source (e.g., AC wall power or battery power). Voltage regulator 150 (which is an external voltage regulator, e.g., a motherboard for platform 100) is controlled by voltage regulator controller 155. As seen, voltage regulator 150 receives a system voltage (Vsys) from a power source and outputs a regulated output voltage VDD under the control of voltage regulator controller 155. Although shown as separate components, in some implementations, voltage regulator 150 may include voltage regulator controller 155, such as which may be implemented as a power management integrated circuit (PMIC).

[0020] The voltage regulator controller 155 monitors the system voltage, for example, via an included voltage comparator that compares the system voltage to a reference voltage (e.g., a so-called critical threshold (Vsys Critical)). When the system voltage drops below a predetermined reference voltage (e.g., due to a loss of battery charge, AC power problems, etc.), the voltage regulator controller 155 issues an input voltage violation signal. Figure 1 As shown in FIG. 1 , the input voltage violation signal is referred to herein as PROCHOT#, which is sent directly to various entities within SoC 110. Receiving this signal notifies the entity of a drop in system voltage, which in turn may cause a voltage sag, which may cause system failure without proper and instantaneous management. Of course, other signals may be used to indicate an input voltage violation.

[0021] As shown, the input voltage violation signal is sent directly to the power controller 140. The voltage regulator controller 155 is also configured to direct the input voltage violation signal directly to certain high-power IP circuits. As shown in the example of the specification, these IP circuits may be the core 114 (and / or individual IP circuits therein). The signal may also be directly routed to other high-power circuits that may exist within the SoC 110, such as coprocessors, accelerators, etc. (for ease of illustration, the signal is not shown in FIG. 1 ). Figure 1 ed in this high-level view).

[0022] Therefore, a hardwired approach is used to provide a hardwired path to directly and instantaneously notify specific IP circuits of input voltage violations. In response to the receipt, these IP circuits are configured to independently and autonomously take appropriate power throttling actions to instantaneously bring their power consumption levels to conventional maximum power levels or lower to avoid system failures, as further described herein.

[0023] In an embodiment, the power controller 140 ensures that the conventional maximum power capability plus the additional boost value is not exceeded at any time. The power controller 140 further ensures that if the boost amount is applied, then when the reaction mechanism (PROCHOT#) is invoked, the peak power drops to a value less than (or equal to) the conventional maximum power capability within a few microseconds. This is the case because violating this requirement may cause system failure.

[0024] To this end, the power controller 140 can therefore identify only those IP circuits that can meet these guarantees when allocating the boosted power budget. In addition, since there is a delay in detecting and reacting to an undervoltage condition during system operation, this detection and reaction delay is taken into account when determining the allowable boost value.

[0025] As shown, NVM 170 may store an operating system (OS) 172, additional system software 174 (which may include a basic input / output system (BIOS) and other firmware), and various applications, drivers, and other software (generally identified at 176). In one or more embodiments, system software 174 may be configured to calculate a boost value based at least in part on certain power characteristics. The determined boost value may be stored in configuration storage 162 so that the boost value may be accessed for use in determining a boosted maximum power level for SoC 110. In an embodiment, the boosted maximum power level may be equal to the sum of the boost value and the traditional maximum power level.

[0026] It should be understood that although Figure 1 The embodiments of the present invention are shown at this high level, but many variations and alternatives are possible, and other implementations of the SoC 110 may also include embodiments. For example, depending on the market segment, the SoC may include only a single type of core, rather than a mixed product with heterogeneous core types. In addition, there may be more or different accelerator types. For example, in addition to or in place of a GPU, the SoC may include a direct streaming accelerator (DSA), a field programmable gate array (FPGA), or other accelerator.

[0027] Reference now Figure 2 , which is a block diagram of a SoC according to another embodiment. More specifically, Figure 2 As shown, SoC 200 is a multi-core processor including a first plurality of cores 210 0-n and the second multiple core 215 0-m. In one or more embodiments, the first cores 210 may be implemented as performance cores, in that they may include a greater amount of circuitry (e.g., more IP circuits and / or wider and deeper pipelines) to perform higher-level computations in a more performant manner. In contrast, the second cores 215 may be configured as smaller cores that consume less power and may perform computations in a more efficient manner (e.g., in terms of power) than the first core 210. In some embodiments, the first core 210 may be referred to as a P-core (for performance core), while the second core 215 may be referred to as an E-core (for efficiency core). Note that there may be different numbers of first cores and second cores in different implementations.

[0028] like Figure 2 As further shown, cache memory 230 may be implemented as a shared cache arranged in a distributed manner. In one or more embodiments, cache memory 230 may be an LLC having a distributed implementation in which one or more blocks are associated with each of the cores.

[0029] As further shown, GPU 220 may include a media processor 222 and a plurality of EUs 224. Graphics processor 220 may be configured to efficiently perform graphics or other operations that may be decomposed to be executed on parallel processing units (such as EUs 224).

[0030] Still refer to Figure 2 There are various interface circuit systems 240 to provide interfaces to other components of the system. Although the embodiments are not limited in this regard, such interface circuit systems may include a Peripheral Component Interconnect Express (PCIe) interface, one or more Thunderbolt TM interface, Gaussian and Neural Accelerator (GNA) coprocessor, etc. As further shown, the processor 200 includes a display controller 250 and an image processing unit (IPU) 255.

[0031] As further shown, SoC 200 also includes memory 260, which can provide memory controller functionality for interfacing to system memory such as DRAM. Figure 2 The embodiment of FIG. 1 is shown at this high level, but many variations and alternatives are possible. Note that in this implementation, components such as Figure 1Depending on the implementation, such components may be separate circuits present within SoC 200, or the functionality may be performed by one or more of the first core and / or the second core or other processing units.

[0032] Using the embodiments herein, SoC 200 can be configured to operate at the increased maximum power level described herein. Then, in response to the input voltage violation signal, the specific IP circuit autonomously performs power throttling to momentarily reduce power consumption to within conventional levels, thereby avoiding system failure.

[0033] Reference now Figure 3 , which is a flow chart of a method according to an embodiment. More specifically, method 300 is performed within a platform including an SoC or other processor that can directly receive an input voltage violation indication and responsively reduce power consumption in response to the indication. Method 300 details operations involved in configuring a processor to enable operation at a power consumption level greater than a conventional maximum power level and responsively responding to an input voltage violation. In this way, method 300 can be performed using hardware circuitry within a processor alone (including a power controller and IP internal circuitry) and / or in combination with firmware and / or software using hardware circuitry within a processor.

[0034] like Figure 3 As shown in , method 300 begins by calculating a boost value based at least in part on power supply characteristics (block 310). System software (such as firmware, BIOS, etc.) can calculate the boost value based on these characteristics. In an embodiment, the boost value is calculated by considering factors that affect the input voltage received by the external voltage regulator, including but not limited to one or more of the following: impedance between the power supply and the voltage regulator input, total capacitance on the power supply output voltage, charge level of the battery, etc. The boost value can be calculated statically or adjusted at run time, for example, as a function of battery charge level. For legacy functions, the boost value can be programmed to a value of zero.

[0035] Next, at block 320, the boost value may be stored in a configuration storage device. As an example, the boost value may be stored in a system memory, or the boost value may be stored in a power controller (e.g., in a configuration register). Using the boost value, the power controller may determine a power budget for a given IP circuit. Note that the operations at blocks 310 and 320 may be used to configure a processor to be used in a given platform based on the characteristics of the power source. Of course, in many implementations, these operations may also occur dynamically as the power source changes, particularly if the power source is a battery, as a function of the battery charge level.

[0036] Thus, the power controller receives the boost value based at least in part on one or more characteristics of the voltage regulator. Based at least in part on the boost value and a conventional maximum power level for the processor, the power controller determines a boosted maximum power level for the processor, and further determines a boosted maximum power budget for one or more IP circuits based at least in part on the boosted maximum power level.

[0037] Still refer to Figure 3 , next at block 330, enabling the processor to operate at a maximum power level based on the boosted value and the traditional maximum power level. In an embodiment, the power controller may be configured to determine the boosted maximum power level as the sum of the boosted value and the traditional maximum power level. Still further, at block 330, the power controller may be configured to determine boosted power budgets for various IP circuits that are to execute high power consumption instructions. In turn, the power controller sends these boosted power budgets to the IP circuits. It should be understood that in some implementations, these IP circuits may also be informed of the traditional power budget, to which they may need to fall back when an input voltage violation is triggered.

[0038] Note that these IP circuits are configured to control their own power consumption to remain within the boosted power budget (or, when an input voltage violation is identified, to remain within the lower conventional power budget.) At this point, the processor can enter normal operation, where these high power IP circuits and other IP circuits within the core and other components execute instructions.

[0039] Still refer to Figure 3 , control passes to diamond block 340, where it is determined whether an indication of an input voltage violation is received. The indication may be received as a setting of a PROCHOT# signal, which directly notifies a particular IP circuit and a power controller of the input voltage violation. In response to the indication, control passes to block 350, where a responsive power reduction is triggered. It should be understood that the power throttling may be performed independently and autonomously within the IP circuits that directly receive the PROCHOT# signal. The responsive power throttling enables these IP circuits to reduce their power consumption to within the traditional power budget. It should be understood that the power consumption throttling may occur almost instantaneously, such as within approximately 1-10 microseconds (which may be a threshold duration), to ensure that system failures do not occur.

[0040] Such operation at the throttled power level may continue until the PROCHOT# signal is no longer asserted (as determined by control returning to diamond 340). Figure 3 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0041] use Figure 3In the arrangement, at least one IP circuit can directly receive an indication that the input voltage to the power supply has dropped below a threshold level (the indication may be sent by a voltage regulator controller implemented as a voltage regulator and coupled to the power supply). In response to the indication, the at least one IP circuit can autonomously reduce its power consumption to a level at or below a conventional power budget or to avoid a catastrophic event.

[0042] Thus, embodiments enable loads to allow operating points to reach conventional plus additional boost instantaneous power consumption, thereby providing higher performance capabilities without increasing the size or cost of the power supply and / or battery.

[0043] Reference now Figure 4 , shown is a graphical illustration of the relationship between the allowable response time and the available boost amount. Diagram 400 shows a conventional maximum power level 410 and a boosted maximum power level 420 according to an embodiment. The conventional level 410 is static and is conservatively set to ensure that the peak power constraint is not violated even if all high power consumption circuits are executing power viruses. The boosted level 420 allows for higher power consumption. Then, if (e.g., at time 1) an input voltage or other event occurs, an almost instantaneous reduction in power consumption occurs to ensure operation avoids system failure. In an embodiment, the boost amount is a function of how quickly the excess can be detected, communicated, and acted upon (this may include consideration of the responsiveness of the power delivery network and IP circuits, which may be offset depending on the operating frequency).

[0044] Notice, Figure 4 The gap between levels 410 and 420 shown by the arrows illustrates the margin or boost enabled by an embodiment. In an example, the response time may include the time it takes for the voltage regulator controller to trigger a reaction (e.g., 3-4 μs), and the SoC circuitry may require additional time (e.g., 3-4 μs) to drive power down to the traditional level 410.

[0045] Figure 5 An example computing system is shown. Multiprocessor system 500 is a system provided with an interface and includes multiple processors or cores, including a first processor 570 and a second processor 580 coupled via an interface 550 such as a point-to-point (PP) interconnect, a fabric, and / or a bus. In some examples, the first processor 570 and the second processor 580 are isomorphic. In some examples, the first processor 570 and the second processor 580 are heterogeneous. Although example system 500 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a SoC.

[0046] Processors 570 and 580 are shown as including integrated memory controller (IMC) circuitry 572 and 582, respectively. Processor 570 also includes interface circuits 576 and 578; similarly, second processor 580 includes interface circuits 586 and 588. Processors 570, 580 can exchange information via interface 550 using interface circuits 578, 588. IMCs 572 and 582 couple processors 570, 580 to respective memories, namely memory 532 and memory 534, which can be portions of main memory locally attached to the respective processors.

[0047] Processors 570, 580 can each use interface circuits 576, 594, 586, 598 to exchange information with a network interface (NW I / F) 590 via separate interfaces 552, 554. Network interface 590 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples, a chipset) can optionally exchange information with a coprocessor 538 via interface circuit 592. In some examples, coprocessor 538 is a special-purpose processor such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0048] A shared cache (not shown) may be included in either processor 570, 580, or external to both processors but connected to these processors via an interface (such as, the PP interconnect) so that if the processor is placed in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0049] The network interface 590 can be coupled to the first interface 516 via the interface circuit 596. In some examples, the first interface 516 can be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 516 is coupled to a power control unit (PCU) 517, which may include circuitry, software, and / or firmware for performing power management operations related to the processors 570, 580, and / or the coprocessor 538. The PCU 517 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 517 also provides control information to control the generated operating voltage. In various examples, the PCU 517 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0050] PCU 517 is illustrated as existing as logic separate from processor 570 and / or processor 580. In other cases, PCU 517 may be executed on a given one or more cores (not shown) of the cores of processor 570 or 580. In some cases, PCU 517 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In other examples, the power management operations to be performed by PCU 517 may be implemented outside the processor, such as by means of a separate power management integrated circuit (PMIC) or another component external to the processor. In other examples, the power management operations to be performed by PCU 517 may be implemented within BIOS or other system software. PCU 517 may be configured to determine the maximum power level of the boost based at least in part on a boost value, which in turn is based on characteristics of the power configuration of system 500, as described herein. The PCU 517 may determine an increased power budget for each IP circuit based at least in part on the increased maximum power level, as described herein.

[0051] Various I / O devices 514 may be coupled to the first interface 516 along with a bus bridge 518, which couples the first interface 516 to the second interface 520. In some examples, one or more additional processors 515 (such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 516. In some examples, the second interface 520 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 520, including, for example, a keyboard and / or mouse 522, a communication device 527, and a storage circuit system 528. The storage circuit system 528 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device that may include instructions / codes and data 530. Further, an audio I / O 524 may be coupled to the second interface 520. Note that other architectures are possible besides the point-to-point architecture described above. For example, a system such as multiprocessor system 500 may implement a multi-drop interface or other such architecture instead of a point-to-point architecture.

[0052] Example core architectures, processors, and computer architectures.

[0053] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors give rise to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which may be included on the same die with the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0054] Figure 6 A block diagram of an example processor and / or SoC 600 that may have one or more cores, and an integrated memory controller is illustrated. The solid line block diagram shows a processor 600 having a single core 602(A), a system agent unit circuitry 610, and a collection of one or more interface controller unit circuitry 616, while the optional addition of dashed line blocks shows an alternative processor 600 having multiple cores 602(A)-(N), a collection of one or more integrated memory controller units 614 in the system agent unit circuitry 610, and dedicated logic 608 and a collection of one or more interface controller unit circuitry 616. Note that the processor 600 may be Figure 5 one of the processors 570 or 580, or the coprocessors 538 or 515.

[0055] Thus, different implementations of processor 600 may include: 1) a CPU, where the dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 602(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 602(A)-(N) are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 602(A)-(N) are a large number of general purpose in-order cores. Thus, processor 600 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 600 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0056] The memory hierarchy includes one or more levels of cache unit circuitry 604(A)-(N) within the cores 602(A)-(N), a set of one or more shared cache unit circuitry 606, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 614. The set of one or more shared cache unit circuitry 606 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. Although in some examples, an interface network circuitry 612 (e.g., a ring interconnect) provides an interface to dedicated logic 608 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuitry 606, and the system agent unit circuitry 610, alternative examples use any number of well-known techniques for providing interfaces to such units. In some examples, coherency is maintained between the shared cache unit circuitry 606 and one or more of the cores 602(A)-(N). In some examples, the interface controller unit circuitry 616 couples the core 602 to one or more other devices 618, such as one or more I / O devices, storage, one or more communication devices (e.g., a wireless network, a wired network, etc.), etc.

[0057] In some examples, one or more of the cores 602(A)-(N) are capable of multithreading. The system agent unit circuitry 610 includes those components that coordinate and operate the cores 602(A)-(N). The system agent unit circuitry 610 may include, for example, a power control unit (PCU) circuitry and / or a display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to perform the following operations: regulate the power state of the cores 602(A)-(N) and / or the dedicated logic 608 (e.g., integrated graphics logic), including determining an increased maximum power budget and communicating the increased maximum power budget to various IP circuits, as described herein. The display unit circuitry is used to drive one or more externally connected displays.

[0058] The cores 602(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 602(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 602(A)-(N) may be capable of executing an ISA, while other cores may only be capable of executing a subset of the ISA or another ISA.

[0059] The following examples relate to further embodiments.

[0060] In one example, a device includes: a first IP circuit for performing an operation on data; and a power controller coupled to the first IP circuit. The power controller is used to: receive a boost value, the boost value being based at least in part on one or more characteristics of a power supply coupled to the device; determine a boosted maximum power level for the device based at least in part on the boost value and a traditional maximum power level for the device, the boosted maximum power level being greater than the traditional maximum power level; and provide a boosted maximum power budget for the first IP circuit based at least in part on the boosted maximum power level, the boosted maximum power budget for the first IP circuit being greater than the traditional maximum power budget for the first IP circuit. In response to receiving an input voltage violation signal, the first IP circuit is used to responsively reduce power consumption to be equal to or below the traditional maximum power budget for the first IP circuit.

[0061] In an example, the first IP circuit is to receive the input voltage violation signal directly from a controller coupled to the power supply.

[0062] In an example, the apparatus further includes a hardwired path coupled to the first IP circuit for providing the input voltage violation signal from the controller directly to the first IP circuit.

[0063] In an example, the power controller is configured to receive the boost value from system software.

[0064] In an example, the apparatus further comprises configuration storage means for storing the boost value.

[0065] In an example, the power controller is to access the boost value from the configuration storage device and determine the boosted maximum power level comprising a sum of the boost value and the conventional maximum power level. In an example, the first IP circuit is to responsively reduce the power consumption to be equal to or below the conventional maximum power budget for the first IP circuit in less than 10 microseconds from receiving the input voltage violation signal.

[0066] In an example, the apparatus further includes at least one storage device for storing the boosted maximum power budget for the first IP circuit and the conventional maximum power budget for the first IP circuit.

[0067] In an example, the first IP circuit is to autonomously and responsively reduce the power consumption to be equal to or below the conventional maximum power budget for the first IP circuit in response to receiving the input voltage violation signal.

[0068] In an example, the apparatus further includes a second IP circuit for performing operations on second data, wherein the power controller is configured to provide a second conventional maximum power budget for the second IP circuit, the second IP circuit not exceeding the second conventional maximum power budget.

[0069] In another example, a method includes: receiving, in at least one IP circuit of a SoC, an indication that an input voltage of a voltage regulator coupled to the SoC has dropped below a threshold level; and in response to the indication, autonomously reducing power consumption of the at least one IP circuit in the at least one IP circuit to a level below a conventional maximum IP power budget set by a power controller of the SoC.

[0070] In an example, the method further includes receiving the indication in the at least one IP circuit via a hardwired connection to a voltage regulator controller coupled to the SoC.

[0071] In an example, the method further comprises reducing the power consumption of the at least one IP circuit to the level below the conventional maximum IP power budget within 10 microseconds from receiving the indication.

[0072] In an example, the method further includes: determining, in a power controller, a boosted maximum power budget for the SoC based at least in part on a boosted value for the SoC and a traditional maximum power budget, the boosted value being based on the voltage regulator, the boosted maximum power budget being greater than the traditional maximum power budget; determining a boosted maximum IP power budget for the at least one IP circuit based at least in part on the boosted maximum power budget; and sending the boosted maximum IP power budget to the at least one IP circuit.

[0073] In an example, the method further includes: operating the at least one IP circuit at the power consumption greater than the legacy maximum IP power budget based on the boosted maximum IP power budget; receiving the indication in the at least one IP circuit; and subsequently operating the at least one IP circuit at the power consumption less than the legacy maximum IP power budget.

[0074] In an example, the method further includes maintaining power consumption of the second IP circuit at a level below a conventional maximum second IP power budget set by the power controller.

[0075] In another example, a computer readable medium includes instructions for executing the method as described in any of the above examples.

[0076] In a further example, a computer readable medium includes data for use by at least one machine to fabricate at least one integrated circuit to perform the method of any of the above examples.

[0077] In a further example, an apparatus includes means for performing the method as in any of the above examples.

[0078] In yet another example, a system includes: a voltage regulator for receiving a system voltage and outputting an operating voltage; a voltage regulator controller for identifying when the system voltage drops below a threshold voltage; a SoC coupled to the voltage regulator; and a non-volatile memory coupled to the SoC. The SoC is for receiving the operating voltage and includes: at least one first IP circuit for performing an operation on a first data; and at least one second IP circuit for performing an operation on a second data. The SoC also includes a power controller for: receiving a boost value based at least in part on one or more characteristics of the voltage regulator; determining a boosted maximum power level for the SoC based at least in part on the boost value and a traditional maximum power level for the SoC, the boosted maximum power level being greater than the traditional maximum power level; and determining a boosted maximum power budget for the at least one first IP circuit based at least in part on the boosted maximum power level, the boosted maximum power budget for the at least one first IP circuit being greater than the traditional maximum power budget for the at least one first IP circuit. In response to the input voltage decreasing below the threshold voltage, the at least one first IP circuit is configured to reduce power consumption to be equal to or below the conventional maximum power budget for the at least one first IP circuit.

[0079] In an example, the voltage regulator controller is configured to send a voltage violation signal to the SoC when the system voltage is below the threshold voltage.

[0080] In an example, the system further includes: a hardwired path coupled between the voltage regulator controller and the at least one first IP circuit, the voltage regulator controller to send the voltage violation signal to the at least one first IP circuit via the hardwired path.

[0081] In an example, the at least one first IP circuit is to autonomously reduce the power consumption to be equal to or below the conventional maximum power budget for the at least one first IP circuit based on the voltage violation signal.

[0082] It should be understood that various combinations of the above examples are possible.

[0083] Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry, and / or any other type of physical hardware component, either alone or in any combination. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and instead, other embodiments may relate to other types of devices for processing instructions, or one or more machine-readable media, the machine-readable medium comprising instructions, in response to executing these instructions on a computing device, which cause the device to perform one or more of the methods and techniques described herein.

[0084] Embodiments may be implemented in code and may be stored on a non-transitory storage medium having instructions stored thereon that may be used to program a system to perform the instructions. Embodiments may also be implemented in data and may be stored on a non-transitory storage medium that, if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Further embodiments may be implemented in a computer-readable storage medium comprising information that, when fabricated in a SOC or other processor, configures the SOC or other processor to perform one or more operations. The storage medium may include, but is not limited to: any type of disk, including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memory (CD-ROMs), compact disk rewritable (CD-RWs), and magneto-optical disks; semiconductor devices, such as read-only memory (ROMs), random access memory (RAMs) such as dynamic random access memory (DRAMs) and static random access memory (SRAMs), erasable programmable read-only memory (EPROMs), flash memory, electrically erasable programmable read-only memory (EEPROMs); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0085] While the present disclosure has been described with reference to a limited number of implementations, those skilled in the art having the benefit of this disclosure will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations.

Claims

1. A device, comprising: A first intellectual property IP circuit for performing operations on data; as well as a power controller coupled to the first IP circuit, wherein the power controller is configured to: receiving a boost value based at least in part on one or more characteristics of a power source coupled to the device; determining a boosted maximum power level for the device based at least in part on the boosted value and a conventional maximum power level for the device, the boosted maximum power level being greater than the conventional maximum power level; and providing an increased maximum power budget for the first IP circuit based at least in part on the increased maximum power level, the increased maximum power budget for the first IP circuit being greater than a conventional maximum power budget for the first IP circuit, In response to receiving the input voltage violation signal, the first IP circuit is used to responsively reduce power consumption to be equal to or lower than the conventional maximum power budget for the first IP circuit.

2. The device according to claim 1, characterized in that The first IP circuit is configured to receive the input voltage violation signal directly from a controller coupled to the power supply.

3. The apparatus of claim 2, further comprising a hardwired path coupled to the first IP circuit for providing the input voltage violation signal from the controller directly to the first IP circuit.

4. The device according to claim 1, characterized in that The power controller is configured to receive the boost value from system software.

5. The apparatus of claim 4, further comprising configuration storage means for storing the boost value.

6. The device according to claim 5, characterized in that The power controller is to access the boost value from the configuration storage device and determine the boosted maximum power level comprising a sum of the boost value and the conventional maximum power level.

7. The device according to claim 1, characterized in that The first IP circuit is to responsively reduce the power consumption to be equal to or below the conventional maximum power budget for the first IP circuit in less than 10 microseconds from receiving the input voltage violation signal.

8. The apparatus of claim 7, further comprising at least one storage device for storing the boosted maximum power budget for the first IP circuit and the conventional maximum power budget for the first IP circuit.

9. The device according to claim 7, characterized in that The first IP circuit is configured to autonomously and responsively reduce the power consumption to be equal to or below the conventional maximum power budget for the first IP circuit in response to receiving the input voltage violation signal.

10. The apparatus of any one of claims 1 to 9, further comprising a second IP circuit for performing an operation on the second data, wherein: The power controller is configured to provide a second conventional maximum power budget for the second IP circuit, the second IP circuit not exceeding the second conventional maximum power budget.

11. A method comprising: receiving, in at least one intellectual property (IP) circuit of a system-on-chip (SoC), an indication that an input voltage of a voltage regulator coupled to the SoC has dropped below a threshold level; as well as In response to the indication, power consumption of the at least one IP circuit is autonomously reduced in the at least one IP circuit to a level below a conventional maximum IP power budget set by a power controller of the SoC.

12. The method of claim 11, further comprising: The indication in the at least one IP circuit is received via a hardwired connection to a voltage regulator controller coupled to the SoC.

13. The method of claim 11, further comprising: Within 10 microseconds of receiving the indication, the power consumption of the at least one IP circuit is reduced to the level below the conventional maximum IP power budget.

14. The method of claim 11, further comprising: determining, in a power controller, a boosted maximum power budget for the SoC based at least in part on a boosted value for the SoC and a conventional maximum power budget, the boosted value being based on the voltage regulator, the boosted maximum power budget being greater than the conventional maximum power budget; determining a boosted maximum IP power budget for the at least one IP circuit based at least in part on the boosted maximum power budget; as well as The increased maximum IP power budget is sent to the at least one IP circuit.

15. The method of claim 14, further comprising: operating the at least one IP circuit at a power consumption greater than the conventional maximum IP power budget based on the boosted maximum IP power budget; receiving the indication in the at least one IP circuit; as well as The at least one IP circuit is then operated at a power consumption that is less than the conventional maximum IP power budget.

16. The method of claim 11, further comprising: The power consumption of the second IP circuit is maintained at a level below a conventional maximum second IP power budget set by the power controller.

17. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 11 to 16.

18. A system, comprising: A voltage regulator, for receiving a system voltage and outputting an operating voltage; a voltage regulator controller for identifying when the system voltage drops below a threshold voltage; A system on chip (SoC) coupled to the voltage regulator, the SoC is used to receive the operating voltage and includes: at least one first intellectual property IP circuit, configured to perform an operation on first data; at least one second IP circuit, configured to perform an operation on second data; and Power controllers for: receiving a boost value based at least in part on one or more characteristics of the voltage regulator; determining a boosted maximum power level for the SoC based at least in part on the boosted value and a conventional maximum power level for the SoC, the boosted maximum power level being greater than the conventional maximum power level; and determining an elevated maximum power budget for the at least one first IP circuit based at least in part on the elevated maximum power level, the elevated maximum power budget for the at least one first IP circuit being greater than a conventional maximum power budget for the at least one first IP circuit, wherein, in response to the input voltage decreasing below the threshold voltage, the at least one first IP circuit is configured to reduce power consumption to be equal to or lower than the conventional maximum power budget for the at least one first IP circuit; and A non-volatile memory is coupled to the SoC.

19. The system of claim 18, wherein: The voltage regulator controller is configured to send a voltage violation signal to the SoC when the system voltage is lower than the threshold voltage.

20. The system of claim 19, further comprising a hardwired path coupled between the voltage regulator controller and the at least one first IP circuit, the voltage regulator controller to send the voltage violation signal to the at least one first IP circuit via the hardwired path.

21. The system of claim 19, wherein: The at least one first IP circuit is configured to autonomously reduce the power consumption to be equal to or below the conventional maximum power budget for the at least one first IP circuit based on the voltage violation signal.

22. A device, comprising: means for receiving, in at least one intellectual property (IP) device, an indication that an input voltage of a voltage regulator coupled to the apparatus has dropped below a threshold level; as well as means for autonomously reducing power consumption of the at least one IP device to a level below a conventional maximum IP power budget in the at least one IP device in response to the indication, the conventional maximum IP power budget being set by the power control means.

23. The apparatus of claim 22, further comprising: Means for receiving the indication via a hardwired connection to the voltage regulator control means.

24. The apparatus of claim 22, further comprising: Means for reducing the power consumption of the at least one IP device to the level below the legacy maximum IP power budget within 10 microseconds from receiving the indication.

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