An optimization method for cold start time of embedded low-power system

Abstract

The application provides an optimization method for cold start time of embedded low-power system, comprising the following steps: S1, two controllers are initialized and are respectively denoted as SFC0 and SFC1; S2, two flashes are initialized and are respectively denoted as Flash0 and Flash1; S3, the LZMA double-channel is switched to a decoding mode; S4, a root file system rootfs is loaded from the Flash1 to the memory by using the SFC1; meanwhile, the kernel is loaded from the Flash0 to the memory by using the SFC0 in parallel; S5, waiting for the SFC1 to be loaded; S6, the rootfs is decompressed by using the LZMA channel 0; meanwhile, the kernel is decompressed by using the LZMA channel 1 in parallel; S7, waiting for the SFC0 to be loaded; and S8, the LZMA is switched to an algorithm mode. The method has the advantages of fast start speed, saved flash space and low memory consumption, and is suitable for the high-time-demand requirement in the embedded system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of low-power product fast starting, and particularly relates to an optimization method for cold starting time of an embedded low-power system. BACKGROUND

[0002] With the emergence of multiple application fields of embedded products, people have higher and higher requirements for power consumption of consumer electronics, and corresponding solutions emerge in an endless stream. Power consumption has become an important bottleneck in the design of embedded systems.

[0003] The Windows starting process is to load the first sector content MBR of the first starting device into RAM through BIOS power-on self-test, start the operating system and run the file system, wherein the starting device can be a U disk, a hard disk or an optical drive.

[0004] The starting process of the embedded Linux system is to run the boot loader from the Nor Flash, load the kernel and the file system into RAM, start the kernel and the file system, and if the Nand Flash is selected for starting, the boot loader needs to be loaded into RAM and then run. In the battery solution, nor Flash is generally selected as the starting storage medium, thereby saving the time for moving code from nand to RAM.

[0005] Generally, a single Flash is selected for an embedded system to save all partition contents, and there is no thread mechanism in the boot loader. Loading the kernel and the file system is a pipeline work, that is, the CPU sequentially processes the program, and needs to perform the loading operation twice in succession.

[0006] However, in the prior art, the kernel needs to be loaded into RAM first, and then the file system is loaded into RAM, which involves two waiting processes for the SFC controller to complete, and is time-consuming.

[0007] For products with extremely fast system starting time requirements, most products use uboot that is trimmed to remove unnecessary modules to obtain a relatively optimal starting speed. However, the main time-consuming process is still loading and decompressing the kernel and the file system related to the user program. The larger the size, the longer the decompression time, and the worse the user experience.

[0008] In addition, the commonly used terms in the prior art include:

[0009] Cold start: the whole machine is powered off, all modules are reset, and the power is reinitialized to start. Thus, the software and hardware processes required for product operation need to be redone. Reboot soft start is only the software code process that is re-run, and does not power off the SOC and peripherals.

[0010] SFC: SPI Flash controller. One is to interact with the Flash device, and the other is to manage and query the Flash device. SPI Flash is a NOR FLASH with a serial communication interface. LZMA: A decompression format, both hardware and software. Using a dictionary encoding mechanism similar to LZ77, the compression rate is higher than bzip2 in general cases, and the maximum variable dictionary for compression can reach 4GB.

[0011] DMA: Direct Memory Access, direct memory access, is a function provided by some computer bus architectures, which can send data from an attached device (such as a disk drive) directly to the computer motherboard memory. SUMMARY

[0012] In order to solve the above problems, the purpose of the present application is to use the LZMA hardware decompression module developed by Beijing Junzheng Integrated Circuit Co., Ltd. (hereinafter referred to as Junzheng) to perform extreme decompression on the kernel and the file system, and to use the double SFC mechanism to load the kernel and the file system into the memory in parallel. The module has a double-channel decoding function and can work synchronously to decompress data.

[0013] Specifically, the present application provides an optimization method for cold start time of an embedded low-power system, which comprises the following steps:

[0014] S1, two controllers are initialized, respectively denoted as SFC0 and SFC1;

[0015] S2, two Flash are initialized, respectively denoted as Flash0 and Flash1; SFC0 corresponds to Flash0, and SFC1 corresponds to Flash1;

[0016] S3, the LZMA double-channel is switched to a decoding mode;

[0017] The working principle of the LZMA double-channel is as follows: the CPU software configures the code stream data base address, code stream size, target data base address and related signals for decoding through the AHB control bus, reads the code stream data from the memory for decoding based on the configured code stream base address through the AXI data bus, and writes the decoded data into the memory through the AXI data bus based on the configured target data address after decoding;

[0018] S4, loading the root file system rootfs from Flash1 into the memory using SFC1; at the same time, parallel processing: loading the kernel from Flash0 into the memory using SFC0;

[0019] SFC1 starts loading, DMA is opened, and DMA is used to carry data to memory, so that CPU can execute the following statements to operate SFC0 and use DMA to do parallel processing.

[0020] S5, wait for SFC1 to complete loading;

[0021] S6, LZMA channel 0 decompresses rootfs; at the same time, parallel processing: LZMA channel 1 decompresses the kernel; S7, wait for SFC0 to complete loading;

[0022] S8, switch the LZMA to the algorithm mode.

[0023] In step S1, the DMA processing mode needs to be configured when the controller SFC is initialized, and the DMA is closed after SFC0 completes loading.

[0024] In step S3, since the hardware LZMA decompression function and the bscaler module for using the algorithm share a switching signal, one bit is set as the trigger bit of the decompression mode, so the bit needs to be switched to the decompression mode before the current function is enabled. The switching of the bit to the decompression mode includes: in the Controller Register, the 31st bit is set as the trigger bit, and when the bit is written once as 1, mode switching is performed once; each time 1 is written, mode switching is performed once, and the bscaler shares a switching signal; 0 indicates that the LZMA encoding mode is not switched; the bscaler module is used for the algorithm and is recorded as the bscaler mode, and the same block of physical memory is used for the LZMA, so the LZMA needs to configure the Controller Register to set the 31st bit for the decompression function.

[0025] After the DMA processing mode is configured, the gap is used to enable another SFC to load data synchronously, that is, step S4 is performed. CPU sequentially executes instructions, cannot execute two instructions at a time, and cannot do two things at a time, so after SFC1 starts loading and DMA is opened, the gap of using DMA to help CPU to carry data is used, and CPU can sequentially execute the next operation SFC0.

[0026] In the method, after SFC1 starts loading the file system to the memory, DMA starts working, and then SFC0 starts loading the kernel to the memory. At this time, SFC1 uses Flash1, and SFC0 uses Flash0, so they do not affect each other when reading.

[0027] In step S8, further comprising: switching the LZMA to the algorithm bscaler mode after the reading is completed, for use after the system is started.

[0028] Therefore, the application has the advantages of fast starting speed, saving of Flash space, and low memory consumption. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application.

[0030] Figure 1 is a schematic diagram of switching one of the bits to a decompression mode before enabling the current function.

[0031] Figure 2 is a schematic diagram of the method flow of the application.

[0032] Figure 3 is a structural schematic diagram of the LZMA double channel in the method embodiment of the application. DETAILED DESCRIPTION

[0033] In order to make the technical content and advantages of the application more clearly understood, the application will be further described in detail in conjunction with the drawings.

[0034] As shown in Figure 1 , the application provides an optimization method for cold start time of an embedded low-power system, comprising the following steps:

[0035] S1, two controllers are initialized, and are respectively denoted as SFC0 and SFC1;

[0036] The DMA processing mode needs to be configured when the controller SFC is initialized, and the SFC0 is closed after the DMA is loaded;

[0037] S2, two Flashes are initialized, and are respectively denoted as Flash0 and Flash1; the SFC0 corresponds to the Flash0, and the SFC1 corresponds to the Flash1;

[0038] S3, the LZMA double channel is switched to a decoding mode;

[0039] The structure of the LZMA double channel can be seen from Figure 3 , and the working principle is as follows: the CPU software configures the code stream data base address, the code stream size, the target data base address, and the decoding related signals through the AHB control bus, reads the code stream data from the memory through the AXI data bus based on the configured code stream base address during decoding, and writes the decoding data into the memory through the AXI data bus based on the configured target data address after decoding;

[0040] Because the hardware LZMA decompression function and the bscaler module for using algorithm share one switch signal, one bit is set as the trigger bit of decompression mode, so before enabling the current function, the bit needs to be switched to the decompression mode, as shown in Figure 2 The switching of one bit as the decompression mode includes: setting the 31st bit as the trigger bit in the Controller Register, when the bit is written as 1 once, the mode switching is performed once; one mode switching is performed once every time 1 is written, and one switch signal is shared with the bscaler; 0 indicates that the LZMA encoding mode is not switched; the bscaler module is used for algorithm, and is recorded as the bscaler mode; the same physical memory is used for the bscaler and the LZMA, so the LZMA needs to configure the Controller Register, and set the 31st bit as the decompression function;

[0041] After the DMA processing mode is configured, the gap is used to enable the other SFC to load data synchronously, that is, the step S4 is performed; the CPU sequentially executes instructions, and cannot execute two instructions at a time, that is, cannot do two things at a time, so after the SFC1 starts loading and the DMA is enabled, the gap of the data carrying performed by the DMA to help the CPU is used, and the CPU can sequentially execute the next operation SFC0;

[0042] S4, loading the root file system rootfs from the Flash1 to the memory using the SFC1; simultaneously, performing parallel processing: loading the kernel from the Flash0 to the memory using the SFC0;

[0043] After the SFC1 starts loading, the DMA is enabled, and the DMA is used to carry data to the memory, so the CPU can execute the following statements to operate the SFC0 and use the DMA to perform parallel processing;

[0044] S5, waiting for the SFC1 to complete loading;

[0045] S6, decompressing the rootfs by the LZMA channel 0; simultaneously, performing parallel processing: decompressing the kernel by the LZMA channel 1; S7, waiting for the SFC0 to complete loading;

[0046] S8, switching the LZMA to the algorithm mode: switching the LZMA to the algorithm bscaler mode after the reading is completed, that is, after the data loading is completed.

[0047] In the method, after the SFC1 starts loading the file system to the memory, the DMA starts working, and then the SFC0 starts loading the kernel to the memory, at this time, the SFC1 uses the Flash1, and the SFC0 uses the Flash0, so the two do not affect each other when reading.

[0048] The above merely provides the preferred embodiments of the present application, but not for limiting the present application. For the person skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for optimizing the cold start time of an embedded low-power system, characterized in that, The method includes the following steps: S1, Initialize the two controllers, denoted as SFC0 and SFC1 respectively; S2, two Flash memory are initialized, denoted as Flash0 and Flash1 respectively; SFC0 corresponds to Flash0, and SFC1 corresponds to Flash1; S3, LZMA dual channels switch to decoding mode; The working principle of the LZMA dual channel is as follows: the CPU software configures the base address of the bitstream data, the bitstream size, the target data base address, and the start-related signals through the AHB control bus for decoding. During decoding, the bitstream data is read from memory through the AXI data bus based on the configured bitstream data base address for decoding. After decoding, the decoded data is written to memory through the AXI data bus based on the configured target data address. S4 loads the root file system (rootfs) from Flash1 into memory using SFC1; simultaneously, in parallel processing, the kernel is loaded from Flash0 into memory using SFC0. After SFC1 starts loading, DMA is enabled, and DMA is used to move data to memory. This allows the CPU to execute statements that operate on SFC0 and use DMA to achieve parallel processing. S5, wait for SFC1 to finish loading; S6, LZMA channel 0 decompresses rootfs; simultaneously, in parallel processing: LZMA channel 1 decompresses the kernel; S7, waiting for SFC0 to finish loading; S8, LZMA switches to algorithm mode.

2. The method for optimizing the cold start time of an embedded low-power system according to claim 1, characterized in that, In step S1, the DMA processing mode needs to be configured during the initialization of the controller SFC, and DMA is turned off after SFC0 is loaded.

3. The method for optimizing the cold start time of an embedded low-power system according to claim 2, characterized in that, In step S3, since the hardware LZMA decompression function and the bscaler module used for the algorithm share a switching signal, one bit is designated as the trigger bit for the decompression mode. Therefore, before enabling the current function, this bit needs to be switched to the decompression mode. Switching this bit to the decompression mode includes: in the Controller Register, the 31st bit is designated as the trigger bit. When this bit is written with a 1, a mode switch will occur. Each time a 1 is written, a mode switch will occur, sharing a switching signal with the bscaler. A 0 indicates that the LZMA encoding mode is not switched. The bscaler module is used by the algorithm and is designated as the bscaler mode. It uses the same physical memory as LZMA, so LZMA needs to be configured in the Controller Register to use the 31st bit for decompression.

4. The method for optimizing the cold start time of an embedded low-power system according to claim 2, characterized in that, After configuring the DMA processing mode, this gap is used to enable another SFC to load data synchronously, i.e., to perform step S4. After SFC1 starts loading and DMA is enabled, the CPU can sequentially execute the next operation SFC0 during the gap when DMA helps the CPU to transfer data.

5. The method for optimizing the cold start time of an embedded low-power system according to claim 1, characterized in that, Step S8 further includes: waiting for the reading to be completed, i.e., after the data loading is completed, switching LZMA to the algorithm bscaler mode for use after system startup.

Images