Secure access methods, apparatus and electronic devices for cache memory

Abstract

This invention provides a secure access method, apparatus, and electronic device for cache memory, relating to the field of cache memory technology. The secure access method for cache memory includes: in response to a function provided by firmware for accessing the cache memory being called, determining whether interrupt requests from various peripherals connected to the processor are masked using the interrupt status bits of the processor's interrupt controller; in response to the interrupt requests from the processor not being masked, masking the interrupt requests from various peripherals using the interrupt control bits of the interrupt controller; and in response to the function for accessing the cache memory returning, restoring the interrupt requests from various peripherals using the interrupt control bits of the interrupt controller. This invention enables secure and efficient access to the cache memory.

Description

Technical Field

[0001] This invention relates to the field of cache memory technology, and in particular to a secure access method, apparatus, and electronic device for cache memory. Background Technology

[0002] Caching technology, as an efficient temporary data storage solution, is widely used in modern computer systems to accelerate data access, reduce latency, and improve overall system performance. Caching is typically deployed in memory, offering significantly faster access speeds than main storage (such as hard drives), and can be implemented at different levels, such as CPU cache, memory cache, and disk cache. By storing frequently accessed data, caching effectively reduces data access latency, thereby increasing system throughput and significantly reducing the frequency of I / O operations.

[0003] With the continuous improvement of processor performance, cache, as a critical component of the processor, plays a crucial role in the stability and security of the entire system due to its data security. However, current processor cache management systems still have many shortcomings in terms of data security. For example, there are various problems such as data inconsistency, performance bottlenecks, increased system complexity, inappropriate expiration policies, security vulnerabilities, and resource contention.

[0004] Therefore, how to access cache memory safely and efficiently is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of the above-mentioned problems in the prior art, the present invention provides a secure access method, apparatus and electronic device for cache memory, so as to securely and efficiently access cache memory.

[0006] This invention provides a secure access method for a cache memory, comprising the following steps.

[0007] In response to the function for accessing cache memory provided by the firmware being called, the interrupt status bit of the processor's interrupt controller is used to determine whether interrupt requests from various peripherals connected to the processor are masked; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt requests from the processor not being masked, the interrupt requests from the various peripherals are masked using the interrupt control bit of the interrupt controller; and in response to the function for accessing cache memory being returned, the interrupt requests from the various peripherals are restored using the interrupt control bit of the interrupt controller.

[0008] According to a secure access method for a cache memory provided by the present invention, interrupt masking code is called at the entry point of the function accessing the cache memory; the step of determining whether interrupt requests from various peripherals connected to the processor are masked by using the interrupt status bit of the interrupt controller of the processor includes: the interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests from various peripherals are masked; the step of masking interrupt requests from various peripherals by using the interrupt control bit of the interrupt controller in response to the interrupt requests from the processor not being masked includes: the interrupt masking code sets the interrupt control bit of the interrupt controller to mask the interrupt requests from various peripherals when it is determined from the query result that the interrupt requests from various peripherals are not masked.

[0009] According to a secure access method for a cache memory provided by the present invention, interrupt recovery code is called at the return point of the function accessing the cache memory; in response to the return of the function accessing the cache memory, interrupt requests from various peripherals are restored using the interrupt control bit of the interrupt controller, including: the interrupt recovery code sets the interrupt control bit of the interrupt controller to restore interrupt requests from various peripherals.

[0010] According to a secure access method for a cache memory provided by the present invention, the method further includes: setting a cache access flag stored at a preset location at the entry point of the function accessing the cache memory; determining whether interrupt requests from various peripherals connected to the processor are masked using the interrupt status bit of the processor's interrupt controller includes: querying the interrupt status bit of the interrupt controller to determine whether interrupt requests from various peripherals are masked when a polling function running in the firmware finds that the cache access flag is set; and masking interrupt requests from various peripherals using the interrupt control bit of the interrupt controller in response to the interrupt requests from the processor not being masked includes: setting the interrupt control bit of the interrupt controller to mask interrupt requests from various peripherals when the polling function determines that the interrupt requests are not masked.

[0011] According to a secure access method for a cache memory provided by the present invention, the cache access flag is cleared at the return point of the function accessing the cache memory; in response to the return of the function accessing the cache memory, interrupt requests from various peripherals are restored using the interrupt control bit of the interrupt controller, including: when the polling function finds that the cache access flag has been cleared, setting the interrupt control bit of the interrupt controller to restore interrupt requests from various peripherals.

[0012] According to a secure access method for a cache memory provided by the present invention, the functions for accessing the cache memory include: an invalid function, a clean function, and a flush function; the calling of the functions for accessing the cache memory includes: any one of the invalid function, clean function, and flush function being called.

[0013] The present invention also provides a secure access device for a cache memory, comprising the following modules:

[0014] A determination module is configured to, in response to a function provided by the firmware for accessing cache memory being called, determine whether interrupt requests from various peripherals connected to the processor are masked using the interrupt status bits of the processor's interrupt controller; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; a masking module is configured to, in response to an interrupt request from the processor not being masked, mask the interrupt requests from the various peripherals using the interrupt control bits of the interrupt controller; and a recovery module is configured to, in response to the function for accessing cache memory being returned, recover the interrupt requests from the various peripherals using the interrupt control bits of the interrupt controller.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements a secure access method for the cache memory as described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a secure access method for a cache memory as described above.

[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a secure access method for a cache memory as described above.

[0018] The secure access method, apparatus, and electronic device for cache memory provided by this invention, when a function for accessing the cache memory provided by the firmware is called, utilizes the interrupt status bits of the processor's interrupt controller to determine whether interrupt requests from various peripherals connected to the processor are masked; if the processor's interrupt requests are not masked, the interrupt control bits of the interrupt controller are used to mask interrupt requests from various peripherals; and when the function for accessing the cache memory returns, the interrupt control bits of the interrupt controller are used to restore interrupt requests from various peripherals. Because various problems caused by interrupt interference can be avoided during cache memory access, secure and efficient access to the cache memory is achieved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is one of the flowcharts illustrating the secure access method for a cache memory provided by the present invention.

[0021] Figure 2 This is the second flowchart illustrating the secure access method for the cache memory provided by the present invention.

[0022] Figure 3 This is the third flowchart illustrating the secure access method for the cache memory provided by this invention.

[0023] Figure 4 This is a schematic diagram of a multi-core processor.

[0024] Figure 5 This is a schematic diagram of the secure access process of the cache memory provided by the present invention.

[0025] Figure 6 This is a schematic diagram of the secure access device for the cache memory provided by the present invention.

[0026] Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0028] The following is combined with Figures 1-5 The present invention describes a secure access method for a cache memory.

[0029] Figure 1 This is one of the flowcharts illustrating the secure access method for a cache memory provided by this invention. The method is executed by firmware running in the processor, such as... Figure 1 As shown, the method includes the following:

[0030] Step 101: In response to the function provided by the firmware for accessing the cache memory being called, the interrupt status bits of the processor's interrupt controller are used to determine whether interrupt requests from various peripherals connected to the processor are masked.

[0031] like Figure 5 As shown, functions for accessing the cache memory (cache functions) may include: invalid function, clean function, and flush function. When any of the invalid function, clean function, or flush function is called, the method provided in this embodiment of the invention is executed to securely access the cache memory.

[0032] The main function of the Invalid function is to mark a specific cache line as invalid. This means that the valid bit in the cache line is set to 0, indicating that the data in the cache is no longer valid or is inconsistent with the data in main memory.

[0033] The Clean function writes cache lines marked as dirty back to main memory and clears their dirty bits. This means that the data in the cache line has been synchronized to main memory, and the cache line is now considered clean.

[0034] The Flush function is generally understood as a combination of Clean and Invalid operations. That is, it first writes all dirty cache lines back to main memory, and then marks all cache lines as invalid.

[0035] The processor includes at least one core. The processor's interrupt controller dispatches interrupt requests from various peripherals to the corresponding core.

[0036] In practical implementation, the firmware can determine in various ways whether a function accessing the cache memory is called, thereby performing interrupt-related processing. See specific embodiments. Figure 2 and Figure 3 The relevant content will not be repeated here.

[0037] The interrupt controller includes interrupt status bits, which can be used to determine whether interrupt requests from various peripherals connected to the processor are masked.

[0038] For example only, such as Figure 4 As shown, the processor has eight A55 processor cores, forming a cluster architecture. The A55 has three levels of cache: L1 and L2 are private to each core, while L3, located within the DSU, is shared by all cores in the cluster architecture. In this cluster architecture, all interrupt signals originate from the Generic Interrupt Controller (GIC). This interrupt controller is specifically designed in the ARM architecture to manage and distribute interrupt requests. It efficiently handles interrupts from various devices and accurately routes them to the appropriate core. The GIC600 version is optimized for large-scale System-on-Chip (SoC) designs. Its distributed IP architecture allows components to be flexibly deployed across different clock domains, power domains, and hardware designs, greatly improving system scalability and adaptability.

[0039] Given that all eight A55 cores of this processor run at the highest execution level, EL3 (EL0 is primarily for application code execution, EL1 is reserved for the operating system, EL2 is the hypervisor's runtime environment, and EL3 is specifically designed for low-level firmware and security code), the GIC defaults to configuring all interrupts as FIQ (Fast Interrupt Request) interrupts. Therefore, in practical implementation, the second bit of the A55 processor's internal register SCR_EL3 can be used to determine whether an interrupt is masked, and to perform operations such as masking and resuming interrupts. For example, when the second bit of SCR_EL3 is 1, it indicates that the interrupt is masked; when it is 0, it indicates that the interrupt is not masked.

[0040] In practice, if it is confirmed that the processor's interrupt requests have been masked, no processing is required on the interrupt controller.

[0041] Step 102: In response to the fact that the interrupt request from the processor is not masked, the interrupt control bit of the interrupt controller is used to mask the interrupt requests from various peripherals.

[0042] Even when processor interrupt requests are not masked, interrupt requests from various peripherals can be masked using the interrupt control bits of the interrupt controller. For example, setting the second bit of the A55 processor's internal register SCR_EL3 to 1 masks interrupts.

[0043] Because this invention relies on the coordinated operation of multiple processor cores, the system must undergo a series of thorough pre-checks before performing the interrupt disable operation. These checks aim to ensure that no process is currently accessing or modifying cached data, thereby maintaining data consistency and integrity. Pre-checks may include steps such as locking relevant resources and a detailed review of concurrent access states.

[0044] Step 103: In response to the function that accesses the cache memory being returned, interrupt requests from various peripherals are resumed using the interrupt control bits of the interrupt controller.

[0045] If the function accessing the cache memory returns, interrupt requests from various peripherals can be resumed using the interrupt control bits of the interrupt controller. For example, clearing the second bit of the A55 processor's internal register SCR_EL3 will resume the interrupt.

[0046] In multitasking or real-time systems, cache operations may face a series of problems due to interruption:

[0047] Unpredictability of interruptions: Interruptions triggered by external events are unpredictable and may occur at critical moments in cache operations, disrupting their normal flow.

[0048] Interrupt priority issue: In a multitasking system, high-priority interrupts may preempt CPU resources, causing cache operations to be delayed or interrupted.

[0049] Data consistency issues: Interruptions may cause data write or update operations in the cache to be incomplete, resulting in data inconsistency and affecting subsequent data processing and system decisions.

[0050] Degraded system performance: Frequent interrupts consume CPU time, delay cache operations, and reduce system response speed and throughput.

[0051] Deadlock and resource contention: Simultaneous access to data by interrupt handlers and cache operations may lead to deadlock or resource contention, affecting system stability.

[0052] Context switching overhead: Context switching when an interrupt occurs incurs additional overhead, which can significantly impact performance, especially when cache operations are frequent.

[0053] Real-time issues: Interruptions may cause cache operations to time out, affecting the performance of real-time systems.

[0054] Error handling complexity: Recovering from cache operations or handling errors after an interruption increases the complexity of the system, requiring guarantees of the atomicity of operations.

[0055] Software and hardware coordination issues: Software-level cache management strategies and hardware interrupt handling mechanisms may be incompatible, leading to improper cache state management.

[0056] Security vulnerability: Improper handling of cache data by interrupt handlers may introduce a security vulnerability, leading to unauthorized access to or tampering of sensitive data.

[0057] In the embodiments provided by this invention, when the function for accessing the cache memory provided by the firmware is called, the interrupt status bits of the processor's interrupt controller are used to determine whether interrupt requests from various peripherals connected to the processor are masked; if the processor's interrupt requests are not masked, the interrupt control bits of the interrupt controller are used to mask the interrupt requests from various peripherals; and when the function for accessing the cache memory returns, the interrupt control bits of the interrupt controller are used to restore the interrupt requests from various peripherals. Because various problems caused by interrupt interference can be avoided during cache memory access, data security can be effectively protected when the processor uses the cache, preventing data leakage and malicious attacks.

[0058] Figure 2 This is a second flowchart illustrating the secure access method for the cache memory provided by the present invention, as shown below. Figure 2 As shown, the method includes the following:

[0059] Step 201: Call the interrupt mask code at the entry point of the function that accesses the cache memory.

[0060] Interrupt masking code is code that enables the masking of interrupts for a specific processor.

[0061] For example, interrupt masking code is used to process the second bit of the A55 processor's internal register SCR_EL3 to check if an interrupt is masked, and to mask it if it is not.

[0062] By calling interrupt-masking code at the entry point of the function accessing the cache memory, the firmware can determine that the function accessing the cache memory has been called when this code is invoked. This ensures that interrupts are masked in a timely manner when accessing the cache memory.

[0063] Step 202: The interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether interrupt requests from various peripherals are masked.

[0064] Interrupt masking codes can query the interrupt status bits of the interrupt controller to determine whether interrupt requests from various peripherals are masked. For example, the second bit of the A55 processor's internal register SCR_EL3 can be read; if it is 0, it indicates that the processor's interrupt bits are masked.

[0065] Step 203: Interrupt Masking Code. If the query results determine that the interrupt requests from various peripherals are not masked, the interrupt control bit of the interrupt controller is set to mask the interrupt requests from various peripherals.

[0066] If the interrupt masking code determines that the processor's interrupt request is not masked, the interrupt control bits of the interrupt controller can be used to mask interrupt requests from various peripherals. For example, the interrupt masking code can set the second bit of the A55 processor's internal register SCR_EL3 to 1, thus masking the interrupt.

[0067] Step 204: Call the interrupt recovery code at the return point of the function that accesses the cache memory.

[0068] Interrupt recovery code is code that enables the recovery of interrupts for a specific processor.

[0069] For example, interrupt recovery code is code that processes the second bit of the A55 processor's internal register SCR_EL3 to recover the interrupt functionality.

[0070] The firmware calls interrupt recovery code at the return point of the function accessing the cache memory. When this code is called, the firmware can determine that the function accessing the cache memory has returned. This ensures that the interrupt can be recovered promptly when the cache memory access is complete.

[0071] Step 205: The interrupt recovery code sets the interrupt control bits of the interrupt controller to recover interrupt requests from various peripherals.

[0072] If the function accessing the cache memory returns, the interrupt recovery code can use the interrupt control bits of the interrupt controller to resume interrupt requests from various peripherals. For example, the second bit of the A55 processor's internal register SCR_EL3 can be cleared to resume the interrupt.

[0073] Figure 3 This is the third flowchart illustrating the secure access method for the cache memory provided by this invention, as shown below. Figure 3 As shown, the method includes the following:

[0074] Step 301: Set the cache access flag stored in a preset location at the entry point of the function that accesses the cache memory.

[0075] Setting the cache access flag to 1 indicates that the cache memory has been accessed.

[0076] Step 302: When the polling function running in the firmware finds that the cache access flag is set, it queries the interrupt status bit of the interrupt controller to determine whether interrupt requests from various peripherals are masked.

[0077] To promptly detect cache access, a polling function can be run in the firmware. This function periodically checks the cache access flag. If the cache access flag is set, the polling function checks the interrupt status bits of the interrupt controller to determine if interrupt requests from various peripherals are masked.

[0078] Step 303: If the polling function determines that the interrupt request has not been masked, it sets the interrupt control bit of the interrupt controller to mask interrupt requests from various peripherals.

[0079] If the polling function determines that the processor's interrupt requests are not masked, interrupt requests from various peripherals can be masked using the interrupt control bits of the interrupt controller. For example, the polling function can set the second bit of the A55 processor's internal register SCR_EL3 to 1, thus masking interrupts.

[0080] Step 304: Clear the cache access flag at the return point of the function that accesses the cache memory.

[0081] The cache access flag is cleared to indicate that the access task to the cache memory has been completed.

[0082] Step 305: When the polling function finds that the cache access flag has been cleared, it sets the interrupt control bit of the interrupt controller to restore interrupt requests from various peripherals.

[0083] If the polling function determines that the function accessing the cache memory has returned, interrupt requests from various peripherals can be resumed using the interrupt control bits of the interrupt controller. For example, the second bit of the A55 processor's internal register SCR_EL3 can be cleared to resume the interrupt.

[0084] The secure access device for a cache memory provided by the present invention is described below. The secure access device for a cache memory described below can be referred to in correspondence with the secure access method for a cache memory described above.

[0085] Figure 6This is a schematic diagram of the secure access device for the cache memory provided by the present invention. Figure 6 As shown, the device 600 includes the following modules.

[0086] The determination module 610 is configured to, in response to the function for accessing the cache memory provided by the firmware being called, determine whether interrupt requests from various peripherals connected to the processor are masked using the interrupt status bits of the processor's interrupt controller; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding core.

[0087] The shielding module 620 is used to shield interrupt requests from various peripherals in response to the fact that the interrupt request of the processor is not shielded, by using the interrupt control bit of the interrupt controller.

[0088] The recovery module 630 is configured to, in response to the function accessing the cache memory being returned, recover the interrupt requests from various peripherals using the interrupt control bits of the interrupt controller.

[0089] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7 As shown, the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 may invoke logical instructions in the memory 730 to execute a secure access method for the cache memory. This method includes: in response to a function provided by the firmware for accessing the cache memory being called, determining whether interrupt requests from various peripherals connected to the processor are masked using an interrupt status bit of the processor's interrupt controller; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt requests from the processor not being masked, masking interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller; and in response to the function for accessing the cache memory being returned, restoring interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller.

[0090] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the secure access method for cache memory provided by the above methods. The method includes: in response to the function for accessing cache memory provided by the firmware being called, determining whether interrupt requests from various peripherals connected to the processor are masked using an interrupt status bit of the interrupt controller of the processor; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt requests from the processor not being masked, masking interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller; and in response to the function for accessing cache memory being returned, restoring interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller.

[0092] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program implements a secure access method for a cache memory provided by the methods described above. The method includes: in response to a function for accessing the cache memory provided by the firmware being called, determining, using an interrupt status bit of the interrupt controller of the processor, whether interrupt requests from various peripherals connected to the processor are masked; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt requests from the processor not being masked, masking interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller; and in response to the function for accessing the cache memory being returned, recovering interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller.

[0093] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0094] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A secure access method for a cache memory, characterized in that, The method is executed by firmware running in the processor, and the method includes: In response to the function for accessing the cache memory provided by the firmware being called, the interrupt status bits of the processor's interrupt controller are used to determine whether interrupt requests from various peripherals connected to the processor are masked; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; In response to the processor's interrupt request not being masked, interrupt requests from the various peripherals are masked using the interrupt control bits of the interrupt controller; and In response to the function that accesses the cache memory being returned, interrupt requests from various peripherals are resumed using the interrupt control bits of the interrupt controller.

2. The secure access method for a cache memory according to claim 1, characterized in that, The interrupt masking code is called at the entry point of the function that accesses the cache memory; The step of using the interrupt status bits of the processor's interrupt controller to determine whether interrupt requests from various peripherals connected to the processor are masked includes: The interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of the various peripherals are masked. In response to the interrupt request from the processor not being masked, the interrupt control bits of the interrupt controller are used to mask interrupt requests from various peripherals, including: If the interrupt masking code determines, based on the query results, that the interrupt requests from the various peripherals are not masked, it sets the interrupt control bit of the interrupt controller to mask the interrupt requests from the various peripherals.

3. The secure access method for a cache memory according to claim 2, characterized in that, The interrupt recovery code is called at the return point of the function that accesses the cache memory; The function responding to the access to the cache memory is returned, and the interrupt requests from various peripherals are resumed using the interrupt control bits of the interrupt controller, including: The interrupt recovery code sets the interrupt control bit of the interrupt controller to recover interrupt requests from various peripherals.

4. The secure access method for a cache memory according to claim 1, characterized in that, The method further includes: setting a cache access flag stored at a preset location at the entry point of the function that accesses the cache memory; The step of using the interrupt status bits of the processor's interrupt controller to determine whether interrupt requests from various peripherals connected to the processor are masked includes: When the polling function running in the firmware finds that the cache access flag is set, it queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of the various peripherals are masked. In response to the interrupt request from the processor not being masked, the interrupt control bits of the interrupt controller are used to mask interrupt requests from various peripherals, including: If the polling function determines that the interrupt request has not been masked, it sets the interrupt control bit of the interrupt controller to mask interrupt requests from the various peripherals.

5. The secure access method for a cache memory according to claim 4, characterized in that, At the return point of the function that accesses the cache memory, the cache access flag is cleared. The function responding to the access to the cache memory is returned, and the interrupt requests from various peripherals are resumed using the interrupt control bits of the interrupt controller, including: When the polling function finds that the cache access flag has been cleared, it sets the interrupt control bit of the interrupt controller to restore interrupt requests from various peripherals.

6. The secure access method for a cache memory according to any one of claims 2 to 5, characterized in that, The functions for accessing the cache memory include: invalid function, clean function, and flush function; The function for accessing the cache memory is called, including: The invalid function, clean function, and flush function are all called.

7. A secure access device for a cache memory, characterized in that, The device includes: A determination module is configured to, in response to a function call provided by the firmware to access the cache memory, determine whether interrupt requests from various peripherals connected to the processor are masked using the interrupt status bits of the processor's interrupt controller; wherein the processor includes at least one core, and the interrupt controller distributes interrupt requests from the various peripherals to the corresponding cores; A masking module, configured to, in response to an interrupt request from the processor not being masked, utilize the interrupt control bits of the interrupt controller to mask interrupt requests from various peripherals; and The recovery module is used to recover interrupt requests from various peripherals in response to the return of the function that accesses the cache memory, using the interrupt control bits of the interrupt controller.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the secure access method for the cache memory as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the secure access method for the cache memory as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the secure access method for the cache memory as described in any one of claims 1 to 6.

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