A spaceborne image data simulation source system

Abstract

The present invention belongs to the field of aerospace payload testing, and relates to a spaceborne image data simulation source system for providing test image data for a spaceborne image processing system, including: a storage and register module implemented based on FPGA and an analog image processing module deployed on a host computer; the storage and register module is used to receive and store the image frame data generated by the image processing module and provide it to the spaceborne image processing system; it is also used to feed back the return data of the spaceborne image processing system to the analog image processing module; the image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, generate image frame data by framing and transmit it to the FPGA; it is also used to receive the return data from the spaceborne image processing system transmitted through the FPGA. The system of the present invention has the advantages of having multiple adaptation interfaces, rich configuration options, high flexibility and strong reliability.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace payload testing, and particularly relates to a spaceborne image data simulation source system. Background Art

[0002] The design and development of various satellites are important ways to realize space science exploration and space application development. Among them, payloads, as the direct tools to achieve the above ways, need to be strictly tested and evaluated before being assembled into satellites. Image processing, as an important part of the on-board data processing function, plays a crucial role. To ensure the performance and reliability of the on-board image acquisition and processing system, the ground comprehensive testing, verification, and evaluation links have become an indispensable part.

[0003] Traditional image data simulation sources mainly rely on CCD cameras to generate image data, but their inherent limitations are difficult to meet the growing diverse needs. Specifically, these simulation sources are unable to output the image content of flexible and variable scenarios, implement multiple transmission formats, and provide rich configuration options.

[0004] In addition, the existing general ground detection systems cannot fully simulate the complex environments and abnormal situations that may be encountered in spaceborne image processing, and it is difficult to deeply optimize and adapt to specific spaceborne image processing algorithms, resulting in problems such as low matching degree and unstable performance in actual applications. And generally, it is usually composed of an industrial computer and an FPGA board card externally connected to a payload interface adapter board. Such an architecture can meet the basic image processing needs, but there are still deficiencies in processing speed and flexibility, and the chassis is also relatively bulky and inconvenient to carry. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and propose a spaceborne image data simulation source system.

[0006] To achieve the above purpose, the present invention provides a spaceborne image data simulation source system for providing test image data for a spaceborne image processing system, including: a storage and register module implemented based on FPGA and a simulated image processing module deployed on a host computer; wherein,

[0007] The storage and register module is used to receive and store the image frame data generated by the image processing module and provide it to the spaceborne image processing system; it is also used to feedback the return data of the spaceborne image processing system to the simulated image processing module;

[0008] The image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, generate image frame data by framing and transmit it to the FPGA; it is also used to receive the return data from the spaceborne image processing system transmitted by the FPGA.

[0009] Preferably, communication between the FPGA and the host computer is carried out through a PCIe high-speed channel, and a PCIe to Thunderbolt 4 adapter board is used.

[0010] Preferably, the storage and register module includes: a configuration control register group, a verification unit, an external memory management unit, a transmission clock control unit, a parallel-to-serial conversion unit, and a serial-to-parallel conversion unit; wherein,

[0011] The configuration control register group is used to implement the functions of the host computer controlling the FPGA and the FPGA returning the working state to the host computer, and includes a control register, an address register, a size register, a peripheral register, a load transmission status register, and a reception status register;

[0012] The verification unit is used to verify the integrity and correctness of the data during the loading process, starts working through a specific field of the control register, performs synchronization header verification, instruction verification, and data verification on the input data, and stores the verification result in a specific field of the reception status register;

[0013] The external memory management unit is used to achieve efficient reading and writing of the external SDRAM memory, provides SRAM memory reading and writing interfaces to other modules, and through the control of the control register, address register, and size register, realizes writing data of a specified size from a logical area to a specified address in the memory, and reading data of a specified size from a specified address in the memory to the logical area;

[0014] The transmission clock control unit is used to generate and select a clock with a corresponding frequency as the transmission clock according to a specific field of the control register;

[0015] The parallel-to-serial conversion unit is used to receive the data from the external memory management unit, and using the transmission clock selected by the transmission clock control unit, converts the parallel data into serial data and outputs it to the external interface of the FPGA board;

[0016] The serial-to-parallel conversion unit is used to convert the serial data received from the external interface of the FPGA board into parallel data according to the enable flag bit of the control register, and transmits it to the external storage management unit in units of bytes.

[0017] Preferably, the control register, address register, size register, and peripheral register support read and write operations, and the load transmission status register and reception status register only support read operations.

[0018] Preferably, the image processing module includes: a system control function unit, an image source database management unit, a loading function unit, a sending function unit, and a receiving function unit, wherein,

[0019] The system control function unit is used to monitor the system status by obtaining the system status field of the control register of the FPGA, to monitor the link status by obtaining the link status information of the PCIe high-speed channel, and is also used to uniformly reset and initialize the image processing module and the FPGA;

[0020] The image source database management unit is used to index and call the local image set, to implement image preview according to the image size information and bit depth information, and is also used for image enhancement;

[0021] The loading function unit is used to frame image data, manage memory, and perform frame loading verification according to the user loading instruction, and send the processed image frame to the FPGA;

[0022] The sending function unit is used to configure the sending instruction and sending parameters to the FPGA according to the user sending instruction;

[0023] The receiving function unit is used to receive the data returned by the FPGA according to the user receiving instruction, and store and display it.

[0024] Preferably, the processing of the loading function unit includes:

[0025] Step 1) Start the loading thread;

[0026] Step 2) Parse the user loading instruction and open the image to be loaded;

[0027] Step 3) Allocate frame space according to the image information and frame format, sequentially add a frame header, image data, and frame tail, frame the image data to be loaded, and use memory management to allocate a memory address, and transfer the image frame data to the external SDRAM memory of the FPGA through DMA of the h2c channel;

[0028] Step 4) Configure the control register, size register, and address register of the FPGA;

[0029] Step 5) Verify the image frame and synchronously feedback the verification result to the graphical user interface;

[0030] Go to Step 2) until all the images to be loaded are transferred, and end the loading thread.

[0031] Preferably, the frame header in the frame format includes: an 8-byte sync header, 2 bytes for the image width, 2 bytes for the image height, 2 bytes for the image bit depth, 4 bytes for the bytes occupied by the image, and 2 bytes for the frame header check;

[0032] The number of bytes occupied by the image data is determined by the actual amount of image data;

[0033] The end frame is a 2-byte data checksum, and its calculation method is to accumulate each byte of the image data. After the accumulation is completed, the accumulated sum is obtained.

[0034] Preferably, the processing process of the receiving functional unit includes:

[0035] Step 1) Start the receiving thread;

[0036] Step 2) Configure the control register;

[0037] Step 3) Detect whether the end flag is set. If it is set, go to Step 5); if it is not set, read the receiving status register; determine whether the receiving block is full. If the determination is no, go to Step 3); otherwise, go to Step 4);

[0038] Step 4) Initiate a DMA request for the c2h channel, read the data of the corresponding block. After the reading is completed, set the corresponding bit of the control register, write the block data into the file, and go to Step 3);

[0039] Step 5) Read the receiving status register, obtain the amount of data already stored in the last block, initiate a DMA request for the c2h channel, write the data of the last block into the file, close the receiving thread, and complete one reception.

[0040] Preferably, the graphical user interface includes:

[0041] A system control area for implementing operations such as starting, stopping, and status monitoring of the system, providing a debugging function entry, and implementing direct reading and writing of the configuration control register group;

[0042] An image source database tab for configuring and managing various types of image source data, providing real-time image preview and parameter adjustment, providing an interface for configuring parameters of the image loading function, and providing an interface for the image loading function;

[0043] A send-receive function tab for browsing the list of loaded images, providing an interface for configuring send parameters, a send function entry, a send status display, and providing a receive function entry, a receive status display, and a quick view of the received file; and

[0044] A log area for displaying detailed log information during the operation of the system and implementing the function of saving and recording log files.

[0045] Compared with the prior art, the advantages of the present invention are:

[0046] 1. The present invention is specifically designed for on-board image processing systems, providing comprehensive management of image data sets, convenient image preview functions, and flexible working condition configuration and sending capabilities. It is characterized by powerful functions, rich configuration options, and a user-friendly graphical interface, ensuring intuitive and simple operations, fully meeting diverse test requirements, and greatly enhancing the user experience;

[0047] 2. The external interface of the present invention adopts a modular design, which can load different on-board device interfaces, match different transmission rates, and has the advantages of strong compatibility and high adaptability;

[0048] 3. The present invention uses a PCIe to Thunderbolt 4 adapter board. Compared with the traditional chassis-type insertion of PCIe boards, a mini host with a USB4 interface can be used as the upper computer. It not only supports hot plugging of the board, but also greatly reduces the system weight, improving the portability and practicality of the system;

[0049] 4. The present invention adopts a modular concept in its design. The units cooperate efficiently with each other, enabling the system to maintain high performance while maintaining high flexibility and scalability, and also facilitating later maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a schematic diagram of the system structure of the present invention;

[0051] Figure 2 is a typical working flowchart of the present invention;

[0052] Figure 3 is a flowchart of the implementation of the loading function of the upper computer of the present invention;

[0053] Figure 4 is a flowchart of the implementation of the sending function of the upper computer of the present invention;

[0054] Figure 5 is a flowchart of the implementation of the receiving function of the upper computer of the present invention;

[0055] Figure 6 is a design block diagram of the verification unit of the FPGA design of the present invention;

[0056] Figure 7 is a design block diagram of the parallel-to-serial conversion unit of the FPGA design of the present invention;

[0057] Figure 8 is a design block diagram of the serial-to-parallel conversion unit of the FPGA design of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0058] The system of the present invention is used to test the functional correctness of different on-board image processing systems. The system includes: a host computer software, a PCIe high-speed channel, an FPGA implementation, and an external interface.

[0059] The host computer software includes a graphical user interface and multiple functional unit modules. The graphical user interface provides a user interaction interface, and the functional unit modules implement specific functions. The graphical user interface is divided into two regions in total, a system control region and a function region. Among them, the function region can be further divided into an image source database tab and a send-receive function tab. Among them,

[0060] The system control region is responsible for monitoring the operating status of the entire system and providing control instructions such as start, stop, and reset. The system control region provides status indicator lights for the board status and link status, which are used to intuitively indicate whether the working status of the board and the link status of the PCIe link are normal. The system control region also provides advanced debugging functions, including a speed measurement function, a send accumulation number, a system reset, and an opening of a debugging interface.

[0061] The above-mentioned advanced debugging functions are used to deeply optimize the system and troubleshoot faults to ensure the stability and efficiency of data transmission.

[0062] The above-mentioned speed measurement function is divided into loading speed measurement and reading speed measurement, which are used to obtain the PCIe link transmission speed through system self-check after the host computer establishes a connection with the FPGA. For the loading speed measurement, a 4MB test data packet is looped 100 times and loaded into the FPGA. By subtracting the timestamp at the start of loading from the timestamp at the completion of loading, the time consumed is obtained, and the speed can be obtained by dividing 400MB by the time. The reading speed measurement is to initiate 100 4MB data reading requests, and the transmission speed is calculated by a similar method;

[0063] The above-mentioned send accumulation number function refers to the function of sending an accumulation number through an external interface, which is used to detect whether the external link to the device under test is correctly connected, as well as to detect the data reception ability of the device under test, and can also be used to detect whether the link of this system is unobstructed during a loopback test;

[0064] The above-mentioned system reset function refers to resetting this system, including resetting the host computer software and the operating status of the FPGA, which is used to make the system enter the initial working state when the system is powered on and run, and is also used to restore the correct working state when the system works abnormally;

[0065] The above-mentioned debugging interface refers to an interface that will be used in the case of the user's non-typical usage flow and is used for internal debugging of the simulated source system. In the debugging interface, the user can directly view and edit the configuration control register group, and directly monitor and control the working status of the FPGA by parsing the definitions of each item in the register group;

[0066] The said Image Source Database tab provides rich image source management functions. Users can import, export, edit, and delete images here, and the image loading function is also implemented in the current tab. The tab mainly provides user interfaces for image dataset management, image preview, and image loading functions.

[0067] The above-mentioned image dataset management function will automatically retrieve legal image sets in the local image set folder during program operation and automatically load the detected image sets into the database. Users can select an image set using the drop-down list. Users can also click on an image to preview it. Users can also select one or more images to execute the loading function.

[0068] The above-mentioned preview function means that when the user clicks on an image, a thumbnail preview and detailed content of the current image will be displayed in the preview window. The user can also check the image brightness enhancement checkbox to adjust the brightness of the image so as to view the details of the image more clearly during preview.

[0069] The above-mentioned loading function means that when the user selects one or more images, selects the synchronization frame header, and clicks the load button, the system will call the loading function unit to frame the selected images and load them into the external memory of the FPGA. At the same time, the user interface will synchronously display the loading progress.

[0070] The said Send and Receive tab provides a send function and a receive function. The send function refers to performing parallel-to-serial conversion on the already loaded image frame data and sending it to the device under test through an external interface; while the receive function is to receive the return data from the device under test through the external interface and save the data to a file. It is mainly divided into two areas: data sending and data receiving.

[0071] The above-mentioned data sending area will display a list of all images that have been loaded into the external memory of the FPGA and show the size of the occupied cache space. In this area, users can view the sending order, adjust the sending rate, check whether to send all, or select partial sending, and click the send button to start the sending process. The system will display the current sending progress during sending.

[0072] The above-mentioned data receiving area provides buttons to start receiving and end receiving. Users can use these buttons to start and stop receiving data. In addition, the receiving area can also display the receiving progress in real time and allows users to set the save path and file name. The file name will be automatically named according to the system time as "MM-dd_HH-mm-ss.bin". A quick open receive folder button is also provided. After the data reception is completed, users can directly perform basic analysis of the data on the interface.

[0073] The log area records various operations and status changes during the program's operation, facilitating users to track the execution process and troubleshoot problems. Meanwhile, this area also has a filtering function, allowing users to screen log information according to their needs and quickly locate key operation records. The entries in the log record are divided into three parts: time, prompt level, and prompt message. Among them, the time is the time when this log entry is generated, accurate to the second. The prompt level is divided into three types: Error, Warning, and Info according to the degree of importance, used to distinguish different types of information during the operation process, and are distinguished by different color fonts so that users can quickly identify and handle various problems.

[0074] The multiple functional unit modules include a system control functional unit, an image source database management unit, a loading functional unit, a receiving functional unit, and a sending functional unit. Among them,

[0075] The above-mentioned system control unit is responsible for the specific implementation of system status monitoring, link status monitoring, global reset, and initialization.

[0076] The above-mentioned link status monitoring is the detection of the PCIe link between the host computer and the FPGA when the system starts running and the real-time monitoring during the running process. When the system starts running, the host computer will allocate a dedicated memory address for the c2h channel and call the system function to open the xdma_h2c, xdma_c2h, and xdma_user devices. If the devices are correctly opened, it means the link status is normal.

[0077] The above-mentioned system status monitoring refers to judging whether the FPGA logic is correct through the reset_n field of the control register in the configuration control register of the FPGA. If it is 1, it means the system is in the working state; if it is 0, it means the system is in the reset state.

[0078] The above-mentioned global reset and initialization include uniformly resetting the status of the devices at both ends of the host computer and the FPGA to ensure that all unit modules of the system can enter the initial state synchronously. Among them, the initialization of the host computer is, on the one hand, to perform the initial default configuration of the user graphical interface, and on the other hand, to initialize each functional unit. The initialization of the FPGA is to write 0 to the 0th bit of the control register through the xdma_user device, and then write 1 after a delay of 100 us to complete the reset.

[0079] The above-mentioned image source database management unit is responsible for image dataset management and provides functions such as image preview, image information preview, and image enhancement preview.

[0080] The above-mentioned image dataset management function means that when the system is running, it will automatically scan the image_set_dir file, find all legal image sets in all folders, and add them all to the database index.

[0081] The definition of the above-mentioned legal image set is a folder containing image files and description files. The name of the folder should be the same as the name of the image set. There is a description file in JSON format named after the image set under the folder. The description file contains image-related information of all images in the image set.

[0082] The above-mentioned image-related information includes image path, image file name, image name, image width, image height, image bit depth, and the name of the image set where the image is located.

[0083] The above-mentioned image preview-related function means that when the user selects an image from the interface, the system will open the raw image, allocate an appropriate amount of memory space for caching the image according to the image-related information, convert the image to a grayscale image with 8-bit or 16-bit color depth according to the bit depth, then scale it to an appropriate size, and display it using the label control. At the same time, if the image enhancement preview function is enabled, the image will be automatically subjected to adaptive histogram equalization operation, so that the details of some darker images can also be clearly shown.

[0084] The above-mentioned loading function unit will preprocess and load the selected image according to the parameters set by the user, mainly including three functional steps: image data framing, memory address management, and frame loading verification. To avoid affecting the user's graphical interface, the implementation of the loading function unit will be executed in a separate thread.

[0085] The above-mentioned image data framing functional step means adding a frame header and a frame tail to the original raw data of the image according to the protocol regulations, and allocating memory space to store the corresponding frame data for direct use in subsequent loading functional steps.

[0086] The above-mentioned image frame format is defined as consisting of three parts: a frame header, image data, and a frame tail in total for one frame of image. In one embodiment, the frame header is set to 20 bytes, including an 8-byte synchronization header with a fixed value of 4954CE1F066B0000, 2 bytes for image width, 2 bytes for image height, 2 bytes for image bit depth, 4 bytes for the number of bytes occupied by the image, and 2 bytes for frame header verification. The image data occupies N bytes, which is determined by the actual data volume of the image. The frame tail is 2 bytes of data verification, and its calculation method is to accumulate each byte of the image data, and the obtained sum after accumulation.

[0087] The above-mentioned memory address management means allocating the image frame to a specific address in the external SDRAM memory of a specific FPGA to ensure the efficiency and stability of data access. In the loading buffer of the external memory, an 8-byte aligned starting address is automatically allocated, and the size of the space occupied by each frame is recorded. After completing the memory address management, the system will enter the frame loading verification functional step.

[0088] The above frame loading verification function steps mainly involve sending the framed data through the PCIe channel to the FPGA and receiving the status field returned by the FPGA, so as to determine whether the loading process is correctly completed.

[0089] Sending the above data through the PCIe channel to the FPGA mainly divides the frame data into small blocks with a maximum of 4MB, copies each small block into the DMA shared memory, initiates a DMA request, and the DMA controller completes the data transfer. And write the address where the current frame needs to be stored and the current frame size into the address register and size register respectively. During the transfer process, by detecting the load_prog field of the load send status register, the data transfer progress is monitored in real time. After the transfer is completed, change the check_en field of the control register from 0 to 1 to generate a rising edge to enable the verification unit of the FPGA, and then detect the check_result field of the load send status register to check whether the loaded data is correct.

[0090] In one embodiment, the load_prog field and the check_result field of the above load send status register are located in the [9:3] bit field and the [2:0] bit field of this register respectively. Among them, the load_prog field is responsible for indicating the data transfer progress. Using 7 bits, it can represent 0 to 127. By quantifying the send size to 7 bits, the send progress is tracked with an accuracy of 1 / 128. Among them, the check_result field is used to display the data verification result. When bit[2] is 1, it means that a verification is completed. Bits [1:0] are used to represent the verification result: 00, verification is correct; 01, no sync header is detected; 10, frame header verification error; 11, frame tail verification error.

[0091] The above receiving functional unit will determine whether it is in the working state according to whether the user enables the receive enable. If it is in the non-working state, no DMA read data request will be initiated, and the response field of the control register is also set to disabled. In this state, the system will maintain the low-power mode and only maintain the necessary register states. When the user sets the receive enable bit, the system will be activated, and the recv_en field (the 3rd bit of the control register) of the configuration control register changes from 0 to 1 to generate a rising edge. At this time, the FPGA starts to receive data. The host computer parses the status of the current received data in real time by continuously querying the recving field, recv_block_flag field and recv_block_last_bytes field of the receive status register.

[0092] The recving field (bit 30) of the receive status register is used to indicate whether the current FPGA enables reception. If the value is 1, it means reception is enabled; if the value is 0, it means reception is not enabled.

[0093] The recv_block_flag field ([29:22] bits) of the receive status register is used to indicate which receive buffer blocks have been filled. The receive buffer is divided into 8 receive buffer blocks, and each bit of this field corresponds to a block. When the bit is 1, it means the corresponding receive buffer block is full, and the host computer needs to read the corresponding data in time to prevent data loss. At the same time, the order of reading the blocks is from block 0 to block 7 and then looping back to block 0.

[0094] The recv_block_last_bytes field of the receive status register is located at bits [21:0] of the receive status register and is used to represent the size of the data received in the last block buffer, with a range of [0, 4MB). Note that its value cannot be 4MB. If a buffer is full, the corresponding bit of recv_block_flag will be set high, and this value refers to the number of bytes filled in the next block.

[0095] The above-mentioned transmission function unit will, according to the user's operation, write specific values to specific fields of specific registers in the configuration control register group and read specific fields of specific registers to track the transmission process.

[0096] Writing specific values to specific fields of specific registers means that the send_clk field of the configuration control register is set to the transmission frequency selected by the user. In one embodiment, 00: 100MHz (default), 01: 200MHz, 10: 300MHz, 11: 400MHz are defined, and the send_en field is enabled for transmission on the rising edge when it changes from 0 to 1. At the same time, the address register and the size register are set to the data address for this transmission.

[0097] Reading specific fields of specific registers to track the transmission process means reading the send_prog field of the load transmission status register. This field is located at bits [16:10] of the register and uses 7 bits to represent 0 to 127. By quantifying the transmission size to 7 bits, the transmission progress is tracked with an accuracy of 1 / 128, so as to monitor the data transmission status in real time.

[0098] The accesses to the above-mentioned control register, address register, size register, peripheral register, load and transmit status register, and receive status register are all implemented through the xdma_user device, and their addresses are respectively mapped to 0x00000, 0x00008, 0x10000, 0x10008, 0x20000, and 0x20008 of the xmda_user device. Configuring the address register and size register can be achieved by reading and writing 32-bit data at these addresses. Among them, the control register, address register, size register, and peripheral register support both reading and writing, while the load and transmit status register and receive status register only support reading.

[0099] The PCIe high-speed channel provides high-speed transmission capabilities for image data, ensuring that the system can maintain efficient and stable performance when processing a large amount of image data. Through this channel, rapid loading, sending, and receiving of images can be achieved, guaranteeing high efficiency and high reliability of the system during operation.

[0100] The FPGA implementation includes a configuration control register group, an external memory management unit, a verification unit, a transmit clock control unit, a serial-to-parallel conversion unit, a parallel-to-serial conversion unit, and an external SDRAM memory. Among them,

[0101] The configuration control register group contains 6 groups of registers, each register having a 32-bit data width. According to different application requirements, they are divided into 6 registers: control register, address register, size register, peripheral register, load and transmit status register, and receive status register. They are connected to the XDMA core through the AXI4-Lite protocol and mapped to the address 0x40000000 through the PCIe to AXI Transation address mapping. The specific implementation of this register group is achieved using AXIGPIO.

[0102] The external memory management unit is responsible for managing the external SDRAM memory, enabling efficient reading and writing of the SDRAM by the logical end. At the same time, the SDRAM space is divided into a load buffer and a receive buffer block area, which are respectively used to store image data to be sent and received return data. Meanwhile, the external memory management unit also has efficient data processing capabilities, responsible for transmitting data to the host computer, reading data from the host computer, transmitting data to the verification unit, providing data to be sent to the parallel-to-serial conversion unit, and receiving data from the serial-to-parallel conversion unit.

[0103] The verification unit includes functions of frame synchronization header verification, checksum verification, and returning verification results. When a rising edge transition is detected in the check_en field of the control register, the verification will start. The internal state machine of the verification unit enters the verification mode, then reads byte data from the data entry, matches the frame synchronization header one by one, calculates the frame header checksum, calculates the data checksum, and compares with the preset verification value. Once any error is found during the verification process, the verification unit will immediately report the error status to the loading status register, that is, write the corresponding verification value to the check_result field, and at the same time stop the current data transmission.

[0104] The transmission clock control unit uses the PLL module to generate clocks with frequencies including but not limited to 100 MHz, 200 MHz, 300 MHz, and 400 MHz, and selects the clock according to the send_clk field of the control register, and switches the used clock frequency as the working clock of the serial-to-parallel conversion module.

[0105] The serial-to-parallel conversion unit receives the data sent by the external memory management unit, converts the data in the ui_clk clock domain to the tx_clk clock domain through a cross-clock domain asynchronous FIFO, and serially sends it bit by bit. When sending, the low byte of the data is sent first, and the high bit of each byte is sent first. And align the rising edge of the clock, and use the rising edge as the data transmission edge.

[0106] The parallel-to-serial conversion unit receives the serial data of the external interface, combines it into bytes in the rx_clk clock domain, sends it to the asynchronous FIFO, and uses the falling edge as the sampling edge to receive the data. The data stored in the asynchronous FIFO will be synchronized to the ui_clk clock domain, and combined into a 128-bit AXIS data packet in this clock domain for processing by the external memory management unit.

[0107] The external interface refers to a level conversion board that can be connected using FMC, such as an LVDS level conversion board, a TLK2711 level conversion board, and an RS422 level conversion board, etc. By connecting level conversion boards with different interfaces, the communication interface standards of different devices under test can be made compatible.

[0108] The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0109] Embodiment

[0110] As Figure 1 shown, an embodiment of the present invention proposes a spaceborne image data simulation source system for providing test image data for a spaceborne image processing system. Users can use this system to manage the image data set, and can send images to the spaceborne image processing system through the external interface and receive the test of the returned data.

[0111] This system is designed and implemented with a host computer plus FPGA, including: a storage and register module implemented based on FPGA and an analog image processing module deployed on the host computer;

[0112] The storage and register module is used to receive and store the image frame data generated by the image processing module and provide it to the on-board image processing system; it is also used to feedback the return data of the on-board image processing system to the analog image processing module;

[0113] The image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, generate image frame data by framing and transmit it to the FPGA; it is also used to receive the return data from the on-board image processing system transmitted by the FPGA.

[0114] The host computer is connected to the FPGA through a PCIe high-speed channel, and by using a PCIe to Thunderbolt 4 adapter board, the hot pluggability of the FPGA board and the lightweight and portability of the overall system can be achieved.

[0115] The functions implemented by this system are: providing a graphical user interface for convenient user operation; supporting the management of the image source database; selecting multiple images for loading; customizing the sending working conditions and sending image frame data to the on-board image processing system to be tested; receiving the return data from the on-board image processing system; displaying and parsing the received data.

[0116] A typical working process of the present invention is as Figure 2As shown below: The user first powers on the simulated source system, connects the FPGA and the host computer, and opens the host computer software to start the simulated source system. Then the system will perform self-check and initialization. By calling the system control function unit, link detection and board status detection are realized. The image source database management unit will automatically scan the local image set, and at the same time, the logging function is enabled to record the startup status. Subsequently, the user can choose to enable reception or browse the image set at any time. After enabling reception, the system will activate the reception thread and prepare to obtain the return data from the on-orbit image processing system under test. If the user chooses to browse the image set in the image source database tab, the image can be previewed by clicking on a certain image, and multiple images can be selected by holding down the ctrl key. Usually, the user will select images with different bit depths and different pixel sizes for testing according to needs, and then click the load button to start loading the image frame and start the data loading process. If more images need to be loaded, the user can continue to select images and execute the load command. The system provides an intuitive progress bar to display the loading progress of each image. After the loading is completed, the system can configure the sending parameters, such as the sending speed, whether to send continuously, whether to send all, the sending interval, etc. After the configuration is completed, the user can start the sending process. At this time, the FPGA will process the image frame data and achieve high-speed communication with the on-orbit image processing system under test through the external interface. In addition, the system also allows the user to monitor the data transmission status in real time during the sending process to ensure the stability and reliability of the data transmission.

[0117] The flowchart of the host computer of the present invention for implementing the loading function is as Figure 3 shown. The graphical user interface runs in the main thread. When the user clicks the start loading button, the loading thread will be started, and the loading operation will be performed in this thread. In the loading thread, first, the image file to be loaded is opened, the space size occupied by a whole frame is calculated according to the image information, and space is allocated for it. In the allocated space, first, the frame header is added, including the synchronization frame header, the image information header, and the frame header checksum. Then the image data is added. If the image bit depth is greater than 8 bits, it will be stored in 2 bytes. Finally, the frame tail, that is, the image checksum, is added. Then the host computer will initiate a DMA transfer on the h2c channel to send the frame data to the external storage management unit of the FPGA. At the same time, the control register is configured to indicate that a loading has been initiated and the verification has started, and the size register and the address register are configured to describe the size and address of the verification. And the corresponding fields of the load send register are read to refresh the load status and the verification status in real time. If there are still images to be loaded, go back to the beginning to open the image file. If all images have been sent, the loading thread will end.

[0118] The flowchart of the host computer of the present invention for implementing the sending function is as Figure 4As shown. After the user configures the sending parameters through the graphical user interface of the main thread and clicks to send, the sending thread will be started at this time. In the sending thread, the send_en fields of the size register, address register, and control register are configured, and the FPGA starts to execute the sending function from this. When sending, the send_prog field of the load sending register will be read to obtain the sending status, and the status refresh display of the main interface is implemented by the Qt signal and slot mechanism. When the sending is completed, the sending thread ends.

[0119] The flowchart of the host computer of the present invention for implementing the receiving function is as Figure 5 As shown. Enable receiving by clicking the enable receiving button on the main interface, and at the same time start the receiving thread. In the receiving thread, first the recv_en field of the control register is configured, and then the loop body starts. It detects whether the end flag is set. If it has not been set yet, the recv_block_flag field of the receive status register is read. If a receive block is full, a DMA request for the c2h channel will be initiated, and the data of the corresponding block will be read. After the reading is completed, the corresponding bit of the recv_fetch_flag field of the control register is set, and then the block data is written into the file, and then it returns to the loop body to start judging the end flag again. If the end flag is set, it means that the user clicks the end receiving button on the main interface. At this time, the recv_block_last_bytes field of the receive status register will be read to know how much data has been stored in the last block, and a DMA request for the c2h channel will be initiated, and the data of the last block will be written into the file. Thus, the receiving thread is closed and a receiving is completed.

[0120] The definition of the configuration control register group of the present invention is shown in Table 1. It includes 6 32-bit registers, namely the control register, address register, size register, peripheral register, load sending status register, and receive status register.

[0121] Table 1 Definition of the control register group

[0122]

[0123]

[0124] The block diagram of the verification unit in the FPGA design of the present invention is as Figure 6As shown. After receiving the check_en synchronous enable, the functional unit will enter the frame synchronization header verification stage. At this time, the tready signal of the AXIS channel will be pulled high, and the frame data of the AXIS channel will be read through the handshake of the tvalid and tready signals. When the defined synchronization header is detected, it will start to detect the image header, accumulate each byte to obtain the accumulated sum, and compare it with the incoming header accumulated sum. If the comparison is correct, it will accumulate and sum the image data, and finally compare it with the frame tail verification. If both are correct, it indicates that the verification is successful, and the verification result returns 00. Among them, there may be cases where the verification fails. If the synchronization header is not detected, the error code is 01; if the frame header verification fails, the error code is 10; if the frame tail verification fails, the error code is 11.

[0125] The block diagram of the serial-to-parallel conversion unit in the FPGA design of the present invention is as Figure 7 shown. After receiving the send_en synchronous enable, the unit will latch the size and enter the SEND state. First, it performs a bit-width conversion on the 128-bit wide frame data, then converts it to the tx_clk clock domain, and seamlessly reads it through two 8-bit wide registers, tx_buf_0 and tx_buf_1, and then outputs the serial-to-parallel conversion. Among them, tx_buf_0 and tx_buf_1 implement the ping-pong operation to ensure the continuity and efficiency of data transmission. When the number of sent bytes reaches the count, it will stop sending and generate a done signal to notify the FPGA that the sending is complete.

[0126] The block diagram of the parallel-to-serial conversion unit in the FPGA design of the present invention is as Figure 8 shown. After receiving the recv_en synchronous enable, it will start to perform parallel processing on the serially input data. In the rx_clk clock domain, it converts the serial single-bit data into byte data, combines the bit-width into 128-bit AXIS data, and reasonably gives corresponding auxiliary signals such as tkeep and tlast to ensure the validity of the data and the integrity of the transmission.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A spaceborne image data simulation source system for providing test image data for a spaceborne image processing system, characterized in that, including: including a storage and register module implemented based on FPGA and an analog image processing module deployed on the host computer; wherein, the storage and register module is used to receive and store the image frame data generated by the image processing module and provide it to the on-board image processing system; it is also used to feedback the return data of the on-board image processing system to the analog image processing module; the image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, generate image frame data by framing and transmit it to the FPGA; it is also used to receive the return data from the on-board image processing system transmitted through the FPGA; the image processing module includes: a system control function unit, an image source database management unit, a loading function unit, a sending function unit and a receiving function unit, wherein, the system control function unit is used to monitor the system state by obtaining the system state field of the control register of the FPGA, monitor the link state by obtaining the link state information of the PCIe high-speed channel, and is also used to perform unified reset and initialization on the image processing module and the FPGA; the image source database management unit is used to index and call the local image set, realize image preview according to the image size information and bit depth information, and is also used to perform image enhancement; the loading function unit is used to realize image data framing, memory management and frame loading verification according to the user loading instruction, and send the processed image frame to the FPGA; the sending function unit is used to configure the sending instruction and sending parameters to the FPGA according to the user sending instruction; the receiving function unit is used to receive the data returned by the FPGA according to the user receiving instruction, store and display it.

2. The on-board image data simulation source system according to claim 1, wherein Communication between the FPGA and the host computer is carried out through a PCIe high-speed channel, and a PCIe to Thunderbolt 4 adapter board is used.

3. The on-board image data simulation source system according to claim 1, characterized in that, the storage and register module includes: a configuration control register group, a verification unit, an external memory management unit, a sending clock control unit, a serial-to-parallel conversion unit and a parallel-to-serial conversion unit; wherein, the configuration control register group is used to realize the function of the host computer controlling the FPGA and the FPGA returning the working state to the host computer, including a control register, an address register, a size register, a peripheral register, a loading and sending status register and a receiving status register; the verification unit is used to verify the integrity and correctness of the data during the loading process, start working through a specific field of the control register, perform sync header verification, instruction verification and data verification on the input data, and store the verification result in a specific field of the receiving status register; the external memory management unit is used to realize the efficient reading and writing of the external SDRAM memory, provide an SRAM memory reading and writing interface to other modules, and realize writing specified-size data from the logical area to the specified address of the memory and reading specified-size data from the specified address of the memory to the logical area through the control of the control register, address register and size register; the sending clock control unit is used to generate and select a clock with a corresponding frequency as the sending clock according to a specific field of the control register; The parallel-to-serial conversion unit is used to receive data from the external memory management unit, and convert the parallel data into serial data using the transmission clock selected by the transmission clock control unit, and output the serial data to the external interface of the FPGA board; The serial-to-parallel conversion unit is used to convert the serial data received by the external interface of the FPGA board into parallel data according to the enable flag bit of the control register, and transmit the parallel data to the external memory management unit in units of bytes.

4. The on-board image data simulation source system according to claim 3, characterized in that The control register, address register, size register, and peripheral register support read and write operations, and the load transmission status register and receive status register only support read operations.

5. The on-orbit image data simulation source system according to claim 1, wherein The processing of the load function unit includes: Step 1) Start the loading thread; Step 2) Parse the user loading instruction and open the image to be loaded; Step 3) Allocate frame space according to the image information and frame format, add the frame header, image data, and frame tail in sequence, frame the image data to be loaded, and use memory management to allocate memory addresses. Transmit the image frame data to the external SDRAM memory of the FPGA through the DMA of the h2c channel; Step 4) Configure the control register, size register, and address register of the FPGA; Step 5) Verify the image frame and synchronously feedback the verification result to the graphical user interface; Go to Step 2) until all images to be loaded are transmitted, and end the loading thread.

6. The on-board image data simulation source system according to claim 5, wherein The frame header in the frame format includes: an 8-byte sync header, 2 bytes of image width, 2 bytes of image height, 2 bytes of image bit depth, 4 bytes of image occupied bytes, and 2 bytes of frame header checksum; The number of bytes occupied by the image data is determined by the actual amount of image data; The frame tail is 2 bytes of data checksum, and its calculation method is to accumulate each byte of the image data, and the accumulated sum is obtained after the accumulation is completed.

7. The on-board image data simulation source system according to claim 1, wherein The processing process of the receive function unit includes: Step 1) Start the receive thread; Step 2) Configure the control register; Step 3) Detect whether the end flag is set. If it is set, go to Step 5); if it is not set, read the receive status register; judge whether the receive block is full. If the judgment is no, go to Step 3), otherwise, go to Step 4); Step 4) Initiate a DMA request for the c2h channel, read the data of the corresponding block, after the reading is completed, set the corresponding bit of the control register, write the block data into the file, and go to Step 3); Step 5) Read the receive status register, obtain the amount of data that has been stored in the last block, initiate a DMA request for the c2h channel, write the data of the last block into the file, close the receive thread, and complete one receive.

8. The on-board image data simulation source system according to claim 1, characterized in that The graphical user interface includes: The system control area is used to implement the start, stop, and status monitoring operations of the system, provide a debugging function entry, and implement the direct read and write of the configuration control register group; The image source database tab is used to configure and manage various types of image source data, provide real-time image preview and parameter adjustment, provide the configuration parameter interface of the image loading function, and provide the image loading function interface; The send and receive function tab is used to browse the list of loaded images, provide a send parameter configuration interface, a send function entry, a send status display, and provide a receive function entry, a receive status display, and a quick view of received files; and The log area is used to display detailed log information during the system operation and implement the function of saving and recording log files.

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