Pixel circuit and display device

Abstract

The invention relates to a pixel circuit and a display device. The pixel circuit includes: a light emitting element including an anode terminal; a first transistor supplying a driving current to the light emitting element, the first transistor including a gate terminal, a first terminal, and a second terminal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor providing a data voltage to the gate terminal of the first transistor in response to a write gate signal; and a third transistor connecting the second terminal of the first transistor and the anode terminal of the light emitting element in response to a first emission signal.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines and pixel circuits. The display panel driver includes a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, and a drive controller for controlling the gate driver and the data driver.

[0003] Recently, display devices for providing virtual reality ("VR") or augmented reality ("AR") have come to the fore. Therefore, a small area and a high pixel per inch ("PPI") are required in the display device. Summary of the invention

[0004] Since the pitch occupied by the pixel circuit is reduced to a small area and a high pixel per inch ("PPI"), there may be a limit on the number of transistors constituting the pixel circuit and the signal applied to the pixel circuit. In addition, as the PPI increases, the data range of the data voltage may decrease. That is, as the PPI increases, the brightness accuracy according to the change of the data voltage may be relatively reduced.

[0005] Embodiments of the inventive concept provide a pixel circuit for a relatively small area and a relatively high PPI.

[0006] Embodiments of the inventive concept provide a display device including a pixel circuit.

[0007] In an embodiment of a pixel circuit conceived according to the present invention, the pixel circuit includes: a light-emitting element including an anode terminal; a first transistor providing a driving current to the light-emitting element, the first transistor including a gate terminal, a first terminal, and a second terminal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor providing a data voltage to the gate terminal of the first transistor in response to a write gate signal; and a third transistor connecting the second terminal of the first transistor and the anode terminal of the light-emitting element in response to a first emission signal.

[0008] In an embodiment, the pixel circuit may further include a fourth transistor providing a first power supply voltage to the first terminal of the first transistor in response to a second emission signal.

[0009] In an embodiment, the pixel circuit may further include a fifth transistor providing a bias voltage to the anode terminal of the light emitting element in response to an initialization gate signal.

[0010] In an embodiment, in a first period, the second emission signal, the write gate signal, and the initialization gate signal may have active levels, and the first emission signal may have an inactive level.

[0011] In an embodiment, in the first period, the second transistor may provide the data voltage to the gate terminal of the first transistor, the first terminal of the first transistor may be initialized to the first power supply voltage, and the second terminal of the first transistor may be initialized to the bias voltage.

[0012] In an embodiment, in a second period after the first period, the write gate signal and the initialization gate signal may have the active level, and the first emission signal and the second emission signal may have the inactive level.

[0013] In an embodiment, in the second period, when the fourth transistor is turned off, the first capacitor stores a threshold voltage of the first transistor.

[0014] In an embodiment, in a third period after the second period, the second emission signal, the write gate signal, and the initialization gate signal may have the active level, and the first emission signal may have the inactive level.

[0015] In an embodiment, during the third period, the first capacitor may maintain a threshold voltage of the first transistor.

[0016] In an embodiment, in the first period to the third period, the third transistor may be turned off so that the second terminal of the first transistor and the anode terminal of the light emitting element may be disconnected from each other.

[0017] In an embodiment, in a fourth period after the third period, the first emission signal and the second emission signal may have the active level, and the write gate signal and the initialization gate signal may have the inactive level.

[0018] In an embodiment, in the fourth period, a voltage of the gate terminal of the first transistor may be divided by the first capacitor and the second capacitor.

[0019] In an embodiment, in the fourth period, the third transistor may be turned on so that the third transistor connects the second terminal of the first transistor and the anode terminal of the light emitting element.

[0020] In an embodiment, the first transistor may include: the gate terminal connected to the first node, the first terminal connected to the second node, and the second terminal connected to the third node; the first capacitor may include: the first terminal connected to the second node and the second terminal connected to the first node; the second capacitor may include: the first terminal connected to the first node and the second terminal connected to the third node; the second transistor may include: a gate terminal receiving the write gate signal, a first terminal connected to the data line, and a second terminal connected to the first node; the third transistor may include: a gate terminal receiving the first emission signal, a first terminal connected to the third node, and a second terminal connected to the anode terminal of the light emitting element; the fourth transistor may include: a gate terminal receiving the second emission signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; the fifth transistor may include: a gate terminal receiving the initialization gate signal, a first terminal connected to the third node, and a second terminal connected to the line transmitting the bias voltage; and the light emitting element may include the anode terminal connected to the second terminal of the third transistor and a cathode terminal connected to the line transmitting the second power supply voltage.

[0021] In an embodiment, a back gate terminal of the first transistor may be connected to the first terminal of the first transistor.

[0022] In an embodiment, back gate terminals of the first to fifth transistors may receive the first power supply voltage.

[0023] In an embodiment, the first to fifth transistors may be P-type transistors.

[0024] In an embodiment of a display device according to the concept of the present invention, the display device includes: a display panel including a pixel circuit, a data driver providing a data voltage to the pixel circuit, a gate driver providing a write gate signal to the pixel circuit, an emission driver providing a first emission signal to the pixel circuit, and a drive controller controlling the data driver, the gate driver, and the emission driver. The pixel circuit includes: a light-emitting element including an anode terminal; a first transistor providing a driving current to the light-emitting element, the first transistor including a gate terminal, a first terminal, and a second terminal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor providing a data voltage to the gate terminal of the first transistor in response to the write gate signal; and a third transistor connecting the second terminal of the first transistor and the anode terminal of the light-emitting element in response to the first emission signal.

[0025] In an embodiment, the emission driver may further provide a second emission signal to the pixel circuit, and the pixel circuit further includes a fourth transistor providing a first power supply voltage to the first terminal of the first transistor in response to the second emission signal.

[0026] In an embodiment, the gate driver may further provide an initialization gate signal to the pixel circuit, and the pixel circuit may further include a fifth transistor that provides a bias voltage to the anode terminal of the light emitting element in response to the initialization gate signal.

[0027] In an embodiment of a display panel and a display device including a pixel circuit, the pixel circuit may include a first capacitor so that the pixel circuit can compensate for the threshold voltage of the first transistor. In the first period to the third period, the third transistor may be turned off, so that the degradation of the light-emitting element can be prevented, and the brightness accuracy according to the data voltage can be improved. The pixel circuit may include a second capacitor so that the data range of the data voltage can be extended by the voltage distribution of the first capacitor and the second capacitor, and the threshold voltage of the first transistor can be additionally compensated. The pixel circuit may connect the back gate terminal of the first transistor to the first terminal of the first transistor, or may provide a first power supply voltage to the back gate terminal of the first transistor, so that the body effect with respect to the first transistor can be minimized, and the threshold voltage compensation capability of the pixel circuit can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the embodiments of the present inventive concept will become more apparent by describing in detail the embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram showing an embodiment of a display device according to the inventive concept;

[0030] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of a pixel circuit;

[0031] Figure 3 It is shown Figure 1 A circuit diagram of an embodiment of a pixel circuit;

[0032] Figure 4 Is shown driving Figure 2 A timing diagram of an embodiment of a pixel circuit;

[0033] Figure 5 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a first cycle;

[0034] Figure 6 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a first cycle;

[0035] Figure 7 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a second cycle;

[0036] Figure 8 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a second cycle;

[0037] Fig. 9 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a third cycle;

[0038] Fig.10 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a third cycle;

[0039] Fig.11 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a fourth cycle;

[0040] Fig.12 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a fourth cycle;

[0041] Fig.13 is a block diagram showing an electronic device; and

[0042] Fig.14 It is shown Fig.13 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a virtual reality (“VR”) device. DETAILED DESCRIPTION

[0043] Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or intervening elements may exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0045] It will be understood that, although the terms "first", "second", and "third", etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this article, the "first element", "component", "region", "layer", or "part" discussed below may be referred to as a second element, component, region, layer, or part.

[0046] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms of "one", "one (kind / person)" and "the (the)" are intended to include plural forms, including "at least one (person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms "include" and / or "comprise" or "contain" and / or "have" illustrate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device is turned over in one of the accompanying drawings, the element described as being on the "lower" side of another element will then be positioned as being on the "upper" side of the other element. Therefore, depending on the specific orientation of the accompanying drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one of the accompanying drawings, the element described as being "below" or "below" other elements will then be positioned as being "above" other elements. Therefore, the exemplary terms "below..." or "below..." can cover both upper and lower orientations.

[0048] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and the terms will not be interpreted in an idealized or overly formalized sense.

[0050] Figure 1 is a block diagram illustrating an embodiment of a display device according to the inventive concept.

[0051] Reference Figure 1 The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0052] For example, in an embodiment, the driving controller 200 and the data driver 500 may be integral with each other. For example, in an embodiment, the driving controller 200, the gamma reference voltage generator 400 and the data driver 500 may be integral with each other. In an embodiment, for example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400 and the data driver 500 may be integral with each other. In an embodiment, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500 and the emission driver 600 may be integral with each other. A driving module in which at least the driving controller 200 and the data driver 500 are integral may also be referred to as a timing controller embedded data driver ("TED").

[0053] The display panel 100 may include a display area displaying an image and a peripheral area disposed adjacent to the display area.

[0054] In an embodiment, for example, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. In another embodiment, the display panel 100 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. In another embodiment, the display panel 100 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter. In another embodiment, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer.

[0055] The display panel 100 may include gate lines GL, data lines DL, emission lines EML, and pixel circuits P electrically connected to the gate lines GL, data lines DL, and emission lines EML. The gate lines GL may extend in a first direction, the data lines DL may extend in a second direction crossing the first direction, and the emission lines EML may extend in the first direction.

[0056] The drive controller 200 may receive input image data IMG and an input control signal CONT from an external device (not shown). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may also include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. However, the present disclosure is not limited thereto, and the input image data IMG may also include other various color data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0057] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0058] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0059] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0060] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0061] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0062] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the emission driver 600 .

[0063] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL.

[0064] In an embodiment, the gate driver 300 may be integrated on a peripheral area of ​​the display panel 100 .

[0065] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The reference voltage VGREF may have a value corresponding to each data signal DATA.

[0066] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0067] The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog type data voltage through the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

[0068] The emission driver 600 may generate an emission signal for driving the emission lines EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission lines EML.

[0069] In an embodiment, the emission driver 600 may be integrated into a peripheral area of ​​the display panel 100. In an embodiment, the emission driver 600 may be disposed (eg, mounted) on a peripheral area of ​​the display panel 100.

[0070] exist Figure 1 For ease of description, the gate driver 300 may be disposed on a first side (eg, Figure 1 ), and the emission driver 600 may be disposed on a second side of the display panel 100 (eg, Figure 1 100). However, the present disclosure is not limited thereto. In an embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on a first side of the display panel 100. For example, in an embodiment, both the gate driver 300 and the emission driver 600 may be disposed on each of opposite sides of the display panel 100. For example, in an embodiment, the gate driver 300 and the emission driver 600 may be integral with each other.

[0071] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of a pixel circuit. Figure 3 It is shown Figure 1 A circuit diagram of an embodiment of a pixel circuit.

[0072] Reference Figures 1 to 3 , the pixel circuit P may include a light emitting element EL, a first transistor T1, a first capacitor C1, a second capacitor C2, a second transistor T2 and a third transistor T3.

[0073] The first transistor T1 may provide a driving current to the light emitting element EL. The first capacitor C1 may include a first terminal connected to the first terminal of the first transistor T1 and a second terminal connected to the gate terminal of the first transistor T1. The second capacitor C2 may include a first terminal connected to the gate terminal of the first transistor T1 and a second terminal connected to the second terminal of the first transistor T1. The second transistor T2 may provide a data voltage VDATA to the gate terminal of the first transistor T1 in response to the write gate signal GW. The third transistor T3 may connect the second terminal of the first transistor T1 and the anode terminal of the light emitting element EL in response to the first emission signal EM1. In an embodiment, the pixel circuit P may further include a fourth transistor T4 that provides a first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to the second emission signal EM2. In an embodiment, the pixel circuit P may further include a fifth transistor T5 that provides a bias voltage VBIAS to the anode terminal of the light emitting element EL in response to the initialization gate signal GI.

[0074] For example, in an embodiment, the first transistor T1 may include a gate terminal connected to the first node N1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first capacitor C1 may include a first terminal connected to the second node N2 and a second terminal connected to the first node N1. The second capacitor C2 may include a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The second transistor T2 may include a gate terminal receiving a write gate signal GW, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The third transistor T3 may include a gate terminal receiving a first emission signal EM1, a first terminal connected to the third node N3, and a second terminal connected to the anode terminal of the light emitting element EL. The fourth transistor T4 may include a gate terminal receiving a second emission signal EM2, a first terminal connected to a line transmitting a first power supply voltage ELVDD, and a second terminal connected to the second node N2. The fifth transistor T5 may include a gate terminal receiving an initialization gate signal GI, a first terminal connected to the third node N3, and a second terminal connected to a line transmitting a bias voltage VBIAS. The light emitting element EL may include an anode terminal connected to the second terminal of the third transistor T3 and a cathode terminal connected to a line transmitting a second power supply voltage ELVSS.

[0075] In an embodiment, the first terminal of the first transistor T1 to the fifth transistor T5 may be a source terminal, and the second terminal of the first transistor T1 to the fifth transistor T5 may be a drain terminal. However, the present disclosure is not limited thereto, and based on the type of the first transistor T1 to the fifth transistor T5, the first terminal of the first transistor T1 to the fifth transistor T5 may be a drain terminal, and the second terminal of the first transistor T1 to the fifth transistor T5 may be a source terminal.

[0076] When a reverse bias is formed at the first terminal (i.e., source terminal) of the first transistor T1 and the back gate terminal of the first transistor T1, a body effect that changes the threshold voltage of the first transistor T1 may occur. As the body effect with respect to the first transistor T1 is minimized, the threshold voltage compensation capability of the pixel circuit P can be improved.

[0077] like Figure 2 As shown in , in an embodiment, the back gate terminal of the first transistor T1 may be connected to the first terminal of the first transistor T1. Therefore, since the voltage difference between the back gate terminal of the first transistor T1 and the first terminal of the first transistor T1 becomes 0, the body effect on the first transistor T1 may be minimized.

[0078] like Figure 3 As shown in , in an embodiment, the back gate terminal of the first transistor T1 can receive the first power supply voltage ELVDD. When the second emission signal EM2 has an effective level, the voltage of the back gate terminal of the first transistor T1 and the voltage of the first terminal of the first transistor T1 can become equal to the first power supply voltage ELVDD. Therefore, the body effect can be minimized.

[0079] In an embodiment, back gate terminals of the second to fifth transistors T2 to T5 may receive the first power supply voltage ELVDD.

[0080] In an embodiment, the first transistor T1 to the fifth transistor T5 may be a P-type transistor. For example, in an embodiment, the first transistor T1 to the fifth transistor T5 may be a low temperature polysilicon ("LTPS") thin film transistor, etc. In this case, a relatively low voltage level may be an effective level, and a relatively high voltage level may be an ineffective level. For example, in an embodiment, when a signal applied to the gate terminal of the P-type transistor has a relatively low voltage level, the P-type transistor may be turned on. For example, in an embodiment, when a signal applied to the gate terminal of the P-type transistor has a relatively high voltage level, the P-type transistor may be turned off.

[0081] However, the inventive concept is not limited thereto. In an embodiment, the first transistor T1 to the fifth transistor T5 may be an N-type transistor. In an embodiment, for example, the first transistor T1 to the fifth transistor T5 may be an oxide thin film transistor. In this case, a relatively high voltage level may be an effective level, and a relatively low voltage level may be an ineffective level. For example, in an embodiment, when a signal applied to a gate terminal of the N-type transistor has a relatively high voltage level, the N-type transistor may be turned on. For example, in an embodiment, when a signal applied to a gate terminal of the N-type transistor has a relatively low voltage level, the N-type transistor may be turned off.

[0082] Figure 4 Is shown driving Figure 2 A timing diagram of an embodiment of a pixel circuit.

[0083] Reference Figures 1 to 4 , in the first period P1, the second emission signal EM2, the write gate signal GW, and the initialization gate signal GI may have active levels, and the first emission signal EM1 may have an inactive level.

[0084] In the second period P2 after the first period P1, the write gate signal GW and the initialization gate signal GI may have active levels, and the second emission signal EM2 and the first emission signal EM1 may have inactive levels.

[0085] In a third period P3 after the second period P2, the second emission signal EM2, the write gate signal GW, the initialization gate signal GI may have an active level, and the first emission signal EM1 may have an inactive level.

[0086] In a fourth period P4 after the third period P3 , the second emission signal EM2 and the first emission signal EM1 may have active levels, and the write gate signal GW and the initialization gate signal GI may have inactive levels.

[0087] Figure 5 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a first cycle. Figure 6 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a first period.

[0088] Reference Figures 1 to 6 , in the first period P1, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be turned on, and the third transistor T3 may be turned off.

[0089] The second transistor T2 may provide the data voltage VDATA to the first node N1 (ie, the gate terminal of the first transistor T1 ).

[0090] A path may be formed by the fourth transistor T4, the first transistor T1, and the fifth transistor T5. The first terminal of the first transistor T1 may be initialized by the path. The anode terminal of the light emitting element EL may be initialized by the path. For example, in an embodiment, the second node N2 (i.e., the first terminal of the first transistor T1) may be initialized to the first power supply voltage ELVDD. For example, in an embodiment, the third node N3 (i.e., the second terminal of the first transistor T1) may be initialized to the bias voltage VBIAS.

[0091] Since the anode terminal of the light emitting element EL is initialized to the bias voltage VBIAS, light emission of the light emitting element EL due to leakage current in the pixel circuit P displaying black can be minimized.

[0092] Figure 7 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a second cycle. Figure 8 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a second period.

[0093] Reference Figures 1 to 8 , in the second period P2, the second transistor T2 and the fifth transistor T5 may be turned on, and the third transistor T3 and the fourth transistor T4 may be turned off.

[0094] Since the second transistor T2 provides the data voltage VDATA to the first node N1 and the fourth transistor T4 is turned off, the voltage of the first node N1 may be the data voltage VDATA, and the voltage of the second node N2 may be VDATA+VTH. Here, VDATA represents the data voltage, and VTH represents the threshold voltage of the first transistor T1. The first capacitor C1 may store the threshold voltage of the first transistor T1. Therefore, the threshold voltage of the first transistor T1 may be compensated.

[0095] Fig. 9 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a third cycle. Fig.10 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a third period.

[0096] Reference Figures 1 to 10 , in the third period P3, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be turned on, and the third transistor T3 may be turned off.

[0097] In the third period P3, the first capacitor C1 may maintain the threshold voltage of the first transistor T1 stored in the second period P2. Therefore, the threshold voltage of the first transistor T1 may be continuously compensated.

[0098] The voltage of the first node N1 may be determined based on the data voltage VDATA, the driving current of the first transistor T1 may be determined based on the voltage of the first node N1, and the light emitting element EL may emit light with brightness corresponding to the driving current of the first transistor T1.

[0099] Fig.11 It is shown Figure 2 A timing diagram of an embodiment of a pixel circuit operating in a fourth cycle.

[0100] Fig.12 It is shown Figure 2 A circuit diagram of an embodiment of a pixel circuit operating in a fourth cycle.

[0101] Reference Figures 1 to 12 , in the fourth period P4, the third transistor T3 and the fourth transistor T4 may be turned on, and the second transistor T2 and the fifth transistor T5 may be turned off.

[0102] Since the voltage of the second node N2 is the first power supply voltage ELVDD and the fifth transistor T5 is turned off, the voltage of the first node N1 (i.e., the voltage of the gate terminal of the first transistor T1) can be divided by the first capacitor C1 and the second capacitor C2. Therefore, the voltage of the first node N1 can be VDATA+(ELVDD-(VDATA+VTH)×(C_C1) / (C_C1+C_C2)). Since the VDATA component of the voltage of the first node N1 is VDATA×(C_C1) / (C_C1+C_C2), and (C_C1) / (C_C1+C_C2) is less than 1, the data range of the data voltage VDATA can be expanded. Here, ELVDD represents the first power supply voltage, VDATA represents the data voltage, VTH represents the threshold voltage of the first transistor T1, C_C1 represents the capacitance of the first capacitor C1, and C_C2 represents the capacitance of the second capacitor C2.

[0103] When the light emitting element EL deteriorates, the voltage of the anode terminal may change. When the voltage of the anode terminal changes, the voltage of the first node N1 may change. When the voltage of the first node N1 changes, the driving current of the first transistor T1 may change. Therefore, the brightness accuracy according to the data voltage VDATA may be reduced.

[0104] In the first period P1 to the third period P3, the third transistor T3 may be turned off so that the second terminal of the first transistor T1 and the anode terminal of the light emitting element EL may not be connected to each other. That is, the anode terminal of the light emitting element EL may be in a floating state, and degradation of the light emitting element EL may be prevented. Therefore, the brightness accuracy according to the data voltage VDATA may be increased.

[0105] In addition, the pixel circuits P may include first transistors T1, respectively, and the threshold voltage of each of the first transistors T1 may be different according to the characteristics of each of the first transistors T1. Therefore, although the same data voltage VDATA is applied to each of the pixel circuits P, the brightness according to the data voltage VDATA may be different for each of the pixel circuits P.

[0106] Since the light emitting element EL emits light in the fourth period P4, the voltage of the third node N3 may vary. The degree of the voltage variation of the third node N3 may vary according to the threshold voltage of each of the first transistors T1.

[0107] When the voltage of the third node N3 changes, due to the voltage distribution of the first capacitor C1 and the second capacitor C2, the voltage of the first node N1 may be VN1+(VN3'-VN3)×C_C2 / (C_C1+C_C2). That is, the voltage of the first node N1 may be VDATA+(ELVDD-(VDATA+VTH)×(C_C1) / (C_C1+C_C2))+VN1+(VN3'-VN3)×C_C2 / (C_C1+C_C2). At the voltage of the first node N1, the component related to VTH may be -VTH×(C_C1) / (C_C1+C_C2)+(VN3'-VN3)×C_C2 / (C_C1+C_C2). Therefore, although the threshold voltage of each of the first transistors T1 is different according to the characteristics of each of the first transistors T1, -VTH×(C_C1) / (C_C1+C_C2) and (VN3′-VN3)×C_C2 / (C_C1+C_C2) can offset each other. Therefore, the pixel circuit P can include a second capacitor C2 so that the threshold voltage of the first transistor T1 can be additionally compensated. Wherein, VN1 represents the voltage of the first node N1, VN3 represents the voltage before the third node N3 changes, and VN3′ represents the voltage after the third node N3 changes.

[0108] Therefore, the pixel circuit P may include a first capacitor C1 so that the pixel circuit P may compensate for the threshold voltage of the first transistor T1. In the first period P1 to the third period P3, the third transistor T3 may be turned off so that the degradation of the light emitting element EL may be prevented and the brightness accuracy according to the data voltage VDATA may be improved. The pixel circuit P may include a second capacitor C2 so that the data range of the data voltage VDATA may be expanded by the voltage distribution of the first capacitor C1 and the second capacitor C2 and the threshold voltage of the first transistor T1 may be additionally compensated. The pixel circuit P may connect the back gate terminal of the first transistor T1 to the first terminal of the first transistor or provide the first power supply voltage ELVDD to the back gate terminal of the first transistor T1 so that the body effect with respect to the first transistor T1 may be minimized and the threshold voltage compensation capability of the pixel circuit P may be improved.

[0109] Fig.13 is a block diagram illustrating an electronic device. Fig.14 It is shown Fig.13 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a virtual reality (“VR”) device.

[0110] Reference Figure 13 to Figure 14 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output ("I / O") device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 In addition, the electronic device 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic devices, or the like.

[0111] In an embodiment, Fig.14 As shown in , the electronic device 1000 can be implemented as a VR device. However, the electronic device 1000 is not limited thereto. In an embodiment, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a notebook computer, or a head-mounted (e.g., head-mounted) display ("HMD") device, etc.

[0112] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit ("CPU"), an application processor ("AP"), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, or a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus.

[0113] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, or a ferroelectric random access memory ("FRAM") device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, or a mobile DRAM device, etc.).

[0114] The storage device 1030 may include a solid state drive ("SSD") device, a hard disk drive ("HDD") device, a compact disk read only memory ("CD-ROM") device, and the like.

[0115] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, or a touch screen, and output devices such as a printer or a speaker. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0116] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0117] The display device 1060 may be connected to other components via a bus or other communication links.

[0118] The inventive concept can be applied to any display device and any electronic device including a touch panel. In an embodiment, for example, the inventive concept can be applied to a mobile phone, a smart phone, a digital television ("TV"), a three-dimensional ("3D") television, a personal computer ("PC") (e.g., a tablet computer or a notebook computer), a home appliance, a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), a digital camera, a music player, a portable game console, and a navigation device, etc.

[0119] The foregoing illustrates the inventive concept and is not to be construed as limiting the inventive concept. Although several embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that, in essence, many modifications are possible in the embodiments without departing from the novel teachings and advantages of the inventive concept. Therefore, all these modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device-plus-function clause is intended to cover structures described herein as performing stated functions, and not only structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing illustrates the inventive concept and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and the equivalents of the claims are included in the inventive concept.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a light emitting element including an anode terminal; a first transistor, providing a driving current to the light emitting element, the first transistor comprising a gate terminal, a first terminal, and a second terminal; a first capacitor comprising a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor comprising a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor that provides a data voltage to the gate terminal of the first transistor in response to a write gate signal; and A third transistor connects the second terminal of the first transistor and the anode terminal of the light emitting element in response to a first emission signal.

2. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: The fourth transistor, The fourth transistor provides a first power supply voltage to the first terminal of the first transistor in response to a second emission signal.

3. The pixel circuit according to claim 2, wherein: The pixel circuit further includes: The fifth transistor, The fifth transistor provides a bias voltage to the anode terminal of the light emitting element in response to an initialization gate signal.

4. The pixel circuit according to claim 3, wherein: In a first period, the second emission signal, the write gate signal, and the initialization gate signal have active levels, and the first emission signal has an inactive level.

5. The pixel circuit according to claim 4, wherein: In the first period, the second transistor provides the data voltage to the gate terminal of the first transistor, the first terminal of the first transistor is initialized to the first power supply voltage, and the second terminal of the first transistor is initialized to the bias voltage.

6. The pixel circuit according to claim 4, wherein: In a second period after the first period, the write gate signal and the initialization gate signal have the active level, and the first emission signal and the second emission signal have the inactive level.

7. The pixel circuit according to claim 6, wherein: In the second period, when the fourth transistor is turned off, the first capacitor stores a threshold voltage of the first transistor.

8. The pixel circuit according to claim 6, wherein: In a third period after the second period, the second emission signal, the write gate signal, and the initialization gate signal have the active level, and the first emission signal has the inactive level.

9. The pixel circuit according to claim 8, wherein: In the third period, the first capacitor maintains a threshold voltage of the first transistor.

10. The pixel circuit according to claim 8, wherein: In the first period to the third period, the third transistor is turned off so that the second terminal of the first transistor and the anode terminal of the light emitting element are not connected to each other.

11. The pixel circuit according to claim 8, wherein: In a fourth period after the third period, the first emission signal and the second emission signal have the active level, and the write gate signal and the initialization gate signal have the inactive level.

12. The pixel circuit according to claim 11, wherein: In the fourth period, the voltage of the gate terminal of the first transistor is divided by the first capacitor and the second capacitor.

13. The pixel circuit according to claim 11, wherein: In the fourth period, the third transistor is turned on so that the third transistor connects the second terminal of the first transistor and the anode terminal of the light emitting element.

14. The pixel circuit according to claim 3, wherein: the gate terminal of the first transistor is connected to a first node, the first terminal of the first transistor is connected to a second node, and the second terminal of the first transistor is connected to a third node; the first terminal of the first capacitor is connected to the second node, and the second terminal of the first capacitor is connected to the first node; the first terminal of the second capacitor is connected to the first node, and the second terminal of the second capacitor is connected to the third node; The second transistor includes a gate terminal receiving the write gate signal, a first terminal connected to the data line, and a second terminal connected to the first node; The third transistor includes a gate terminal receiving the first emission signal, a first terminal connected to the third node, and a second terminal connected to the anode terminal of the light emitting element; the fourth transistor includes a gate terminal receiving the second transmission signal, a first terminal connected to a line transmitting the first power supply voltage, and a second terminal connected to the second node; The fifth transistor includes a gate terminal receiving the initialization gate signal, a first terminal connected to the third node, and a second terminal connected to a line transmitting the bias voltage; as well as The anode terminal of the light emitting element is connected to the second terminal of the third transistor, and the light emitting element further includes a cathode terminal connected to a line transmitting a second power supply voltage.

15. The pixel circuit according to claim 3, wherein: A back gate terminal of the first transistor is connected to the first terminal of the first transistor.

16. The pixel circuit according to claim 3, wherein: Back gate terminals of the first to fifth transistors receive the first power supply voltage.

17. The pixel circuit according to claim 3, wherein: The first to fifth transistors are P-type transistors.

18. A display device, wherein: The display device comprises: The display panel includes a pixel circuit, wherein the pixel circuit includes: a light emitting element including an anode terminal; a first transistor, providing a driving current to the light emitting element, the first transistor comprising a gate terminal, a first terminal, and a second terminal; a first capacitor comprising a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor comprising a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor that provides a data voltage to the gate terminal of the first transistor in response to a write gate signal; and a third transistor connecting the second terminal of the first transistor and the anode terminal of the light emitting element in response to a first emission signal; A data driver, providing the data voltage to the pixel circuit; A gate driver, providing the write gate signal to the pixel circuit; an emission driver, providing the first emission signal to the pixel circuit; and A driving controller controls the data driver, the gate driver and the emission driver.

19. The display device according to claim 18, wherein: The emission driver also provides a second emission signal to the pixel circuit, and The pixel circuit also includes a fourth transistor that provides a first power supply voltage to the first terminal of the first transistor in response to the second emission signal.

20. The display device according to claim 19, wherein: The gate driver also provides an initialization gate signal to the pixel circuit, and The pixel circuit further includes a fifth transistor that provides a bias voltage to the anode terminal of the light emitting element in response to the initialization gate signal.

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