Display panel and display device

Abstract

The invention provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises at least one first pixel driving circuit. The first pixel driving circuit comprises a second transistor, a third transistor, a fourth transistor and a storage capacitor; the second electrode of the second transistor is electrically connected with the grid electrode of the third transistor and the first electrode of the storage capacitor; the fourth transistor is used for writing data voltage into the storage capacitor; the third transistor is used for controlling the magnitude of the output driving current according to the voltage on the grid electrode of the third transistor; the display panel is provided with a first scanning signal wire used for being electrically connected with the grid electrode of the fourth transistor. The grid electrode of the fourth transistor and the first scanning signal line are positioned on different film layers; the grid electrode of the fourth transistor has a first coupling structure. The second electrode of the second transistor has a second coupling structure. And the first coupling structure and the second coupling structure are overlapped. The display panel can reduce the risk that the black voltage exceeds the chip driving capability.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the application of OLED (organic light-emitting diode) technology in large-screen products such as foldable mobile phones, notebooks, and car displays, large-size OLED displays are becoming more and more widely used. The increase in the size of OLED displays will cause the signal routing to become longer, the load caused by the signal routing will also be greater, and the impact on the display effect will also be greater.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device to reduce the risk of black state voltage exceeding the chip driving capability.

[0005] According to one aspect of the present disclosure, there is provided a display panel, comprising a base substrate, a driving layer and a pixel layer stacked in sequence; the driving layer has a pixel driving circuit for driving sub-pixels;

[0006] The pixel driving circuit includes a second transistor, a third transistor, a fourth transistor and a storage capacitor; the second electrode of the second transistor is electrically connected to the gate of the third transistor and the first electrode of the storage capacitor, and the fourth transistor is used to write a data voltage to the storage capacitor; the third transistor is used to control the magnitude of the output driving current according to the voltage on the gate of the third transistor; the display panel is provided with a first scanning signal line electrically connected to the gate of the fourth transistor; the gate of the fourth transistor and the first scanning signal line are located in different film layers;

[0007] The pixel driving circuit includes at least a first pixel driving circuit; in the first pixel driving circuit, the gate of the fourth transistor has a first coupling structure, and the second electrode of the second transistor has a second coupling structure; the orthographic projection of the first coupling structure on the substrate at least partially overlaps with the orthographic projection of the second coupling structure on the substrate.

[0008] According to an embodiment of the present disclosure, in the first pixel driving circuit, the width of the second coupling structure is greater than the width of the channel region of the second transistor; and the extension direction of the first coupling structure is parallel to the length direction of the second coupling structure.

[0009] According to an embodiment of the present disclosure, in the first pixel driving circuit, the first coupling structure and the second coupling structure both extend in the row direction; in the column direction, the orthographic projection of the second coupling structure on the substrate does not exceed the orthographic projection of the first coupling structure on the substrate, or the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

[0010] According to an embodiment of the present disclosure, in the first pixel driving circuit, the first coupling structure and the second coupling structure both extend along the row direction; along the row direction, both ends of the first coupling structure exceed the second coupling structure; along the column direction, the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

[0011] According to an embodiment of the present disclosure, in the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion and the first coupling structure connected in sequence; the second metal portion is overlapped and connected to the first scanning signal wiring through a via;

[0012] A width of the first coupling structure is smaller than a width of the first metal portion.

[0013] According to one embodiment of the present disclosure, in the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure and a first connecting portion; the first connecting portion extends along the column direction, one end of the first connecting portion is connected to an end of the second coupling structure away from the channel region of the fourth transistor, and the other end of the first connecting portion is electrically connected to the channel region of the second transistor.

[0014] According to an embodiment of the present disclosure, in the first pixel driving circuit, the first coupling structure and the second coupling structure both extend along a row direction; along the row direction, one end of the first coupling structure does not exceed the second coupling structure;

[0015] The gate of the fourth transistor includes a first metal part, a second metal part and the first coupling structure which are connected in sequence; the second metal part is overlapped and connected to the first scanning signal line through a via; the width of the first coupling structure is greater than the width of the first metal part; the width of the second coupling structure is greater than the width of the channel region of the second transistor.

[0016] According to one embodiment of the present disclosure, in the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure, the second connection part and the first connection part which are connected in sequence; the second connection part extends along the row direction, and the first connection part extends along the column direction; the width of the second connection part and the first connection part is smaller than the width of the second coupling structure.

[0017] According to an embodiment of the present disclosure, in the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, a third metal portion and the first coupling structure connected in sequence, and the second metal portion is overlapped and connected to the first scanning signal wiring through a via; the gate of the fourth transistor extends in the row direction, and the size of the first coupling structure in the column direction is larger than the size of the third metal portion in the column direction;

[0018] The second electrode of the second transistor includes the second coupling structure, the first connection part and the second connection part connected in sequence; the first connection part extends along the row direction, and the second connection part extends along the column direction; the size of the second coupling structure in the column direction is larger than the size of the second connection part in the column direction.

[0019] According to an embodiment of the present disclosure, the third transistor and the fourth transistor are P-type thin film transistors.

[0020] According to an embodiment of the present disclosure, the pixel layer has sub-pixels of multiple different colors; the pixel driving circuit for driving the sub-pixels with the highest luminous efficiency is the first pixel driving circuit.

[0021] According to an embodiment of the present disclosure, each pixel driving circuit is the first pixel driving circuit.

[0022] According to an embodiment of the present disclosure, the pixel layer has a plurality of sub-pixels of different colors, the sub-pixels include a first sub-pixel and a second sub-pixel, and the luminous efficiency of the first sub-pixel is greater than the luminous efficiency of the second sub-pixel;

[0023] The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the first pixel driving circuit;

[0024] Among them, in the first pixel driving circuit that drives the first sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is a first area; in the first pixel driving circuit that drives the second sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is a second area; the first area is greater than the second area.

[0025] According to an embodiment of the present disclosure, the pixel layer has a plurality of sub-pixels of different colors, the sub-pixels include a first sub-pixel and a second sub-pixel, and the luminous efficiency of the first sub-pixel is greater than the luminous efficiency of the second sub-pixel;

[0026] The pixel driving circuit comprises a second pixel driving circuit, wherein the gate of the fourth transistor of the second pixel driving circuit does not overlap with the second electrode of the second transistor;

[0027] The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the second pixel driving circuit.

[0028] According to another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel and a driving module for driving the display panel.

[0029] According to one embodiment of the present disclosure, the driving module is configured to provide a driving power supply voltage to the display panel, and the driving power supply voltage is used to be loaded to the pixel driving circuit to drive the pixel driving circuit; the voltage of the driving power supply voltage is not less than 4.0V.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0032] Figure 1 FIG. 4 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0033] Figure 2 FIG. 1 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0034] Figure 3 This is a schematic diagram of a partial structure of a display panel near a first node in the first embodiment of the present disclosure.

[0035] Figure 4 This is a schematic diagram of a structure in which a gate electrode of a fourth transistor and a second electrode of a second transistor are stacked in the first embodiment of the present disclosure.

[0036] Figure 5This is a schematic diagram of a partial structure of a display panel near a first node in the second embodiment of the present disclosure.

[0037] Figure 6 This is a schematic diagram of a structure in which a gate of a fourth transistor is stacked with a second electrode of a second transistor in a second embodiment of the present disclosure.

[0038] Figure 7 This is a schematic diagram of a portion of the structure of the display panel near the first node in the third embodiment of the present disclosure.

[0039] Figure 8 This is a schematic diagram of a structure in which a gate of a fourth transistor is stacked with a second electrode of a second transistor in a third embodiment of the present disclosure.

[0040] Fig. 9 Schematic diagram of the structure of the gate of the fourth transistor in the third embodiment of the present disclosure.

[0041] Fig.10 Schematic diagram of the structure of the active layer of the second transistor in the third embodiment of the present disclosure.

[0042] Fig.11 It is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0043] Fig.12 It is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0044] Fig.13 This is a schematic diagram of the local structure of the first source-drain metal layer in the first layout example disclosed in the present invention.

[0045] Fig.14 This is a schematic diagram of the local structure of the first semiconductor layer in the first layout example disclosed in the present invention.

[0046] Fig.15 This is a schematic diagram of the local structural stacking of the first semiconductor layer and the first source-drain metal layer in the first layout example disclosed in the present invention.

[0047] Fig.16 This is a schematic diagram of the local structure of the first gate layer in the first layout example disclosed in the present invention.

[0048] Fig.17 This is a schematic diagram of the local structural stacking of the first semiconductor layer and the first gate layer in the first layout example of the present disclosure.

[0049] Fig.18 This is a schematic diagram of the local structural stacking of the first gate layer and the first source-drain metal layer in the first layout example of the present disclosure.

[0050] Fig.19 This is a schematic diagram of the local structure of the second gate layer in the first layout example disclosed in the present invention.

[0051] Fig. 20 It is a schematic diagram of the local structural stacking of the second gate layer and the first source-drain metal layer in the first layout example of the present disclosure.

[0052] Fig.21 This is a schematic diagram of the local structure of the second semiconductor layer in the first layout example disclosed in the present invention.

[0053] Fig. 22 This is a schematic diagram of the local structural stacking of the second gate layer and the second semiconductor layer in the first layout example of the present disclosure.

[0054] Fig.23 This is a schematic diagram of the local structural stacking of the second semiconductor layer and the first source-drain metal layer in the first layout example disclosed in the present invention.

[0055] Fig.24 This is a schematic diagram of the local structure of the third gate layer in the first layout example disclosed in the present invention.

[0056] Fig.25 This is a schematic diagram of the local structural stacking of the second semiconductor layer and the third gate layer in the first layout example of the present disclosure.

[0057] Fig.26 It is a schematic diagram of the local structural stacking of the third gate layer and the first source-drain metal layer in the first layout example of the present disclosure.

[0058] Fig. 27 This is a schematic diagram of the local structure of the second source-drain metal layer in the first layout example disclosed in the present invention.

[0059] Fig.28 This is a schematic diagram of the local structural stacking of the first source-drain metal layer and the second source-drain metal layer in the first layout example of the present disclosure.

[0060] Fig.29 This is a schematic diagram of the local structure of the third source-drain metal layer in the first layout example disclosed in the present invention.

[0061] Fig.30 It is a schematic diagram of the local structural stacking of the second source-drain metal layer and the third source-drain metal layer in the first layout example of the present disclosure.

[0062] Fig.31 This is a schematic diagram of the local structure of the first source-drain metal layer in the second layout example disclosed in the present invention.

[0063] Fig.32 This is a schematic diagram of the local structure of the second source-drain metal layer in the second layout example disclosed in the present invention.

[0064] Fig.33 This is a schematic diagram of the partial structural stacking of the first source-drain metal layer and the second source-drain metal layer in the second layout example of the present disclosure. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0066] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0067] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0068] In the present disclosure, the structure layer A is located on the side of the structure layer B away from the base substrate, which can be understood as the structure layer A is formed on the side of the structure layer B away from the base substrate. When the structure layer B is a patterned structure, part of the structure layer A may also be located at the same physical height as the structure layer B or lower than the physical height of the structure layer B, wherein the base substrate is a height reference.

[0069] In the present disclosure, when describing the overlapping arrangement of structure C and structure D, it means that structure C and structure D are respectively in different film layers, but the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate at least partially overlap.

[0070] In the present disclosure, a transistor refers to an element including at least three electrodes: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, a drain region, or a drain electrode) and the source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or the case where the current direction changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0071] For large-size display panels, changes in signal load have a greater impact on the display effect. Figure 1 Taking the pixel driving circuit as an example, the first scanning signal line GPL for loading the first scanning signal Gate_P can control the data voltage Vdata to be written into the first node N1, but the first scanning signal line GPL or the gate T4G of the fourth transistor T4 itself will be coupled with the structure of the first node N1 (for example, the second electrode T2D of the second transistor T2), and this coupling will affect the voltage written into the first node N1. Figure 1 Taking the pixel driving circuit as an example, the effect of the coupling between the first scanning signal line GPL or the gate T4G of the fourth transistor T4 and the first node N1 is described as an example. It can be understood that this effect is not limited to Figure 1 The illustrated pixel driving circuit.

[0072] exist Figure 1In the illustrated pixel driving circuit, the pixel driving circuit includes a first transistor T1 (as a gate reset transistor for resetting the gate of the driving transistor), a second transistor T2 (as a threshold compensation transistor for compensating the threshold voltage of the driving transistor), a third transistor T3 (as a driving transistor), a fourth transistor T4 (as a data writing transistor for writing data voltage to the pixel driving circuit), a fifth transistor T5 (as a first light emitting control transistor), a sixth transistor T6 (as a second light emitting control transistor), a seventh transistor T7 (as an electrode reset transistor for resetting the pixel electrode) and an eighth transistor T8 (as a source reset transistor for resetting the source of the driving transistor). Among them, the second transistor T2 is an N-type thin film transistor, such as a metal oxide thin film transistor. The third transistor T3 and the fourth transistor T4 are P-type transistors, such as P-type low temperature polysilicon thin film transistors. Among them, the second electrode T2D of the second transistor T2, the first electrode CP1 of the storage capacitor, and the gate of the third transistor T3 (which can be reused as the first electrode CP1 of the storage capacitor) are electrically connected to the first node N1; the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, the second electrode of the eighth transistor T8, and the first electrode of the third transistor T3 are electrically connected to the second node N2; the second electrode of the third transistor T3, the first electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the sixth transistor T6 are electrically connected to the third node N3; the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are electrically connected to the fourth node N4 and are electrically connected to the light emitting element; the first electrode of the fifth transistor T5 and the second electrode CP2 of the storage capacitor are electrically connected to the driving power supply voltage terminal (for loading the driving power supply voltage VDD); the first electrode of the fourth transistor T4 is electrically connected to the data voltage terminal (for loading the data voltage Vdata); the first electrode of the eighth transistor T8 is electrically connected to the third initialization voltage terminal. a voltage terminal (for loading a third initialization voltage Vinit3) is electrically connected; a first electrode of the first transistor T1 is electrically connected to the first initialization voltage terminal (for loading the first initialization voltage Vinit1); a first electrode of the seventh transistor T7 is electrically connected to the second initialization voltage terminal (for loading the second initialization voltage Vinit2); a gate of the first transistor T1 is electrically connected to the first reset signal terminal (for loading the first reset signal Reset_P), a gate of the second transistor T2 is electrically connected to the second scan signal terminal (for loading the second scan signal Gate_N), a gate T4G of the fourth transistor T4 is electrically connected to the first scan signal terminal (for loading the first scan signal Gate_P), a gate of the fifth transistor T5 and a gate of the sixth transistor T6 are both electrically connected to the light emitting control signal terminal (for loading the light emitting control signal EM), and a gate of the seventh transistor T7 and a gate of the eighth transistor T8 are both electrically connected to the second reset signal terminal (for loading the second reset signal Reset_H).

[0073] In this example, in the data writing stage, the first scanning signal terminal is loaded with a low level to turn on the fourth transistor T4, and the second scanning signal terminal is loaded with a high level to turn on the second transistor T2, so that the data voltage Vdata on the data voltage terminal is written to the first node N1. After the data writing stage, the first scanning signal terminal becomes a high level to turn off the fourth transistor T4, and the second scanning signal terminal is loaded with a low level to turn off the second transistor T2. In the related art, the voltage value of the driving power supply voltage VDD used by the pixel driving circuit is about 2.8V. At this time, the black state voltage required by the pixel driving circuit is also relatively low and within the chip output capacity. Therefore, it is necessary to reduce the coupling between the first scanning signal terminal and the first node N1 as much as possible to avoid the voltage of the first node N1 being pulled up by coupling when the voltage of the first scanning signal terminal is pulled up.

[0074] The inventors have found that when the pixel driving circuit uses a driving power supply voltage VDD with a higher voltage value, for example, a driving power supply voltage VDD of 4.6V, the black state voltage of the pixel driving circuit will also be greatly increased, and there is a possibility that the black state voltage exceeds the output capacity of the chip (for example, the source driver chip). The black state voltage of the pixel driving circuit is the voltage that the data voltage terminal is loaded to the pixel driving circuit to ensure that the third transistor T3 is completely turned off.

[0075] Based on this, the embodiment of the present disclosure provides a display device and a display panel PNL of the display device, wherein at least part of the pixel driving circuit of the display panel PNL is an improved pixel driving circuit, and the coupling capacitance between the first scan signal terminal and the first node N1 in the improved pixel driving circuit is increased, so as to increase the voltage of the first node N1 by means of the coupling effect between the first scan signal terminal and the first node N1, thereby reducing the voltage value of the black state voltage required by the pixel driving circuit. The display device also includes a driving module for driving the display panel. The driving module is configured to provide a driving power supply voltage VDD to the display panel PNL, and the driving power supply voltage VDD is used to load the pixel driving circuit to drive the pixel driving circuit. Since at least part of the pixel driving circuit in the PNL provided in the embodiment of the present disclosure is an improved pixel driving circuit, it is not easy to have the risk of the black state voltage exceeding the output capacity of the driving chip under a high driving power supply voltage.

[0076] See also Figure 2 The display panel PNL includes a base substrate SBT, a driving layer DRL and a pixel layer PXL which are stacked in sequence; the driving layer DRL has a pixel driving circuit for driving the sub-pixels PX. Figure 2In the example of FIG. 1 , a light emitting element LD as a sub-pixel PX is provided in the pixel layer PXL, and the output end of the pixel driving circuit is electrically connected to the light emitting element LD. In the embodiment of the present disclosure, the pixel driving circuit can be Figure 1 The pixel driving circuit shown, but not limited to Figure 1 .

[0077] See also Figure 1 and Figures 3 to 10 , the pixel driving circuit includes a second transistor T2, a third transistor T3, a fourth transistor T4 and a storage capacitor CST. The second electrode T2D of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first electrode CP1 of the storage capacitor, and the fourth transistor T4 is used to write a data voltage Vdata to the storage capacitor CST. The third transistor T3 is used to control the magnitude of the output drive current according to the voltage on the gate of the third transistor T3. The display panel PNL is provided with a first scanning signal line GPL for being electrically connected to the gate T4G of the fourth transistor T4 (for example, the gate T4G of the fourth transistor T4 is electrically connected to the first scanning signal line GPL through a via); the gate T4G of the fourth transistor T4 and the first scanning signal line GPL are located in different film layers. The pixel driving circuit at least includes a first pixel driving circuit PDC1 (i.e., an improved pixel driving circuit); in the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 has a first coupling structure CA, and the second electrode T2D of the second transistor T2 has a second coupling structure CB; the orthographic projection of the first coupling structure CA on the substrate SBT at least partially overlaps with the orthographic projection of the second coupling structure CB on the substrate SBT.

[0078] In other words, in the embodiment of the present disclosure, a first pixel driving circuit PDC1 is provided on the display panel PNL, and the gate T4G of the fourth transistor T4 of the first pixel driving circuit PDC1 overlaps with the second electrode T2D of the second transistor T2, so that the first scanning signal terminal and the first node N1 have a large coupling capacitance, and then the black state voltage of the first pixel driving circuit PDC1 is reduced by the coupling effect between the first scanning signal terminal and the first node N1. Specifically, after the first scanning signal terminal is loaded with a low level to write the data voltage Vdata to the pixel driving circuit, the first scanning signal terminal is loaded with a high level to turn off the fourth transistor T4; in the process of level increase on the first scanning signal terminal, the voltage of the first node N1 can be raised by coupling; in this way, when writing the black state voltage to the pixel driving circuit, a lower black state voltage can be written. In some embodiments of the present disclosure, all pixel driving circuits are the first pixel driving circuit PDC1, that is, all adopt a design that makes the gate T4G of the fourth transistor T4 overlap with the second electrode T2D of the second transistor T2. In some other implementations, only part of the pixel driving circuits may be the first pixel driving circuit PDC1, that is, the gate T4G of the fourth transistor T4 of another part of the pixel driving circuits does not overlap with the second electrode T2D of the second transistor T2.

[0079] In one embodiment of the present disclosure, see Figure 4 , Figure 6 and Fig.10 , the active layer of the second transistor T2 includes the first electrode of the second transistor T2, the channel region T2A of the second transistor and the second electrode T2D of the second transistor T2 connected in sequence; wherein the channel region T2A of the second transistor can maintain semiconductor characteristics, and the first electrode of the second transistor T2 and the second electrode T2D of the second transistor T2 can be conductorized. wherein the width of the second coupling structure CB of the second electrode T2D of the second transistor T2 can be greater than the width of the channel region T2A of the second transistor. on the one hand, this is conducive to increasing the coupling capacitance between the second coupling structure CB and the first coupling structure CA, and on the other hand, it can avoid excessive coupling between the second scanning signal terminal and the first node N1. it can be understood that after the data writing stage, the second scanning signal terminal needs to be pulled down to turn off the second transistor T2. if the coupling between the second scanning signal terminal and the first node N1 increases, then the voltage pull-down of the second scanning signal terminal will cause the voltage of the first node N1 to be pulled down, which will cause the black state voltage of the pixel driving circuit to become higher, which will worsen the risk of the black state voltage exceeding the chip driving capability.

[0080] In one embodiment of the present disclosure, the extension direction of the first coupling structure CA is parallel to the length direction of the second coupling structure CB. For example, the extension direction of the first coupling structure CA and the length direction of the second coupling structure CB are both the row direction DH. In this example, the length direction of the second coupling structure CB refers to the extension direction of the active layer of the second transistor T2, which is perpendicular to the width direction of the active layer of the second transistor T2. Figures 3 to 10 In the example of FIG. 5 , the length direction of the second coupling structure CB is the row direction DH, and the length direction of the channel region T2A of the second transistor is the column direction DV.

[0081] In one embodiment of the present disclosure, see Figure 4 and Figure 6 In the first pixel driving circuit PDC1, the extension direction of the first coupling structure CA is parallel to the length direction of the second coupling structure CB. In this way, the overlapping area between the first coupling structure CA and the second coupling structure CB is increased, thereby increasing the coupling capacitance between the first scanning signal terminal and the first node N1.

[0082] Optionally, the extension direction of the first coupling structure CA is parallel to the extension direction of the second coupling structure CB, for example, both extend along the row direction DH. Further, the extension middle line of the first coupling structure CA is arranged to overlap with the extension middle line of the second coupling structure CB. In this way, while maximizing the overlapping area between the first coupling structure CA and the second coupling structure CB, the first coupling structure CA can be shielded by the second coupling structure CB to minimize the coupling between the first coupling structure CA and the other structures, thereby reducing the load of the first scanning signal routing line GPL.

[0083] In another example, see Figure 4 , in the column direction DV, the orthographic projection of the first coupling structure CA on the substrate SBT does not exceed the orthographic projection of the second coupling structure CB on the substrate SBT. In particular, in the column direction DV, the orthographic projection of the first coupling structure CA on the substrate SBT is located within the orthographic projection of the second coupling structure CB on the substrate SBT. This can ensure the stability of the overlapping area between the first coupling structure CA and the second coupling structure CB, avoid the change of the coupling capacitance caused by the relative position change of the first coupling structure CA and the second coupling structure CB, and further ensure the stability of the coupling capacitance between the first scanning signal terminal and the first node N1, and improve the uniformity of each first pixel driving circuit PDC1.

[0084] In one example, see Figure 6, in the column direction DV, the orthographic projection of the second coupling structure CB on the substrate SBT does not exceed the orthographic projection of the first coupling structure CA on the substrate SBT. In particular, in the column direction DV, the orthographic projection of the second coupling structure CB on the substrate SBT is located within the orthographic projection of the first coupling structure CA on the substrate SBT. This can ensure the stability of the overlapping area between the first coupling structure CA and the second coupling structure CB, avoid the change of the coupling capacitance caused by the relative position change of the first coupling structure CA and the second coupling structure CB, and further ensure the stability of the coupling capacitance between the first scanning signal terminal and the first node N1, and improve the uniformity of each first pixel driving circuit PDC1.

[0085] In one embodiment of the present disclosure, the display panel PNL is provided with a first conductive structure MA1 corresponding to the pixel driving circuit one by one, and the first conductive structure MA1 is electrically connected to the second electrode T2D of the second transistor T2 and the first electrode CP1 of the storage capacitor through vias. Among them, the second coupling structure CB of the second electrode T2D of the second transistor T2 can be provided with a via area, and the via area on the second coupling structure CB is overlapped with the first conductive structure MA1 through the via. In this embodiment, the second coupling structure CB needs to have a larger width so as to have a larger contact area with the first conductive structure MA1, thereby reducing the contact resistance between the second coupling structure CB and the first conductive structure MA1. In this way, the first coupling structure CA can have a larger coupling with the second electrode T2D of the second transistor T2 without additionally increasing the width of the second coupling structure CB or minimizing the adjustment of the width of the second electrode T2D of the second transistor T2.

[0086] In the first embodiment of the present disclosure, see Figure 3 and Figure 4 In the first pixel driving circuit PDC1, the first coupling structure CA and the second coupling structure CB both extend along the row direction DH; along the row direction DH, both ends of the first coupling structure CA exceed the second coupling structure CB; along the column direction DV, the orthographic projection of the first coupling structure CA on the substrate SBT does not exceed the orthographic projection of the second coupling structure CB on the substrate SBT. In this embodiment, the end of the gate T4G of the fourth transistor T4 close to the second electrode T2D of the second transistor T2 is extended in the direction toward the second electrode T2D of the second transistor T2 until it exceeds the range of the second coupling structure CB, for example, exceeds the channel area T2A of the second transistor in the row direction DH. This can be achieved by making the first coupling structure CA as long as possible to achieve the purpose of increasing the overlapping area between the first coupling structure CA and the second coupling structure CB.

[0087] In one example of this implementation, two adjacent pixel driving circuits in the same row can form a pixel driving circuit group, and the two pixel driving circuits in the pixel driving circuit group can be arranged in mirror symmetry, and the channel area T2A of the second transistor is arranged near the symmetry center; the first coupling structure CA of the gate T4G of the fourth transistor T4 of the two pixel driving circuits in the pixel driving circuit group can extend toward each other to be connected to each other. In this way, the gate T4G of the interconnected fourth transistor T4 is arranged in parallel with the first scanning signal line GPL, which can further reduce the impedance of the first scanning signal line GPL and reduce the transmission delay of the first scanning signal Gate_P. In another example of this implementation, the first coupling structures CA of the two first pixel driving circuits PDC1 in the same pixel driving circuit group can extend toward each other, but the two do not extend to be connected to each other, for example, they only slightly exceed the channel area T2A of the second transistor. This can avoid the first coupling structure CA coupling with other conductive structures to increase the load of the first scanning signal line GPL.

[0088] In another example of this implementation, two adjacent pixel driving circuits in the same row can form a pixel driving circuit group, and the two pixel driving circuits in the pixel driving circuit group can be arranged in mirror symmetry, and the channel region T2A of the second transistor is arranged away from the symmetry center; the gates T4G of the fourth transistors T4 of the two pixel driving circuits in the pixel driving circuit group can extend toward each other to be connected to each other. In this way, the gates T4G of the interconnected fourth transistors T4 are arranged in parallel with the first scanning signal line GPL, which can further reduce the impedance of the first scanning signal line GPL and reduce the transmission delay of the first scanning signal Gate_P.

[0089] In one example of this implementation, see Figure 3 and Figure 4 In the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 includes a first metal portion GA, a second metal portion GB and the first coupling structure CA which are connected in sequence; the second metal portion GB is overlapped and connected to the first scanning signal line GPL through a via hole; the width of the first coupling structure CA is smaller than the width of the first metal portion GA. Figure 4 In the example, the second metal part GB has a first bottom via area HA1, the first scan signal line GPL has a first top via area HB1, the first bottom via area HA1 overlaps with the first top via area HB1 and is connected by via lap connection. The first metal part GA is located on the side of the second metal part GB away from the channel area T2A of the second transistor, and overlaps with the channel area T4A of the fourth transistor. The width of the first coupling structure CA is smaller than the width of the first metal part GA to avoid the width of the first coupling structure CA being too large, which may cause the coupling capacitance between the first scan signal terminal and the first node N1 to be too large.

[0090] In one example of this implementation, see Figure 3 and Figure 4 In the first pixel driving circuit PDC1, the second electrode T2D of the second transistor T2 includes the second coupling structure CB and the first connection portion OXA; the first connection portion OXA extends along the column direction DV, one end of the first connection portion OXA is connected to the end of the second coupling structure CB away from the channel region T4A of the fourth transistor, and the other end of the first connection portion OXA is electrically connected to the channel region T2A of the second transistor. In this way, it can be ensured that the second coupling structure CB has a larger length in the row direction DH, thereby ensuring that the overlapping area between the first coupling structure CA and the second coupling structure CB is large enough.

[0091] exist Figure 3 and Figure 4 In the example of FIG. 1 , the first pixel driving circuit PDC1 adopts a strategy of making the first coupling structure CA narrow and long to increase the coupling area between the first coupling structure CA and the second coupling structure CB. In other embodiments of the present disclosure, a strategy of making at least a part of the second coupling structure CB narrow and wide may also be adopted, for example, making the width of the second coupling structure CB smaller than the width of the first coupling structure CA.

[0092] In the second embodiment of the present disclosure, see Figure 5 and Figure 6 , in the first pixel driving circuit PDC1, the first coupling structure CA and the second coupling structure CB both extend along the row direction DH; along the row direction DH, one end of the first coupling structure CA does not exceed the second coupling structure CB, that is, the first coupling structure CA and the second coupling structure CB partially overlap in the row direction DH. Among them, the gate T4G of the fourth transistor T4 includes a first metal part GA, a second metal part GB and a first coupling structure CA connected in sequence, and the width of the first coupling structure CA is greater than the width of the first metal part GA; the width of the second coupling structure CB is greater than the width of the channel region T2A of the second transistor. In this way, the first coupling structure CA and the second coupling structure CB are both widened and partially overlapped to ensure that there is a large coupling capacitance between the first coupling structure CA and the second coupling structure CB.

[0093] exist Figure 5 and Figure 6In the example of the present disclosure, the width of the first coupling structure CA is greater than the width of the second coupling structure CB, so that the orthographic projection of the second coupling structure CB on the substrate SBT in the column direction DV is located within the orthographic projection of the first coupling structure CA on the substrate SBT. In some other examples of the present disclosure, the width of the second coupling structure CB may be greater than the width of the first coupling structure CA, for example, so that the orthographic projection of the second coupling structure CB on the substrate SBT in the column direction DV is located within the orthographic projection of the first coupling structure CA on the substrate SBT.

[0094] exist Figure 5 and Figure 6 In the example, the width of the first coupling structure CA is greater than the width of the first metal portion GA, and the width change of the gate T4G of the fourth transistor T4 occurs at the first metal portion GA. In some other embodiments of the present disclosure, the width change may also occur at the first metal portion GA or the first coupling structure CA, subject to the width change not overlapping the second coupling structure CB.

[0095] In an example of this embodiment, in the first pixel driving circuit PDC1, the second electrode T2D of the second transistor T2 includes the second coupling structure CB, the second connection part OXB and the first connection part OXA connected in sequence; the second connection part OXB extends along the row direction DH, and the first connection part OXA extends along the column direction DV; the widths of the second connection part OXB and the first connection part OXA are smaller than the width of the second coupling structure CB. In other words, the second electrode T2D of the second transistor T2 can be widened only at the second coupling structure CB to ensure the overlapping area with the first coupling structure CA. In other examples of the present disclosure, at least one of the second connection part OXB and the first connection part OXA can also be widened, for example, the width of the second connection part OXB is the same as the width of the second coupling structure CB.

[0096] In the third embodiment of the present disclosure, see Figure 7 to Figure 10In the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 includes a first metal part GA, a second metal part GB, a third metal part GC and the first coupling structure CA connected in sequence, and the second metal part GB is overlapped and connected to the first scanning signal line GPL through a via; the gate T4G of the fourth transistor T4 extends along the row direction DH, and the size of the first coupling structure CA in the column direction DV is larger than the size of the third metal part GC in the column direction DV; the second electrode T2D of the second transistor T2 includes the second coupling structure CB, the first connection part OXA and the second connection part OXB connected in sequence; the first connection part OXA extends along the row direction DH, and the second connection part OXB extends along the column direction DV; the size of the second coupling structure CB in the column direction DV is larger than the size of the second connection part OXB in the column direction DV.

[0097] In this embodiment, the gate T4G of the fourth transistor T4 is enlarged near the end of the second transistor T2 and is called the first coupling structure CA, and the second electrode T2D of the second transistor T2 is enlarged near the end of the fourth transistor T4 to form a second coupling structure CB. The first coupling structure CA and the second coupling structure CB are overlapped so that a larger coupling capacitance is provided between the first scan signal terminal and the first node N1.

[0098] exist Figure 7 to Figure 10 In the example of the present disclosure, the width of the second connection portion OXB and the first connection portion OXA is not increased, which can prevent the second electrode T2D of the second transistor T2 from being excessively increased, thereby causing the coupling capacitance between the second electrode T2D of the second transistor T2 and other structures to be excessively increased. In other examples of the present disclosure, the width of at least one of the second connection portion OXB and the first connection portion OXA can also be increased, for example, so that the width of the second connection portion OXB is smaller than the second coupling structure CB and larger than the first connection portion OXA.

[0099] exist Figure 7 to Figure 10 In the example, the width of the third metal portion GC is smaller than the first coupling structure CA, which can prevent the third metal portion GC from coupling with other structures and causing an increase in the load of the first scan signal routing line GPL. Further, the width of the third metal portion GC is smaller than the width of the first metal portion GA.

[0100] exist Figure 7 to Figure 10 In the example of , the width of the second metal portion GB is equal to the width of the first metal portion GA. In other examples of the present disclosure, the width of the second metal portion GB may also be adjusted, for example, the width of the second metal portion GB is increased to be greater than the first metal portion GA, or the width of the second metal portion GB is reduced (for example, reduced to the same width as the third metal portion GC).

[0101] In one embodiment of the present disclosure, see Figure 2 , the driving layer DRL includes a first gate layer GT1, a second semiconductor layer OSCL and a first source-drain metal layer SD1 which are sequentially stacked on one side of the substrate SBT; the gate T4G of the fourth transistor T4 is arranged on the first gate layer GT1, the first scan signal line GPL is arranged on the first source-drain metal layer SD1, and the second electrode T2D of the second transistor T2 is located on the second semiconductor layer OSCL. Among them, the first scan signal line GPL is arranged on the first source-drain metal layer SD1, which can reduce the resistivity of the first scan signal line GPL, thereby facilitating the reduction of the rise time and fall time of the first scan signal Gate_P, reducing the delay of the first scan signal Gate_P, so as to facilitate the timely opening and closing of the fourth transistor T4, and facilitate the full writing of the data voltage Vdata. There is no thick organic insulating layer between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2, so the step difference between the first coupling structure CA and the second coupling structure CB is small, which is conducive to improving the coupling capacitance between the first coupling structure CA and the second coupling structure CB.

[0102] In the embodiment of the present disclosure, when the voltage value of the driving power supply voltage VDD is 4.6V, the inventor also evaluated the influence of changes in the capacitance value between the first scanning signal terminal and the first node N1 and the capacitance value between the second scanning signal terminal and the first node N1 on the black state voltage of different sub-pixels.

[0103] The results of the first evaluation are shown in Table 1. In this evaluation, the inventors evaluated the coupling and black state voltage of the improved solution, as well as the coupling and black state voltage of the solution before the improvement. Figure 3 and Figure 4 As shown; the local structure of the scheme before improvement is basically the same as Figure 3 , Figure 4 The example is similar to that shown, but the gate T4G of the fourth transistor T4 is not provided with the first coupling structure CA overlapping with the second coupling structure CB.

[0104] Table 1 Difference in black state voltage (VGMP) between the improved solution and the solution before improvement

[0105]

[0106]

[0107] It can be seen from Table 1 that, compared with the solution before the improvement, the coupling capacitance between the second scan signal terminal and the first node N1 of the improved solution is basically unchanged, but the coupling capacitance between the first scan signal terminal and the first node N1 of the improved solution increases. Of course, as the coupling capacitance between the first scan signal terminal and the first node N1 increases, the parasitic capacitance of the first scan signal terminal also increases.

[0108] Since the green sub-pixel has the highest luminous efficiency, it is the most difficult to turn into a black state in the luminous state, and its corresponding black state voltage is the highest. Therefore, the inventor evaluated the black state voltage of the green sub-pixel at different maximum luminous brightness (the greater the maximum luminous brightness, the more difficult it is for the sub-pixel to be completely turned off, and the higher the required black state voltage). In the scheme before the improvement, the black state voltage corresponding to the green sub-pixel at 500nit is 7.192V, and the black state voltage corresponding to the green sub-pixel at 1200nit is 7.549V. In the improved scheme, the black state voltage corresponding to the green sub-pixel at 500nit is 6.669V, and the black state voltage corresponding to the green sub-pixel at 1200nit is 7.032V. Therefore, the improved scheme can reduce the black state voltage of the green sub-pixel by about 0.5V. Especially in the case of high brightness, the improved scheme makes it easier for the black state voltage not to exceed the output capacity of the chip by reducing the black state voltage, reducing the risk of the black state voltage exceeding the chip output capacity due to the high driving power supply voltage VDD.

[0109] The inventors also evaluated the black state voltages corresponding to different sub-pixels in different improvement schemes. The differences among these improvement schemes are mainly in the coupling capacitance between the first scanning signal terminal and the first node N1, and the coupling capacitance between the second scanning signal terminal and the first node N1. The evaluation results are shown in Table 2.

[0110] Table 2: Differences in black state voltage (VGMP) of different improvement schemes

[0111]

[0112]

[0113] In Table 2, C N1-Gtp is the coupling capacitance between the first scanning signal terminal and the first node; C N1-Gtn is a coupling capacitor between the second scanning signal terminal and the first node. PXR represents a red sub-pixel, PXG represents a green sub-pixel, and PXB represents a blue sub-pixel.

[0114] According to Table 2, when the coupling capacitance of the first scan signal terminal of the two improved solutions is substantially consistent with the first node N1, the black state voltage of the sub-pixel of the improved solution with a larger coupling capacitance of the second scan signal terminal and the first node N1 is larger. When the coupling capacitance of the second scan signal terminal of the two improved solutions is substantially consistent with the first node N1, the black state voltage of the sub-pixel of the improved solution with a larger coupling capacitance of the first scan signal terminal and the first node N1 is smaller. In each of the improved solutions evaluated in Table 2, the black state voltage of each sub-pixel is not too high, for example, none of them exceeds 6.8V, which enables these improved solutions to reduce the risk of the black state voltage exceeding the output capacity of the IC in products with a high voltage (for example, 4.6V) of the driving power supply voltage VDD, thereby improving the stability and quality of these products. In response, after the display product adopts the improved solution provided by the embodiment of the present disclosure, a higher voltage driving power supply voltage VDD can be adopted with lower risk, thereby making the output of the IC (for example, the source driver chip) more efficient.

[0115] In one embodiment of the present disclosure, the voltage of the driving power supply voltage VDD is not less than 4.0V, for example, the voltage of the driving power supply voltage VDD is 4.6V.

[0116] In some embodiments of the present disclosure, the sub-pixel PX may include a plurality of sub-pixels PX of different colors, and the luminous efficiency of the sub-pixels PX of different colors may be different. In this case, if no improvement is made to the pixel driving circuit on the display panel PNL, the pixel driving circuit with the highest luminous efficiency is most likely to have the problem that the black state voltage exceeds the chip driving capability. Therefore, in these embodiments, at least the pixel driving circuit used to drive the sub-pixel PX with the highest luminous efficiency may be the first pixel driving circuit PDC1, so as to at least reduce the black state voltage corresponding to the sub-pixel PX with the highest luminous efficiency. For the sub-pixel PX with non-highest luminous efficiency, it can be determined whether the corresponding pixel driving circuit is improved as needed, for example, all other pixel driving circuits are improved to the first pixel driving circuit PDC1, or some pixel driving circuits are improved to the first pixel driving circuit PDC1, or none of the other pixel driving circuits are improved to the first pixel driving circuit PDC1, or the first pixel driving circuit PDC1 has different black state voltage reduction capabilities according to the luminous efficiency of the sub-pixel PX.

[0117] In one embodiment, see Fig.11, each pixel driving circuit on the display panel PNL is a first pixel driving circuit PDC1, that is, each pixel driving circuit adopts an improved method of making the gate electrode T4G of the fourth transistor T4 overlap with the second electrode T2D of the second transistor T2. In other words, the pixel driving circuit corresponding to each sub-pixel PX is the first pixel driving circuit PDC1 to reduce the black state voltage required by the pixel driving circuit corresponding to each sub-pixel PX.

[0118] In one example, the sub-pixel PX includes a plurality of sub-pixels PX of different colors, and the luminous efficiency of these sub-pixels PX may be different. For example, the sub-pixel PX may include a red sub-pixel PXR, a green sub-pixel PXG, a blue sub-pixel PXB, and the like. The sub-pixels PX of different colors or different luminous efficiency use a substantially identical structure of the first pixel driving circuit PDC1, for example, the coupling capacitance between the first scanning signal terminal of each first pixel driving circuit PDC1 and the first node N1 is substantially consistent, and the coupling capacitance between the second scanning signal terminal of each first pixel driving circuit PDC1 and the first node N1 is substantially consistent. In this way, the pixel driving circuit corresponding to each sub-pixel PX does not need to be differentiated in design, which is beneficial to the design and preparation of the display panel PNL.

[0119] In another example, the display panel PNL may include a plurality of different first pixel driving circuits PDC1, and the main difference between the different first pixel driving circuits PDC1 is that the overlapping areas of the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 are different so as to have different abilities to reduce the black state voltage. The larger the overlapping area of ​​the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2, the stronger the ability of the first pixel driving circuit PDC1 to reduce the black state voltage. The display panel PNL adapts different first pixel driving circuits PDC1 to different sub-pixels PX according to the difference in luminous efficiency of different sub-pixels PX: for sub-pixels PX with higher luminous efficiency, a first pixel driving circuit PDC1 with stronger ability to reduce the black state voltage is configured.

[0120] For example, see Fig.11, the sub-pixel PX includes a first sub-pixel PX1 and a second sub-pixel PX2, wherein the luminous efficiency of the first sub-pixel PX1 is greater than the luminous efficiency of the second sub-pixel PX2. The pixel driving circuit corresponding to the first sub-pixel PX1 and the pixel driving circuit corresponding to the second sub-pixel PX2 are both the first pixel driving circuit PDC1, that is, both are designed so that the gate T4G of the fourth transistor T4 overlaps with the second electrode T2D of the second transistor T2. However, in the first pixel driving circuit PDC1 that drives the first sub-pixel PX1, the overlapping area between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 is the first area; in the first pixel driving circuit PDC1 that drives the second sub-pixel PX2, the overlapping area between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 is the second area; the first area is greater than the second area. Thus, the luminous efficiency of the first subpixel PX1 is higher than that of the second subpixel PX2, and the first pixel driving circuit PDC1 driving the first subpixel PX1 has a stronger ability to reduce the black state voltage than the first pixel driving circuit PDC1 driving the second subpixel PX2.

[0121] In another embodiment, see Fig.12 , the pixel layer PXL has a plurality of sub-pixels PX of different colors, the sub-pixels PX include a first sub-pixel PX1 and a second sub-pixel PX2, the luminous efficiency of the first sub-pixel PX1 is greater than the luminous efficiency of the second sub-pixel PX2; the pixel driving circuit includes a second pixel driving circuit PDC2, the gate T4G of the fourth transistor T4 of the second pixel driving circuit PDC2 does not overlap with the second electrode T2D of the second transistor T2; the pixel driving circuit corresponding to the first sub-pixel PX1 is the first pixel driving circuit PDC1, and the pixel driving circuit corresponding to the second sub-pixel PX2 is the second pixel driving circuit PDC2. In this embodiment, only the pixel driving circuit driving the first sub-pixel PX1 is the first pixel driving circuit PDC1 with the ability to reduce the black state voltage, and the pixel driving circuit driving the second sub-pixel PX2 does not adopt the improved solution of making the gate T4G of the fourth transistor T4 overlap with the second electrode T2D of the second transistor T2.

[0122] As an example, see Fig.12 , the sub-pixel PX includes a red sub-pixel PXR, a green sub-pixel PXG and a blue sub-pixel PXB, wherein the green sub-pixel PXG is used as the first sub-pixel PX1 and the red sub-pixel PXR and the blue sub-pixel PXB are used as the second sub-pixel PX2. In this example, the green sub-pixel PXG is driven by the first pixel driving circuit PDC1, and the blue sub-pixel PXB and the red sub-pixel PXR are driven by the second pixel driving circuit PDC2.

[0123] As an example, see Figure 2 The driving layer DRL further includes a first semiconductor layer PSCL, which is used to form an active layer of the third transistor T3, the fourth transistor T4, etc. Optionally, in the film layer stacking sequence, the first gate layer GT1 is located between the first semiconductor layer PSCL and the second semiconductor layer OSCL.

[0124] As an example, see Figure 2 The driving layer DRL further includes a second gate layer GT2, a third gate layer GT3, etc. The second gate layer GT2 and the third gate layer GT3 can form a top gate and a bottom gate of the second transistor T2, as well as form other required structures.

[0125] As an example, see Figure 2 The driving layer DRL further includes a second source-drain metal layer SD2 and a third source-drain metal layer SD3 located on a side of the first source-drain metal layer SD1 away from the substrate SBT, so as to better transmit signals or perform electrical connection.

[0126] As another example, the driving layer DRL may be provided with only two source-drain metal layers instead of three source-drain metal layers.

[0127] It is understandable that a film layer formed of insulating material may be provided between adjacent metal layers and semiconductor layers.

[0128] As an example, see Figure 2 The driving layer DRL includes a first inorganic buffer layer BLA, a first semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BLB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer SD3 and a third planarization layer PLN3, which are sequentially stacked on one side of the substrate SBT. Among them, the active layer of the P-type transistor can be set in the first semiconductor layer PSCL, and the active layer of the N-type transistor can be set in the second semiconductor layer OSCL. In one example, the first semiconductor layer PSCL can be a low-temperature polysilicon semiconductor layer. The second semiconductor layer OSCL can be a metal oxide semiconductor layer.

[0129] Understandably, Figure 2 This is only an example of the driving layer DRL of the embodiment of the present disclosure. The driving layer DRL of other embodiments of the present disclosure may be Figure 2Different, for example, only two gate layers are included under the premise of including the first semiconductor layer PSCL and the second semiconductor layer OSCL at the same time, and for another example, only two source and drain metal layers are included instead of three source and drain metal layers.

[0130] In one embodiment of the present disclosure, see Figure 2 , the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL and a common electrode layer COML which are stacked in sequence. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes in the display area of ​​the display panel. The pixel definition layer PDL has a plurality of through pixel openings which are arranged one by one in correspondence with the plurality of pixel electrodes, and any one of the pixel openings exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EFL), and further define the light-emitting area and light-emitting area of ​​the sub-pixel PX. The common electrode layer COML covers the light-emitting functional layer EFL as a common electrode. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The portion of the light-emitting functional layer EFL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel PX. The pixel electrode, the common electrode layer COML, and the light emitting functional unit form a light emitting element LD as a sub-pixel PX, wherein one of the pixel electrode and the common electrode layer COML serves as an anode of the light emitting element LD, and the other serves as a cathode of the light emitting element LD.

[0131] In one example, the display panel PNL is an OLED display substrate. The light-emitting functional layer EFL may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.

[0132] In another example, the display panel PNL is a QLED display substrate. The light emitting functional layer EFL may include a quantum dot layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0133] In one embodiment of the present disclosure, see Figure 2, the display panel PNL is provided with a thin film encapsulation layer TFE on the surface of the pixel layer PXL away from the substrate SBT, and the thin film encapsulation layer TFE may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PXL and causing aging of the material in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of the present disclosure, the thin film encapsulation layer TFE may also adopt other structures, for example, a multi-layered inorganic encapsulation layer may be adopted. In other embodiments, the display panel may not be provided with a thin film encapsulation layer, but the pixel layer may be encapsulated and protected in other ways.

[0134] As follows, Figures 13 to 30 Taking the first layout example as an example, a first pixel driving circuit PDC1 of the embodiment of the present disclosure is exemplarily introduced. In the first layout example, the equivalent circuit of the first pixel driving circuit PDC1 is as follows: Figure 1 As shown. The driving layer DRL includes a first inorganic buffer layer BLA, a first semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BLB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer SD3 and a third planarization layer PLN3, which are stacked in sequence.

[0135] Fig.13 FIG. 4 is a schematic diagram of the local structure of the first source-drain metal layer SD1 in the first layout example. Fig.14 FIG. 4 is a schematic diagram of the local structure of the first semiconductor layer PSCL in the first layout example. Fig.15 It is a schematic diagram of the local structural stacking of the first semiconductor layer PSCL and the first source-drain metal layer SD1 in the first layout example of the present disclosure.

[0136] See also Fig.14The first semiconductor layer PSCL has channel regions of multiple thin film transistors, for example, a channel region T1A of a first transistor, a channel region T3A of a third transistor, a channel region T4A of a fourth transistor, a channel region T5A of a fifth transistor, a channel region T6A of a sixth transistor, a channel region T7A of a seventh transistor and a channel region T8A of an eighth transistor, and conductive parts located on both sides of the channel region as the first pole or the second pole of the thin film transistor.

[0137] See also Figure 13 to Figure 15 , the first semiconductor layer PSCL is provided with the second electrode of the fifth transistor T5 as part of the second node N2, the second electrode of the eighth transistor T8, the second electrode of the fourth transistor T4 and the first electrode of the third transistor T3 located in the first semiconductor layer PSCL. The first electrode of the third transistor T3, the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4 are connected to each other, and the second electrode of the eighth transistor T8 and the second electrode of the fifth transistor T5 are electrically connected to each other through the second conductive structure MA2 located in the first source-drain metal layer SD1. Among them, the second electrode of the fifth transistor T5 has a fourth bottom via area HA4, and the second conductive structure MA2 has a fourth top via area HB4; the fourth bottom via area HA4 overlaps with the fourth top via area HB4 and is overlapped through the via; the second electrode of the eighth transistor T8 has a fifth bottom via area HA5, and the second conductive structure MA2 has a fifth top via area HB5; the fifth bottom via area HA5 overlaps with the fifth top via area HB5 and is overlapped through the via.

[0138] The first semiconductor layer PSCL is provided with a second electrode of a first transistor T1 as part of a third node N3, a second electrode of a third transistor T3, and a first electrode of a sixth transistor T6. The second electrode of the third transistor T3 is connected to the first electrode of the sixth transistor T6, and the second electrode of the first transistor T1 is electrically connected to the second electrode of the third transistor T3 through the third conductive structure MA3 located in the first source-drain metal layer SD1. Among them, the second electrode of the first transistor T1 has a sixth bottom via area HA6, and the third conductive structure MA3 has a sixth top via area HB6; the sixth bottom via area HA6 overlaps with the sixth top via area HB6 and is overlapped through the via; the second electrode of the third transistor T3 has an eighth bottom via area HA8, and the third conductive structure MA3 has an eighth top via area HB8; the eighth bottom via area HA8 overlaps with the eighth top via area HB8 and is overlapped through the via.

[0139] The first semiconductor layer PSCL is provided with a second electrode of a sixth transistor T6 and a second electrode of a seventh transistor T7 as a part of a fourth node N4. The second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is electrically connected to the fourth conductive structure MA4 located in the first source-drain metal layer SD1 through a via. The second electrode of the sixth transistor T6 has a ninth bottom via area HA9, and the fourth conductive structure MA4 has a ninth top via area HB9; the ninth bottom via area HA9 overlaps with the ninth top via area HB9 and is overlapped through the via.

[0140] The first semiconductor layer PSCL is provided with a first electrode of a fifth transistor T5 as a part of a driving power supply voltage node. The first electrode of the fifth transistor T5 is electrically connected to the fifth conductive structure MA5 located in the first source-drain metal layer SD1 through a via. The first electrode of the fifth transistor T5 has a fifteenth bottom via area HA15, and the fifth conductive structure MA5 has a fifteenth top via area HB15. The fifteenth bottom via area HA15 and the fifteenth top via area HB15 overlap each other and are overlapped through the via.

[0141] The first semiconductor layer PSCL is provided with a first electrode of a fourth transistor T4 as a part of a data voltage node. The first electrode of the fourth transistor T4 is electrically connected to the sixth conductive structure MA6 located in the first source-drain metal layer SD1 through a via. The first electrode of the fourth transistor T4 has a sixteenth bottom via area HA16, and the sixth conductive structure MA6 has a sixteenth top via area HB16. The sixteenth bottom via area HA16 and the sixteenth top via area HB16 overlap each other and are overlapped through the via.

[0142] The first semiconductor layer PSCL is provided with a first electrode of a first transistor T1 as part of a first initialization voltage node. The first electrode of the first transistor T1 is electrically connected to the seventh conductive structure MA7 located in the first source-drain metal layer SD1 through a via. The first electrode of the first transistor T1 has a nineteenth bottom via area HA19, and the seventh conductive structure MA7 has a nineteenth top via area HB19. The nineteenth bottom via area HA19 and the nineteenth top via area HB19 overlap each other and are overlapped through the via.

[0143] The first semiconductor layer PSCL is provided with a first electrode of a seventh transistor T7 as a part of the second initialization voltage node. The first electrode of the seventh transistor T7 is electrically connected to the eighth conductive structure MA8 located in the first source-drain metal layer SD1 through a via. The first electrode of the seventh transistor T7 has a twenty-first bottom via area HA21, and the eighth conductive structure MA8 has a twenty-first top via area HB21. The twenty-first bottom via area HA21 and the twenty-first top via area HB21 overlap each other and are overlapped through the via.

[0144] The first semiconductor layer PSCL is provided with a first electrode of an eighth transistor T8 as a part of the third initialization voltage node. The first electrode of the eighth transistor T8 is electrically connected to the ninth conductive structure MA9 located in the first source-drain metal layer SD1 through a via. The first electrode of the eighth transistor T8 has a twenty-third bottom via area HA23, and the ninth conductive structure MA9 has a twenty-third top via area HB23, and the twenty-third bottom via area HA23 and the twenty-third top via area HB23 overlap each other and are overlapped through the via.

[0145] Fig.16 FIG. 1 is a schematic diagram of a partial structure of the first gate layer GT1 in the first layout example of the present disclosure. Fig.17 It is a schematic diagram of the partial structural stacking of the first semiconductor layer PSCL and the first gate layer GT1 in the first layout example of the present disclosure. Fig.18 It is a schematic diagram of the local structural stacking of the first gate layer GT1 and the first source-drain metal layer SD1 in the first layout example of the present disclosure.

[0146] See also Figure 16 to Figure 18 The first gate layer GT1 is provided with a first electrode CP1 of a storage capacitor as a part of the first node N1. The first electrode CP1 of the storage capacitor is overlapped with the channel region T3A of the third transistor and reused as the gate of the third transistor T3. The first electrode CP1 of the storage capacitor is electrically connected to the first conductive structure MA1 located in the first source-drain metal layer SD1 through a via. The first electrode CP1 of the storage capacitor has a second bottom via region HA2, and the first conductive structure MA1 has a second top via region HB2. The second bottom via region HA2 overlaps with the second top via region HB2 and is overlapped through the via.

[0147] The first gate layer GT1 is provided with a gate T4G of the fourth transistor T4 as a part of the first scan signal node. The gate T4G of the fourth transistor T4 is electrically connected to the first scan signal line GPL located in the first source-drain metal layer SD1 through a via. The gate T4G of the fourth transistor T4 has a first bottom via area HA1, and the first scan signal line GPL has a first top via area HB1. The first bottom via area HA1 and the first top via area HB1 overlap each other and are overlapped through the via.

[0148] The first gate layer GT1 is provided with a light emitting control line EML as a light emitting control signal terminal. The light emitting control line EML is used to load the light emitting control line EML and extends along the row direction DH; the light emitting control line EML overlaps with the channel region T5A of the fifth transistor and the channel region T6A of the sixth transistor to be multiplexed as the gate of the fifth transistor T5 and the gate of the sixth transistor T6.

[0149] The first gate layer GT1 is provided with a second reset signal line RHL as a second reset signal terminal. The second reset signal line RHL is used to load the second reset signal Reset_H and extends along the row direction DH; the second reset signal line RHL is overlapped with the channel region T7A of the seventh transistor and the channel region T8A of the eighth transistor respectively to be multiplexed as the gate of the seventh transistor T7 and the gate of the eighth transistor T8.

[0150] The first gate layer GT1 is provided with a first reset signal line RPL as a first reset signal terminal. The first reset signal line RPL is used to load the first reset signal Reset_P and extends along the row direction DH; the first reset signal line RPL overlaps with the channel region T1A of the first transistor of the next row of pixel driving circuits to serve as the gate of the first transistor T1 of the next row of pixel driving circuits.

[0151] Fig.19 Schematic diagram of the local structure of the second gate layer GT2 in the first layout example of the present disclosure. Fig. 20 It is a schematic diagram of the local structural stacking of the second gate layer GT2 and the first source-drain metal layer SD1 in the first layout example of the present disclosure. Fig.21 This is a schematic diagram of the local structure of the second semiconductor layer OSCL in the first layout example disclosed in the present invention. Fig. 22 It is a schematic diagram of the partial structural stacking of the second gate layer GT2 and the second semiconductor layer OSCL in the first layout example of the present disclosure. Fig.23 It is a schematic diagram of the partial structural stacking of the second semiconductor layer OSCL and the first source-drain metal layer SD1 in the first layout example of the present disclosure.

[0152] See also Figure 19 to Figure 23 , the second gate layer GT2 is provided with a second electrode CP2 of a storage capacitor as part of a driving power supply voltage node. The second electrode CP2 of the storage capacitor is electrically connected to the fifth conductive structure MA5 located on the first source-drain metal layer SD1 through a via. Among them, the second electrode CP2 of the storage capacitor has a fourteenth bottom via area HA14, and the fifth conductive structure MA5 has a fourteenth top via area HB14, and the fourteenth bottom via area HA14 and the fourteenth top via area HB14 overlap with each other and are overlapped through vias. Optionally, the second electrodes CP2 of adjacent storage capacitors in the same row are electrically connected to each other, so that the distribution of the driving power supply voltage VDD is gridded, thereby improving the uniformity of the distribution of the driving power supply voltage VDD.

[0153] The second gate layer GT2 is provided with a second scan signal bottom wiring GNLA as a second scan signal terminal. The second scan signal bottom wiring GNLA is used to load the second scan signal Gate_N and extends along the row direction DH; the second scan signal bottom wiring GNLA overlaps with the channel region T2A of the second transistor to serve as the bottom gate of the second transistor T2.

[0154] The second semiconductor layer OSCL is provided with an active layer of a second transistor T2, and the active layer of the second transistor T2 includes a first electrode of the second transistor T2, a channel region T2A of the second transistor, and a second electrode T2D of the second transistor T2 connected in sequence. The second electrode T2D of the second transistor T2 serves as a part of the first node N1. The second electrode T2D of the second transistor T2 is electrically connected to the first conductive structure MA1 located in the first source-drain metal layer SD1 through a via. Among them, the second electrode T2D of the second transistor T2 has a third bottom via region HA3, and the first conductive structure MA1 has a third top via region HB3, and the third bottom via region HA3 overlaps with the third top via region HB3 and is overlapped through the via. The first electrode of the second transistor T2 serves as a part of the third node N3. The first electrode of the second transistor T2 is electrically connected to the third conductive structure MA3 located in the first source-drain metal layer SD1 through a via. The first electrode of the second transistor T2 has a seventh bottom via region HA7, the third conductive structure MA3 has a seventh top via region HB7, and the seventh bottom via region HA7 and the seventh top via region HB7 overlap with each other and are overlapped through vias.

[0155] Figure 3 This is a partial schematic diagram of the first layout example, see Figure 3 The gate electrode T4G of the fourth transistor T4 is overlapped with the second electrode T2D of the second transistor T2 so that a large coupling capacitance exists between the first scan signal terminal and the first node N1.

[0156] Fig.24 Schematic diagram of the local structure of the third gate layer GT3 in the first layout example of the present disclosure. Fig.25 It is a schematic diagram of the local structural stacking of the second semiconductor layer OSCL and the third gate layer GT3 in the first layout example of the present disclosure. Fig.26 It is a schematic diagram of the local structural stacking of the third gate layer GT3 and the first source-drain metal layer SD1 in the first layout example of the present disclosure.

[0157] See also Figure 24 to Figure 26The third gate layer GT3 is provided with a first initialization voltage line VTL1 as a first initialization voltage terminal. The first initialization voltage line VTL1 is used to load the first initialization voltage Vinit1 and extends along the row direction DH. The first initialization voltage line VTL1 is electrically connected to the seventh conductive structure MA7 located in the first source and drain metal layer SD1 through a via. Among them, the first initialization voltage line VTL1 has a twentieth bottom via area HA20, and the seventh conductive structure MA7 has a twentieth top via area HB20, and the twentieth bottom via area HA20 and the twentieth top via area HB20 overlap each other and are overlapped through the via.

[0158] The third gate layer GT3 is provided with a second initialization voltage line VTL2 as a second initialization voltage terminal. The second initialization voltage line VTL2 is used to load the second initialization voltage Vinit2 and extends along the row direction DH. The second initialization voltage line VTL2 is electrically connected to the eighth conductive structure MA8 located in the first source-drain metal layer SD1 through a via. Among them, the second initialization voltage line VTL2 has a twenty-second bottom via area HA22, and the eighth conductive structure MA8 has a twenty-second top via area HB22, and the twenty-second bottom via area HA22 and the twenty-second top via area HB22 overlap each other and are overlapped through the via.

[0159] The third gate layer GT3 is provided with a third initialization voltage line VTL3 as a third initialization voltage terminal. The third initialization voltage line VTL3 is used to load the third initialization voltage Vinit3 and extends along the row direction DH. The third initialization voltage line VTL3 is electrically connected to the ninth conductive structure MA9 located in the first source and drain metal layer SD1 through a via. Among them, the third initialization voltage line VTL3 has a twenty-fourth bottom via area HA24, and the ninth conductive structure MA9 has a twenty-fourth top via area HB24, and the twenty-fourth bottom via area HA24 and the twenty-fourth top via area HB24 overlap each other and are overlapped through the via.

[0160] The third gate layer GT3 is provided with a second scan signal top wiring GNLB as a second scan signal terminal. The second scan signal top wiring GNLB is used to load the second scan signal Gate_N and extends along the row direction DH; the second scan signal top wiring GNLB overlaps with the channel region T2A of the second transistor to serve as the top gate of the second transistor T2.

[0161] Fig. 27 Schematic diagram of the local structure of the second source / drain metal layer SD2 in the first layout example disclosed in the present invention. Fig.28 Schematic diagram of the local structural stacking of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 in the first layout example of the present disclosure. Fig.29Schematic diagram of the local structure of the third source-drain metal layer SD3 in the first layout example of the present disclosure. Fig.30 Schematic diagram of the local structural stacking of the second source-drain metal layer SD2 and the third source-drain metal layer SD3 in the first layout example of the present disclosure.

[0162] See also Figure 27 to Figure 30 The second source-drain metal layer SD2 is provided with a tenth conductive structure MB1 as a part of the fourth node N4. The tenth conductive structure MB1 is electrically connected to the thirteenth conductive structure MC1 located in the third source-drain metal layer SD3 through a via. The tenth conductive structure MB1 has an eleventh bottom via area HA11, and the thirteenth conductive structure MC1 has an eleventh top via area HB11. The eleventh bottom via area HA11 and the eleventh top via area HB11 overlap each other and are overlapped through vias.

[0163] The second source-drain metal layer SD2 is provided with an eleventh conductive structure MB2 as a part of the driving power supply voltage node. The eleventh conductive structure MB2 is electrically connected to the driving power supply voltage routing line VDDL located in the third source-drain metal layer SD3 through a via, and is electrically connected to the fifth conductive structure MA5 located in the first source-drain metal layer SD1 through a via. Among them, the eleventh conductive structure MB2 has a twelfth bottom via area HA12 and a thirteenth top via area HB13; the fifth conductive structure MA5 has a thirteenth bottom via area HA13, the thirteenth bottom via area HA13 and the thirteenth top via area HB13 overlap each other and are overlapped through vias. The driving power supply voltage routing line VDDL has a twelfth top via area HB12, the twelfth bottom via area HA12 and the twelfth top via area HB12 overlap each other and are overlapped through vias. Optionally, the eleventh conductive structure MB2 extends along the row direction DH to form a routing line, which makes the distribution of the driving power supply voltage VDD grid-like, and can improve the uniformity of the driving power supply voltage VDD.

[0164] The second source-drain metal layer SD2 is provided with a twelfth conductive structure MB3 as a part of the driving power supply voltage node. The twelfth conductive structure MB3 is electrically connected to the data line DL located in the third source-drain metal layer SD3 through a via. The twelfth conductive structure MB3 has an eighteenth bottom via area HA18, and the data line DL has an eighteenth top via area HB18. The eighteenth bottom via area HA18 and the eighteenth top via area HB18 overlap each other and are overlapped through the via.

[0165] The third source-drain metal layer SD3 is provided with a thirteenth conductive structure MC1 as a part of the fourth node N4. The thirteenth conductive structure MC1 is used to be electrically connected to the pixel electrode through a via hole so that the driving current of the pixel driving circuit is loaded to the light emitting element LD.

[0166] The third source-drain metal layer SD3 is provided with a driving power voltage VDD as a driving power voltage terminal. The driving power voltage line VDDL is used to load the driving power voltage VDD and extends along the column direction DV.

[0167] The third source-drain metal layer SD3 is provided with a data line DL as a data voltage terminal. The data line DL is used to load the data voltage Vdata and extends along the column direction DV.

[0168] In the first layout example of the present disclosure, the display panel PNL is also provided with a plurality of auxiliary routing lines extending along the column direction DV. The auxiliary routing lines may include one or more types, and any auxiliary routing line may be connected to a certain voltage routing line to improve the uniformity of the voltage distribution. Among them, the auxiliary routing lines may avoid the routing lines extending along the row direction DH by means of bridging. Optionally, the auxiliary routing lines may include alternatingly connected main routing lines segments and bridging routing lines segments; the main routing lines segments may be arranged in the first source and drain metal layer SD1 and extend along the column direction DV; the bridging routing lines segments may be arranged in the second gate layer GT2 and extend along the column direction DV. The main routing lines segments and the bridging routing lines segments may be connected by vias. In this way, with the help of the bridging routing lines segments, the auxiliary routing lines may avoid the first scanning signal routing lines GPL and other routing lines.

[0169] As an example of auxiliary routing, Fig.13 FIG. 4 schematically shows a main wiring segment VTX1 of an auxiliary wiring for loading a second initialization voltage Vinit2. Fig.19 FIG. 4 illustrates a bridge wiring segment VTX2 of an auxiliary wiring for loading a second initialization voltage Vinit2. Fig. 20 This auxiliary routing is shown in Figure 2. Fig. 20 The auxiliary wiring for loading the second initialization voltage Vinit2 includes a main wiring segment VTX1 arranged on the first source-drain metal layer SD1, and a bridge wiring segment VTX2 arranged on the second gate layer GT2. The main wiring segment VTX1 and the bridge wiring segment VTX2 are electrically connected through vias. In the first source-drain metal layer SD1, the main wiring segments VTX1 are disconnected before two adjacent main wiring segments VTX1 to avoid the first scan signal wiring GPL; the bridge wiring segment VTX2 crosses the first scan signal wiring GPL to ensure the electrical continuity of the auxiliary wiring. See Fig.26 At the intersection of the auxiliary wiring and the second initialization voltage wiring VTL2, the main wiring segment VTX1 can be electrically connected to the second initialization voltage wiring VTL2 through a via.

[0170] The present disclosure also provides a second layout example, in which the display panel PNL is not provided with a third source-drain metal layer SD3, and is not provided with an auxiliary wiring. The second layout example is substantially consistent with the first layout example in terms of the first semiconductor layer PSCL, the first gate layer GT1, the second gate layer GT2, the second semiconductor layer OSCL, the third gate layer GT3 and other film layers. Fig.31 is a schematic diagram of the local structure of the first source-drain metal layer SD1 in the second layout example, Fig.32 is a schematic diagram of the local structure of the second source-drain metal layer SD2 in the second layout example, Fig.33 FIG. 1 is a schematic diagram of a partial stacking structure of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 in the second layout example. Fig.31 The structure of the first source-drain metal layer SD1 of the second layout example is generally similar to that of the first layout example, with the main difference being that the fifth conductive structure MA5 has a side branch structure, which is used to be electrically connected to the driving power supply voltage line VDDL disposed on the second source-drain metal layer SD2 through a via. Specifically, the fifth conductive structure MA5 has a twenty-fourth bottom via area HA24, and the driving power supply voltage line VDDL located on the second source-drain metal layer SD2 has a twenty-fourth top via area HB24, and the twenty-fourth bottom via area HA24 overlaps with the twenty-fourth top via area HB24 and is electrically connected through a via. The second source-drain metal layer SD2 is provided with a fourteenth conductive structure MB4, and the fourteenth conductive structure MB4 has a tenth top via area HB10, and the tenth top via area HB10 overlaps with the tenth bottom via area HA10 on the fourth conductive structure MA4 and is connected through a via. In this way, the fourteenth conductive structure MB4 can be used as the output end of the pixel driving circuit and electrically connected to the light-emitting element LD. The data line DL on the second source-drain metal layer SD2 is provided with a seventeenth top via area HB17, which can overlap with the seventeenth bottom via area HA17 located on the sixth conductive structure MA6 and be electrically connected through the via, so that the data voltage Vdata can be loaded to the first electrode of the fourth transistor T4 through the sixth conductive structure MA6.

[0171] It is understandable that the improved pixel driving circuit provided in the embodiment of the present disclosure, namely the first pixel driving circuit PDC1, is not limited to Figure 1 The layout setting of the structure illustrated is not limited to the first layout example or the second layout example of the present disclosure.

[0172] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a base substrate, a driving layer and a pixel layer stacked in sequence; the driving layer has a pixel driving circuit for driving sub-pixels; The pixel driving circuit includes a second transistor, a third transistor, a fourth transistor and a storage capacitor; the second electrode of the second transistor is electrically connected to the gate of the third transistor and the first electrode of the storage capacitor, and the fourth transistor is used to write a data voltage to the storage capacitor; the third transistor is used to control the magnitude of the output driving current according to the voltage on the gate of the third transistor; the display panel is provided with a first scanning signal line electrically connected to the gate of the fourth transistor; the gate of the fourth transistor and the first scanning signal line are located in different film layers; The pixel driving circuit comprises at least a first pixel driving circuit; In the first pixel driving circuit, the gate of the fourth transistor has a first coupling structure, and the second electrode of the second transistor has a second coupling structure; The orthographic projection of the first coupling structure on the substrate at least partially overlaps with the orthographic projection of the second coupling structure on the substrate.

2. The display panel according to claim 1, wherein: In the first pixel driving circuit, the width of the second coupling structure is greater than the width of the channel region of the second transistor; An extending direction of the first coupling structure is parallel to a length direction of the second coupling structure.

3. The display panel according to claim 2, wherein: In the first pixel driving circuit, the first coupling structure and the second coupling structure both extend in the row direction; in the column direction, the orthographic projection of the second coupling structure on the substrate does not exceed the orthographic projection of the first coupling structure on the substrate, or the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

4. The display panel according to claim 1, wherein: In the first pixel driving circuit, the first coupling structure and the second coupling structure both extend along a row direction; Along the row direction, both ends of the first coupling structure exceed the second coupling structure; Along the column direction, the orthographic projection of the first coupling structure on the base substrate does not exceed the orthographic projection of the second coupling structure on the base substrate.

5. The display panel according to claim 4, wherein: In the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion and the first coupling structure connected in sequence; the second metal portion is overlapped and connected to the first scanning signal wiring through a via hole; A width of the first coupling structure is smaller than a width of the first metal portion.

6. The display panel according to claim 4, wherein: In the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure and a first connecting portion; the first connecting portion extends along the column direction, one end of the first connecting portion is connected to an end of the second coupling structure away from the channel region of the fourth transistor, and the other end of the first connecting portion is electrically connected to the channel region of the second transistor.

7. The display panel according to claim 1, wherein: In the first pixel driving circuit, the first coupling structure and the second coupling structure both extend along a row direction; along the row direction, one end of the first coupling structure does not exceed the second coupling structure; The gate of the fourth transistor includes a first metal portion, a second metal portion and the first coupling structure connected in sequence; The second metal portion is overlapped and connected with the first scanning signal wiring through a via hole; the width of the first coupling structure is greater than the width of the first metal portion; The width of the second coupling structure is greater than the width of the channel region of the second transistor.

8. The display panel according to claim 7, wherein: In the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure, the second connection part and the first connection part which are connected in sequence; the second connection part extends along the row direction, and the first connection part extends along the column direction; the width of the second connection part and the first connection part is smaller than the width of the second coupling structure.

9. The display panel according to claim 1, wherein: In the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, a third metal portion and the first coupling structure connected in sequence, the second metal portion is overlapped and connected to the first scanning signal wiring through a via hole; the gate of the fourth transistor extends in a row direction, and a size of the first coupling structure in a column direction is larger than a size of the third metal portion in the column direction; The second electrode of the second transistor includes the second coupling structure, the first connection part and the second connection part connected in sequence; the first connection part extends along the row direction, and the second connection part extends along the column direction; the size of the second coupling structure in the column direction is larger than the size of the second connection part in the column direction.

10. The display panel according to claim 1, wherein: The third transistor and the fourth transistor are P-type thin film transistors.

11. The display panel according to claim 1, wherein: The pixel layer has sub-pixels of multiple different colors; the pixel driving circuit used to drive the sub-pixels with the highest luminous efficiency is the first pixel driving circuit.

12. The display panel according to claim 1, wherein: Each pixel driving circuit is the first pixel driving circuit.

13. The display panel according to claim 12, wherein: The pixel layer has a plurality of sub-pixels of different colors, the sub-pixels include a first sub-pixel and a second sub-pixel, and the luminous efficiency of the first sub-pixel is greater than the luminous efficiency of the second sub-pixel; The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the first pixel driving circuit; Among them, in the first pixel driving circuit that drives the first sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is a first area; in the first pixel driving circuit that drives the second sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is a second area; the first area is greater than the second area.

14. The display panel according to claim 1, wherein: The pixel layer has a plurality of sub-pixels of different colors, the sub-pixels include a first sub-pixel and a second sub-pixel, and the luminous efficiency of the first sub-pixel is greater than the luminous efficiency of the second sub-pixel; The pixel driving circuit comprises a second pixel driving circuit, wherein the gate of the fourth transistor of the second pixel driving circuit does not overlap with the second electrode of the second transistor; The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the second pixel driving circuit. 15 . A display device, comprising the display panel according to claim 1 , and a driving module for driving the display panel.

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