Packaging core plate, packaging substrate and preparation method thereof

Abstract

The invention provides a packaging core plate, a packaging substrate and a preparation method thereof, and relates to the technical field of semiconductor packaging. The packaging core board preparation method comprises the steps that a core board is provided, the core board is provided with a front face and a back face which are opposite, a plurality of interconnection holes are formed in the core board, and the interconnection holes are arranged at intervals and penetrate through the core board; forming a groove in the front surface of the core plate; forming a conductive interconnection layer, wherein the conductive interconnection layer comprises a first conductive layer formed above the metal seed layer on the surface of the groove, conductive columns filling the interconnection holes, and patterned second conductive layers formed on the front surface and the back surface of the core plate; and mounting a passive device in the groove. According to the packaging core plate, the passive devices mounted on the surface of an existing packaging substrate are embedded into the grooves of the packaging core plate, the space, used for mounting the passive devices, of the surface of the packaging substrate is released, the surface space utilization rate of the packaging substrate is increased, more integrated chips can be mounted on the surface of the packaging substrate, and the packaging effect is improved. Therefore, the interconnection performance of the packaging substrate is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor integrated circuit technology, and in particular, relates to a packaging core board, a packaging substrate and a preparation method thereof. Background Art

[0002] With the rapid development of electronic technology, the number of I / O pins on chips continues to increase, and the circuits of packaging substrates are becoming more and more sophisticated, which puts higher requirements on packaging substrates. At the same time, packaging substrates are constantly developing in the direction of more layers. In the production process of packaging substrates, due to the different thermal expansion coefficients of each layer of material, after the thermal process pressing, the packaging substrate is prone to warping. Excessive substrate warping usually leads to poor contact between the substrate and the chip or the solder joints on the circuit board during packaging, and even causes some pads of the substrate to be unable to contact the solder to form solder joints during wave soldering, which seriously affects the reliability of the product.

[0003] Since glass has the characteristics of high toughness, low thermal expansion coefficient, and good thermal conductivity, using glass core board as the core board layer of the packaging substrate can effectively reduce the warping of the packaging substrate and improve the reliability of the packaging substrate. However, the passive devices such as capacitors and resistors mounted on the surface of the packaging substrate greatly affect the surface space utilization of the packaging substrate and reduce the mounting density of the chip, thus limiting the interconnection performance of the packaging substrate to a certain extent.

[0004] Therefore, it is necessary to provide an improved technical solution to address the deficiencies in the above-mentioned prior art. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a packaging core board, a packaging substrate and a preparation method thereof, so as to solve at least one of the above-mentioned series of problems faced in the packaging process in the prior art.

[0006] To achieve the above-mentioned and other related purposes, the present application provides a method for preparing a packaging core board, comprising the following steps:

[0007] Providing a core plate, the core plate having a front side and a back side opposite to each other, and forming a plurality of interconnected holes in the core plate, the interconnected holes being arranged at intervals and penetrating the core plate;

[0008] forming a groove on the front side of the core plate;

[0009] Forming a metal seed layer covering the surface of the core board and the sidewalls of the interconnection holes, and forming a patterned shielding layer on the surface of the metal seed layer to expose the metal seed layer corresponding to the groove;

[0010] forming a metal interconnect layer covering the exposed surface of the metal seed layer based on the patterned shielding layer;

[0011] The shielding layer and the metal seed layer corresponding to the bottom of the shielding layer are removed to obtain the conductive interconnection layer; the conductive interconnection layer includes a first conductive layer formed above the metal seed layer on the surface of the groove, a conductive column filling the interconnection hole, and a patterned second conductive layer formed on the front and back sides of the core board;

[0012] Passive components are mounted in the grooves.

[0013] In one embodiment, the cross-sectional shape of the groove is rectangular or trapezoidal with a relatively large opening.

[0014] In one embodiment, the passive component is mounted by dispensing glue in the groove or mounting an adhesive film on the mounting surface of the passive component.

[0015] In one embodiment, the core plate is one of alkali-free glass, alkali glass, aluminum oxide glass, high borosilicate glass and quartz glass.

[0016] In one embodiment, a method of forming the interconnection holes and the grooves includes mechanical drilling or laser induced etching.

[0017] In one embodiment, the steps of forming the conductive interconnect layer include film lamination, exposure, development, electroplating, film stripping and etching.

[0018] The present application also provides a method for preparing a packaging substrate, comprising the following steps:

[0019] Providing a packaging core board prepared by the preparation method of any one of the above technical solutions;

[0020] forming a dielectric layer on the front side and the back side of the packaging core board;

[0021] Patterning the dielectric layer to form a blind hole penetrating the dielectric layer;

[0022] A patterned circuit connection layer electrically connected to the packaging core board is formed based on the blind hole.

[0023] In one embodiment, the steps of preparing the dielectric layer and the circuit connection layer are repeated until the required number of build-up layers is completed to form the packaging substrate.

[0024] The present application also provides a packaging core board, which is prepared by the preparation method described in any one of the above technical solutions, and includes: a core board, a patterned metal seed layer and a conductive interconnect layer; wherein,

[0025] The core plate has a front side and a back side opposite to each other, and interconnected holes are arranged on the core plate at intervals and penetrate the core plate;

[0026] A groove is arranged on the front side of the core plate;

[0027] The metal seed layer covers the front and back surfaces of the core board and the surfaces of the interconnecting holes;

[0028] The conductive interconnection layer covers the surface of the metal seed layer and fills the interconnection holes.

[0029] The present application also provides a packaging substrate, comprising a packaging core board and at least one build-up layer as described in the above technical solution; wherein,

[0030] The build-up layer includes a dielectric layer and a circuit connection layer, a blind hole penetrating the dielectric layer is formed in the dielectric layer, and the circuit connection layer fills the blind hole and extends to a portion of the surface of the dielectric layer;

[0031] The circuit connection layer of the build-up layer is connected to the conductive interconnect layer of the package core board.

[0032] As described above, compared with the prior art, the technical solution provided by this application has the following beneficial effects:

[0033] 1. The present application optimizes the preparation method of the packaging core board and the packaging substrate, processes grooves on the surface of the core board, and embeds the passive devices mounted on the surface of the existing packaging substrate into the grooves of the packaging core board, thereby releasing the space on the surface of the packaging substrate for mounting passive devices, thereby improving the surface space utilization of the packaging substrate, allowing more integrated chips to be mounted on the surface of the packaging substrate, thereby promoting the improvement of the interconnection performance of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of the core board in the method for preparing the packaged core board of the present application;

[0035] Figure 2 This is a schematic diagram of the structure of forming grooves and interconnected holes in the method for preparing the package core board of the present application;

[0036] Figure 3 This is a schematic diagram of the structure of forming a metal seed layer in the method for preparing a package core board of the present application;

[0037] Figure 4 This is a schematic diagram of the structure of the laminating shielding layer in the method for preparing the package core board of the present application;

[0038] Figure 5 This is a schematic diagram of the structure of forming a metal interconnection layer in the method for preparing a package core board of the present application;

[0039] Figure 6A schematic diagram of the structure of the package core board for this application;

[0040] Figure 7 This is a schematic diagram of the structure after passive devices are embedded in the package core board of this application;

[0041] Figure 8 This is a schematic structural diagram of forming a dielectric layer in the method for preparing a packaging substrate of the present application;

[0042] Fig. 9 This is a schematic structural diagram of forming a second metal seed layer in a build-up layer of a package substrate of the present application;

[0043] Fig.10 This is a schematic diagram of a structure in which a second shielding layer is bonded to a build-up layer of a packaging substrate of the present application;

[0044] Fig.11 This is a schematic diagram of a structure in which a conductive interconnect layer is formed in a build-up layer of a packaging substrate of the present application;

[0045] Fig.12 This is a schematic diagram of a structure in which a circuit connection layer is formed in a build-up layer of a package substrate of the present application;

[0046] Fig.13 This is a schematic diagram of the structure after forming a multi-layer build-up layer in the method for preparing a packaging substrate of the present application;

[0047] Fig.14 It is a schematic diagram of the structure after the solder mask layer and the surface treatment layer are formed in the preparation method of the packaging substrate of the present application.

[0048] Component number description:

[0049] 100 package core board

[0050] 101 Core Board

[0051] 102 grooves

[0052] 103 interconnecting holes

[0053] 104 Metal seed layer

[0054] 105 shielding layer

[0055] 106 Metal Interconnect Layer

[0056] 107 Passive Components

[0057] 108 adhesive layer

[0058] 110 first conductive layer

[0059] 120 second conductive layer

[0060] 130 Conductive Column

[0061] 201 Dielectric layer

[0062] 202 Blind hole

[0063] 203 second metal seed layer

[0064] 204 Second shielding layer

[0065] 205 Second metal interconnection layer

[0066] 206 solder mask

[0067] 207 Surface treatment layer

[0068] A1 First Addition Layer

[0069] A2 Second Addition Floor DETAILED DESCRIPTION

[0070] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and principles of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0071] Please note that Figures 1 to 14 The structures, proportions, sizes, etc. illustrated in the drawings of the specification of this application are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0072] The prior art packaging method of passive devices such as capacitors and resistors mounted on the surface of the packaging substrate greatly affects the surface space utilization of the packaging substrate and reduces the mounting density of the chip, thereby limiting the interconnection performance of the packaging substrate to a certain extent.

[0073] Therefore, the present application provides a packaging core board, a packaging substrate and a preparation method thereof, which are used to solve the above-mentioned problems faced in the packaging process in the prior art. The technical solution of the present application will be described in detail through the following specific embodiments.

[0074] Embodiment 1:

[0075] This embodiment provides a method for preparing a package core board, comprising the following steps:

[0076] A core plate 101 is provided, wherein the core plate 101 has a front side and a back side opposite to each other, and a plurality of interconnected holes 103 are formed in the core plate 101, wherein the interconnected holes 103 are arranged at intervals and penetrate the core plate 101;

[0077] A groove 102 is formed on the front side of the core plate 101;

[0078] Forming a conductive interconnection layer, the conductive interconnection layer comprising a first conductive layer 110 formed on the metal seed layer 104 on the surface of the groove 102, a conductive column 130 filling the interconnection hole 103, and a patterned second conductive layer 120 formed on the front and back sides of the core board 101;

[0079] A passive component 107 is mounted in the groove 102 .

[0080] The preparation method of the packaging core board of this embodiment releases the space on the surface of the packaging substrate for mounting the passive device 107 by processing the groove 102 for embedding the passive device 107 on the core board 101. Embedding the passive device 107 inside the groove 102 can also reduce the overall warping deformation of the packaging substrate, so that the product has better coplanarity, thereby promoting the improvement of the quality stability and interconnection performance of the packaging substrate.

[0081] The following is combined with Figures 1 to 14 , further introduces the preparation method of the packaging core board and the structure of the packaging core board, specifically including:

[0082] First, see Figures 1-2 , providing a core plate 101, the core plate 101 having a front side and a back side opposite to each other, and forming a plurality of interconnected holes 103 in the core plate 101, the interconnected holes 103 are arranged at intervals and penetrate the core plate 101; a groove 102 is formed on the front side of the core plate 101.

[0083] As an example, the core plate 101 is one of alkali-free glass, alkaline glass, aluminum oxide glass, high borosilicate glass and quartz glass, wherein the thickness of the core plate 101 is between 0.2 and 1.2 mm, the thermal expansion coefficient is between 1 ppm / °C and 10 ppm / °C, and the thermal conductivity is between 1 W / m·K and 5 W / m·K. It should be noted that the parameters in this embodiment are all data ranges including endpoint values, for example, the thickness of the core plate 101 is between 0.2 mm and 1.2 mm, and can be 0.2 mm, 0.6 mm, 0.8 mm, 1.0 mm or 1.2 mm, etc.

[0084] Specifically, when the grooves 102 and the interconnecting holes 103 are made on the core board 101, mechanical drilling or laser induced etching methods can be used, but are not limited to the above methods; wherein, in the process of forming the grooves 102, laser induced etching is preferred. The extremely small laser focused spot and highly circular hole structure produced in this method can ensure the hole-forming stability of the morphological dimensions of the grooves 102, and reserve precise accommodation space for the installation of the passive device 107, thereby ensuring the working stability of the passive device 107 and the product quality of the packaged core board.

[0085] Furthermore, when the groove 102 is formed by an etching process, the etching degree gradually decreases as the depth extends. Therefore, the groove 102 with a preset size can be formed by controlling the etching process parameters. Generally, the groove 102 is formed into a trapezoidal cross-sectional structure with a relatively large opening. Figure 2 The two groove structures on the right side of the middle, by controlling the process parameters, the depth of the groove 102 with a trapezoidal cross-section is between 5μm and 800μm, the upper width of the groove 102 is between 100μm and 100mm, and the bottom width of the groove 102 is between 80μm and 80mm. The formation of the groove 102 with the above structural parameters can better make the dielectric layer uniformly filled, and has a better filling effect and better reliability than the existing vertical grooves. Preferably, the side wall inclination angle range of the groove 102 is between 89.9 degrees and 70 degrees. The setting of this angle range can meet the requirements of dielectric layer filling, prevent the generation of bubbles, and cause poor reliability problems, and obtain the beneficial effect of improving the yield. Preferably, the depth of the groove 102 is specifically 100μm, the upper width is 5.25mm, and the side wall inclination angle of the groove 102 is 80 degrees.

[0086] Next, see Figures 3 to 6 , Figures 3 to 6 The packaging core board forming process in the figure shows two different groove structures: a groove with a rectangular cross-section and a groove with a trapezoidal cross-section obtained by different hole forming methods. Figures 3 to 6 The step of forming the conductive interconnection layer on the core board 110 having the groove 102, wherein the conductive interconnection layer includes a metal interconnection layer 106 corresponding to the metal seed layer 104, and the step of preparing the conductive interconnection layer includes:

[0087] A metal seed layer 104 is formed to cover the surface of the core board 101 and the sidewalls of the interconnection hole 103, and a patterned shielding layer 105 is formed on the surface of the metal seed layer 104 to expose the metal seed layer 104 corresponding to the groove 102; a metal interconnection layer 106 is formed to cover the exposed surface of the metal seed layer 104 based on the patterned shielding layer 105, and the shielding layer 105 and the metal seed layer 104 corresponding to the bottom of the shielding layer 105 are removed to obtain a conductive interconnection layer.

[0088] Specifically, see first Figure 3 , a chemical copper deposition process is used to form a metal seed layer 104 on the front and back of the core board 101, that is, the metal seed layer 104 is covered on the surface of the entire structure. The metal seed layer 104 not only provides a growth basis for the metal interconnect layer 106, but also plays a role in protecting the structure of the groove 102, preventing the groove from being structurally damaged in subsequent processes and failing to form a suitable installation position for the passive device 107. The method for forming the metal seed layer 104 is not limited here, and copper metal layer covering methods such as magnetron sputtering and chemical evaporation can also be used. Since copper has good thermal conductivity and has excellent performance in heat transfer and heat dissipation, that is, copper has good thermal uniformity and can evenly conduct heat to adjacent parts of the core board structure, preventing the active device 107 in the groove 102 from affecting its service life due to excessively high operating temperatures. In addition, copper has a relatively low thermal expansion coefficient, which means that when the temperature changes, the volume change of the copper material is relatively small, which makes the copper deposited layer in the groove 102 more stable in high temperature environments and more firmly attached to the groove 102, ensuring the stability and efficiency of electrical signal transmission as a conductive layer.

[0089] Next, see Figure 4 A shielding layer 105 is attached to the surface of the metal seed layer 104. The shielding layer 105 is a photosensitive material, and then an exposure and development process is performed to produce a conductive pattern outline on the core board 101, and at the same time, the groove 102 is protected and filled.

[0090] Next, see Figures 5-6 , a conductive interconnection pattern is produced by electroplating, and then the shielding layer 105 is removed, and then the metal seed layer 104 corresponding to the bottom of the shielding layer 105 is removed to prepare a package core board. Among them, the method of removing the shielding layer 105 and the metal seed layer 104 corresponding to the bottom of the shielding layer 105 can be selected from the flash etching process.

[0091] Understandable, continue to see Figure 6In the package core board obtained by the preparation method provided in this embodiment, the conductive interconnection layer is divided into three parts by structure, namely, the first conductive layer 110 formed above the metal seed layer 104 on the surface of the groove 102, the conductive column 130 filling the interconnection hole 103, and the patterned second conductive layer 120 formed on the front and back sides of the core board 101. Preferably, the thickness ratio of the metal seed layer 104 and the first conductive layer 110 sequentially formed in the groove 102 is between 0.005 and 1, preferably, the thickness ratio of the metal seed layer 104 and the first conductive layer 110 is between 0.05-1, for example, 0.05:1, 0.1:1, 0.2:1, 0.5:1 and 1:1. By controlling the sputtering and copper plating process to obtain a stack with a preset thickness ratio, the thickness ratio parameter setting can better control the overall thickness of the conductive layer and achieve the best conductive effect. Preferably, the thickness of the first conductive layer 110 is 15μm.

[0092] Finally, see Figure 7 , and the passive component 107 is mounted.

[0093] Specifically, there are two ways to mount the passive device 107. One is to apply silver glue in the groove 102, and then place the passive device 107 in the groove 102 for positioning and mounting; the other is to first apply adhesive film on the bonding surface of the passive device 107, and then mount the passive device 107 in the groove 102. Specifically, the material of the adhesive film is a DAF film with a thinner and flatter structure, and the film thickness is preferably 5μm to 20μm, to ensure that the upper surface of the passive device 107 after mounting is lower than the front horizontal surface of the core board 101.

[0094] This embodiment also provides a packaging core board, which is prepared by the preparation method of the above technical solution, see Figures 6-7 , comprising: a core board 101, a patterned metal seed layer 104 and a patterned metal interconnect layer 106; wherein,

[0095] The core plate 101 has a front side and a back side opposite to each other, and interconnected holes 103 are arranged at intervals on the core plate 101 and penetrate the core plate 101;

[0096] The front side of the core plate 101 is provided with a groove 102;

[0097] The metal seed layer 104 covers the front and back surfaces of the core board 101 and the surfaces of the interconnection holes 103;

[0098] The metal interconnection layer 106 covers the surface of the metal seed layer 104 and fills the interconnection holes 103 .

[0099] The present embodiment provides a packaging core board with a groove 102, and the passive device 107 located on the packaging substrate in the prior art is embedded in the groove 102 of the core board 101, so that the passive device 107 can be invisible mounted, freeing up the space on the surface of the packaging substrate for mounting the passive device 107, and reducing the warping deformation of the product during the packaging process. Since the passive device 107 is completely located inside the groove 102, the obtained packaging core board has better coplanarity and thus has better structural stability.

[0100] Embodiment 2:

[0101] This embodiment provides a method for preparing a packaging substrate, comprising the following steps:

[0102] A packaging core board 100 prepared by the method for preparing the packaging core board in Example 1 is provided;

[0103] Forming a dielectric layer 201 on the front and back sides of the package core board 100;

[0104] Patterning the dielectric layer 201 to form a blind hole 202 penetrating the dielectric layer 201;

[0105] A patterned circuit connection layer electrically connected to the package core board 100 is formed based on the blind hole 202;

[0106] The steps of preparing the dielectric layer 201 and the circuit connection layer are repeated until the required number of build-up layers is completed to form the package substrate.

[0107] The preparation method of the packaging substrate of the present embodiment is to manufacture multiple build-up layers on the packaging core board 100 in which the passive device 107 has been embedded. Since the packaging core board 100 has a flat surface, the prepared packaging substrate also has good flatness, which effectively reduces the overall warping deformation of the packaging substrate and makes the product have better coplanarity, thereby promoting the improvement of the quality stability and interconnection performance of the packaging substrate.

[0108] The following is combined with Figures 8 to 14 , further introduces the preparation method of the packaging substrate and the structure of the packaging substrate, specifically including:

[0109] First, see Figure 8, a dielectric layer 201 is formed on the front and back of the package core board 100. The dielectric layer 201 uses ABF film (Ajinomoto build-up film) as the dielectric material. The ABF film is a thermosetting film with low thermal expansion coefficient and low dielectric loss. It is easy to process fine circuits, has good mechanical properties and good durability. It is particularly suitable for use on the surface of the core structure with grooves 102 and embedded passive devices 107. It can be understood that the type of the dielectric layer 201 is not limited to this, and can be selected according to specific needs, and no excessive restrictions are made here.

[0110] As an example, the dielectric layer 201 can be made by a pressing method, such as a vacuum pressing method, to form the dielectric layer 201 with good bonding force on two opposite sides of the packaging core board 100. The thickness of the dielectric layer 201 is not excessively limited here.

[0111] Continue to see Figure 8 , the dielectric layer 201 is patterned to form a blind hole 202 penetrating the dielectric layer 201. The blind hole 202 is formed by a laser drilling process. Specifically, a carbon dioxide laser or a UV laser can be used, and the laser pulse is at the nanosecond level, picosecond level, or femtosecond level.

[0112] Next, see Figures 9 to 13 , a patterned circuit connection layer electrically connected to the package core board 100 is formed based on the blind hole 202; the specific process is similar to the preparation process of the core board structure, which is described in detail as follows:

[0113] See also Fig. 9 , Desmear+PTH is used to remove the slag at the bottom of the hole and chemical copper deposition as the second metal seed layer 203 for electroplating. The purpose of Desmear is to remove the slag caused by the high temperature generated by the drilling process due to the friction of the drill bit, and to roughen the surface of the package core board 100 so that the chemical copper deposition has a good bonding force with the package core board 100; the purpose of PTH is to deposit a layer of conductive chemical copper on the non-conductive hole wall as the electroplating base, so as to facilitate the conduction of the upper and lower boards and the inner board circuits.

[0114] See also Figures 10-12 A patterned second shielding layer 204 is formed on the surface of the second metal seed layer 203, and the second shielding layer 204 is a photosensitive material. Subsequently, an exposure and development process is performed to produce a conductive pattern profile on the build-up layer; based on the patterned second shielding layer 204, a second metal interconnection layer 205 covering the exposed surface of the second metal seed layer 203 is formed, and the second shielding layer 204 and the second metal seed layer 203 corresponding to the bottom of the second shielding layer 204 are removed to obtain a circuit connection layer.

[0115] See also Fig.13, repeat the steps of preparing the dielectric layer 201 and the circuit connection layer until the required number of build-up layers is completed to form the packaging substrate. Fig.13 Two layers of the circuit connection layer are formed on both sides of the packaging core board 100. It can be understood that the number of layers of the circuit connection layer is set according to actual needs and is not excessively restricted here.

[0116] See also Fig.14 After forming the required number of circuit connection layers, the method further includes: preparing a solder resist layer 206 and a surface treatment layer 207 on the surface of the obtained structure in sequence. The surface treatment layer 207 can be made of chemical nickel-palladium-gold, which protects the circuit connection layer from copper oxidation and maintains the solderability of the line connection layer.

[0117] This embodiment also provides a packaging substrate. Fig.14 , comprising a package core board and at least one build-up layer as provided in Example 1; wherein,

[0118] The build-up layer includes a dielectric layer 201 and a circuit connection layer, wherein a blind hole 202 penetrating the dielectric layer 201 is formed in the dielectric layer 201, and the circuit connection layer fills the blind hole 202 and extends to a portion of the surface of the dielectric layer 201;

[0119] The circuit connection layer of the build-up layer is connected to the conductive interconnect layer of the package core board 100 .

[0120] A specific example of preparing a packaging substrate is provided below:

[0121] s1: Provide a glass core board, and use laser induced etching to process grooves for embedding passive components on the front side of the glass core board, and at the same time process interconnection holes that penetrate the glass core board;

[0122] s2: chemically depositing copper on the glass core board to form a metal seed layer on the surface of the glass core board;

[0123] s3: Paste the photosensitive material, expose and develop, make the conductive pattern outline on the glass core board, and protect and fill the groove part;

[0124] s4: Based on the package core board with the metal seed layer made above, the metal layer is thickened by electroplating copper to form a metal interconnection layer;

[0125] s5: using etching process to remove photosensitive materials;

[0126] s6: Use flash etching process to remove the metal seed layer under the photosensitive material to form a packaging core board with a reliable conductive interconnect layer;

[0127] s7: mounting passive components into the grooves of the package core board obtained above;

[0128] s8: Paste ABF film to make the added layer;

[0129] s9: UV laser drilling is performed on the build-up layer to process blind holes on the build-up layer;

[0130] s10: Desmear+PTH is used to remove the slag at the bottom of the hole and chemical copper is used as the second metal seed layer for electroplating;

[0131] s11: Paste the photosensitive material, expose and develop, and make the conductive pattern outline on the build-up layer;

[0132] s12: Use copper electroplating to make conductive patterns and blind hole metallization;

[0133] s13: stripping and flash etching to remove excess photosensitive material and the second metal seed layer under the photosensitive material;

[0134] s14: Repeat steps 10 to 13 to make more layers;

[0135] s15: Apply solder mask ink to form a solder mask layer to protect the circuit, and at the same time open a window to expose the circuit that needs to be connected to the outside.

[0136] s16: Make a surface treatment layer to protect the copper surface of the circuit from oxidation. At this point, the process of making all packaging substrates is completed.

[0137] In summary, in the technical solution of the present application, grooves are processed on the surface of the core board, and the passive devices mounted on the surface of the existing packaging substrate are embedded into the grooves of the packaging core board, thereby releasing the space on the surface of the packaging core board for mounting passive devices, thereby improving the surface space utilization rate of the packaging core board, and the metal layer in the groove of the glass core board can improve the heat dissipation performance, thereby promoting the improvement of the interconnection performance of the packaging core board; the present application also solves the problem of serious warping deformation caused by the increase in the number of packaging substrate layers, and at the same time improves the surface space utilization rate of the packaging substrate, so that more integrated chips can be mounted on the surface of the packaging substrate, thereby promoting the improvement of the interconnection performance of the packaging substrate, promoting the expansion of the glass substrate market, and giving more application scenarios to products based on glass substrates. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0138] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for preparing a package core board, characterized in that: The following steps are involved: Providing a core plate, the core plate having a front side and a back side opposite to each other, and forming a plurality of interconnected holes in the core plate, the interconnected holes being arranged at intervals and penetrating the core plate; forming a groove on the front side of the core plate; Forming a metal seed layer covering the surface of the core board and the sidewalls of the interconnection holes, and forming a patterned shielding layer on the surface of the metal seed layer to expose the metal seed layer corresponding to the groove; forming a metal interconnect layer covering the exposed surface of the metal seed layer based on the patterned shielding layer; The shielding layer and the metal seed layer corresponding to the bottom of the shielding layer are removed to obtain the conductive interconnection layer; the conductive interconnection layer includes a first conductive layer formed above the metal seed layer on the surface of the groove, a conductive column filling the interconnection hole, and a patterned second conductive layer formed on the front and back sides of the core board; Passive components are mounted in the grooves.

2. The method for preparing a package core board according to claim 1, characterized in that: The cross-sectional shape of the groove is a rectangle or a trapezoid with a larger opening.

3. The method for preparing a package core board according to claim 1, characterized in that: The passive device is mounted by dispensing glue in the groove or mounting a glue film on the passive device bonding surface.

4. The method for preparing a package core board according to claim 1, characterized in that: The core plate is one of alkali-free glass, alkaline glass, aluminum oxide glass, high borosilicate glass and quartz glass.

5. The method for preparing a packaging core board according to claim 1, characterized in that: Methods of forming the interconnection holes and the grooves include mechanical drilling or laser induced etching.

6. The method for preparing a package core board according to claim 1, characterized in that: The steps of forming the conductive interconnection layer include film lamination, exposure, development, electroplating, film stripping and etching.

7. A method for preparing a packaging substrate, characterized in that: The following steps are involved: Providing a packaging core board prepared by the preparation method according to any one of claims 1 to 6; forming a dielectric layer on the front side and the back side of the packaging core board; Patterning the dielectric layer to form a blind hole penetrating the dielectric layer; A patterned circuit connection layer electrically connected to the packaging core board is formed based on the blind hole.

8. The method for preparing a packaging substrate according to claim 7, characterized in that: The steps of preparing the dielectric layer and the circuit connection layer are repeated until the required number of build-up layers is completed to form the packaging substrate.

9. A packaging core board, characterized in that: The packaging core board is prepared by the preparation method according to any one of claims 1 to 6, comprising: a core board, a patterned metal seed layer and a conductive interconnect layer; wherein, The core plate has a front side and a back side opposite to each other, and interconnected holes are arranged on the core plate at intervals and penetrate the core plate; A groove is arranged on the front side of the core plate; The metal seed layer covers the front and back surfaces of the core board and the surfaces of the interconnecting holes; The conductive interconnection layer covers the surface of the metal seed layer and fills the interconnection holes.

10. A packaging substrate, characterized in that: The method comprises a package core board as claimed in claim 9 and at least one build-up layer; wherein: The build-up layer includes a dielectric layer and a circuit connection layer, a blind hole penetrating the dielectric layer is formed in the dielectric layer, and the circuit connection layer fills the blind hole and extends to a portion of the surface of the dielectric layer; The circuit connection layer of the build-up layer is connected to the conductive interconnect layer of the package core board.

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