Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes depositing a dielectric layer over a package component having a first warpage; and performing an implantation process to implant the dielectric layer with a stress modulated dopant. After the implantation process, the package component has a second warpage that is less than the first warpage. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Integrated circuit packages can have multiple package components, such as device dies and package substrates, bonded together to increase functionality and integration levels. Warping can occur due to differences between the different materials of the multiple package components. Warping can cause delamination issues, and some conductive parts that are intended to bond to each other do not bond, causing circuit failure. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: depositing a dielectric layer on a packaging component having a first warp; and performing an implantation process to implant the dielectric layer with a stress-modulated dopant, wherein after the implantation process, the packaging component has a second warp that is smaller than the first warp.

[0004] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, including: a first dielectric layer; a second dielectric layer, located above the first dielectric layer and in contact with the first dielectric layer, wherein the second dielectric layer includes: a first portion, which includes a stress modulation dopant, wherein the first portion of the stress modulation dopant has a first peak concentration in the second dielectric layer; and a second portion, wherein the second portion of the stress modulation dopant has a second peak concentration in the second dielectric layer, and the second peak concentration is lower than the first peak concentration; and a third dielectric layer, located above the second dielectric layer.

[0005] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate; an active device located in the semiconductor substrate; an interconnect structure located above the active device, wherein the interconnect structure comprises: a passivation layer comprising a first portion and a second portion, wherein the first portion comprises a stress-modulation dopant and the second portion has a concentration of the stress-modulation dopant at least lower than that of the first portion; and a plurality of conductive components located in the passivation layer, wherein each of the plurality of conductive components is surrounded by one of the second portions of the passivation layer and is spaced apart from the first portion; and a bonding layer located above the passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1Ashows an outline of a die having warpage according to some embodiments;

[0008] Figure 1B shows the warpage of a die measured along two directions according to some embodiments;

[0009] Figure 1C shows a cross-sectional view of a die having a weeping profile according to some embodiments;

[0010] Figure 2A shows an outline of a die receiving an implant for warpage reduction according to some embodiments;

[0011] Figure 2B shows a cross-sectional view of a die receiving an implant for warpage reduction according to some embodiments;

[0012] Figure 3-Figure 9 illustrates a cross-sectional view of an intermediate stage in the formation of a package by face-to-face bonding according to some embodiments;

[0013] Figure 10-13 illustrates a cross-sectional view of an intermediate stage in the formation of a package by face-to-back bonding according to some embodiments;

[0014] Figure 14-16 illustrates a cross-sectional view of an intermediate stage in the formation of a package including a functional wafer bonded to a carrier wafer in accordance with some embodiments;

[0015] Fig.17 illustrates a cross-sectional view of a package including two functional wafers bonded to each other according to some embodiments;

[0016] Figure 18-Figure 20 illustrates a cross-sectional view of an intermediate stage in the formation of a package including a stress modulation layer formed on a back side of a wafer in accordance with some embodiments;

[0017] Figure 21-23 illustrates a cross-sectional view of an intermediate stage in the formation of a package that may be used for further packaging according to some embodiments;

[0018] Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A ,and Fig.27B shows a top view and a cross-sectional view of a stress modulation layer / region in a die according to some embodiments;

[0019] Figure 28-Figure 31 shows the pattern and location of stress modulation layers / regions in a wafer according to some embodiments;

[0020] Fig.32A and Fig.32B 10 and 11 respectively show a vertical stress dopant distribution profile and a horizontal stress dopant distribution profile according to some embodiments;

[0021] Fig.33 A process flow for forming a package including a stress modulating layer or region is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] A method for forming a stress modulation layer and / or region (hereinafter referred to as layer / region) to reduce the warpage of a package component, and the resulting structure are provided. According to some embodiments of the present invention, a package component such as a die or a wafer is measured to determine the warpage of the package component. An implantation process is implemented to implant stress modulation dopants and form a stress modulation layer / region to reduce the warpage. The embodiments discussed herein are intended to provide examples of how the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same figure numbers are used to represent the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may also be implemented in any logical order.

[0025] Figure 1AA top view of a package assembly 10 is shown, which may be a device die according to some embodiments. Contour lines are shown to represent warpage contours, where each contour line represents a location on the same level. For example, if the package assembly is placed on a plane, some points of the package assembly are in contact with the plane and have a distance from the plane of zero. Due to warpage, some portions of the package assembly may be above the plane and spaced apart from the plane. Contour lines may represent the distances of different portions of the package assembly from the plane.

[0026] Figure 1B An exemplary warpage profile measured from package assembly 10 is shown. Figure 1B Line 107 from Figure 1A The cross section 104 in the figure is obtained. Figure 1B Line 109 from Figure 1A The cross section 106 in FIG. 1 is obtained. Line 107 indicates that the edge portion of the package component 10 is lower than the center portion of the package component 10. The corresponding profile is called a weeping profile. An exemplary weeping profile is shown in FIG. Figure 1C . Line 109 indicates that the edge portion of the package component 10 is higher than the center portion of the package component 10. The corresponding contour is called a smile contour. An exemplary smile contour is shown in Figure 2B Shown in.

[0027] The crying profile also means that when package component 10 is placed on top of another package component, when the edge portion of package component 10 contacts the other package component, the center portion of package component 10 may be spaced apart from the other package component. Although both the crying profile and the smiling profile are undesirable, the crying profile is less desirable than the smiling profile. Even less desirable is that in different cross-sections (e.g., Figure 1A 104 and 106 in FIG. 1 ), the warping profiles are opposite to each other, one being a smiling profile and the other being a crying profile.

[0028] Figures 3 to 9 1 shows a cross-sectional view of an intermediate stage in the formation of a package by die bonding on a wafer according to some embodiments of the present invention. The corresponding process is also schematically shown in Fig.33 In the process flow shown in .

[0029] Figure 3 A cross-sectional view of package assembly 20 is shown. According to some embodiments, package assembly 20 is a portion of wafer 18 and is a die including active devices and possibly passive devices, which are shown as integrated circuit devices 25. Integrated circuit devices 25 may not be subsequently Figure 4-Figure 9, although it may also be present (or not present). According to an alternative embodiment, package assembly 20 is a plug-in die, which has no active devices and may or may not include passive devices. According to yet another alternative embodiment, package assembly 20 is or includes a package such as an integrated fan-out (InFO) package.

[0030] According to some embodiments, package assembly 20 includes a semiconductor substrate 24, and components formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may include or be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate.

[0031] According to some embodiments, the package assembly 20 includes an integrated circuit device formed on the top surface of the semiconductor substrate. According to some embodiments, the integrated circuit device may include a complementary metal oxide semiconductor (CMOS) transistor, a resistor, a capacitor, a diode, etc. The details of the integrated circuit device are not shown here.

[0032] Package assembly 20 may include through-vias 26 (also referred to as through-silicon vias (TSVs) or through-semiconductor vias (also referred to as TSVs)) extending to an intermediate level of semiconductor substrate 24 , wherein the intermediate level is located between a top surface and a bottom surface of semiconductor substrate 24 .

[0033] An interconnect structure 28 is formed over semiconductor substrate 24. According to some embodiments, interconnect structure 28 includes a plurality of dielectric layers 30, and a plurality of conductive features in dielectric layers 30, such as metal lines / pads 34 and vias 36. Dielectric layers 30 may include an interlayer dielectric (ILD) (not shown separately) that fills spaces between gate stacks of transistors in integrated circuit device 25. According to some embodiments, the ILD is formed by phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, etc. The ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0034] According to some embodiments, dielectric layer 30 may further include a low-k dielectric layer (also referred to as an intermetallic dielectric (IMD)). For example, the dielectric constant (k value) of the low-k dielectric layer may be lower than about 3.5 or 3.0. The low-k dielectric layer may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0035] The conductive feature may include a contact plug in the ILD for electrically connecting to the integrated circuit device 25. According to some embodiments, the contact plug includes or is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0036] Conductive components may include metal lines 34 and vias 36, which are formed in corresponding dielectric layers 30 and are electrically connected to integrated circuit devices 25 and through vias 26. Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, interconnect structure 28 includes a plurality of metal layers interconnected by vias 36. Metal lines 34 and vias 36 may be formed of copper, copper alloys, and / or other metals.

[0037] Interconnect structure 28 may also include a passivation layer 32 that is located above and may contact underlying dielectric layer 30. Metal lines / pads 34 in passivation layer 32 are also referred to below as top conductive features 34A. Passivation layer 32 may be formed of a non-low-k dielectric material, which may include silicon, and additional elements including oxygen, nitrogen, carbon, and / or the like. Passivation layer 32 may be denoted as SiO x N y C z , wherein x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, z is in a range between about 0 and about 1, and x, y, and z will not all be equal to 0. For example, the passivation layer 32 may include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc., or be formed thereof.

[0038] Figure 4 An implantation process 38 is shown that forms a stress modulated region in the passivation layer 32 in accordance with some embodiments. According to alternative embodiments, the implantation process 38 is not performed, and thus no stress modulated region is formed in the passivation layer 32.

[0039] Prior to the implantation process 38, the portion of the passivation layer 32 to be implanted is determined. According to some embodiments, the warpage of the package component 20 is measured. Alternatively, a sample package component having the same structure as the package component 20 is measured. The corresponding process is shown as follows Fig.33 The process 201 in the process flow 200 shown in FIG. The measurement can be performed by moiré measurement, during which a tool is used to measure the package assembly. The measurement provides a warpage profile of the package assembly 20, such as which parts have warpage and the degree of warpage. For example, Figure 1A An exemplary warpage profile of package assembly 10 is shown, assuming that package assembly 20 has the same structure as package assembly 10 .

[0040] Based on the warpage profile, the portion of the package component 20 to be injected is determined. The corresponding process is shown as follows Fig.33 The process 202 in the process flow 200 shown in FIG. Figure 1A In the embodiment, part 110 has the highest warpage value, and the warpage is a crying profile. According to some embodiments, area 110 of package component 10 (which is package component 20) is to be implanted. According to some embodiments, along Y-direction line 106, the warpage profile is a smiling profile, and the warpage is not so severe. Accordingly, implantation is not performed on the relevant area, or alternatively, implantation is performed on some areas with severe warpage.

[0041] Return to reference Figure 4 , forming and patterning an implantation mask 40. According to some embodiments, the implantation mask 40 comprises a patterned photoresist. According to an alternative embodiment, the implantation mask 40 is a three-layer mask, comprising a bottom layer, an intermediate layer located above the bottom layer, and a top layer (photoresist) located above the intermediate layer. According to other embodiments, the implantation mask 40 comprises a hard mask formed of a material different from that of the passivation layer 32, and is patterned with the help of a photoresist. For example, the implantation mask 40 may comprise titanium nitride, boron nitride, etc.

[0042] The material of implantation mask 40 is selected so that when implantation mask 40 is removed in a subsequent process, passivation layer 32 is not damaged. The remaining portion of patterned implantation mask 40 covers the non-implanted portion of passivation layer 32 while leaving the implanted portion open.

[0043] Further references Figure 4 , perform (ion) implantation process 38. The corresponding process is shown as follows Fig.33 204 in the process flow 200 shown in . According to some embodiments, the implanted ions (hereinafter also referred to as stress modulation dopants) may include Ge, B, P, As, Ga, etc., or a combination thereof. The implanted ions may also include H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, or a combination thereof, and / or a combination with Ge, B, P, As, and / or Ga. The concentration of the stress modulation dopant in the passivation layer may be greater than about 1E14 / cm 3 , and according to some embodiments, may be about 1E14 / cm 3 and about 1E16 / cm 3 in the range between.

[0044] According to an alternative embodiment, implant mask 40 is not formed and implant process 38 is not performed. Accordingly, implant mask 40 and implant process 38 are shown as dashed lines to indicate that these features / processes may not be used. In addition, processes 202 and 204 are also shown as dashed lines to indicate that these processes may be performed or may be skipped.

[0045] According to some embodiments, implantation process 38 is controlled such that the peak concentration of the implanted stress modulation dopant is within passivation layer 32. Throughout the description, the letter "I" is used to denote a region implanted with a stress modulation dopant (standing for "implanted"), and the implanted region of passivation layer 32 is denoted as portion 32-I. The symbol "UI" is used to denote a region not implanted with a stress modulation dopant (standing for "unimplanted"), and thus the unimplanted portion of passivation layer 32 is denoted as portion 32-UI. According to some embodiments in which implantation process 38 is performed, passivation layer 32 may have a thickness greater than about 100 Å. The thickness makes the effect of reducing warpage significant enough.

[0046] According to some embodiments, all top conductive features 34A are covered by the patterned implantation mask 40, so that no top conductive features 34A are implanted. According to some embodiments, the lateral distance S1 between the top conductive features 34A closest to the implantation area is greater than 0 μm, and may be greater than about 0.5 μm to allow for sufficient process margin. Each top conductive feature 34A may therefore be surrounded by a non-implanted portion of the passivation layer.

[0047] By implantation process 38, the material of passivation layer 32 is modified. In addition, the density of the implanted portion is increased. Therefore, the warpage of package assembly 20 is reduced and the warpage profile is also modified. For example, implantation process 38 and / or the subsequently formed stress modulation layer alone or together may cause the warpage profile to change from Figure 1A The outline shown in the figure is modified to Figure 2A The profile shown in FIG. 1 is a schematic diagram showing a warping profile in which the warping profile along the X direction is closer to the warping profile along the Y direction. After implantation, the warping profile can be close to a circle. In addition, the warping can be changed to a smile profile along both the X and Y directions, as shown in FIG. Figure 2B In one example, Figure 2B The maximum warpage value WP2 in Figure 1A The maximum warpage value WP1 in.

[0048] Figure 5 The formation of dielectric layer 42 is shown. The corresponding process is shown as follows Fig.33206 in the process flow 200 shown in FIG. According to some embodiments, dielectric layer 42 includes a material similar to that of passivation layer 32, which may include silicon, and additional elements including oxygen, nitrogen, carbon, and / or the like. According to alternative embodiments, dielectric layer 42 may be an etch stop layer, which may include, or be formed of, AlN, AlO, SiOC, etc., or multiple layers thereof.

[0049] Figure 6 4 shows the deposition of the stress modulation layer 44 according to some embodiments. The corresponding process is shown as follows Fig.33 208 in the process flow 200 shown in FIG. 200. According to some embodiments, the stress modulation layer 44 may include or be formed of a dielectric material including silicon and additional elements including oxygen, nitrogen, carbon, and / or the like. The stress modulation layer 44 may also be denoted as SiO x N y C z , wherein x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, and z is in a range between about 0 and about 1, and x, y, and z will not all be equal to zero. For example, the stress modulation layer 44 may include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc., or be formed thereof. The thickness of the stress modulation layer 44 may be greater than about For example, in about Peace in the range between.

[0050] Next, an implantation process 45 is performed. The corresponding process is shown as follows Fig.33 2. The implanted ions (stress modulation dopants) may be selected from the same set of candidate elements used for implant process 38, and may be the same or different from the implant elements used in implant process 38. In addition, the peak concentration of the implanted ions is within stress modulation layer 44. The concentration of the implanted stress modulation dopant may be in the same range as the concentration of the implanted stress modulation dopant introduced by implant process 38.

[0051] According to some embodiments, the implantation process 45 is a blanket implantation process, in which no implantation mask is used, so that the entire stress modulation layer 44 (the entire wafer or tube core) is implanted. According to alternative embodiments, the implantation process 45 is selective, in which the implantation mask 43 is formed to mask some portions of the stress modulation layer 44 while leaving other portions open for implantation. Hereinafter, the implanted portion of the stress modulation layer 44 is denoted as portion 44-I, and the unimplanted portion of the stress modulation layer 44 is denoted as portion 44-UI.

[0052] According to alternative embodiments in which stress modulation region 32-I is formed, stress modulation layer 44 may or may not be formed. Fig.33 Processes 208 and 210 are also shown as dashed lines.

[0053] According to some embodiments, the location for the selective implant process 45 is determined by measuring the package assembly 20 (or another sample package assembly) at Figure 3 The corresponding determination is substantially the same as the position determination for the implantation process 38. According to an alternative embodiment, the position for the selective implantation is determined by measuring the package component 20, which is measured at Figure 4 Alternatively, the implantation process 45 may be performed to further reduce the warpage of the package component that has been modulated by the implantation process 38 .

[0054] Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A ,and Fig.27B A top view and a cross-sectional view of a stress modulation layer / region in a device die according to some embodiments are shown. Features adjacent to the illustrated stress modulation layer / region are not shown, although these features can be found with reference to the cross-sectional views discussed previously. Fig.24A and Fig. 24B A cross-sectional view and a top view, respectively, are shown of a blanket stress modulation layer 44 , which is not patterned and may extend (in the top view) throughout the entire package assembly 20 , which may be a die.

[0055] Fig.25A and Fig.25B 1 and 2 show a cross-sectional view and a top view of a stress modulation region 44-I and / or 32-I and an undoped region 44-UI and / or 32UI according to some embodiments. The stress modulation region 44-I and / or 32-I may be formed where stress is high, for example, in a corner region of the package component 20, such as Fig.25B The stress modulation regions 44 -I and / or 32 -I may also be formed at other locations where the stress is not high, but forming the stress modulation regions 44 -I and / or 32 -I in these areas may also modify the overall warpage profile of the package assembly 20 .

[0056] Fig.26A and Fig.26BA cross-sectional view and a top view of a blanket multilayer stress modulation layer 44 are shown, respectively. According to some embodiments, the multilayer stress modulation layer 44 includes a plurality of sublayers including a sublayer 44-1 and a sublayer 44-2. The materials of the sublayer 44-1 and the sublayer 44-2 may be selected from the same group of candidate materials used to form the stress modulation layer 44 discussed previously, which may include a silicon-containing dielectric material. The materials of the sublayer 44-1 and the sublayer 44-2 may be the same as or different from each other. The stress modulation dopants of the sublayer 44-1 and the sublayer 44-2 may be selected from the same group of candidate stress modulation dopants used to form the stress modulation layer 44 and the stress modulation region 32-I, and may be the same as or different from each other.

[0057] According to some embodiments, the formation of the multilayer stress modulation layer 44 may include: depositing a sublayer 44-1, performing a first implantation process to implant the sublayer 44-1. A peak concentration PC44-1 of a corresponding stress modulation dopant introduced by the first implantation process is within the sublayer 44-1. Then, a sublayer 44-2 is deposited on the sublayer 44-1, followed by a second implantation process to implant the sublayer 44-2. A peak concentration PC44-2 of a corresponding stress modulation dopant introduced by the second implantation process is within the sublayer 44-2. According to some embodiments, the peak concentration PC44-2 is higher or lower than the peak concentration PC44-1, and the peak concentration ratio PC44-2 / PC44-1 is, for example, greater than about 5 or 10, or lower than about 0.2 and 0.1.

[0058] Fig.27A and Fig.27B 4 and 5 show a cross-sectional view and a top view of a multilayer stress modulation layer 44 according to alternative embodiments. These embodiments are substantially similar to Fig.26A and Fig.26B , except that a selective deposition, rather than a blanket deposition process, is performed to form the stress modulation regions 44-1-I and 44-2-I. Likewise, the modulation regions 44-1-I and 44-2-I are formed in separate implantation processes, with peak concentrations in the corresponding sub-layers 44-1 and 44-2, respectively. The peak concentration ratio PC44-2 / PC44-1 may also be in a similar range as discussed above.

[0059] like Fig.27A and Fig.27BAs shown, stress modulation regions 44-2-I may partially overlap corresponding underlying stress modulation regions 44-1-I. Some or all of stress modulation regions 44-2-I may also be completely offset from stress modulation regions 44-1-I. Stress modulation regions 44-3-I may also be present below stress modulation regions 44-1-I. Stress modulation regions 44-3-I may also be formed by a third implantation process. A peak concentration PC44-3 of stress modulation dopants introduced by the third implantation process is in sublayer 44-3. Peak concentration PC44-3 may be higher, equal to, or lower than each of peak concentrations PC44-1 and PC44-2.

[0060] refer to Figure 7 , forming a through hole 49, a bonding layer 46, and a bonding pad 48. The corresponding process is shown as follows Fig.33 200. The via 49 may pass through the stress modulation layer 44. The bonding layer 46 may be formed of a silicon-containing dielectric material, which may be selected from the same group of candidate materials used to form the stress modulation layer 44. The bonding pad 48 may include copper and may be formed by a damascene process. According to an alternative embodiment, the solder area is formed as a top surface feature of the package component 20.

[0061] According to some embodiments, at the wafer level, Figures 3 to 7 In the previous process shown in FIG. 1 , the package assembly 20 is part of the wafer 18. Next, as shown in FIG. Figure 7 As shown in FIG. 1 , in a singulation process that can be performed using saw dicing, the wafer 18 is diced. The wafer 18 is thus separated into discrete package components 20. The corresponding process is shown as Fig.33 Process 214 in the process flow 200 shown in FIG.

[0062] refer to Figure 8 , forming a package assembly 118. According to some embodiments, the package assembly 118 is a device wafer (functional wafer), an insert wafer, a reconstructed wafer including a packaged device die, a package substrate strip, etc. The package assembly 120 can accordingly be a device die, an insert die, a package, a package substrate, etc.

[0063] In some embodiments, package component 120 has a structure similar to that of package component 20. The structure and materials of components in package component 120 can be found by referring to similar components in package component 20, wherein similar components in package component 120 are indicated by adding a number “1” before the reference numerals of the corresponding components in package component 20. For example, the substrate in package component 20 is indicated as 24, and accordingly, the substrate in package component 120 is indicated as 124.

[0064] Package assembly 120 may include an integrated circuit device (not shown), an interconnect structure 128, a bonding pad 148, and a bonding layer 146. The details of these components may be similar to the corresponding components in package assembly 20 and are not repeated here. Package assembly 120 may or may not include stress modulation regions and stress modulation layers. When formed, the stress modulation regions and stress modulation layers may be substantially the same as the stress modulation regions and stress modulation layers in package assembly 20. Some exemplary stress modulation regions and stress modulation layers in package assembly 120 may be shown in FIG. Fig.17 as an example.

[0065] The package component 20 is bonded to the package component 120. The corresponding process is shown as follows Fig.33 216 in the process flow 200 shown in . In the example shown, a hybrid bonding process is implemented such that the bonding pad 48 is bonded to the bonding pad 148 by metal-to-metal bonding, and the bonding layer 46 is bonded to the bonding layer 146 by fusion bonding (wherein a Si-O-Si bond is formed). According to alternative embodiments, other types of bonding may be implemented, such as direct metal-to-metal bonding, solder bonding, etc. Although one package component 20 is shown, multiple package components 20 (e.g., dies) may be bonded to corresponding package components 120 in the package components 118.

[0066] Fig. 9 1 shows a gap filling process for filling the gaps between the package components 20 with the gap filling region 50. The corresponding process is shown as follows Fig.33 218 in the process flow 200 shown in FIG. The gap-filling region 50 may be formed by an inorganic dielectric material, such as a silicon nitride liner and a silicon oxide region on the silicon nitride liner. Alternatively, the gap-filling region 50 may be formed by a molding compound.

[0067] Fig. 9 It is also shown that a backside interconnect structure 52 is formed on the backside of the package component 20. According to some embodiments, the gap-filling region 50 and the substrate 24 of the package component 20 are planarized, for example, in a chemical mechanical polishing (CMP) process or a mechanical polishing process, until the through-hole vias 26 are exposed. The corresponding process is shown as follows. Fig.33 Process 220 in the process flow 200 shown in FIG.

[0068] Next, a backside interconnect structure 52 including a dielectric layer 54 and a redistribution line (RDL) 56 is formed. The corresponding process is shown as follows. Fig.33 The process 222 in the process flow 200 shown in FIG. 8 is then formed into the electrical connector 58 (eg, solder area), thereby forming the reconstructed wafer 82. Subsequently, a singulation process may be performed to separate the reconstructed wafer 82 into identical discrete packages 82'. The corresponding process is shown as follows Fig.33 Process 224 in the process flow 200 shown in FIG.

[0069] The previous embodiments show a face-to-face bonding process. Figure 10-13 A cross-sectional view of an intermediate stage in the formation of a package formed by a face-to-back bonding process according to an alternative embodiment of the present invention is shown. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as similar components represented by similar reference numerals in the previous embodiments. The details about materials, structures, and formation processes provided in each embodiment described throughout can be applied to any other embodiment, as long as applicable. In addition, whenever a package component is referred to as including a stress modulation layer / region throughout the description, the discussion of the formation process of stress modulation layers / regions 32-I and 44 also applies.

[0070] The initial steps of these embodiments are Figures 3 to 7 is substantially the same as shown in FIG. 1 , wherein a package assembly 20 is formed. Next, Fig.10 FIG. 2 shows the bonding / connection of the package component 20 to the carrier 66. The carrier 66 includes a semiconductor substrate 62, which may be a silicon substrate according to some embodiments. A bonding layer 64 is formed on the semiconductor substrate 62. The bonding layer 64 may be formed by a deposition process or a thermal oxidation process and may be formed of a silicon-containing dielectric material, which may be selected from the bonding layer 46 ( Figure 7 According to some embodiments, the bonding of bonding layer 64 to bonding layer 46 may be by fusion bonding.

[0071] According to alternative embodiments, carrier 66 includes a transparent substrate (also indicated by reference numeral 62), such as a glass substrate, wherein package component 20 is connected to carrier 66 by an adhesive, such as a light-to-heat conversion (LTHC) material (also indicated by reference numeral 64), which is configured to decompose under the heat of light (e.g., a laser beam). According to these embodiments, bonding layer 46 in package component 20 can be a polymer layer, such as a polyimide layer, a benzocyclobutene (BCB) layer, etc.

[0072] Gap-filling region 68 is then formed to fill the gaps between package components 20. Gap-filling region 68 may be formed by an inorganic dielectric material, for example, including a silicon nitride liner and a silicon oxide layer over the silicon nitride liner. Alternatively, gap-filling region 68 may be formed by a molding compound.

[0073] Next, refer to Fig.11A back grinding process is performed on the gap-filling region 68 of the package component 120 and the semiconductor substrate 24 to expose the through-hole via 26. A backside interconnect structure 52 is then formed on the backside of the package component 20. The backside interconnect structure 52 may include a bonding pad 96.

[0074] Package component 120 is bonded to package component 20. Package component 120 may be a device die, a package, an insert, etc. According to some embodiments, package component 120 includes an active device such as a transistor. In addition, package component 120 may include stress modulation layer / region 132-I and / or 144. Stress modulation layer / region 132-I / 144 may be formed using substantially the same method as the stress modulation region / layer in package component 20 and having the same set of candidate structures as the stress modulation region / layer in package component 20. For example, stress modulation region 132-I is formed by implantation without implanting portion 132-UI. Stress modulation layer 144 may also be formed by deposition and implantation.

[0075] Fig.12 The formation of the gap filling region 70 is shown, and the gap filling region 70 can be formed by an inorganic dielectric material, such as a silicon nitride liner and a silicon oxide layer above the silicon nitride liner. Alternatively, the gap filling region 70 can be formed by a molding compound. A back grinding process is performed to flatten the top surface of the package component 120 and the gap filling region 70.

[0076] Fig.13 The connection / bonding of carrier 76 to package component 120 and gap-filling region 70 is shown. Carrier 76 includes substrate 72 and bonding layer 74. The structure and material of carrier 76 can be selected from the same group of candidate structures and materials as carrier 66. The connection / bonding can be a fusion bond through bonding layer 74 to substrate 124 of package component 120 and gap-filling region 70.

[0077] Then remove the carrier 66 ( Fig.12 ), and an interconnect structure 78 and an electrical connector 80 (e.g., a solder area or a metal bump) are formed on the front side of the package component 20. A reconstructed wafer 82 is thereby formed. In a subsequent process, a singulation process is performed to saw the reconstructed wafer 82 into a plurality of packages 82'. The packages 82' can be used for a further packaging process, in which a portion of the carrier 76 can be removed and the through-holes in the package component 120 are exposed for forming further electrical connections thereon.

[0078] Figure 14-16A wafer-on-wafer bonding process is shown, where a functional wafer (including functional integrated circuits (active devices / circuits)) is bonded to a carrier wafer 84. According to some embodiments, the carrier wafer 84 includes a semiconductor substrate (e.g., a silicon substrate) 86, a dielectric layer 88, and a stress modulation layer 90. The stress modulation layer 90 may be deposited and may include a silicon-containing dielectric material including silicon and an element selected from N, O, C, and combinations thereof.

[0079] According to some embodiments, an implantation process 94 is performed to implant a stress modulation dopant, which may be selected from process 38 ( Figure 4 ) and 45( Figure 6 ). The implantation process 94 may be a blanket implantation process, without the use of an implantation mask, so that the entire stress modulation layer 90 of the entire carrier wafer 84 is implanted. According to alternative embodiments, experiments may be performed to measure the stress modulation layer 90 of the carrier wafer 84 and / or the resulting sample reconstructed wafer 82 ( Fig.16 ) to find the warpage value and warpage profile of the entire carrier wafer 84. Based on the measured warpage profile, selected areas of the stress modulation layer 90 are implanted to reduce the warpage and modify the warpage profile of the resulting reconstructed wafer 82. For example, the implantation mask 93 can be formed so that the selected areas 90-I are implanted while the areas 90-UI are not implanted. Likewise, the peak dopant concentration of the implanted stress modulation dopant is within the stress modulation layer 90.

[0080] Figure 28-Figure 31 Some wafers (which may be carrier wafer 84 and / or wafers 18 and 118 discussed in subsequent processes, hereinafter referred to as 84 / 18 / 118) and implanted portions according to different embodiments are shown. Fig.28 As shown in , the entire carrier wafer 84 / 18 / 118 is implanted. Fig.29 In the embodiment, some strip portions of the carrier wafer 84 / 18 / 118 are implanted. The overlapping area of ​​the implant strips having a longitudinal direction along the X direction and the implant strips having a longitudinal direction along the Y direction may overlap with the area of ​​the carrier wafer 84 / 18 / 118 with the highest warpage value. Fig.30 An embodiment is shown in which the implanted area is a circular area, or may include multiple circular areas. Fig.31 An embodiment is shown in which implantation is performed on selected and isolated areas.

[0081] refer to Fig.15 , depositing a bonding layer 92 on the stress modulation layer 90. The bonding layer 92 may also be formed by a silicon-containing dielectric material, which may include silicon and an element selected from N, O, C, and a combination thereof. Next, as Fig.16As shown in FIG, the carrier wafer 84 is bonded to the functional wafer 18 by fusion bonding. Figure 3-Figure 7 The process shown in FIG. 1 forms a functional wafer 18 .

[0082] exist Fig.16 In the structure shown in FIG. 8 , according to some embodiments, the stress modulation layer / region is formed in the carrier wafer 84 but not in the functional wafer 18. According to an alternative embodiment, the stress modulation layer / region is formed in the functional wafer 18 but not in the carrier wafer 84. According to yet another alternative embodiment, the stress modulation layer / region is formed in both the functional wafer 18 and the carrier wafer 84.

[0083] Fig.17 The formation of a package according to an alternative embodiment is shown. The package includes face-to-face bonding of wafers 18 and 118, which include device dies 20 and 120, respectively. The details of device dies 20 and 120 are discussed in previous embodiments and are not repeated here. Similarly, the stress modulation layer / region can be formed in either or both of the device dies 20 and 120 (and wafers 18 and 118). In addition, the stress modulation layer / region can be formed at the die level, such as Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A ,and Fig.27B As shown in , or forming a stress modulation layer / region at the wafer level, such as Figure 28-Figure 31 As shown in .

[0084] Figure 18-Figure 20 FIG. 4 shows forming a stress modulation layer on the back side of a functional wafer according to some embodiments. Fig.18 , the functional wafer 18 is bonded to the carrier wafer 84. The stress modulation layer / region may be formed in either or both of the front side of the functional wafer 18 and the carrier wafer 84. The bonding may include fusion bonding according to some embodiments. Next, referring to Fig.19 The semiconductor substrate 24 of the functional wafer 18 is thinned to expose the through-hole vias 26. A back dielectric layer 98 is formed, and a bonding pad 96 is formed in the back dielectric layer 98.

[0085] Next, a stress modulation layer 110 is deposited, which may be formed of a material similar to that of other stress modulation layers, such as stress modulation layer 44. An implantation process 114 may be performed to introduce a stress modulation dopant into the stress modulation layer 110, wherein the peak concentration of the stress modulation dopant is within the stress modulation layer 110. The implantation process may be a blanket process, such as Fig.28 As shown in , it can also be optional, such as Figure 29-Figure 31 As shown in Fig.19 The implantation mask 112 shown in FIG. 1 is used to define implantation regions in a selective implantation process.

[0086] Fig. 20 The formation of a bonding layer 115 and bonding pads 116 that may be used in a hybrid bonding process is shown. A reconstituted wafer 82 is thereby formed. The reconstituted wafer 82 may then be singulated to form a plurality of discrete packages 82'.

[0087] Figure 21-23 Also shown is a wafer-to-wafer bonding process for forming a package, which can be further packaged. Fig.21 , the wafer 18 is bonded to the carrier wafer 84. Next, the substrate 24 of the wafer 18 is thinned to expose the through-holes 26, and a backside structure is formed on the backside of the wafer 18, such as Fig. 22 As shown in .

[0088] Further references Fig. 22 , wafer 118 is bonded to wafer 18. In a subsequent process, substrate 124 of wafer 118 is thinned to expose through-holes 126, and a backside structure is formed on the backside of wafer 118 to form reconstructed wafer 82, as shown in FIG. Fig.23 The resulting reconstituted wafer 82 may then be singulated to form discrete packages.

[0089] exist Fig. 22 In the structure shown in FIG. 8 , the stress modulation layer / region may be formed in one or more or all of the carrier wafer 84 , wafer 18 , and wafer 118 in any combination.

[0090] Fig.32A A vertical profile of a stress modulation dopant in a stress modulation region 140 is shown, which represents any of the stress modulation layers / regions 32-1, 44, 144, 110, etc. discussed above. Layers 142 and 144 represent dielectric layers above (if present) and below the modulation region 140. The concentration of the stress modulation dopant is shown in FIG. Fig.32A According to some embodiments, the peak concentration of the stress modulation dopant is in the stress modulation region 140 (and may be at or close to the middle level of the stress modulation region 140). From where the peak concentration occurs, the concentration of the stress modulation dopant may gradually decrease in the upward direction and the downward direction.

[0091] Fig.32BHorizontal distribution of stress modulation dopants in implanted regions 150-I and unimplanted regions 150-UI in dielectric layer 150 is shown. Dielectric layer 150 may represent any of the selectively implanted stress modulation layers / regions discussed above. According to some embodiments, the peak concentration of stress modulation dopants is in implanted region 150-I (and may be at or near the middle of implanted region 150-I). The concentration of stress modulation dopants may gradually decrease into unimplanted regions 150-UI. Some portions of unimplanted regions 150-UI may be free of stress modulation dopants.

[0092] In the embodiments shown above, some processes and features are discussed according to some embodiments of the present invention to form a three-dimensional (3D) package. Other features and processes may also be included. For example, a test structure may be included to assist in the verification test of a 3D package or a 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC device to be tested using a probe and / or a probe card, etc. The verification test may be implemented either on an intermediate structure or on a final structure. In addition, the structures and methods disclosed herein may be used in combination with a test method for intermediate verification of a known good die to increase yield and reduce costs.

[0093] Embodiments of the present invention have several advantageous features: By forming a stress modulation layer / region in a die and / or wafer by ion implantation, the warpage of the device die and / or wafer may be reduced and the warpage profile may be modified.

[0094] According to some embodiments of the present invention, a method of forming a semiconductor structure includes: depositing a dielectric layer on a package component having a first warpage; and performing an implantation process to implant the dielectric layer with a stress modulation dopant, wherein after the implantation process, the package component has a second warpage that is less than the first warpage. In one embodiment, the implantation process causes the package component to warp in an opposite direction compared to before the implantation process. In one embodiment, the implantation process is a blanket implantation process.

[0095] In one embodiment, the method further comprises: forming a through hole through the dielectric layer; forming a bonding layer located above and in contact with the dielectric layer; forming a bonding pad located in the bonding layer above and in contact with the through hole. In one embodiment, the implantation process is a selective implantation process, wherein a first portion of the dielectric layer is implanted, and wherein, during the implantation process, a second portion of the dielectric layer is masked from the implantation process. In one embodiment, the method further comprises: measuring a first warpage of an additional package component having the same structure as the package component; and determining a position of the dielectric layer to be implanted, wherein determining the position is based on the first warpage, and wherein, during the implantation process, the position is implanted.

[0096] In one embodiment, a portion of the implanted location is located in a corner region of the package assembly, and wherein a central portion of the package assembly is masked from the implantation process. In one embodiment, the package assembly includes a metal line located in a dielectric layer, and wherein the metal line is masked from the implantation process. In one embodiment, the stress modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In one embodiment, the stress modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In one embodiment, the package assembly includes an active device, and wherein the dielectric layer is located on the front side of the package assembly. In one embodiment, the package assembly includes an active device, and wherein the dielectric layer is located on the back side of the package assembly.

[0097] According to some embodiments of the present invention, a semiconductor structure includes: a first dielectric layer; a second dielectric layer located above the first dielectric layer and in contact with the first dielectric layer, wherein the second dielectric layer includes: a first portion including a stress modulation dopant, wherein the first portion of the stress modulation dopant has a first peak concentration in the second dielectric layer; and a second portion, wherein the second portion of the stress modulation dopant has a second peak concentration in the second dielectric layer and the second peak concentration is lower than the first peak concentration; and a third dielectric layer located above the second dielectric layer.

[0098] In one embodiment, the concentration of the stress-modulating dopant decreases continuously from the location where the first peak concentration occurs upward into the third dielectric layer, or downward into the first dielectric layer, and wherein the concentration of the stress-modulating dopant also decreases continuously from the first portion to the second portion. In one embodiment, the stress-modulating dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof.

[0099] In one embodiment, the stress modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In one embodiment, the semiconductor structure further comprises: a metal line located in the second dielectric layer, wherein the metal line is located in the second portion. In one embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer are included in a die, and wherein the first portion is located in a corner region of the die and the second portion is located in a center region of the die.

[0100] According to some embodiments of the present invention, a semiconductor structure includes: a semiconductor substrate; an active device located in the semiconductor substrate; an interconnect structure located above the active device, wherein the interconnect structure includes a passivation layer, the passivation layer includes a first portion and a second portion, wherein the first portion includes a stress modulation dopant, and the second portion has a concentration of the stress modulation dopant at least lower than that of the first portion; and a plurality of conductive features located in the passivation layer, wherein each of the plurality of conductive features is surrounded by one of the second portions of the passivation layer and is spaced apart from the first portion; and a bonding layer located above the passivation layer. In one embodiment, a peak concentration of the stress modulation dopant is in the passivation layer, and the concentration of the stress modulation dopant gradually decreases in an upward direction and a downward direction starting from the location where the peak concentration occurs.

[0101] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: depositing a dielectric layer on the package component having the first warpage; as well as An implantation process is performed to implant the dielectric layer with a stress modulating dopant, wherein after the implantation process, the package assembly has a second warp that is less than the first warp.

2. The method according to claim 1, wherein: The implantation process causes the package assembly to warp in an opposite direction compared to before the implantation process.

3. The method according to claim 1, further comprising: forming a through hole through the dielectric layer; forming a bonding layer over and in contact with the dielectric layer; as well as A bonding pad in the bonding layer is formed over and in contact with the via.

4. The method according to claim 1, wherein: The implantation process is a selective implantation process, wherein a first portion of the dielectric layer is implanted, and wherein, during the implantation process, a second portion of the dielectric layer is masked from the implantation process.

5. The method according to claim 4, wherein: Portions of the locations for implantation are located in corner regions of the package component, and wherein a central portion of the package component is masked from the implantation process.

6. The method according to claim 4, wherein: The package assembly includes metal lines in the dielectric layer, and wherein the metal lines are masked from the implantation process.

7. A semiconductor structure comprising: a first dielectric layer; A second dielectric layer is located above the first dielectric layer and contacts the first dielectric layer, wherein the second dielectric layer comprises: a first portion comprising a stress-modulation dopant, wherein the first portion of the stress-modulation dopant has a first peak concentration in the second dielectric layer; and a second portion, wherein the second portion of the stress-modulation dopant has a second peak concentration in the second dielectric layer, and the second peak concentration is lower than the first peak concentration; and The third dielectric layer is located above the second dielectric layer.

8. The semiconductor structure according to claim 7, wherein: The concentration of the stress-modulation dopant decreases continuously from the location where the first peak concentration occurs upward into the third dielectric layer, or downward into the first dielectric layer, and wherein the concentration of the stress-modulation dopant also decreases continuously from the first portion to the second portion.

9. The semiconductor structure according to claim 7, wherein: The first dielectric layer, the second dielectric layer, and the third dielectric layer are included in a die, and wherein the first portion is located in a corner region of the die and the second portion is located in a center region of the die.

10. A semiconductor structure comprising: Semiconductor substrate; An active device located in the semiconductor substrate; An interconnect structure, located above the active device, wherein the interconnect structure comprises: a passivation layer comprising a first portion and a second portion, wherein the first portion comprises a stress-modulation dopant and the second portion has at least a lower concentration of the stress-modulation dopant than the first portion; and a plurality of conductive features disposed in the passivation layer, wherein each of the plurality of conductive features is surrounded by one of the second portions of the passivation layer and is spaced apart from the first portion; and The bonding layer is located above the passivation layer.

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