Semiconductor package with improved structural stability

Abstract

An example semiconductor package includes: a first redistribution layer; a bridge chip attached to a top surface of the first redistribution layer; a molding layer on the first redistribution layer and surrounding the bridge chip; a second redistribution layer disposed on the molding layer; a conductive pillar vertically extending through the molding layer and connecting the first redistribution layer and the second redistribution layer; and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer includes a pad layer, and an interconnect layer disposed on the pad layer. The pad layer includes a first insulating layer, and a pad in the first insulating layer. A top surface of the pad is exposed to an exterior of a top surface of the first insulating layer, and a bottom surface of the pad is exposed to an exterior of a bottom surface of the first insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0108510 filed in the Korean Intellectual Property Office on August 18, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor packaging. Background Art

[0004] In view of the recent developments in the electronics industry, the demand for high-performance, high-speed, and compact electronic components has been steadily increasing. As a result, the development of packaging technology allows multiple semiconductor chips to be mounted within a single package.

[0005] In order to reduce the size and weight of electronic components, it is necessary to develop technologies for reducing the size of each component and packaging technologies for integrating multiple components in a single package. In particular, for semiconductor packages used to process high-frequency signals, it is necessary not only to reduce the size of the product but also to achieve good electrical characteristics.

[0006] Typically, a plurality of memory chips are stacked on a package substrate using a through silicon via (TSV) process, a flip chip process, a wire bonding process, etc. However, the complexity and cost of the TSV process are high, and therefore, a process that can overcome these difficulties in the TSV process needs to be developed.

[0007] Semiconductor packages are configured to facilitate the use of integrated circuit chips as components in electronic products. Typically, semiconductor packages include a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to the PCB through bonding wiring or bumps. With the recent development of the electronics industry, semiconductor packaging technology has developed in various ways with the goal of miniaturization, light weight, and reduced manufacturing costs. In addition, as the utilization of this technology expands to different fields including mass storage devices, various types of semiconductor packages are emerging. Summary of the invention

[0008] The present disclosure relates to semiconductor packages, including semiconductor packages with improved structural stability and semiconductor packages with small size and high integration density and methods of manufacturing the same, including methods of reducing failure rates in a process of manufacturing semiconductor packages.

[0009] In some embodiments, a semiconductor package includes: a first redistribution layer; a bridge chip disposed on a top surface of the first redistribution layer and attached to the top surface of the first redistribution layer; a molding layer disposed on the first redistribution layer to surround the bridge chip; a second redistribution layer disposed on the molding layer; a conductive column disposed to vertically penetrate the molding layer and connect the first redistribution layer to the second redistribution layer; and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer may include a pad layer, and an interconnect layer disposed on the pad layer. The pad layer may include a first insulating layer, and a pad disposed in the first insulating layer. The top surface of the pad may be exposed to the outside of the first insulating layer near the top surface of the first insulating layer, and the bottom surface of the pad may be exposed to the outside of the first insulating layer near the bottom surface of the first insulating layer. The surface flatness of the top surface of the pad layer may be greater than the surface flatness of the bottom surface of the pad layer.

[0010] In some embodiments, a semiconductor package includes: a first redistribution layer; a bridge chip on the top surface of the first redistribution layer; a molding layer disposed on the first redistribution layer to surround the bridge chip; a second redistribution layer disposed on the molding layer; a conductive column disposed to vertically penetrate the molding layer and connect the first redistribution layer to the second redistribution layer; and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer may include: a substrate protection layer and a pad layer, the pad layer including an outer pad vertically penetrating the substrate protection layer, the top surface of the substrate protection layer and the top surface of the outer pad being substantially flat and coplanar with each other; an insulating pattern covering the substrate protection layer and the outer pad; and an interconnection pattern disposed on the insulating pattern. The interconnection pattern may include a head and a tail, the head being disposed on the top surface of the insulating pattern, the tail extending from the bottom surface of the head to vertically penetrate the insulating pattern and connected to the outer pad. The total thickness variation (TTV) of the pad layer may be in the range of 0 μm to 10 μm.

[0011] In some embodiments, a semiconductor package includes: a first redistribution layer; a second redistribution layer disposed on the first redistribution layer; a bridge chip mounted on the bottom surface of the second redistribution layer; a molding layer surrounding the bridge chip between the first redistribution layer and the second redistribution layer; a conductive pillar disposed to vertically penetrate the molding layer and connect the first redistribution layer to the second redistribution layer; a first semiconductor chip mounted on the top surface of the second redistribution layer; and a chip stack including a second semiconductor chip vertically stacked on the top surface of the second redistribution layer to be horizontally spaced apart from the first semiconductor chip. The first redistribution layer may include: a pad layer including an outer pad and a substrate protection layer horizontally surrounding the outer pad; an insulating pattern covering the outer pad and the substrate protection layer; and an interconnection pattern disposed on the insulating pattern to penetrate the insulating pattern and coupled to the outer pad. The top surface of the outer pad may be exposed to the outside of the substrate protection layer near the top surface of the substrate protection layer, and the top surface of the pad layer may be substantially flat. A bottom surface of the outer pad may be exposed to the outside of the substrate protection layer near a bottom surface of the substrate protection layer, and the bottom surface of the pad layer may be uneven.

[0012] In some embodiments, a method for manufacturing a semiconductor package includes: forming a sacrificial layer on a carrier substrate; performing an exposure process on the carrier substrate to form an opening that vertically penetrates the sacrificial layer; filling the opening with a conductive material to form a pad; removing the sacrificial layer; forming a substrate protective layer on the carrier substrate to cover the pad; performing a first planarization process on the substrate protective layer and the pad to expose the pad from the substrate protective layer near the top surface of the substrate protective layer; forming an insulating layer on the substrate protective layer and the pad; patterning the insulating layer to form an insulating pattern; forming a conductive layer on the insulating pattern, and patterning the conductive layer to form an interconnection pattern; forming a conductive column on the interconnection pattern; attaching a bridge chip to the insulating pattern; forming a molding layer on the insulating pattern to cover the conductive column and the bridge chip; and performing a second planarization process on the molding layer to expose the conductive column from the molding layer near the top surface of the molding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing an example of a semiconductor package.

[0014] Figure 2 It shows Figure 1 An example enlarged cross-sectional view of portion "A".

[0015] Figures 3 to 8 are cross-sectional views each showing an example of a semiconductor package.

[0016] Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17 is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor package.

[0017] Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B It shows Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A and Fig.16A An example enlarged cross-sectional view of portion "B". DETAILED DESCRIPTION

[0018] Example embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0019] Figure 1 is a cross-sectional view showing an example of a semiconductor package. Figure 2 It shows Figure 1 An example enlarged cross-sectional view of portion "A". Figure 3 is a cross-sectional view showing an example of a semiconductor package.

[0020] refer to Figure 1 and Figure 2 , a first redistribution layer 100 is provided. For example, the first redistribution layer 100 may include a first substrate interconnection layer consisting of a first substrate insulation pattern 110 and a first substrate interconnection pattern 120 on the first substrate insulation pattern 110 .

[0021] The first substrate insulating pattern 110 may be formed of or include at least one of an insulating polymer or a photoimageable polymer (e.g., a photoimageable dielectric (PID) material). For example, the photoimageable polymer may include at least one of a photoimageable polyimide (PI), a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0022] The first substrate interconnection pattern 120 may be disposed on the first substrate insulation pattern 110. The first substrate interconnection pattern 120 on the first substrate insulation pattern 110 may extend horizontally. The first substrate interconnection pattern 120 may be disposed on the top surface of the first substrate insulation pattern 110. The first substrate interconnection pattern 120 may include a protruding portion extending to a level higher than the top surface of the first substrate insulation pattern 110. At least one of the first substrate interconnection patterns 120 may be used as a redistribution pad coupled to the conductive pillar 310. Here, the first substrate interconnection pattern 120 used as a redistribution pad may be placed on an edge region of the first redistribution layer 100. Although not shown, at least one of the first substrate interconnection patterns 120 may extend horizontally on the first substrate insulation pattern 110. As described above, the first substrate interconnection pattern 120 may be a pad portion or a wiring portion of the first substrate interconnection layer. In other words, the first substrate interconnection pattern 120 may be an element for horizontal redistribution in the first redistribution layer 100. The first substrate interconnection pattern 120 may include a conductive material. For example, the first substrate interconnection pattern 120 may be formed of or include at least one metal material (eg, copper (Cu)).

[0023] The first substrate interconnection pattern 120 may have a mosaic structure. For example, each first substrate interconnection pattern 120 or at least a portion of the first substrate interconnection pattern 120 may include a via portion extending protrudingly from its bottom surface. The via portion may be an element for vertical interconnection in the first substrate interconnection layer. For example, the via portion may extend from the bottom surface of the first substrate interconnection pattern 120 to penetrate the first substrate insulation pattern 110, and may be coupled to the top surface of the outer pad 130 to be described below. The upper portion of the first substrate interconnection pattern 120 placed on the first substrate insulation pattern 110 may be a head for horizontal interconnection or as a pad, and the via portion of the first substrate interconnection pattern 120 may be a tail. The width of the tail may be less than the width of the head. The width of the tail may decrease as the distance from the head of the first substrate interconnection pattern 120 increases. That is, the tail may have a tapered shape. Each first substrate interconnection pattern 120 or at least a portion of the first substrate interconnection pattern 120 may have the shape of the letter "T".

[0024] The first seed / barrier layer 122 may be disposed between the first substrate interconnection pattern 120 and the first substrate insulation pattern 110. Figure 2As shown, each first seed / barrier layer 122 may cover the bottom surface of a corresponding first substrate interconnection pattern 120 in the first substrate interconnection patterns 120. The first seed / barrier layer 122 may conformally cover the bottom surface of the first substrate interconnection pattern 120. The first seed / barrier layer 122 may be disposed to expose the side surface of the first substrate interconnection pattern 120. However, in some embodiments, each first seed / barrier layer 122 may be disposed to cover the bottom surface and the side surface of the corresponding first substrate interconnection pattern 120 in the first substrate interconnection patterns 120. In this case, the first seed / barrier layer 122 may conformally cover the bottom surface and the side surface of the first substrate interconnection pattern 120. The distance between the first substrate insulating pattern 110 and the first substrate interconnection pattern 120 (i.e., the thickness of the first seed / barrier layer 122) may be in the range of 1 to 50°. to In the case where the first seed crystal / barrier layer 122 is used as a seed crystal layer, the first seed crystal / barrier layer 122 may include a metal material (e.g., gold (Au)). In the case where the first seed crystal / barrier layer 122 is used as a barrier layer, the first seed crystal / barrier layer 122 may include a metal material (e.g., titanium (Ti) and tantalum (Ta)), or a metal nitride material (e.g., titanium nitride (TiN) and tantalum nitride (TaN)). In some embodiments, the first seed crystal / barrier layer 122 may not be provided.

[0025] Figure 1 and Figure 2 1 shows an example in which the first redistribution layer 100 has one first substrate interconnection layer, but the present invention is not limited to this example. For example, the first redistribution layer 100 may include at least two first substrate interconnection layers stacked in sequence, such as Figure 3As shown. The first substrate interconnection pattern 120 of one first substrate interconnection layer in the first substrate interconnection layer can be electrically connected to the first substrate interconnection pattern 120 of another first substrate interconnection layer adjacent thereto. The first substrate interconnection pattern 120 on the first substrate insulation pattern 110 can be covered by another first substrate insulation pattern 110 disposed thereon. The first substrate interconnection pattern 120 disposed in the uppermost first substrate interconnection layer of the first substrate interconnection layer can be used as a redistribution pad, to which the conductive pillar 310 is coupled. The via portion of the first substrate interconnection pattern 120 can be an element for vertically connecting the first substrate interconnection pattern 120 of the adjacent first substrate interconnection layer in the first substrate interconnection layer. For example, the via portion can extend from the bottom surface of the first substrate interconnection pattern 120 to penetrate the first substrate insulation pattern 110, and can be coupled to the top surface of the first substrate interconnection pattern 120 of another first substrate interconnection layer below it. Alternatively, the via portion can be an element for connecting the first substrate interconnection pattern 120 of the lowermost first substrate interconnection layer in the first substrate interconnection layer to the external pad 130. For example, the via portion may extend from the bottom surface of the first substrate interconnection pattern 120 to penetrate the lowermost first substrate insulation pattern 110 of the first substrate insulation pattern 110, and may be coupled to the top surface of the outer pad 130. For the sake of brevity, the following description will refer to Figure 1 and Figure 2 implementation method.

[0026] The first redistribution layer 100 may further include a pad layer PL disposed under the first substrate interconnection layer. The pad layer PL may be composed of a substrate protection layer 140 and an outer pad 130 disposed in the substrate protection layer 140.

[0027] The outer pad 130 may be disposed on the bottom surface of the first substrate interconnect layer. The outer pad 130 may be electrically connected to the first substrate interconnect pattern 120. For example, the tail of the first substrate interconnect pattern 120 may be disposed to penetrate the first substrate insulating pattern 110 and may be coupled to the top surface of the outer pad 130. The outer pad 130 may be used as a pad to which the external terminal 150 is coupled. Regardless of the position in the vertical direction, the width W1 of the outer pad 130 may be uniform. Here, the term "vertical direction" may refer to a direction from the top surface of the outer pad 130 toward the bottom surface of the outer pad 130. The width W1 of the outer pad 130 may be equal to or similar to the width W2 of the first substrate interconnect pattern 120. However, the present disclosure is not limited to this example. The thickness T1 of the outer pad 130 may be equal to or less than the thickness T2 of the first substrate interconnect pattern 120. The thickness T1 of the outer pad 130 may be in the range of 5 μm to 20 μm. The distance P1 between the outer pads 130 may be equal to or less than the distance P2 between the first substrate interconnection patterns 120. The distance P1 between the outer pads 130 may be in the range of 10 μm to 150 μm. However, the thickness T1 and the distance P1 of the outer pads 130 are not limited to the above ranges. The outer pads 130 may include a conductive material. For example, the outer pads 130 may be formed of at least one metal material (e.g., copper (Cu)), or include at least one metal material (e.g., copper (Cu)).

[0028] The substrate protection layer 140 may be disposed on the bottom surface of the first substrate interconnection layer. The substrate protection layer 140 may cover the bottom surface of the first substrate interconnection layer and may expose the outer pad 130. For example, the top surface of the outer pad 130 may be exposed to the outside of the substrate protection layer 140 near the top surface of the substrate protection layer 140, and the bottom surface of the outer pad 130 may be exposed to the outside of the substrate protection layer 140 near the bottom surface of the substrate protection layer 140. In other words, the outer pad 130 may vertically penetrate the substrate protection layer 140. The top surface of the outer pad 130 and the top surface of the substrate protection layer 140 may be coplanar with each other, and the bottom surface of the outer pad 130 and the bottom surface of the substrate protection layer 140 may be coplanar with each other. The substrate protection layer 140 may include a material different from the first substrate insulation pattern 110. For example, the substrate protection layer 140 may include a molding member. In some embodiments, the molding member may include an insulating polymer material (e.g., epoxy molding compound (EMC) or Ajinomoto build-up film (ABF)).

[0029] In some embodiments, the outer pad 130 may not protrude to an area on the bottom surface of the substrate protection layer 140. In addition, the outer pad 130 may have a thickness equal to or less than the substrate interconnect pattern 120. That is, the pad layer PL may have a small thickness, and this may make it possible to reduce the size of the semiconductor package. In addition, the outer pad 130 may be provided to have a width and distance equal to or similar to the width and distance of the substrate interconnect pattern 120. Therefore, the integration density of the outer pad 130 for connecting the semiconductor package to an external device may be increased, and the planar size of the outer pad 130 may be reduced. That is, the semiconductor package may be provided to have a reduced size and an increased integration density.

[0030] Return to reference Figure 1 and Figure 2 , the pad layer PL may have a total thickness variation (TTV) of 0 or more. In the present specification, the total thickness variation (TTV) may be defined as the maximum variation of the thickness of the substrate or wafer, and may be calculated as the maximum variation of the thickness of the substrate or wafer measured at multiple positions of the substrate or wafer. The total thickness variation (TTV) of the pad layer PL may be in the range of 0 μm to 10 μm. Regarding the shape of the pad layer PL, the top surface PLa of the pad layer PL may have a surface flatness different from that of the bottom surface PLb of the pad layer PL. For example, the surface flatness of the top surface PLa of the pad layer PL may be greater than the surface flatness of the bottom surface PLb of the pad layer PL. In some embodiments, the top surface PLa of the pad layer PL may be substantially flat. In other words, the top surface of the substrate protection layer 140 and the top surface of the outer pad 130 may be substantially flat and may be located at substantially the same level. The bottom surface PLb of the pad layer PL may have an uneven shape. For example, the bottom surface of the substrate protection layer 140 and the bottom surface of the outer pad 130 may be curved or bent. In detail, the bottom surface PLb of the pad layer PL may have a waveform shape. For example, the bottom surface PLb may have a waveform shape in which concave and convex (e.g., recessed and protruding) portions are repeated, wherein the concave or recessed portion is concavely curved in a direction toward the inside of the pad layer PL, and the convex or protruding portion is convexly curved in a direction away from the pad layer PL. Here, the level difference between the high point and the low point in the waveform structure of the bottom surface PLb (i.e., the height difference between the concave portion and the convex portion) may be in the range of 0 μm to 10 μm.

[0031] In some embodiments, even when the bottom surface PLb of the pad layer PL has an uneven shape, the top surface PLa of the pad layer PL may have a flat shape. In other words, even when the pad layer PL has a large total thickness variation (TTV), the first substrate interconnect layer disposed on the pad layer PL may be disposed to have a flat or planarized shape, and the conductive pillars 310 disposed on the first substrate interconnect layer may be placed at substantially the same level. This enables the structural stability of the semiconductor package to be improved. While forming the first redistribution layer 100, the total thickness variation (TTV) of the pad layer PL may have a limited value. This will be described in more detail with reference to the manufacturing method described below.

[0032] Return to reference Figure 1 and Figure 2 , the external terminal 150 may be disposed on the exposed bottom surface of the external pad 130. The external terminal 150 may include a solder ball or a solder bump, and the semiconductor package may include the solder ball or the solder bump, and the semiconductor package may be classified into a ball grid array (BGA) package, a fine ball grid array (FBGA) package, or a land grid array (LGA) package according to the type and arrangement of the external terminal 150.

[0033] The bridge chip 200 may be disposed on the first redistribution layer 100. The bridge chip 200 may be disposed on the central area of ​​the first redistribution layer 100. The bridge chip 200 may be in contact with the top surface of the first redistribution layer 100. In detail, the bridge chip 200 may be placed between a portion of the first substrate interconnection pattern 120 (e.g., the redistribution pad of the first redistribution layer 100) exposed from the first substrate insulation pattern 110. The bridge chip 200 may be attached to the top surface of the first substrate insulation pattern 110. The bridge chip 200 may have a front surface and a rear surface. Hereinafter, in this specification, the front surface may be defined as a surface of a semiconductor chip, which serves as an active surface having an integrated device and on which an interconnection line or pad is formed; and the rear surface may be defined as a surface opposite to the front surface of the semiconductor chip. The rear surface of the bridge chip 200 may face the first redistribution layer 100. That is, the bridge chip 200 may be disposed on the first redistribution layer 100 in a face-up manner. The bridge chip 200 may be attached to the first redistribution layer 100 using an adhesive layer 202. For example, the adhesive layer 202 may be interposed between the bottom surface of the bridge chip 200 and the top surface of the first redistribution layer 100 (i.e., the top surface of the first substrate insulation pattern 110). The redistribution pads of the first redistribution layer 100 may not be disposed under the bridge chip 200. The bridge chip 200 may include a bridge base layer 210 and a bridge interconnect layer 220.

[0034] The bridging base layer 210 may include a semiconductor substrate. For example, the bridging base layer 210 may be a semiconductor substrate (e.g., a semiconductor wafer). The bridging base layer 210 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V semiconductor substrate, or a substrate including an epitaxial film formed by a selective epitaxial growth (SEG) process. The bridging base layer 210 may be formed of at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs).

[0035] The bridge interconnection layer 220 may be disposed on the top surface of the bridge base layer 210. For example, the bridge interconnection layer 220 may include a bridge insulation pattern 222 and a bridge interconnection pattern 224 formed on the top surface of the bridge base layer 210. If necessary, the bridge interconnection layer 220 may further include a circuit pattern or a protective layer.

[0036] The bridging insulating pattern 222 may include an insulating material. For example, the bridging insulating pattern 222 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or an insulating polymer, or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or an insulating polymer. Alternatively, the bridging insulating pattern 222 may be formed of at least one of an insulating polymer or a photoimageable dielectric (PID) material, or include at least one of an insulating polymer or a photoimageable dielectric (PID) material. Here, the PID material may include at least one of a photoimageable polyimide (PI), a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0037] The bridging interconnection pattern 224 may be disposed in the bridging insulating pattern 222. The bridging interconnection pattern 224 may be an element for electrical connection between the semiconductor chips 500. The bridging interconnection pattern 224 may include a conductive material. For example, the bridging interconnection pattern 224 may be formed of at least one of a conductive material (e.g., copper (Cu) or aluminum (Al)), or include at least one of a conductive material (e.g., copper (Cu) or aluminum (Al)).

[0038] Figure 1An example in which the bridge insulation pattern 222 is a single layer is shown, but the present disclosure is not limited to this example. In some embodiments, the bridge insulation pattern 222 may have a plurality of insulation layers, and the bridge interconnection pattern 224 may be an interconnection pattern disposed in the insulation layer.

[0039] The bridge chip 200 may include a chip bump 230 disposed on the top surface of the bridge chip 200. The chip bump 230 may be disposed on the top surface of the bridge chip 200 (i.e., the top surface of the bridge interconnect layer 220). For example, the chip bump 230 may protrude to a level higher than the top surface of the bridge chip 200. However, the present disclosure is not limited to this example, and the chip bump 230 may be a part of the bridge interconnect pattern 224 and may be disposed in the bridge insulation pattern 222. In this case, the chip bump 230 may be exposed to the outside of the bridge insulation pattern 222 near the top surface of the bridge insulation pattern 222. The chip bump 230 may be connected to the bridge interconnect pattern 224 of the bridge interconnect layer 220. At least some of the chip bumps 230 may be electrically connected to other chip bumps 230 in the chip bump 230 via the bridge interconnect pattern 224. Figure 1 A portion of the bridge interconnection pattern 224 is shown, and the chip bumps 230 may not be disconnected from each other or may not be in an electrically floating state.

[0040] Figure 1 An example in which the bridge chip 200 is provided for electrical connection between the semiconductor chips 500 is shown, but the present disclosure is not limited to this example. For example, a passive device chip such as a resistor, a capacitor, or an inductor may be provided instead of the bridge chip 200 .

[0041] The conductive pillar 310 may be disposed on the first redistribution layer 100. The conductive pillar 310 may be disposed on an edge region of the first redistribution layer 100. For example, the conductive pillar 310 may be horizontally spaced apart from the bridge chip 200. The conductive pillar 310 may be disposed on a redistribution pad of the first redistribution layer 100. In detail, each conductive pillar 310 may be in direct contact with the top surface of one of the first substrate interconnect patterns 120 in the first redistribution layer 100. The conductive pillar 310 may be an element for connecting the first redistribution layer 100 to the second redistribution layer 400 described below. That is, the conductive pillar 310 may correspond to a vertical connection terminal. The conductive pillar 310 may be a columnar pattern extending in a direction perpendicular to the top surface of the first redistribution layer 100. However, the present disclosure is not limited to this example, and the conductive pillar 310 may have various shapes that allow vertical connection. The width of the conductive pillar 310 may be uniform in the vertical direction. For example, each conductive pillar 310 may be a columnar pattern having a uniform width. Figure 1Unlike shown in , the width of the conductive pillar 310 can decrease as the distance from the first redistribution layer 100 decreases. The top surface of the conductive pillar 310 and the top surface of the chip bump 230 of the bridge chip 200 can be located on the same plane. The conductive pillar 310 may include a conductive material. For example, the conductive pillar 310 may be formed of at least one metal material (e.g., copper (Cu) or tungsten (W)), or include at least one metal material (e.g., copper (Cu) or tungsten (W)).

[0042] Each conductive pillar 310 may further include a seed layer 312 disposed to surround the side surface thereof. The seed layer 312 may extend to the bottom surface of the conductive pillar 310. That is, the conductive pillar 310 may be connected to the redistribution pad of the first redistribution layer 100 through the seed layer 312 interposed therebetween. The seed layer 312 may conformally cover the bottom surface and the side surface of the conductive pillar 310. The thickness of the seed layer 312 may be between 100 and 200 nm. to The seed layer 312 may include a metal material (eg, gold (Au)).

[0043] The first mold layer 320 may be disposed on the first redistribution layer 100. The first mold layer 320 on the first redistribution layer 100 may surround the bridge chip 200 and the conductive pillar 310. The first mold layer 320 may cover the bridge interconnect layer 220 of the bridge chip 200. Here, the first mold layer 320 may surround the chip bump 230 of the bridge chip 200. The chip bump 230 may not be covered by the first mold layer 320 and may be exposed to the outside of the first mold layer 320 near the top surface of the first mold layer 320. The top surface of the first mold layer 320, the top surface of the chip bump 230, and the top surface of the conductive pillar 310 may be substantially flat and may be coplanar with each other. The first mold layer 320 may include a molding member. In some embodiments, the molding member may include an insulating polymer material (e.g., epoxy molding compound (EMC) or Ajinomoto build-up film (ABF)).

[0044] The second redistribution layer 400 may be disposed on the bridge chip 200, the conductive pillars 310, and the first mold layer 320. The second redistribution layer 400 may directly contact the top surfaces of the chip bumps 230 of the bridge chip 200, the conductive pillars 310, and the first mold layer 320.

[0045] The second redistribution layer 400 may include one or more second substrate interconnection layers stacked on top of each other. Each second substrate interconnection layer may include a second substrate insulation pattern 410, and a second substrate interconnection pattern 420 in the second substrate insulation pattern 410. In the case where a plurality of second substrate interconnection layers are provided, the second substrate interconnection pattern 420 of one of the second substrate interconnection layers may be electrically connected to the second substrate interconnection pattern 420 of another second substrate interconnection layer adjacent thereto.

[0046] The second substrate insulating pattern 410 may be formed of or include at least one of an insulating polymer or a photoimageable polymer (e.g., a photoimageable dielectric (PID) material). For example, the photoimageable polymer may include at least one of a photoimageable polyimide (PI), a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0047] The second substrate interconnection pattern 420 may be disposed on the second substrate insulation pattern 410. The second substrate interconnection pattern 420 on the second substrate insulation pattern 410 may extend horizontally. The second substrate interconnection pattern 420 may be disposed on the top surface of the second substrate insulation pattern 410. The second substrate interconnection pattern 420 may include a protruding portion extending to a level higher than the top surface of the second substrate insulation pattern 410. The second substrate interconnection pattern 420 on the second substrate insulation pattern 410 may be covered by another second substrate insulation pattern 410 disposed thereon. The second substrate interconnection pattern 420 disposed in the uppermost second substrate interconnection layer of the second substrate interconnection layer may be used as a substrate pad, wherein the semiconductor chip 500 is coupled to the substrate pad. As described above, the second substrate interconnection pattern 420 may be a pad portion or a wiring portion of the second substrate interconnection layer. In other words, the second substrate interconnection pattern 420 may be an element for horizontal redistribution in the second redistribution layer 400. The second substrate interconnection pattern 420 may include a conductive material. For example, the second substrate interconnection pattern 420 may be formed of at least one metal material (e.g., copper (Cu)), or include at least one metal material (e.g., copper (Cu)).

[0048] The second substrate interconnection pattern 420 may have a mosaic structure. For example, the second substrate interconnection pattern 420 may include a via portion extending protrudingly from its bottom surface. The via portion may be an element for vertically connecting the second substrate interconnection patterns 420 of adjacent second substrate interconnection layers of the second substrate interconnection layer to each other. For example, the via portion may extend from the bottom surface of the second substrate interconnection pattern 420 to penetrate the second substrate insulation pattern 410, and may be coupled to the top surface of the second substrate interconnection pattern 420 of another second substrate interconnection layer below it. Alternatively, the via portion may be an element for connecting the second substrate interconnection pattern 420 of the lowest second substrate interconnection layer of the second substrate interconnection layer to the conductive pillar 310, or for connecting the second substrate interconnection pattern 420 of the lowest second substrate interconnection layer of the second substrate interconnection layer to the chip bump 230. For example, the via portion may extend from the bottom surface of the second substrate interconnection pattern 420 to penetrate the lowest second substrate insulation pattern 410 of the second substrate insulation pattern 410, and may be coupled to the top surface of the conductive pillar 310, or the top surface of the chip bump 230. In other words, the bridge chip 200 can be mounted on the bottom surface of the second redistribution layer 400 using the chip bump 230. In other words, the upper portion of the second substrate interconnection pattern 420 placed on the second substrate insulation pattern 410 can be a head used as a horizontal interconnection line or a pad, and the via portion of the second substrate interconnection pattern 420 can be a tail. The width of the tail can be less than the width of the head. The width of the tail can decrease as the distance from the head of the second substrate interconnection pattern 420 increases. In other words, the tail can have a tapered shape. The second substrate interconnection pattern 420 can have the shape of the letter "T".

[0049] Although not shown, the second seed / barrier layer may be disposed between the second substrate interconnection pattern 420 and the second substrate insulation pattern 410. Each second seed / barrier layer may cover the bottom surface of one of the second substrate interconnection patterns 420. In some embodiments, the second seed / barrier layer may conformally cover the bottom surface of the second substrate interconnection pattern 420. The second seed / barrier layer may be disposed to expose the side surface of the second substrate interconnection pattern 420. Alternatively, each second seed / barrier layer may be disposed to cover the bottom surface and the side surface of one of the second substrate interconnection patterns 420. In this case, the second seed / barrier layer may conformally cover the bottom surface and the side surface of the second substrate interconnection pattern 420. The distance between the second substrate insulation pattern 410 and the second substrate interconnection pattern 420 (i.e., the thickness of the second seed / barrier layer) may be at to In the case where the second seed crystal / barrier layer is used as a seed crystal layer, the second seed crystal / barrier layer may include a metal material, such as gold (Au). In the case where the second seed crystal / barrier layer is used as a barrier layer, the second seed crystal / barrier layer may include a metal material such as titanium (Ti) and tantalum (Ta), or a metal nitride material such as titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the second seed crystal / barrier layer may not be provided.

[0050] The semiconductor chip 500 may be disposed on the second redistribution layer 400. Each semiconductor chip 500 may include at least two parts, one of which vertically overlaps the bridge chip 200, and the other of which vertically overlaps at least one of the conductive pillars 310. However, the present disclosure is not limited to this example. The arrangement of the semiconductor chip 500 may be variously changed according to the interconnection layout of the second redistribution layer 400. The semiconductor chip 500 may include a chip substrate layer 510 and a chip interconnection layer 520.

[0051] The chip base layer 510 may include a semiconductor substrate. For example, the chip base layer 510 may be a semiconductor substrate, such as a semiconductor wafer. The chip base layer 510 may be a silicon substrate, a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a germanium on insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V semiconductor substrate, or a substrate including an epitaxial film formed by a selective epitaxial growth (SEG) process. The chip base layer 510 may be formed of at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). An integrated circuit may be disposed on the bottom surface of the chip base layer 510. The integrated circuit may include a logic circuit or a memory circuit. That is, the semiconductor chip 500 may be a logic chip or a memory chip. However, the present disclosure is not limited to this example, and the semiconductor chip 500 may include a logic chip, a memory chip, a semiconductor chip with other integrated circuits, or a passive device. The integrated circuits provided in the semiconductor chip 500 may be the same or different from each other. That is, the semiconductor chip 500 may be a semiconductor chip of the same kind or different kinds. The bottom surface of the semiconductor chip 500 may be an active surface, and the top surface of the semiconductor chip 500 may be a non-active surface. In other words, the semiconductor chip 500 may be provided on the second redistribution layer 400 in a face-down manner.

[0052] The chip interconnection layer 520 may be disposed on the bottom surface of the chip substrate layer 510. For example, the chip interconnection layer 520 may include a chip insulation pattern 522 and a chip interconnection pattern 524 formed on the bottom surface of the chip substrate layer 510. In some embodiments, the chip interconnection layer 520 may further include a circuit pattern or a protective layer.

[0053] The chip insulation pattern 522 on the bottom surface of the chip substrate layer 510 may cover the integrated circuit. The chip insulation pattern 522 may include an insulating material. For example, the chip insulation pattern 522 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or an insulating polymer, or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or an insulating polymer. Alternatively, the chip insulation pattern 522 may be formed of at least one of an insulating polymer or a photoimageable polymer (e.g., a photoimageable dielectric (PID) material), or include at least one of an insulating polymer or a photoimageable polymer (e.g., a photoimageable dielectric (PID) material). For example, the photoimageable polymer may include at least one of a photoimageable polyimide (PI), a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0054] The chip interconnection pattern 524 may be disposed in the chip insulation pattern 522. The chip interconnection pattern 524 may be electrically connected to an integrated circuit formed on the bottom surface of the chip substrate layer 510. The chip interconnection pattern 524 may include a conductive material. For example, the chip interconnection pattern 524 may be formed of copper (Cu) or aluminum (Al), or include copper (Cu) or aluminum (Al).

[0055] The semiconductor chip 500 may include a chip pad 526 disposed on the bottom surface thereof. The chip pad 526 may be disposed on the bottom surface of the semiconductor chip 500 (i.e., the bottom surface of the chip interconnection layer 520). That is, the chip pad 526 may be exposed to the outside of the semiconductor chip 500 near the bottom surface of the semiconductor chip 500. The chip pad 526 may be electrically connected to the integrated circuit formed on the bottom surface of the chip substrate layer 510 through the chip interconnection pattern 524 in the chip interconnection layer 520.

[0056] The semiconductor chip 500 may be mounted on the second redistribution layer 400. For example, the semiconductor chip 500 may be mounted on the second redistribution layer 400 in a flip chip manner. In detail, the semiconductor chip 500 may be electrically connected to the substrate pad of the second redistribution layer 400 through the connection terminal 530. The connection terminal 530 may be provided between the chip pad 526 and the substrate pad of the second redistribution layer 400. The semiconductor chip 500 may be electrically connected to each other through the connection terminal 530, the second redistribution layer 400, and the bridge chip 200. The semiconductor chip 500 may be electrically connected to the first redistribution layer 100 through the connection terminal 530, the second redistribution layer 400, and the conductive pillar 310. Since the semiconductor chip 500 is mounted using the connection terminal 530, the semiconductor chip 500 may be spaced apart from the top surface of the second redistribution layer 400.

[0057] The second mold layer 600 may be disposed on the second redistribution layer 400. The second mold layer 600 on the second redistribution layer 400 may surround the semiconductor chip 500. The second mold layer 600 may cover the semiconductor chip 500. In some embodiments, the semiconductor chip 500 may have a top surface exposed to the outside of the second mold layer 600 near the top surface of the second mold layer 600. The second mold layer 600 may fill the space between the semiconductor chip 500 and the second redistribution layer 400. Under the semiconductor chip 500, the second mold layer 600 may surround the connection terminal 530. The second mold layer 600 may include a molding member. In some embodiments, the molding member may include an insulating polymer material (e.g., epoxy molding compound (EMC) or Ajinomoto build-up film (ABF)).

[0058] In the following, for the convenience of description, the previous reference Figures 1 to 3 The elements described herein may be identified by the same reference numerals and will not be described in detail. Figures 1 to 3 The technical features in the implementation methods are different from the technical features.

[0059] Figure 4 is a cross-sectional view showing an example of a semiconductor package.

[0060] refer to Figure 4 ,and Figures 1 to 3 Unlike the embodiments described above, the semiconductor package does not include the second redistribution layer 400 .

[0061] The bridge chip 200, the conductive pillars 310, and the first mold layer 320 may be disposed on the first redistribution layer 100. Top surfaces of the first mold layer 320, the chip bumps 230, and the conductive pillars 310 may be substantially flat and may be coplanar with each other.

[0062] The semiconductor chip 500 may be mounted on the bridge chip 200, the conductive pillar 310, and the first mold layer 320. For example, the semiconductor chip 500 may be mounted in a flip chip manner. In detail, each semiconductor chip 500 may be electrically connected to the conductive pillar 310 and the chip bump 230 of the bridge chip 200 through the connection terminal 530. The semiconductor chips 500 may be electrically connected to each other through the connection terminal 530 and the bridge chip 200. The semiconductor chip 500 may be electrically connected to the first redistribution layer 100 through the connection terminal 530 and the conductive pillar 310.

[0063] The second mold layer 600 may be disposed on the first mold layer 320. The second mold layer 600 on the first mold layer 320 may surround the semiconductor chip 500. The second mold layer 600 may cover the semiconductor chip 500.

[0064] Figure 5 is a cross-sectional view showing an example of a semiconductor package.

[0065] refer to Figure 5 The bridge chip 200 further includes a chip via 212 and a chip backside pad 242 .

[0066] The chip via 212 may be disposed to vertically penetrate the bridging substrate layer 210 and may be connected to the bridging interconnect layer 220. The chip via 212 may be exposed to the outside of the bridging substrate layer 210 near the inactive surface of the bridging substrate layer 210 (i.e., the bottom surface of the bridging substrate layer 210). The chip via 212 may include a conductive material. For example, the chip via 212 may be formed of at least one of a metal material (e.g., copper (Cu) or tungsten (W)), or include at least one of a metal material (e.g., copper (Cu) or tungsten (W)).

[0067] The chip backside pads 242 may be disposed on the bottom surface of the bridging substrate layer 210. Each chip backside pad 242 on the bottom surface of the bridging substrate layer 210 may be connected to a corresponding chip via 212 in the chip vias 212. The chip backside pads 242 may include a conductive material. For example, the chip backside pads 242 may be formed of, or include, for example, at least one of a metal material (e.g., copper (Cu) or tungsten (W)).

[0068] The back protective layer 244 may be disposed on the bottom surface of the bridging substrate layer 210. The back protective layer 244 may cover the bottom surface of the bridging substrate layer 210. The back protective layer 244 may surround the chip back pad 242. Here, the bottom surface of the back protective layer 244 and the bottom surface of the chip back pad 242 may be substantially flat and may be coplanar with each other. The back protective layer 244 may include an insulating material. For example, the back protective layer 244 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), or include at least one of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In some embodiments, the back protective layer 244 may not be provided.

[0069] The bridge chip 200 may be disposed on the first redistribution layer 100. The bridge chip 200 may be in contact with the top surface of the first redistribution layer 100. In detail, the chip backside pad 242 and the backside protection layer 244 of the bridge chip 200 may be in contact with the top surface of the first redistribution layer 100. Here, the first substrate interconnection pattern 120 of the first redistribution layer 100 may be connected to the chip backside pad 242. Therefore, the bridge chip 200 may be electrically connected to the first redistribution layer 100 through the chip via 212 and the chip backside pad 242.

[0070] The first redistribution layer 100 may further include an additional first substrate insulating pattern 110 disposed on the first substrate insulating pattern 110 to surround the redistribution pad (i.e., the first substrate interconnection pattern 120). The top surface of the additional first substrate insulating pattern 110 and the top surface of the first substrate interconnection pattern 120 may be substantially flat and may be coplanar with each other. In this case, the additional first substrate insulating pattern 110 may be in direct contact with the back side protective layer 244 of the bridge chip 200.

[0071] Figure 6 is a cross-sectional view showing an example of a semiconductor package.

[0072] refer to Figure 6 , the bridge chip 200 is disposed on the first redistribution layer 100. The bridge chip 200 has a front surface and a rear surface. The front surface of the bridge chip 200 faces the first redistribution layer 100. That is, the bridge chip 200 is disposed on the first redistribution layer 100 in a face-down manner. The bridge chip 200 includes a bridge substrate layer 210 and a bridge interconnect layer 220.

[0073] The bridge interconnection layer 220 may be disposed on the bottom surface of the bridge substrate layer 210. For example, the bridge interconnection layer 220 may include a bridge insulation pattern 222 and a bridge interconnection pattern 224 formed on the bottom surface of the bridge substrate layer 210.

[0074] The bridge chip 200 may be disposed on the first redistribution layer 100. The bridge chip 200 may be in contact with the top surface of the first redistribution layer 100. In detail, the bridge interconnection layer 220 of the bridge chip 200 may be in contact with the top surface of the first redistribution layer 100. Here, the first substrate interconnection pattern 120 of the first redistribution layer 100 may be connected to the bridge interconnection pattern 224 of the bridge interconnection layer 220. Therefore, the bridge chip 200 may be electrically connected to the first redistribution layer 100.

[0075] The conductive pillar 310 may be disposed on the first redistribution layer 100. The conductive pillar 310 may be disposed on an edge region of the first redistribution layer 100. For example, the conductive pillar 310 may be horizontally spaced apart from the bridge chip 200.

[0076] The first mold layer 320 may be disposed on the first redistribution layer 100. The first mold layer 320 on the first redistribution layer 100 may surround the bridge chip 200 and the conductive pillars 310. The first mold layer 320 may cover the bridge chip 200. Accordingly, the bridge chip 200 may be exposed to the outside of the first mold layer 320 near the top surface of the first mold layer 320. Alternatively, the top surface of the bridge chip 200 (i.e., the rear surface of the bridge substrate layer 210) may be exposed to the outside of the first mold layer 320 near the top surface of the first mold layer 320.

[0077] The second redistribution layer 400 may be disposed on the conductive pillar 310 and the first mold layer 320. The second redistribution layer 400 may directly contact the top surface of the conductive pillar 310 and the top surface of the first mold layer 320. The second substrate interconnection pattern 420 of the second redistribution layer 400 may be connected to the conductive pillar 310.

[0078] The semiconductor chip 500 may be mounted on the second redistribution layer 400. The semiconductor chip 500 may be electrically connected to the bridge chip 200 through the second redistribution layer 400, the conductive pillars 310, and the first redistribution layer 100.

[0079] Figure 7 is a cross-sectional view showing an example of a semiconductor package.

[0080] refer to Figure 7 ,and Figure 6 Different from the implementation manner, the bridge chip 200 of the semiconductor package further includes a chip via 212 and a chip backside pad 242 .

[0081] The chip via 212 may be disposed to vertically penetrate the bridging substrate layer 210 and may be connected to the bridging interconnection layer 220. The chip via 212 may be exposed to the outside of the bridging substrate layer 210 near an inactive surface (ie, a top surface) of the bridging substrate layer 210.

[0082] The chip back side pads 242 may be disposed on the top surface of the bridging substrate layer 210. Each of the chip back side pads 242 on the top surface of the bridging substrate layer 210 may be connected to a corresponding one of the chip vias 212.

[0083] The back protective layer 244 may be disposed on the top surface of the bridging substrate layer 210. The back protective layer 244 may cover the top surface of the bridging substrate layer 210. The back protective layer 244 may surround the chip back pad 242. Here, the top surface of the back protective layer 244 and the top surface of the chip back pad 242 may be substantially flat and may be coplanar with each other.

[0084] The first mold layer 320 may be disposed on the first redistribution layer 100. The first mold layer 320 on the first redistribution layer 100 may surround the bridge chip 200 and the conductive pillars 310. The top surface of the bridge chip 200 may be exposed to the outside of the first mold layer 320 near the top surface thereof.

[0085] The second redistribution layer 400 may be disposed on the bridge chip 200, the conductive pillars 310, and the first mold layer 320. The second redistribution layer 400 may be in direct contact with the top surface of the bridge chip 200, the top surface of the conductive pillars 310, and the top surface of the first mold layer 320. The second substrate interconnection pattern 420 of the second redistribution layer 400 may be connected to the chip backside pad 242 of the bridge chip 200 and the conductive pillars 310.

[0086] The semiconductor chip 500 may be mounted on the second redistribution layer 400. The semiconductor chip 500 may be electrically connected to the first redistribution layer 100 through the second redistribution layer 400 and the conductive pillars 310, or may be electrically connected to the first redistribution layer 100 through the second redistribution layer 400 and the bridge chip 200. The semiconductor chips 500 may be electrically connected to each other through the second redistribution layer 400 and the bridge chip 200.

[0087] Figure 8 is a cross-sectional view showing an example of a semiconductor package.

[0088] refer to Figure 8 , the semiconductor package includes a chip stack 700 disposed to replace one of the semiconductor chips 500. Hereinafter, the semiconductor chip 500 directly mounted on the second redistribution layer 400 will be referred to as a first semiconductor chip 500.

[0089] The first semiconductor chip 500 may include a logic circuit. In other words, the first semiconductor chip 500 may be a logic chip. As an example, the first semiconductor chip 500 may include a graphics processing unit.

[0090] The chip stack 700 may be disposed on the second redistribution layer 400. The chip stack 700 may be spaced apart from the first semiconductor chip 500. The thickness of the first semiconductor chip 500 may be greater than the thickness of the semiconductor chips 710 and 720 of the chip stack 700. The top surface of the chip stack 700 may be located at a level equal to or higher than the top surface of the first semiconductor chip 500.

[0091] The chip stack 700 may include a base substrate, a second semiconductor chip 720 stacked on the base substrate, and a mold layer 730 surrounding the second semiconductor chip 720. Hereinafter, the structure of the chip stack 700 will be described in more detail.

[0092] The base substrate may be a base semiconductor chip 710. For example, the base substrate may be a wafer-level semiconductor substrate formed of a semiconductor material, such as silicon (Si). Hereinafter, the base semiconductor chip 710 may be the same element as the base substrate, and the same reference numerals may be used to identify the base semiconductor chip and the base substrate.

[0093] The basic semiconductor chip 710 may include a basic circuit layer 712 and a basic through-electrode 714. The basic circuit layer 712 may be disposed on the bottom surface of the basic semiconductor chip 710. The basic circuit layer 712 may include an integrated circuit. For example, the basic circuit layer 712 may be a memory circuit. That is, the basic semiconductor chip 710 may be one of memory chips such as DRAM, SRAM, MRAM, and flash memory chips. Alternatively, the basic semiconductor chip 710 may be a logic chip. The basic through-electrode 714 may penetrate the basic semiconductor chip 710 in a direction perpendicular to the top surface of the second redistribution layer 400. The basic through-electrode 714 and the basic circuit layer 712 may be electrically connected to each other. The bottom surface of the basic semiconductor chip 710 may be an active surface. In some embodiments, the base substrate may be an interconnect substrate that does not include the basic semiconductor chip 710.

[0094] The second semiconductor chip 720 may be mounted on the base semiconductor chip 710. That is, the second semiconductor chip 720 and the base semiconductor chip 710 may form a chip-on-wafer (COW) structure. The width of the second semiconductor chip 720 may be smaller than that of the base semiconductor chip 710.

[0095] The second semiconductor chip 720 may include a second circuit layer 722 and a chip through electrode 724. The second circuit layer 722 may include a memory circuit. In other words, the second semiconductor chip 720 may be one of memory chips such as DRAM, SRAM, MRAM, and flash memory chips. The second circuit layer 722 may include the same circuit as the base circuit layer 712, but the present disclosure is not limited to this example. The chip through electrode 724 may penetrate the second semiconductor chip 720 in a direction perpendicular to the top surface of the second redistribution layer 400. The chip through electrode 724 and the second circuit layer 722 may be electrically connected to each other. The bottom surface of the second semiconductor chip 720 may be an active surface.

[0096] The second semiconductor chip 720 may be bonded to the base semiconductor chip 710. For example, the pads of the second circuit layer 722 of the second semiconductor chip 720 may contact the top surface of the base through-electrode 714, which is exposed to the outside of the base semiconductor chip 710 near the top surface of the base semiconductor chip 710. Alternatively, the second semiconductor chip 720 may be mounted on the top surface of the base through-electrode 714 using a terminal provided on the pads of the second circuit layer 722.

[0097] In some embodiments, a plurality of second semiconductor chips 720 may be provided. For example, a plurality of second semiconductor chips 720 may be stacked on the base semiconductor chip 710. In some embodiments, the number of stacked second semiconductor chips 720 may be in the range of 4 to 32. Here, the uppermost second semiconductor chip of the second semiconductor chips 720 may not include the chip through-electrode 724. In addition, the thickness of the uppermost second semiconductor chip of the second semiconductor chips 720 may be greater than the thickness of the second semiconductor chip 720 therebelow.

[0098] The second semiconductor chips 720 adjacent to each other may be bonded to each other. For example, the pads of the second circuit layer 722 in each second semiconductor chip 720 may contact the top surface of the chip through-electrode 724, and the chip through-electrode 724 is exposed to the outside of the second semiconductor chip 720 near the top surface of the second semiconductor chip 720 therebelow. Alternatively, the second semiconductor chip 720 may be mounted on the top surface of the chip through-electrode 724 using a terminal provided on the pads of the second circuit layer 722.

[0099] The mold layer 730 may be disposed on the top surface of the base semiconductor chip 710. The mold layer 730 may cover the base semiconductor chip 710, and may surround the second semiconductor chip 720. The top surface of the mold layer 730 may be coplanar with the top surface of the uppermost second semiconductor chip of the second semiconductor chips 720, and the uppermost second semiconductor chip of the second semiconductor chips 720 may be exposed from the mold layer 730. The mold layer 730 may include an insulating polymer material (e.g., epoxy mold compound (EMC)).

[0100] The chip stack 700 may be provided to have the aforementioned structure.

[0101] The connection terminal 702 may be disposed on a bottom surface of the chip stack 700 (ie, a bottom surface of the base circuit layer 712 ). The chip stack 700 may be coupled to the second redistribution layer 400 through the connection terminal 702 .

[0102] The second mold layer 600 may be disposed on the second redistribution layer 400. The second mold layer 600 may cover a top surface of the second redistribution layer 400. The second mold layer 600 may surround the first semiconductor chip 500 and the chip stack 700. A top surface of the second mold layer 600 may be located at the same level as a top surface of the chip stack 700.

[0103] Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17 is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor package. Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B It shows Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A and Fig.16A An example enlarged cross-sectional view of portion "B".

[0104] refer to Fig. 9A and Fig. 9B , a carrier substrate 900 may be provided. The carrier substrate 900 may be an insulating substrate including at least one of an organic insulating material or a polymer material.

[0105] In the case where the carrier substrate 900 includes an organic insulating material or a polymer material, the total thickness variation (TTV) characteristic or the surface flatness characteristic of the carrier substrate 900 may deteriorate as the area of ​​the carrier substrate 900 increases. For example, the carrier substrate 900 may have an uneven shape. For example, the top surface of the carrier substrate 900 may have a waveform shape, and the bottom surface of the carrier substrate 900 may have a waveform shape. In some embodiments, each of the top and bottom surfaces of the carrier substrate 900 may have a waveform shape in which concave or convex (i.e., concave and convex) portions are repeated, wherein the concave or concave portion is concavely curved in a direction toward the inside of the carrier substrate 900, and the convex or convex portion is convexly curved in a direction away from the carrier substrate 900. Here, in the top and bottom surfaces of the carrier substrate 900, the level difference between the high point and the low point in the waveform structure (i.e., the height difference between the concave portion and the convex portion) may be in the range of 10 μm to 500 μm. The total thickness variation (TTV) of the carrier substrate 900 may be in the range of 10 μm to 500 μm.

[0106] The carrier substrate 900 may further include a seed layer 910 disposed on the top surface of the carrier substrate 900. As an example, the seed layer 910 may include a metal material (e.g., gold (Au)). In the case where the seed layer 910 is formed on the top surface of the carrier substrate 900, the surface shape of the top surface of the carrier substrate 900 may be copied to the seed layer 910. That is, the seed layer 910 may have an uneven shape, and the top surface 910a of the seed layer 910 may have a wavy shape.

[0107] refer to Fig. 10A and Fig. 10B , an outer pad 130 may be formed. In detail, a sacrificial layer may be formed by coating the carrier substrate 900 with a photoimageable material. An exposure and development process may be performed on the sacrificial layer to define an area in which the outer pad 130 is formed, and to form an opening exposing the top surface 910a of the seed layer 910. The opening formed by the photolithography process may have a uniform width in the vertical direction. The outer pad 130 may be formed by an electroplating process using the seed layer 910 exposed through the opening. Therefore, the outer pad 130 may have a uniform width in the vertical direction.

[0108] In some embodiments, the outer pad 130 may be formed by a photolithography process, wherein the external terminal 150 (eg, see Figure 1 ) are attached to the outer pads 130. Accordingly, the width or distance of the outer pads 130 can be easily reduced. In other words, the semiconductor package can be manufactured to have a reduced size.

[0109] The surface shape of the top surface 910a of the seed layer 910 may be copied to the outer pad 130. For example, the outer pad 130 may be formed to have an uneven shape. Therefore, the top surface 130a of the outer pad 130 may be formed to have an uneven shape. In some embodiments, the outer pad 130 may have top surfaces located at different levels depending on the position on the top surface 910a of the seed layer 910. For example, the level of the top surface of the outer pad 130 formed on the concave or recessed portion of the top surface 910a of the seed layer 910 may be lower than the top surface of the outer pad 130 formed on the convex or protruding portion of the top surface 910a of the seed layer 910.

[0110] refer to Fig.11A and Fig. 11B , a substrate protection layer 140 may be formed on the carrier substrate 900. For example, the substrate protection layer 140 may be formed by coating an insulating material on the seed layer 910 to cover the outer pad 130. In some embodiments, a curing process may be performed on the insulating material. The insulating material may be selected to allow a grinding or polishing process. The material may include an insulating polymer material (e.g., epoxy molding compound (EMC) or ajinomoto deposited film (ABF)). The outer pad 130 on the carrier substrate 900 may be buried in the substrate protection layer 140.

[0111] refer to Fig. 12A and Fig. 12B , a first planarization process may be performed on the substrate protection layer 140. For example, the first planarization process may include a chemical mechanical polishing (CMP) process. The first planarization process may be performed to expose the top surface of the outer pad 130. After exposing the top surface of the outer pad 130, the first planarization process may be further performed. For example, the first planarization process may be performed to effectively reduce the thickness of the outer pad 130. The thickness T1 of the outer pad 130 may be in the range of 5 μm to 20 μm. The pad layer PL may be formed by the first planarization process. After the first planarization process, the top surface of the substrate protection layer 140 and the top surface 130a of the outer pad 130 may be coplanar with each other. The top surface of the substrate protection layer 140 and the top surface 130a of the outer pad 130 may be substantially flat. The total thickness variation (TTV) of the pad layer PL may be in the range of 0 μm to 10 μm.

[0112] In some embodiments, a first planarization process may be performed on the pad layer PL. Therefore, even when the outer pad 130 is formed to have an uneven top surface due to the uneven shape of the carrier substrate 900, or the top surface of the outer pad 130 is formed at different levels, the pad layer PL may be formed to have a flat top surface. That is, the top surface 130a of each outer pad 130 may be formed to be flat, and further, the top surface 130a of the outer pad 130 may be formed at substantially the same level. As a result, when a back-end process is performed on the pad layer PL, process errors or failures that may be caused by an uneven surface or thickness variation may be reduced. In addition, the first planarization process may allow the pad layer PL to have a sufficiently small thickness, and in this case, the semiconductor package may be formed to have a reduced size.

[0113] refer to Fig.13A and Fig. 13B , a first substrate insulating pattern 110 may be formed on the substrate protection layer 140. The first substrate insulating pattern 110 may be formed using a deposition process or a coating process. The first substrate insulating pattern 110 may cover the substrate protection layer 140 and the outer pad 130. A first substrate interconnection pattern 120 may be formed on the first substrate insulating pattern 110. In some embodiments, the first substrate insulating pattern 110 may be patterned to form an opening exposing the outer pad 130, a seed layer may be formed to conformally cover the top surface of the first substrate insulating pattern 110 and the inner surface of the opening, an electroplating process using the seed layer may be performed to form a conductive layer covering the first substrate insulating pattern 110 and filling the opening, and the conductive layer and the seed layer may be patterned to form the first substrate interconnection pattern 120 and the first seed / barrier layer 122. The first substrate interconnection layer formed as a result of the above process may include the first substrate insulating pattern 110 disposed on the substrate protection layer 140 and the outer pad 130, and the first substrate interconnection pattern 120 disposed in the first substrate insulating pattern 110. The pad layer PL and the first substrate interconnection layer may constitute a first redistribution layer 100 .

[0114] Since the top surfaces 130a of the outer pads 130 are flat and located at the same level, top surfaces of the first substrate interconnection patterns 120 may be formed at substantially the same level.

[0115] refer to Fig.14A and Fig. 14B, a conductive pillar 310 may be formed. In detail, a sacrificial layer may be formed on the first redistribution layer 100. The sacrificial layer may cover the top surface of the first redistribution layer 100. The sacrificial layer may be patterned to form a hole exposing a substrate pad (i.e., a portion of the first substrate interconnect pattern 120) of the first redistribution layer 100. Then, the conductive pillar 310 may be formed by filling the hole with a conductive material. For example, a seed layer may be formed to conformally cover the top surface of the sacrificial layer and the inner surface of the hole, and an electroplating process using the seed layer may be performed to form the conductive pillar 310 filling the hole. Alternatively, the conductive pillar 310 may be formed by an electroplating process using the top surface of the first substrate interconnect pattern 120 exposed via the hole as a seed. Then, the sacrificial layer may be removed.

[0116] Since the top surfaces of the first substrate interconnection patterns 120 are formed at substantially the same level, the top surfaces of the conductive pillars 310 may be formed at substantially the same level.

[0117] The bridge chip 200 may be attached to the first redistribution layer 100. The bridge chip 200 may be provided with a Figures 1 to 8 An adhesive layer 202 may be used to attach the bridge chip 200 to the first redistribution layer 100 .

[0118] refer to Fig.15A and Fig. 15B , a first mold layer 320 may be formed on the first redistribution layer 100. For example, an insulating layer may be coated on the first redistribution layer 100 to cover the bridge chip 200 and the conductive pillar 310, and the insulating layer may be cured to form the first mold layer 320. The bridge chip 200 and the conductive pillar 310 on the first redistribution layer 100 may be buried in the first mold layer 320. The first mold layer 320 may include a molding member. In some embodiments, the molding member may include an insulating polymer material (e.g., epoxy molding compound (EMC) or Ajinomoto build-up film (ABF)).

[0119] refer to Fig.16A and Fig. 16B , a second planarization process may be performed on the first mold layer 320. For example, the second planarization process may include a chemical mechanical polishing (CMP) process. The second planarization process may be performed to expose the top surface of the conductive pillar 310 and the top surface of the chip bump 230 of the bridge chip 200. After the second planarization process, the top surface of the conductive pillar 310, the top surface of the first mold layer 320, and the top surface of the chip bump 230 may be coplanar with each other. In some embodiments, the top surface of the conductive pillar 310, the top surface of the first mold layer 320, and the top surface of the chip bump 230 may be substantially flat.

[0120] If the top surface of the pad layer PL has an uneven shape, the surface shape of the top surface of the pad layer PL may be copied to the first substrate interconnect layer formed on the pad layer PL. Accordingly, the top surfaces of the conductive pillars 310 formed on the pad layer PL and the first substrate interconnect layer may be formed at different levels or may have an uneven shape. In this case, in the second planarization process, some of the conductive pillars 310 may not be exposed from the top surface of the first mold layer 320 and may be buried in the first mold layer 320. The unopened conductive pillars in the conductive pillars 310 may not be electrically connected to the second redistribution layer 400 formed on the first mold layer 320; that is, there may be an electrical disconnection failure.

[0121] In some embodiments, after forming the outer pad 130, the substrate protection layer 140 may be formed using a molding member. Therefore, a first planarization process may be performed on the outer pad 130 and the substrate protection layer 140 to planarize the top surface of the pad layer PL. The first substrate interconnect layer and the conductive pillar 310 formed in the back-end process may be formed to have a flat top surface, and the top surface of the conductive pillar 310 may be formed at the same level. Therefore, when the second planarization process is performed on the first mold layer 320, the top surface of the conductive pillar 310 may be exposed substantially at the same time. That is, failures caused by the shape of the carrier substrate 900 or the pad layer PL in the back-end process may be reduced.

[0122] refer to Fig.17 , a second substrate insulating pattern 410 may be formed on the first mold layer 320. The second substrate insulating pattern 410 may be formed using a deposition process or a coating process. The second substrate insulating pattern 410 may cover the conductive pillars 310, the first mold layer 320, and the chip bumps 230. A second substrate interconnection pattern 420 may be formed on the second substrate insulating pattern 410. For example, the second substrate insulating pattern 410 may be patterned to form an opening exposing the conductive pillars 310 and the chip bumps 230, a seed layer may be formed to conformally cover the top surface of the second substrate insulating pattern 410 and the inner surface of the opening, an electroplating process using the seed layer may be performed to form a conductive layer covering the second substrate insulating pattern 410 and filling the opening, and then, the conductive layer may be patterned to form the second substrate interconnection pattern 420.

[0123] The second substrate interconnection layer formed as a result of the above process may include a second substrate insulation pattern 410 formed on the first mold layer 320, and a second substrate interconnection pattern 420 formed in the second substrate insulation pattern 410. The process of forming the second substrate interconnection layer may be repeatedly performed to form the second redistribution layer 400. The second substrate interconnection pattern 420 disposed in the uppermost second substrate interconnection layer of the second substrate interconnection layer may be used as a substrate pad on which the semiconductor chip 500 is mounted.

[0124] Thereafter, a singulation process may be performed on the carrier substrate 900 along the cutting lines SL. For example, the second redistribution layer 400, the first mold layer 320, and the first redistribution layer 100 may be sequentially cut through the singulation process. Here, the cutting lines SL may be horizontally spaced apart from the bridge chip 200 and the conductive pillars 310, and the bridge chip 200 and the conductive pillars 310 may not be cut by the singulation process.

[0125] Return to reference Figure 1 , the semiconductor chip 500 may be mounted on the second redistribution layer 400. The semiconductor chip 500 may be mounted in a flip chip manner.

[0126] The carrier substrate 900 may be removed. For example, the carrier substrate 900 and the seed layer 910 of the carrier substrate 900 may be removed to expose the bottom surface of the first redistribution layer 100.

[0127] The external terminal 150 may be disposed on the exposed bottom surface of the first redistribution layer 100, and may be coupled to the outer pad 130. The external terminal 150 may include a solder ball or a solder bump.

[0128] In some embodiments, in a semiconductor package, an external pad may be arranged to have a thickness equal to or similar to that of a substrate interconnect pattern. That is, the pad layer may be arranged to have a smaller thickness, and this may make it possible to reduce the size of the semiconductor package. In addition, the external pad may be arranged to have a width and distance equal to or similar to that of the substrate interconnect pattern. Therefore, the integration density of the external pad used to connect the semiconductor package to an external device may be increased, and the planar size of the external pad may be reduced. That is, the semiconductor package may be arranged to have a reduced size and an increased integration density.

[0129] Even when the pad layer has an uneven shape, at least the top surface of the pad layer can be flat. The substrate interconnect layer disposed on the pad layer can be flat, and the conductive pillars disposed on the substrate interconnect layer can be located at substantially the same level. This enables the structural stability of the semiconductor package to be improved.

[0130] In some embodiments, in a method for manufacturing a semiconductor package, a planarization process may be performed to planarize the top surface of the pad layer. The substrate interconnect layer and the conductive pillar formed by the back-end process may be formed to have a flat top surface, and the top surfaces of the conductive pillars may be formed at substantially the same level. Therefore, when the planarization process is performed on the mold layer, the top surfaces of the conductive pillars may be exposed substantially at the same time. That is, failures caused by the shape of the carrier substrate or the pad layer in the back-end process may be reduced.

[0131] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. In a single embodiment, certain features described in this specification in the context of a separate embodiment may also be implemented in combination. On the contrary, different features described in a single implementation context may also be implemented in multiple implementations, or in appropriate sub-combinations. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0132] While example embodiments of the present disclosure have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first redistribution layer; a bridge chip attached to a top surface of the first redistribution layer; A molding layer, on the first redistribution layer, the molding layer surrounding the bridge chip; a second redistribution layer, disposed on the molding layer; a conductive pillar extending vertically through the molding layer and connecting the first redistribution layer and the second redistribution layer; as well as a first semiconductor chip mounted on the second redistribution layer, Wherein, the first redistribution layer comprises: a pad layer; and an interconnect layer, disposed on the pad layer, Wherein, the pad layer comprises: a first insulating layer; and A plurality of pads, in the first insulating layer, wherein a plurality of top surfaces of the plurality of pads are exposed to the outside of the first insulating layer near a top surface of the first insulating layer, wherein a plurality of bottom surfaces of the plurality of pads are exposed to the outside of the first insulating layer near the bottom surface of the first insulating layer, and The surface flatness of the top surface of the pad layer is greater than the surface flatness of the bottom surface of the pad layer.

2. The semiconductor package according to claim 1, wherein Each of the plurality of pads has a uniform width in a vertical direction.

3. The semiconductor package according to claim 1, wherein: The total thickness variation TTV of the pad layer ranges from 0 μm to 10 μm.

4. The semiconductor package according to claim 1, wherein: The interconnect layer comprises: a second insulating layer covering the first insulating layer and the plurality of pads; and An interconnection pattern is disposed on the second insulating layer, extends through the second insulating layer, and is coupled to the plurality of pads.

5. The semiconductor package according to claim 4, wherein: The first insulating layer and the second insulating layer include materials different from each other.

6. The semiconductor package according to claim 5, wherein: The first insulating layer includes epoxy molding compound EMC or Ajinomoto build-up film ABF, and Wherein, the second insulating layer comprises a photoimageable dielectric material.

7. The semiconductor package according to claim 4, wherein: The conductive pillar is coupled to a top surface of the interconnection pattern.

8. The semiconductor package according to claim 4, wherein: The interconnect pattern comprises: a head on a top surface of the second insulating layer; and a tail portion extending vertically through the second insulating layer and connected to a bottom surface of the head portion, Wherein, the width of the tail portion is smaller than the width of the head portion.

9. The semiconductor package according to claim 4, wherein: The thickness of the plurality of pads is equal to or smaller than the thickness of the interconnection pattern, and the width of the plurality of pads is equal to or smaller than the width of the interconnection pattern.

10. The semiconductor package according to claim 1, wherein The plurality of pads have a thickness ranging from 5 μm to 20 μm, and Wherein, a distance between two adjacent pads among the plurality of pads is 10 μm to 150 μm.

11. The semiconductor package according to claim 1, wherein The top surfaces of the plurality of pads are coplanar with the top surface of the first insulating layer, and The bottom surfaces of the pads are coplanar with the bottom surface of the first insulating layer.

12. The semiconductor package according to claim 1, wherein The inactive surface of the bridge chip is attached to the top surface of the first redistribution layer, and Wherein, the bridge chip includes a plurality of bumps on a top surface of the bridge chip.

13. The semiconductor package according to claim 12, wherein: A top surface of the conductive pillar, a top surface of the mold layer, and top surfaces of the bumps are substantially flat and coplanar with each other.

14. A semiconductor package, comprising: a first redistribution layer; A bridge chip, on the first redistribution layer; A molding layer, on the first redistribution layer, the molding layer surrounding the bridge chip; a second redistribution layer, disposed on the molding layer; a conductive pillar extending vertically through the molding layer and connecting the first redistribution layer and the second redistribution layer; as well as a first semiconductor chip mounted on the second redistribution layer, Wherein, the first redistribution layer comprises: Substrate protection layer; a pad layer including a plurality of outer pads extending vertically through the substrate protection layer, a top surface of the substrate protection layer and a plurality of top surfaces of the plurality of outer pads being substantially flat and coplanar with each other; an insulating pattern covering the substrate protection layer and the plurality of external pads; and a plurality of interconnection patterns disposed on the insulating pattern, Wherein, each of the plurality of interconnection patterns comprises: a head on a top surface of the insulating pattern; and a tail portion extending vertically from a bottom surface of the head portion through the insulating pattern and connected to the plurality of outer pads, Wherein, the total thickness variation TTV of the pad layer ranges from 0 μm to 10 μm.

15. The semiconductor package according to claim 14, wherein: A surface flatness of a top surface of the pad layer is greater than a surface flatness of a bottom surface of the pad layer.

16. The semiconductor package according to claim 14, wherein: Each of the plurality of outer pads has a uniform width in a vertical direction.

17. The semiconductor package according to claim 14, wherein: The plurality of top surfaces of the plurality of outer pads are exposed to the outside of the substrate protection layer near the top surface of the substrate protection layer, and The bottom surfaces of the outer pads are exposed to the outside of the substrate protection layer near the bottom surface of the substrate protection layer.

18. The semiconductor package according to claim 14, wherein: The substrate protection layer and the insulating pattern include materials different from each other.

19. The semiconductor package according to claim 14, wherein: The thickness of the plurality of outer pads is equal to or smaller than the thickness of the plurality of interconnection patterns, and wherein the width of the plurality of outer pads is equal to or smaller than the width of the plurality of interconnection patterns.

20. A semiconductor package, comprising: a first redistribution layer; a second redistribution layer, disposed on the first redistribution layer; a bridge chip mounted on the bottom surface of the second redistribution layer; a molding layer, surrounding the bridge chip, wherein the molding layer is between the first redistribution layer and the second redistribution layer; a conductive pillar extending vertically through the molding layer and connecting the first redistribution layer and the second redistribution layer; a first semiconductor chip mounted on a top surface of the second redistribution layer; as well as a chip stack including a plurality of second semiconductor chips vertically stacked on the top surface of the second redistribution layer and horizontally spaced apart from the first semiconductor chip, Wherein, the first redistribution layer comprises: A pad layer, comprising a plurality of outer pads and a substrate protection layer horizontally surrounding the plurality of outer pads; an insulating pattern covering the plurality of outer pads and the substrate protection layer; and an interconnection pattern disposed on the insulating pattern, extending through the insulating pattern, and coupled to the plurality of external pads, wherein the top surfaces of the plurality of outer pads are exposed to the outside of the substrate protection layer near the top surface of the substrate protection layer, wherein the top surface of the pad layer is substantially flat, wherein the bottom surfaces of the plurality of outer pads are exposed to the outside of the substrate protection layer near the bottom surface of the substrate protection layer, and Wherein, the bottom surface of the pad layer is uneven.

Images