Design method of pipelined analog-to-digital converter and pipelined analog-to-digital converter

Abstract

The invention discloses a pipelined analog-to-digital converter design method and a pipelined analog-to-digital converter thereof, and the method comprises the following steps: S1, multiplying a second-stage quantization result by 1 / A, and then feeding back the result to a secondary bit of a first-stage DAC, so as to regenerate a first-stage residual error; s2, amplifying the residual error by A times and taking the amplified residual error as the input of the second stage, and re-quantizing the second stage; and S3, combining the signal after the first-stage quantization and the signal after the second-stage quantization into a final digital output signal through a combiner. According to the invention, the result of the second-stage quantization is fed back to the lower position of the first-stage DAC, then the first-stage residual error is amplified again, and the second-stage quantization is carried out once again, so that the performance requirements on the first-stage quantizer and the inter-stage amplifier are greatly reduced, and the linearity of the ADC is improved; and meanwhile, the process can be repeated for multiple times, so that the power consumption of the first-stage quantizer and the inter-stage amplifier is reduced, namely the power consumption is reduced while the linearity of the pipelined ADC is ensured.

Description

Technical Field

[0001] The invention relates to the technical field of analog-to-digital converter design, and in particular to a pipeline analog-to-digital converter design method and a pipeline analog-to-digital converter. Background Art

[0002] Analog-to-digital converter (ADC) is an important device that converts analog signals into digital signals and is widely used in modern electronic devices. Among them, in high-speed, high-precision data acquisition systems, pipeline ADC is widely used because it can achieve high sampling rate and high resolution. In the pipeline ADC, the input analog signal is quantized in sequence through multiple quantization stages, each of which includes a digital-to-analog converter (DAC) and a quantizer.

[0003] Existing pipeline ADCs are usually composed of multiple identical quantization stages, each of which quantizes the input signal once. In practical applications, the number of bits of the first-stage quantizer determines the dynamic range and linearity of the entire ADC. However, increasing the number of bits of the first-stage quantizer will significantly increase the accuracy requirements of the first-stage quantizer, which in turn significantly increases power consumption and area. In order to balance linearity and power consumption, existing designs use fewer first-stage quantization bits, but this approach will reduce the linearity of the ADC.

[0004] It can be seen that the existing pipeline ADC design faces a dilemma, that is, if a smaller number of first-stage quantization bits is used, although the power consumption can be reduced, the linearity of the ADC will be reduced; if a larger number of first-stage quantization bits is used, although the linearity of the ADC can be improved, the power consumption will be greatly increased.

[0005] In addition, existing designs usually require that the DAC and quantizer of each quantization stage have high performance, which increases the complexity and cost of the design.

[0006] Therefore, there is a difficult-to-balance contradiction between power consumption and linearity in existing pipeline ADC designs. Summary of the invention

[0007] The technical problem to be solved by the present invention is how to balance the conflicts among linearity, power consumption and cost of a pipeline ADC.

[0008] In a first aspect of the present invention, in order to solve the above technical problem, the present invention provides a design method of a pipelined analog-to-digital converter, the method comprising the following steps: S1, the result of the second stage quantization is multiplied by 1 / A and fed back to the minor bit of the DAC of the first stage to regenerate the residual of the first stage; S2, amplifying the residual by A times as the input of the second stage, and re-quantizing the second stage; S3. Combining the first-stage quantized signal and the second-stage quantized signal through a combiner to obtain a final digital output signal.

[0009] Further, the S2 can reuse the interstage amplifier between the first stage and the second stage and the second stage quantizer of the second stage.

[0010] Furthermore, the processes of S1 and S2 may be repeated multiple times in sequence.

[0011] A second aspect of the present invention provides a pipelined analog-to-digital converter, to which the design method of the pipelined analog-to-digital converter is applied.

[0012] Furthermore, it comprises at least two stages of cascade circuits, namely, a first stage and a second stage, wherein the first stage comprises a first stage quantization circuit or a first stage quantizer.

[0013] Furthermore, the first-level quantization circuit includes a switch array, a capacitor array, a comparator, and a logic control module, wherein: The input signal is connected to the negative input terminal of the comparator through the switch array and the capacitor array in sequence, the positive input terminal of the comparator is grounded, the output terminal of the comparator is connected to the input terminal of the logic control module, the output terminal of the logic control module outputs the first-level quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

[0014] Furthermore, the input signal is outputted as a first-stage quantized signal to the combiner via the first-stage quantizer.

[0015] Furthermore, the second stage includes a switch array, a capacitor array, a second-stage quantizer and a multiplier, and an interstage amplifier is arranged between the first stage and the second stage; wherein the input signal is connected to the input end of the interstage amplifier through the switch array, the capacitor array and the input end of the interstage amplifier in sequence, the output end of the interstage amplifier is connected to the input end of the second-stage quantizer, the output end of the second-stage quantizer is connected to the input end of the multiplier, and the output end of the multiplier is connected to the switch array.

[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The present invention feeds back the result of the second-stage quantization to the lower bits of the first-stage DAC, then re-amplifies the first-stage residual, and re-quantizes the second stage, thereby greatly reducing the performance requirements for the first-stage quantizer and the inter-stage amplifier, thereby improving the linearity of the ADC; at the same time, the above process can be repeated multiple times, reducing the power consumption of the first-stage quantizer and the inter-stage amplifier, that is, reducing the power consumption while ensuring the linearity of the pipeline ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a flowchart of the present invention; Figure 2 This is a schematic diagram of the circuit principle disclosed in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the circuit principle disclosed in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The present invention aims to solve the conflict problem in the traditional pipeline ADC design that a small number of first-stage quantization bits will reduce the ADC linearity while a large number of first-stage quantization bits will greatly increase the power consumption of the first stage.

[0021] It is known from the common knowledge in the field that the first-stage quantizer plays a vital role in the pipeline ADC because it directly determines the dynamic range and linearity of the subsequent quantization stages. If the number of bits of the first-stage quantizer is insufficient, it will not be able to provide enough resolution to support the high-precision requirements of the subsequent quantization stages, resulting in a decrease in the performance of the entire ADC.

[0022] The first aspect of the present invention provides a design method for a pipeline analog-to-digital converter. Figure 1 , the method comprises the following steps: S1. The result of the second-stage quantization is multiplied by 1 / A and fed back to the minor bit of the DAC of the first stage to regenerate the residual of the first stage.

[0023] S2: The residual is amplified by A times and used as the input of the second stage, and the second stage is requantized again.

[0024] S3. Combining the first-stage quantized signal and the second-stage quantized signal through a combiner to obtain a final digital output signal.

[0025] The second stage includes a second-stage quantizer, and an interstage amplifier is provided between the first stage and the second stage. Step S2 can reuse the interstage amplifier and the second-stage quantizer. This repetition can not only make full use of existing resources, but also reduce the error accumulation caused by multiple quantizations, thereby improving the performance of the ADC; at the same time, the processes of S1 and S2 can be repeated multiple times in sequence. This can greatly reduce the performance requirements for the first-stage quantizer and the interstage amplifier, thereby improving the linearity of the ADC.

[0026] Those skilled in the art further explain that the "minor bits", i.e., the lower bits of the first-stage DAC, refer to the bits with smaller weights in the DAC, which have relatively less impact on the final output, but are still important.

[0027] The second aspect of the present invention provides a specific structure of a pipelined analog-to-digital converter.

[0028] Embodiment 1 See also Figure 2 The pipelined analog-to-digital converter includes at least a first-stage and a second-stage cascade circuit, wherein the first stage includes a first-stage quantization circuit; the second stage includes a switch array, a capacitor array, an interstage amplifier, a second-stage quantizer, and a multiplier.

[0029] First, the specific structure of the first level is described.

[0030] The first-level quantization circuit includes a switch array, a capacitor array, a comparator and a logic control module.

[0031] The input signal is connected to the negative input terminal of the comparator through the switch array and the capacitor array in sequence, the positive input terminal of the comparator is grounded, the output terminal of the comparator is connected to the input terminal of the logic control module, the output terminal of the logic control module outputs the first-level quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

[0032] Those skilled in the art further explain that the logic control module controls the opening and closing of corresponding switches in the switch network according to the received second-stage quantization result. These switches are connected to different bits of the first-stage DAC to achieve fine adjustment of the lower bits.

[0033] The first-level DAC is composed of capacitors C1 and C2. In the first-level DAC, the capacitor array is a key component for realizing analog signal conversion. Each capacitor corresponds to a specific weight, and different weight combinations can be achieved through switch control.

[0034] Next, the specific structure of the second stage will be described.

[0035] The input signal is connected to the input of the interstage amplifier through the switch array and the capacitor array in sequence, the output of the interstage amplifier is connected to the input of the second-stage quantizer, the output of the second-stage quantizer is connected to the input of the multiplier, and the output of the multiplier is connected to the switch array.

[0036] Embodiment 2 See also Figure 3 The pipelined analog-to-digital converter includes at least a first-stage and a second-stage cascade circuit, wherein the first stage includes a first-stage quantizer; the second stage includes a switch array, a capacitor array, an interstage amplifier, a second-stage quantizer and a multiplier.

[0037] First, the specific structure of the first level is described.

[0038] The input signal is outputted to the combiner through the first-stage quantizer as a signal after the first-stage quantization; meanwhile, the output end of the first-stage quantizer is connected to the switch array.

[0039] Next, the specific structure of the second stage will be described.

[0040] The input signal is connected to the input of the interstage amplifier through the switch array and the capacitor array in sequence, the output of the interstage amplifier is connected to the input of the second-stage quantizer, the output of the second-stage quantizer is connected to the input of the multiplier, and the output of the multiplier is connected to the switch array.

[0041] In other schemes, there may also be a post-stage inter-stage amplifier and quantizer after the second stage.

[0042] The present invention has the following beneficial effects: 1. Improve linearity: By feeding back the result of the second-stage quantization to the lower bits of the first-stage DAC, and then re-amplifying the residual, the second stage is re-quantized once, and this process can be repeated many times. This method can greatly reduce the performance requirements for the first-stage quantizer and inter-stage amplifier, thereby improving the linearity of the ADC.

[0043] 2. Reduce power consumption: By reusing the interstage amplifier and the second-stage quantizer, the power consumption of the first-stage quantizer and the interstage amplifier is greatly reduced. Therefore, while ensuring linearity, power consumption is reduced, thereby improving energy efficiency.

[0044] 3. Reduce design cost: By reducing the performance requirements for the first-stage quantizer and interstage amplifier, the design and manufacturing process are simplified, thereby reducing the design cost. This has important economic significance for large-scale production.

[0045] 4. Flexibility: The structure of the pipeline ADC of the present invention can be flexibly adjusted, and different quantization levels and bits can be selected according to actual needs to meet the needs of different application scenarios.

[0046] 5. Improve signal-to-noise ratio: Since the pipeline ADC of the present invention performs multiple quantizations, it can effectively reduce quantization noise, thereby improving the signal-to-noise ratio, which is of great significance for high-precision data acquisition systems.

[0047] The present invention can be widely used in application fields such as analog-to-digital converter design, integrated circuit design, and signal processing technology.

[0048] First, in the field of analog-to-digital converter design, by reusing the interstage amplifier and the second-stage quantizer, the performance requirements of the first-stage quantizer and the interstage amplifier are greatly reduced, thereby reducing the design cost. This new structure is of great significance for improving the performance of analog-to-digital converters and reducing costs.

[0049] Secondly, in the field of integrated circuit design, the present invention provides a new integrated circuit design idea, which achieves a balance between power consumption and linearity by optimizing the structure of the pipeline ADC, which is of great value for improving the performance of integrated circuits and reducing power consumption. With the development of integrated circuit technology, the demand for high-performance, low-power integrated circuits is increasing, and this technical solution is expected to be widely used in the field of integrated circuit design.

[0050] Finally, in the field of signal processing technology, the new pipeline ADC structure proposed in this technical solution can improve the accuracy and quality of signal processing, which is of great significance to the development of signal processing technology. With the widespread application of signal processing technology in various fields, such as communication, audio processing, image processing, etc., this technical solution is expected to be widely used in the field of signal processing technology.

[0051] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A design method for a pipelined analog-to-digital converter, characterized in that: The method comprises the following steps: S1, the result of the second stage quantization is multiplied by 1 / A and then fed back to the minor bit of the DAC of the first stage to regenerate the residual of the first stage; S2, amplifying the residual by A times as the input of the second stage, and re-quantizing the second stage; S3. Combining the first-stage quantized signal and the second-stage quantized signal through a combiner to obtain a final digital output signal.

2. The design method of the pipelined analog-to-digital converter according to claim 1, characterized in that: The S2 can reuse the interstage amplifier between the first stage and the second stage and the second stage quantizer of the second stage.

3. The design method of the pipelined analog-to-digital converter according to claim 1, characterized in that: The processes of S1 and S2 can be repeated multiple times in sequence.

4. A pipelined analog-to-digital converter, characterized in that: A design method for a pipelined analog-to-digital converter according to any one of claims 1 to 3 is applied.

5. The pipelined analog-to-digital converter according to claim 4, characterized in that: It comprises at least two stages of cascade circuits, namely, a first stage and a second stage, wherein the first stage comprises a first stage quantization circuit or a first stage quantizer.

6. The pipelined analog-to-digital converter according to claim 5, characterized in that: The first-level quantization circuit includes a switch array, a capacitor array, a comparator and a logic control module, wherein: The input signal is connected to the negative input terminal of the comparator through the switch array and the capacitor array in sequence, the positive input terminal of the comparator is grounded, the output terminal of the comparator is connected to the input terminal of the logic control module, the output terminal of the logic control module outputs the first-level quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

7. The pipelined analog-to-digital converter according to claim 5, characterized in that: The input signal is outputted through the first-stage quantizer as a first-stage quantized signal to the combiner.

8. The pipelined analog-to-digital converter according to claim 5, characterized in that: The second stage includes a switch array, a capacitor array, a second stage quantizer and a multiplier, and an interstage amplifier is arranged between the first stage and the second stage; wherein the input signal is connected to the input end of the interstage amplifier through the switch array, the capacitor array and the input end of the interstage amplifier in sequence, the output end of the interstage amplifier is connected to the input end of the second stage quantizer, the output end of the second stage quantizer is connected to the input end of the multiplier, and the output end of the multiplier is connected to the switch array.

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