Neural network prediction of quality of wireless signals

Abstract

The invention discloses a neural network for predicting the quality of a wireless signal. Apparatus, systems, processors, circuits, and techniques predict a quality of one or more wireless signals based at least in part on one or more reference signals using one or more neural networks. In at least one embodiment, apparatuses, systems, processors, circuits, and techniques use one or more neural networks to determine that a radio link is unstable or stable over a period of time or several frames (e.g., 10 consecutive frames).

Description

Technical Field

[0001] At least one embodiment is directed to a processor, computing system, device, non-transitory computer medium, and / or method for monitoring and / or adjusting (e.g., repairing) radio link communications using a neural network. For example, a processor includes circuitry that uses one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals. Background Art

[0002] When a user equipment (UE) is connected to a radio access network (RAN), it can monitor the connection between the UE and the RAN (e.g., the connection to the radio unit and / or base station). This process is generally referred to as radio link monitoring (RLM). RLM may face some challenges. For example, if RLM occurs frequently (e.g., every millisecond), it may use a lot of computing resources, thereby degrading the performance of devices using the RAN. As another example, RLM may require the use of power to measure the radio link quality, which may require the RAN or the user equipment to consume a lot of power, resulting in reduced power efficiency of the RAN or the user equipment. Therefore, there is a need for improved radio link monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A computing environment of a user equipment and a base station according to at least one embodiment is shown;

[0004] Figure 2 shows a schematic overview of how a prediction of a radio link quality is generated according to at least one embodiment;

[0005] Figure 3 is a process flow diagram for generating predictions while monitoring radio link quality according to at least one embodiment;

[0006] Figure 4 is a process flow diagram for generating a radio link prediction and performing a response action using the prediction according to at least one embodiment;

[0007] Figure 5 is a process flow diagram for generating predictions for radio links and using these predictions to perform response actions in accordance with at least one embodiment;

[0008] Figure 6 is a schematic block diagram illustrating the use of a neural network to generate a prediction regarding radio link quality according to at least one embodiment;

[0009] Figure 7is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment;

[0010] Fig. 8A illustrates logic according to at least one embodiment;

[0011] Figure 8B illustrates logic according to at least one embodiment;

[0012] Fig. 9 illustrates the training and deployment of a neural network according to at least one embodiment;

[0013] Fig.10 An example data center system is shown in accordance with at least one embodiment;

[0014] Fig.11A An example of an autonomous vehicle is shown in accordance with at least one embodiment;

[0015] Fig. 11B According to at least one embodiment, Fig.11A Examples of camera positions and fields of view for autonomous vehicles;

[0016] Fig. 11C is an illustration according to at least one embodiment Fig.11A A block diagram of an example system architecture for an autonomous vehicle;

[0017] Fig.11D is a diagram illustrating a method for one or more cloud-based servers and Fig.11A A diagram of a system for communicating between autonomous vehicles;

[0018] Fig.12 is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Fig.13 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Fig.14 A computer system according to at least one embodiment is shown;

[0021] Fig.15 A computer system according to at least one embodiment is shown;

[0022] Fig.16A A computer system according to at least one embodiment is shown;

[0023] Fig. 16B A computer system according to at least one embodiment is shown;

[0024] Fig. 16C A computer system according to at least one embodiment is shown;

[0025] Fig.16D A computer system according to at least one embodiment is shown;

[0026] Fig.16E and Fig.16F illustrates a shared programming model according to at least one embodiment;

[0027] Fig.17 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0028] Fig.18A and Fig.18B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Fig.19A and Fig.19B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0030] Fig. 20 A computer system according to at least one embodiment is shown;

[0031] Fig.21A A parallel processor according to at least one embodiment is shown;

[0032] Fig. 21B shows a partition unit according to at least one embodiment;

[0033] Fig. 21C illustrates a processing cluster according to at least one embodiment;

[0034] Fig.21D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0035] Fig. 22 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0036] Fig.23 A graphics processor according to at least one embodiment is shown;

[0037] Fig.24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0038] Fig.25 A deep learning application processor according to at least one embodiment is shown;

[0039] Fig.26is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0040] Fig. 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0041] Fig.28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Fig.29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Fig.30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0044] Fig.31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0045] Fig.32A and Fig.32B Thread execution logic is shown that includes an array of processing elements of a graphics processor core in accordance with at least one embodiment.

[0046] Fig.33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0047] Fig.34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0048] Fig.35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0049] Fig.36 A streaming multiprocessor is shown according to at least one embodiment;

[0050] Fig.37 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0051] Fig.38 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0052] Fig.39 includes an example illustration of a high-level computational pipeline for processing imaging data according to at least one embodiment;

[0053] Fig.40AAn example data flow diagram including a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0054] Fig.40B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0055] Fig.41A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0056] Fig.41B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment. DETAILED DESCRIPTION

[0057] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the concepts of the present invention may be implemented without one or more of these specific details.

[0058] In at least one embodiment, the technique for determining whether the radio link should be repaired requires the UE to continuously monitor the radio link quality. For example, the user equipment monitors the radio link quality of a given cell, estimates the radio link quality, and compares the estimate with a threshold specified by the manufacturer. In at least one embodiment, if the estimated radio link quality does not meet the threshold, the UE determines that the radio link has failed.

[0059] In at least one embodiment, the UE performs RLM to detect any failure in the radio link. In at least one embodiment, the RLM procedure may include continuous monitoring of the physical layer, the media access control (MAC) layer, and the radio resource control (RRC) layer. In at least one embodiment, the radio link or connection between the UE and the base station may fail due to a variety of reasons. For example, the lower layers of the radio access network software stack may fail due to frequency and / or time offset. As another example, interference between the UE and the base station may cause wireless signal degradation, poor carrier connection, and synchronization failure between the UE and the base station. As another example, the failure may also occur during a handover procedure, a cell reselection procedure, a cyclic redundancy check (CRC) failure, and other initialization procedures.

[0060] In at least one embodiment, in a radio link failure (RLF) procedure, receiving consecutive out-of-sync indications from lower layers (e.g., a signal or packet cannot be decoded correctly or the timing of the message is incorrect) informs the UE that there is a problem with the downlink radio link. In at least one embodiment, the duration of the timer allows the UE or base station to take certain measures to adjust the radio link or wait for the radio link quality to exceed an acceptable threshold. In at least one embodiment, the timer can be stopped when a consecutive in-sync indication is received from a lower layer (e.g., a signal or packet is decoded correctly or decoded at the right time) or a handover command (e.g., RRCReconfiguration with reconfigurationWithSync) is received. In at least one embodiment, the procedure may be challenging. For example, there may be no consecutive in-sync indications from lower layers when the timer is running. Another example problem is that the risk of handover failure is high (e.g., the UE may not successfully receive the handover command) due to unreliable downlink radio link quality when the timer is running. In at least one embodiment, when the timer expires, the UE may declare a radio link failure, forcing the UE to enter RRC_IDLE or initiate a connection reestablishment procedure. In at least one embodiment, while in the RRC-IDLE state, the UE is not registered to a particular cell and is not connected to a base station to facilitate data transmission. In at least one embodiment, the UE periodically checks for paging messages from the network. In at least one embodiment, the UE reestablishes connection with the network only after successfully receiving a paging message from the network. In at least one embodiment, a UE in the RRC_IDLE state or with a connection reestablishment procedure initiated may experience severe communication interruption.

[0061] In at least one embodiment, a technical problem is that the techniques used to monitor radio link quality in fifth generation (5G), new radio (NR) networks are reactive, which causes the 5G network to react too late (e.g., seconds after an error occurs) or to initiate time-consuming repair procedures only after it is determined that the link quality is below a threshold and performance has been affected for a long time. In at least one embodiment, radio link quality refers to the number of packets successfully decoded by the device (e.g., 99% of received packets being successfully decoded would be a high-quality radio link). In at least one embodiment, because poor radio link quality can only be remedied after it is detected, users may experience poor connectivity for a significant amount of time.

[0062] In at least one embodiment, in order to solve at least the above-mentioned technical problems (e.g., reactive or slow response to radio link problems), the UE or base station uses a neural network to reason about the predicted future state of the radio link connection between the UE and the base station (e.g., gNB in ​​a 5G-NR network). In at least one embodiment, the neural network can then provide reasoning to the UE or base station, which notifies the UE or base station of the future state of the radio link. Using the provided reasoning, the UE can perform operations to adjust (e.g., repair, change) the radio link, maintain the radio link, and / or avoid (e.g., unnecessary) radio link repairs or other changes.

[0063] In at least one embodiment, the neural network generates a prediction of the radio link quality based on a reference signal. In at least one embodiment, the reference signal is a signal that does not contain user data (e.g., data transmitted by a software program, such as video content), but is used for the purpose of configuring and maintaining a wireless connection between a base station and a UE. In at least one embodiment, there are different types of reference signals used for various purposes, such as synchronization and for determining information about a channel being used (e.g., the effects of interference). In at least one embodiment, the reference signal corresponds to a signal-to-interference ratio, a signal-to-noise ratio, a reference signal received power (RSRP), a reference signal received quality (RSRQ), or a combination thereof.

[0064] In at least one embodiment, at the UE, a neural network receives a reference signal, determines properties of the reference signal, such as signal-to-noise ratio, signal-to-interference ratio, and frequency, and then uses these properties to predict radio link quality. In at least one embodiment, software at the UE can then use the predicted link quality to remediate any connectivity issues before they occur.

[0065] For example, a neural network may receive a reference signal and then predict that within the next 100 seconds, the radio link quality will meet or exceed a threshold (e.g., packets will be decoded with a 99% success rate). In at least one embodiment, the UE may use the output of the neural network (e.g., predicted link quality and / or predicted duration of link quality) to proactively adjust the radio link (e.g., change frequency, adjust power) to improve the radio link quality. The UE does not need to wait until low radio link quality is detected, instead, if the predicted quality will be below the threshold, the UE can immediately start adjusting the radio link, which can be a long time before performance is affected. In at least one embodiment, the neural network proactively generates a prediction of the radio link quality based on receiving a reference signal. In at least one embodiment, using the output of the neural network, the UE also does not need to wait until low radio link quality is detected to start adjusting the radio link quality, instead, if the predicted quality will be below the threshold (e.g., a certain percentage of signals cannot be successfully decoded or the signal-to-noise ratio is too low, or the parameters of the 5G reference signal do not meet the threshold), the UE can immediately start adjusting the radio link. In at least one embodiment, the neural network can be used for 3G, 4G, 5G, 6G and other wireless communication protocols. In at least one embodiment, a processor including one or more circuits will use the predicted quality of one or more wireless signals to immediately start one or more processes of adjusting one or more radio links between the user equipment and the radio unit. In at least one embodiment, immediately includes immediately, simultaneously, or without any intermediate time or space. For example, the UE can start the radio link requirement procedure without waiting for another measurement window. As another example, the base station can receive information about the reference signal from the UE and immediately start adjusting the radio link.

[0066] In at least one embodiment, a UE is any device used by an end user to communicate. Examples of user equipment include cellular phones, laptops, servers, computers, and any other hardware devices capable of communicating. In at least one embodiment, a UE includes one or more processors, one or more circuits, memory, power supplies, and all the hardware required for the UE to operate within a wireless communication network. For example, a user equipment includes any device capable of communicating via a 3GPP-LTE, 4G, 5G-New Radio wireless network, a sixth generation (6G) wireless network, or other wireless communication standards from the Third Generation Partnership Project.

[0067] Figure 1A computing environment 100 is shown that includes a user equipment (UE) 101 and a base station 102. In at least one embodiment, the UE 101 and the base station 102 each include a neural network 102, a radio link monitor 103, a reference signal manager 104, and a processor 105. In at least one embodiment, the UE 101 and the base station 102 communicate using a radio link 106, for example, they can transmit, receive, or otherwise share information, such as data packets, reference signals, or other communications (e.g., as part of a wireless communication standard determined by IEEE). In at least one embodiment, the radio link includes radio frequency signals, channels, or other information for connecting or communicating with a 5G network. In at least one embodiment, apparatuses, systems, methods, and techniques are disclosed herein, wherein a reference signal is transmitted by the base station 102 to the UE 101 in a downlink manner, and training, learning, or reasoning is performed at the UE 101. In at least one embodiment, apparatuses, systems, methods, and techniques are disclosed herein, wherein the UE 101 receives a reference signal and transmits it to the base station 102 for training, learning, reasoning, or otherwise using the reference signal.

[0068] In at least one embodiment, the processor 105 executes, uses, or otherwise implements the neural network 102, the radio link monitor 103, and the reference signal manager 104. In at least one embodiment, the processor 105 may be any processor, such as Fig.21A 3600. In at least one embodiment, the processor 105 uses the neural network 102 to predict radio link quality, including, for example, out-of-sync events and in-sync events. In at least one embodiment, the neural network 102 can be remotely located and configured to be communicatively coupled to the UE 101. In at least one embodiment, the UE 101 collects, receives, or otherwise uses a reference signal and provides it to the neural network 102 (e.g., in downlink operations).

[0069] In at least one embodiment, using the reference signal input, the processor using the neural network 102 can reason about whether the radio link between the UE and the base station 102 will remain synchronized, no longer synchronized, or no longer synchronized but can be restored at a future time. The neural network 102 can then provide its reasoning to the UE, and the UE can take corrective measures if necessary. In at least one embodiment, by reasoning about the predicted state of the radio link at a future time, the UE 101 can avoid the costs associated with the current RLF procedure, provide a stable radio link, reduce bandwidth usage, reduce computing resource usage, and / or save power.

[0070] In at least one embodiment, the base station 102 is a transceiver that is a communication point for one or more UEs (e.g., UE 101). In at least one embodiment, the base station 102 can send and receive wireless signals. In at least one embodiment, the base station 102 includes one or more radio frequency (RF) antennas to send and receive RF signals to other devices (e.g., UE 101). In at least one embodiment, the base station 102 can send and receive 5G-NR signals, including reference signals.

[0071] In at least one embodiment, the neural network 102 includes a convolutional neural network (CNN), a transform, an encoder, a decoder, a recurrent neural network (RNN), a long short-term memory (LSTM), a radial basis network (RBN), an autoencoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), and / or any combination thereof. In at least one embodiment, the one or more reference signals are one or more inputs to the neural network 102, and the predicted quality of the one or more wireless signals is one or more outputs of the neural network 102. In at least one embodiment, the processor 105 may execute, use, train, or otherwise cause the neural network 102 to predict the quality of the one or more wireless signals based at least in part on the one or more reference signals.

[0072] In at least one embodiment, the processor 105 uses, implements or executes a radio link monitor 103, which is software, module, circuit, logic or a combination thereof. In at least one embodiment, the processor 105 uses the radio link monitor 103 to perform radio link monitoring (RLM) on the active DL BWP of the primary serving cell (Primary serving cell, PCell) of the master cell group (Master Cell Group, MCG). If the UE is configured with a secondary cell group (Secondary Cell Group, SCG), the UE also monitors the downlink radio link quality on the active DL BWP of the primary SCG cell (PSCell). In at least one embodiment, the radio link monitor 103 includes software for executing the physical layer, monitoring the DL radio link quality and / or sending the measurement results to the upper layer. In at least one embodiment, the radio link monitor includes software for executing or using a MAC layer including beam failure detection and recovery. In at least one embodiment, the radio link monitor includes an RRC layer and is configured to execute the PHY and MAC layers, radio link failure detection and RRC establishment.

[0073] In at least one embodiment, the reference signal manager 104 includes software, logic, circuitry, or a combination thereof for generating, receiving, and analyzing reference signals. In at least one embodiment, a reference signal is a signal that does not contain user data (e.g., data transmitted by a software program, such as video content), but is used for the purpose of configuring and maintaining a wireless connection between a base station and a UE. In at least one embodiment, there are different types of reference signals used for various purposes, such as synchronization and for determining information about the channel being used (e.g., the impact of interference). In at least one embodiment, in 5G-NR, PDSCH is a physical downlink channel that carries user data, and DM-RS and PT-RS are reference signals associated with PDSCH, wherein the reference signal manager 104 receives, analyzes, or otherwise uses these signals generated within a PDSCH allocation, as defined in TS 38.211 Section 7.4. In at least one embodiment, the processor 105 reference signal manager 104 receives, analyzes, or otherwise uses a reference signal that includes a predefined signal that occupies a specific resource element within a downlink time-frequency grid (e.g., within a 5G NR network).

[0074] In at least one embodiment, the processor 105 includes one or more circuits to predict the quality of one or more wireless signals based at least in part on one or more reference signals using one or more neural networks. In at least one embodiment, the processor 105 is or includes Fig.21A to the SM 3600 processor.

[0075] Figure 2 A schematic diagram showing how to generate a prediction of radio link quality according to at least one embodiment. Figure 2An example 200 of radio link monitoring and predicted radio link state is shown. In at least one embodiment, the radio link monitor 103 of the UE 101 monitors (e.g., receives, analyzes) one or more reference signals 201a-201n (e.g., radio link monitoring reference signal (RLM-RS) resources). In at least one embodiment, the RLM-RS resource can be a synchronization signal block (SSB), a channel state information reference signal (CSI-RS), or a mixture of SSB and CSI-RS. In at least one embodiment, the reference signals 201a-201n are collected at corresponding past times t[-P]–t[0]. In at least one embodiment, the reference signals are collected during a measurement window 205. For example, at a past time t[-P], the radio link monitor 103 collects the corresponding reference signal 201. Although only three time instants are depicted, the radio link monitor 103 can collect any number of reference signals. In at least one embodiment, the radio link monitor 103 transmits each reference signal to the neural network 102. In at least one embodiment, neural network 102 infers whether UE 101's radio link will experience consecutive out-of-sync events 202-204 (eg, N310 consecutive out-of-sync) within prediction window 206 based on reference signals (eg, 201a-201n).

[0076] In at least one embodiment, if the neural network 102 predicts that there will be consecutive out-of-sync events 202-204 in the future within the prediction window 206, the UE 101 assumes that a hypothetical timer 207 (e.g., timer T310) will be started after the event of the consecutive out-of-sync events 202-204. In at least one embodiment, the predicted timer 207 starts at time 208 and stops at time 209. In at least one embodiment, the predicted timer 207 expires at time 210.

[0077] In at least one embodiment, neural network 102 predicts whether consecutive synchronization events 211 - 213 (eg, N311 synchronizations) will occur at future times within prediction window 214 that fall within the duration of the assumed runtime of timer 207 .

[0078] In at least one embodiment, if the neural network 102 predicts that N310 consecutive out-of-sync events 202-204 will occur at a future time, and further predicts that N311 consecutive in-sync events 206 will occur thereafter for the duration of the timer T310, the UE 101 assumes that the radio link will become unreliable but will recover, and therefore does not take any further action.

[0079] In at least one embodiment, the neural network 102 predicts that continuous desynchronization 204-206 will occur at a future moment and further predicts that continuous synchronization 211-213 will not occur within the duration of the timer 207 thereafter, and the UE 101 may take one or more of the following measures: the UE 101 notifies its serving base station 102 of the UE's prediction that the UE's radio link will fail; the UE 101 notifies its serving base station 102 of the UE's prediction that the UE's radio link will fail and the associated probability, which indicates the likelihood of the radio link failure; the UE 101 notifies its serving base station 102 of the UE's prediction that the UE's radio link will fail and / or the confidence of the associated probability, which indicates the likelihood of the radio link failure; the UE 101 sends a measurement report to its serving base station 102, the measurement report including measurement results of reference signals of the serving cell and neighboring cells; the UE 101 requests its serving base station 102 to switch the UE 101's connection from the current serving cell to a different serving cell that will provide better radio link quality; the UE UE 101 autonomously initiates a handover procedure by performing an access procedure to a different cell that will provide better radio link quality; UE 101 initiates an RRC connection reestablishment procedure; and UE 101 performs actions upon entering RRC_IDLE.

[0080] In at least one embodiment, when the neural network 102 predicts that the radio link quality is worse than a threshold value (e.g., Qout) for all resources in the resource set used for radio link prediction at each corresponding consecutive future time instant, the neural network 102 predicts that there will be several consecutive out-of-sync events for the downlink radio link at several consecutive future time instants. In at least one embodiment, the threshold value is defined as a level at which the downlink radio link cannot be reliably received and should correspond to an out-of-sync block error rate (BLERout). In at least one embodiment, the threshold value is derived based on an assumed physical downlink control channel (PDCCH) transmission parameter of the out-of-sync evaluation associated with the corresponding type of RLM-RS, for example, a value of BLERout is 10%.

[0081] Figure 3 is a flow chart of a process 300 for generating predictions while monitoring radio link quality according to at least one embodiment. In at least one embodiment, Figure 1 to Figure 2 The components disclosed in are used to perform part or all of process 300, for example, Figure 1Processor 105 in performs process 300 using neural network 102. In at least one embodiment, by performing process 300, a processor including one or more circuits uses one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals. In at least one embodiment, Figure 1 to Figure 2 The systems and components disclosed in the can perform part or all of process 300, or be integrated into process 300. In at least one embodiment, process 300 can be combined with Figure 4 The process 400 disclosed in the embodiment is performed concurrently or sequentially. In at least one embodiment, FIG. 8 to FIG. Fig.41B The systems and processors disclosed in perform part or all of process 300.

[0082] In at least one embodiment, part or all of process 300 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer executable instructions and implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more applications) executed together on one or more processors, by hardware, software, or a combination thereof. In at least one embodiment, process 300 is executed by Figure 1 to Figure 2 In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program, which includes a plurality of computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 300 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 300 is at least partially performed on a computer system (e.g., a computer system described elsewhere in the present disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 300. In at least one embodiment, process 500 can start with receiving operation 305 and continue to generate prediction operation 310.

[0083] At receiving operation 305, a processor in the UE receives a reference signal. For example, a mobile device using a 5G network can receive a clock synchronization signal. In at least one embodiment, a reference signal is a signal that does not contain user data (e.g., data transmitted by a software program, such as video content), but is used for the purpose of configuring and maintaining a wireless connection between a base station and a UE. In at least one embodiment, there are different types of reference signals used for various purposes, such as synchronization and for determining information about a channel being used (e.g., the effects of interference). In at least one embodiment, the UE can receive several reference signals. In at least one embodiment, the UE can receive a reference signal in a downlink path and then transmit the result of receiving the reference signal to the base station. In at least one embodiment, the processor receives the reference signal during a measurement window, such as Figure 2 shown.

[0084] At generating operation 310, the processor provides the received reference signal or received reference signal as input to a neural network, which generates a prediction based on the reference signal. In at least one embodiment, the processor executing the neural network generates a prediction that the radio link quality is good, high, or above a threshold (e.g., BLER is less than 2% or 98% of packets can be decoded). In at least one embodiment, the processor executing the neural network generates a prediction that the radio link will have a number of out-of-sync messages (e.g., 10 to 100) or will be out of sync for a number of frames (e.g., 10 consecutive frames). In at least one embodiment, the processor executing the neural network generates a prediction that the out-of-sync message will only last for a few frames or a short period of time (e.g., 25 milliseconds).

[0085] At the determination response operation 315, a processor (e.g., a processor of UE 101) generates a response based on the prediction operation 315 (e.g., the output of the neural network). In at least one embodiment, the prediction may be provided to a controller or UE, or to a base station. For example, the UE notifies its serving base station 102 of the UE's prediction that the UE's radio link will fail. As another example, the UE 101 notifies its serving base station 102 of the UE's prediction that the UE's radio link will fail and the associated probability, which indicates the likelihood of the radio link failing, and takes corrective measures, such as reestablishing the radio link or adjusting parameters. As another example, the UE 101 notifies its serving base station 102 of the UE's confidence in the prediction that the UE's radio link will fail and / or the associated probability, which indicates the likelihood of the radio link failing. As another example, the UE 101 sends a measurement report to its serving base station 102, the measurement report including measurement results of reference signals of the serving cell and the neighboring cells. As another example, UE 101 requests its serving base station 102 to hand over the connection of UE 101 from the current serving cell to a different serving cell that will provide better radio link quality. As another example, UE 101 autonomously initiates the handover procedure by performing an access procedure to access a different cell that will provide better radio link quality. As another example, UE 101 initiates an RRC connection reestablishment procedure; and UE 101 performs actions upon entering RRC_IDLE.

[0086] At decision operation 320, the processor determines whether process 320 should be stopped based on whether it is necessary to continue monitoring the radio link. Based on the information from operations 310 and 315, the processor can receive notification about the length of time that the radio link is predicted to have good quality or low quality (e.g., equal to or above a threshold for 5G stability). In at least one embodiment, the processor can stop measuring until the stability period expires, or it can use process 300 again to obtain another prediction.

[0087] In at least one embodiment, after decision operation 320, the processor including one or more circuits stops or ends process 300. In at least one embodiment, the processor including one or more circuits may continue to perform process 300. For example, the processor including one or more circuits or one or more processors may continue to monitor the radio link to determine predicted radio link quality and perform adjustments if necessary.

[0088] Figure 4 is a flow chart of a process 400 for generating a prediction of a radio link and performing a response action using the prediction according to at least one embodiment. In at least one embodiment, Figures 1 to 3The components disclosed in are used to perform part or all of process 400, for example, processor 105 performs process 400. In at least one embodiment, by performing process 400, a processor including one or more circuits uses one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals. In at least one embodiment, Figure 1 to Figure 2 The systems and components disclosed in the can perform part or all of process 300, or be integrated into process 300. In at least one embodiment, process 400 can be combined with Figure 3 The process 300 disclosed in the embodiment of the present invention is performed concurrently or sequentially. In at least one embodiment, FIG. 8 to FIG. Fig.41B The systems and processors disclosed in perform part or all of process 400.

[0089] In at least one embodiment, part or all of process 400 (or any other process described herein, or a variation and / or combination thereof) is executed under the control of one or more computer systems configured with computer executable instructions and implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more applications) executed together on one or more processors, by hardware, software, or a combination thereof. In at least one embodiment, process 400 is executed by Figure 1 to Figure 2 In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program, which includes a plurality of computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 400 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 400 is at least partially executed on a computer system (e.g., a computer system described elsewhere in the present disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes process 400. In at least one embodiment, process 400 can start with receiving operation 405 and continue to generate prediction operation 410.

[0090] At receiving operation 405, a processor in the UE receives a reference signal. For example, a mobile device using a 5G network can receive a clock synchronization signal. In at least one embodiment, a reference signal is a signal that does not contain user data (e.g., data transmitted by a software program, such as video content), but is used for the purpose of configuring and maintaining a wireless connection between a base station and a UE. In at least one embodiment, there are different types of reference signals used for various purposes, such as synchronization and for determining information about a channel being used (e.g., the effects of interference). In at least one embodiment, the UE can receive several reference signals. In at least one embodiment, the UE can receive a reference signal in a downlink path and then transmit the result of receiving the reference signal to the base station. In at least one embodiment, the processor receives the reference signal during a measurement window, such as Figure 2 shown.

[0091] At generating operation 410, the processor provides the received reference signal or received reference signal as input to a neural network, which generates a prediction based on the reference signal. In at least one embodiment, the processor executing the neural network generates a prediction that the radio link quality is good, high, or above a threshold (e.g., BLER is less than 2% or 98% of packets can be decoded). In at least one embodiment, the processor executing the neural network generates a prediction that the radio link will have a number of out-of-sync messages (e.g., 10 to 100) or will be out of sync for a number of frames (e.g., 10 consecutive frames). In at least one embodiment, the processor executing the neural network generates a prediction that the out-of-sync message will only last for a few frames or a short period of time (e.g., 25 milliseconds).

[0092] At determination operation 415, the processor determines that the radio link is below a threshold (eg, more than 10 out-of-sync messages are expected to be received within the next 20 frames or milliseconds, or the BLER is predicted to be above 2% for a longer period of time).

[0093] At decision operation 420, the processor determines whether the prediction below the threshold value lasts only for a short period of time and then stability will return to the radio link, or whether the prediction below the threshold value lasts for a longer period of time and corrective action needs to be taken. If the processor determines that corrective action is not needed because the instability is only temporary or the timer will not expire before stability is restored, the process 400 can end. If the prediction instability will last for a longer period of time, the processor can immediately take action to perform a response action 425. For example, the UE 101 sends a measurement report to its serving base station 102, which includes measurement results of reference signals of the serving cell and neighboring cells. For example, the UE 101 requests its serving base station 102 to switch the connection of the UE 101 from the current serving cell to a different serving cell that will provide better radio link quality. As another example, the UE 101 autonomously initiates a handover procedure by performing an access procedure to access a different cell that will provide better radio link quality. For example, the UE 101 initiates an RRC connection reestablishment procedure.

[0094] In at least one embodiment, after decision operation 420, the processor including one or more circuits stops or ends process 400. In at least one embodiment, the processor including one or more circuits may continue to perform process 400. For example, the processor including one or more circuits or one or more processors may continue to monitor the radio link to determine predicted radio link quality and perform adjustments if necessary.

[0095] Figure 5 is a process flow diagram for generating radio link predictions and performing response actions using these predictions according to at least one embodiment. Figure 1 to Figure 2 The components disclosed in are used to perform part or all of process 300, for example, processor 105 performs process 500. In at least one embodiment, by performing process 300, a processor including one or more circuits uses one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals. In at least one embodiment, Figure 1 to Figure 2 The systems and components disclosed in the can perform part or all of process 500, or be integrated into process 500. In at least one embodiment, process 300 can be combined with Figure 4 The process 400 disclosed in the embodiment is performed concurrently or sequentially. In at least one embodiment, FIG. 8 to FIG. Fig.41BThe system and processor disclosed in the embodiment perform part or all of process 500. In at least one embodiment, process 500 is a specific example of processes 300 and 400. In at least one embodiment, process 500 includes a measurement operation 505 (e.g., measuring a reference signal for radio link monitoring), a prediction operation 510 (e.g., predicting the quality of the radio link at a future time in a first prediction window), a decision operation 515 (e.g., determining whether the event includes consecutive out-of-sync packets or whether a signal is predicted to be received), and if not, the radio link is considered stable 520. If there are predicted out-of-sync messages for consecutive frames, the neural network can predict what will happen to the radio link in the future and a waiting period or timer 525 (e.g., a future time in a second prediction window after the first prediction window). If the neural network predicts an event with N311 continuous synchronization, the processor can receive the prediction and consider that the radio link quality will become unreliable but will recover 535, for example, the controller of the UE or base station does not need to take any action. If the processor determines that the radio link quality will become unstable and will not recover 540, the processor can send a signal to the controller or base station to perform preventive measures to avoid the predicted radio link failure. For example, the processor may immediately request the UE to initiate a reestablishment procedure or a handover procedure. As another example, the UE may change the base station or adjust its radio link parameters to improve the radio link quality.

[0096] Figure 6 is a schematic block diagram illustrating the use of a neural network to generate a prediction regarding radio link quality in accordance with at least one embodiment. Figure 6A reference signal specific model 600 is shown including a method for predicting consecutive out-of-sync events for multiple units (e.g., milliseconds, frames) in the future. In at least one embodiment, one or more UEs 101 and base stations may be used to train reference signal resource specific neural networks 602a-602n to obtain out-of-sync prediction outputs 603a-603n at future moments, and out-of-sync prediction outputs 603a-603n may be used for reasoning, for example, to predict whether the radio link quality will be above a threshold. In at least one embodiment, for each reference signal measurement window 601a-601n, there is a specific neural network 602a-602n: the input of the neural network is based on the measurement values ​​of the reference signals 201a-201n at time points {t[-P], ..., t[0]}. In at least one embodiment, the neural network 602a-602n generates a prediction, e.g., output 603a-603n, that there will be a number Q of consecutive "out of sync" events by applying the reference signal specific neural network 602a-602n to look ahead by 1 step, 2 steps, etc., to obtain a set look ahead prediction. In at least one embodiment, if the neural network generates a predicted output 603a-603n (including the link quality at all times t[1] to t[Q]) that is worse than Qout, the controller 604 (which is software executed by a processor such as processor 105) generates an output bit equal to 1. In at least one embodiment, otherwise, an output bit equal to 0 is generated. In at least one embodiment, the controller 604 receives the output predictions from the neural network 602a-602n and uses these predictions to perform radio link failure operations (e.g., change to another base station, reconnect, or reestablish a connection with a base station). In at least one embodiment, a processor (e.g., processor 102) provides outputs 603a-603n to a controller 604 (e.g., a controller in a UE or a controller in a base station), where the controller 604 is software that controls parameters, circuits, and other components of a radio link. In at least one embodiment, the controller 604 may use the outputs 603a-603n to generate a control signal or adjust parameters of the UE or base station to adjust the radio link quality. In at least one embodiment, a processor including one or more circuits will use the predicted quality of one or more wireless signals as an input to the control circuit to adjust one or more radio links between the user equipment and the base node.

[0097] In at least one embodiment, UE 101 and / or base station 102 are used to train multiple reference signal inputs of neural network 602a-602n to predict consecutive asynchronous events multiple steps in advance and use them for inference. For example, for measurement window 601a-601n, each reference signal 201a-201n (e.g. Figure 2) are input to the neural network 602a-602n, and the neural network 602a-602n predicts that there will be Q consecutive out-of-sync events by applying the multiple reference signal input neural network 602a-602n to predict 1 step ahead, 2 steps ahead, and Q steps ahead. In at least one embodiment, the same multiple reference signal input neural network is applied to the 1 step ahead, 2 steps ahead, and Q steps ahead prediction. In at least one embodiment, different multiple reference signal input neural networks are applied to different step-ahead predictions. In at least one embodiment, if the prediction is an out-of-sync event, the neural network 602a-602n outputs a bit 1 at each step t[x], x=1,2,3, until Q, and / or if the prediction is not an out-of-sync event, the neural network 602a-602n outputs a bit 0 at each step t[x], x=1,2,3, until Q. In at least one embodiment, if the neural network output is 1, the UE 101 uses the neural network to infer that there will be Q consecutive "out-of-sync" events, and if the neural network output is 0, the UE 101 uses the neural network to infer that there will be no out-of-sync events. In at least one embodiment, on each RS resource 201a-201n used for downlink radio link quality prediction, the UE101 executing the neural network 602a-602n infers the downlink radio link quality at a future time based on the neural network predicting whether the downlink radio link can be reliably received at the future time (e.g., if the quality is above a threshold Qin).

[0098] In at least one embodiment, the threshold Qin corresponds to a synchronization block error rate threshold (BLERin). For example, the value of BLERin is 2%. The predicted synchronization block error rate is derived based on the assumed PDCCH transmission parameters used for synchronization prediction. In at least one embodiment, the assumed PDCCH transmission parameter set includes one or more of the following: downlink control information (DCI) format, the number of control orthogonal frequency division multiplexing (OFDM) symbols, the aggregation level in terms of the number of control channel elements (CCEs), the ratio of the assumed PDCCH resource element (RE) energy to the average secondary synchronization signal (SSS) RE energy, the ratio of the assumed PDCCH RE energy to the average CSI-RS RE energy, the ratio of the assumed PDCCH demodulation RS (DMRS) energy to the average SSS RE energy, the ratio of the assumed PDCCH DMRS energy to the average CSI-RS RE energy, the bandwidth in terms of the number of physical resource blocks (PRBs), the subcarrier spacing, the DMRS precoder granularity, the resource element group (REG) bundling size, the cyclic prefix (CP) length, and the mapping from REG to CCE. In at least one embodiment, for SSB-based radio link prediction, the first set of values ​​of the one or more assumed PDCCH transmission parameters is used for synchronization block error rate prediction. In at least one embodiment, for CSI-RS-based radio link prediction, the second set of values ​​of the one or more assumed PDCCH transmission parameters is used for synchronization block error rate prediction.

[0099] In at least one embodiment, when the neural network 102 predicts that the radio link quality is better than a threshold Qin of any resource in the set of radio link prediction resources, the neural networks 602a-602n predict that a synchronization event will occur in the downlink radio link at a future time.

[0100] In at least one embodiment, the neural network 102 assumes that the timer T310 will start after the N310 continuous out-of-sync event. Then, the neural network 102 further predicts whether N311 continuous synchronization will occur in the future within the duration of the assumed running time T310.

[0101] In at least one embodiment, if the neural network predicts that continuous desynchronization will occur at a future time (e.g., N310), and further predicts that continuous synchronization will occur within the duration of timer T310 (e.g., N311) thereafter, UE 101 assumes that the radio link will become unreliable but will recover, and therefore does not take any further action at this time.

[0102] In at least one embodiment, the training data set for the neural network 602a-602n may include one or more prediction windows corresponding to one or more reference signals (e.g., 201a-201n) and radio link states with labels (e.g., high, low, medium, poor, or good radio link quality). In at least one embodiment, the neural network (e.g., neural network 102) is trained by a processor using labeled training, which includes one or more prediction windows corresponding to one or more reference signals (e.g., 201a-201n) and radio link states with labels (e.g., high, low, medium, poor, or good radio link quality).

[0103] In at least one embodiment, for each RLM-RS resource, the training data set includes thresholds, such as Qout and Qin. Qout is a threshold at which the radio link quality cannot be reliably received and corresponds to a desynchronization error rate (BLERout). In at least one embodiment, Qout is based on a physical downlink control channel (PDCCH) transmission parameter for desynchronization assessment associated with the corresponding type of RLM-RS. For example, the BLERout threshold is 10%.

[0104] In at least one embodiment, Qin is a threshold level at which the radio link quality can be received with higher reliability than under Qout. Qin corresponds to a synchronization block error rate (BLERin). The threshold Qin is based on a PDCCH transmission parameter for synchronization assessment associated with a corresponding type of RLM-RS. For example, the BLERin threshold is 2%. Exceeding Qin or passing the Qin threshold indicates that data transmitted on the radio link can be reliably received. Exceeding Qin or passing the Qin threshold also indicates that the radio link between the UE and the base station is synchronized.

[0105] In at least one embodiment, the training data set includes a constant N310, where the constant N310 can be used to evaluate the maximum number of consecutive out-of-sync or early out-of-sync indications of the primary serving cell (PCell) received from the lower layer. In at least one embodiment, after receiving a threshold number of consecutive N310 "out-of-sync" indications from the lower layer, the UE will start a timer T310 for the corresponding cell. After the timer T310 expires, the UE will consider that a radio link failure of the cell has been detected, and the UE can then enter RRC_IDLE or start a connection reestablishment procedure.

[0106] In at least one embodiment, the training data set includes a constant N311, where the constant N311 evaluates the maximum number of consecutive in-sync indications received from the lower layer for the PCell. In at least one embodiment, upon receiving N311 consecutive "in-sync" indications for the cell from the lower layer while T310 is running, the UE may stop timer T310 for the corresponding cell. In at least one embodiment, the UE does not declare a radio link failure because the N311 consecutive "in-sync" indications mean that the downlink radio link has recovered to a satisfactory level.

[0107] In at least one embodiment, the processor trains a neural network on training data comprising one or more RLM-RS resources.

[0108] In at least one embodiment, for SSB-based radio link prediction, the first set of values ​​of the one or more hypothesized PDCCH transmission parameters is used for out-of-sync block error rate prediction.

[0109] In at least one embodiment, for CSI-RS based radio link prediction, the second set of values ​​of the one or more hypothesized PDCCH transmission parameters is used for out-of-sync block error rate prediction.

[0110] Figure 7 702 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 702 may be provided by Figures 1 to 7 For example, processor 105 may execute an API to access, use, or otherwise implement neural network 102. In at least one embodiment, software program 702 is a software module. In at least one embodiment, software program 702 includes one or more software modules. In at least one embodiment, one or more software modules such as Figure 7710 is further described in a non-exclusive manner. In at least one embodiment, one or more APIs 710 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, runtime 704, driver 704, and / or any other software and / or executable code group further described herein. In at least one embodiment, one or more APIs 710 perform one or more computing operations in response to a call from a software program 702. In at least one embodiment, a software program 702 is a collection of software codes, commands, instructions, or other text sequences for instructing a computing device to perform one or more computing operations and / or call one or more other instruction sets to be executed, such as an API 710 or an API function 712. In at least one embodiment, the functionality provided by one or more APIs 710 includes a software function 712, such as a software function that can be used to accelerate one or more parts of a software program 702 using one or more parallel processing units (PPUs) (e.g., a graphics processing unit (GPU)).

[0111] In at least one embodiment, the API 710 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 710 described herein are implemented as one or more circuits for performing the following combined Figures 2 to 6 In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following combined Figures 2 to 6 One or more techniques further described.

[0112] In at least one embodiment, the software program 702 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 710 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, the one or more APIs 710 provide a set of callable functions 712 (referred to herein as APIs, API functions, and / or functions) that individually perform one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, the one or more APIs 710 provide functions 712 to enable the scheduler 716 to sort one or more jobs in a scheduling queue based on credits associated with the jobs.

[0113] In at least one embodiment, one or more software programs 702 interact or otherwise communicate with one or more APIs 710 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that will be accelerated at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to facilitate parallel computing using remote or local interfaces.

[0114] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, the software program 702 uses the native interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to one or more APIs 710. In at least one embodiment, the one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that include instructions to execute the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are dynamically compiled and the one or more software programs are linked to the one or more precompiled libraries 706 that include the one or more APIs 710 using a linker.

[0115] In at least one embodiment, the software program 702 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 706 including one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 706 including one or more APIs 710 are to be executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 706 including one or more APIs 710 are to be executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702.

[0116] In at least one embodiment, a processor executing or using one or more software programs 702 calls, uses, executes, or otherwise implements one or more APIs 710 to allocate and otherwise manage memory to be used by the software programs 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory to be used by one or more portions of the software programs 702 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors further described herein). These software programs 702 request the neural network to perform image generation, feature information generation, and / or depth information generation using functions 712 provided by one or more APIs 710 in an embodiment.

[0117] In at least one embodiment, the API 710 is an API for facilitating parallel computing. In at least one embodiment, the API 710 is any other API further described herein. In at least one embodiment, the API 710 is provided by a driver and / or runtime 704. In at least one embodiment, the API 710 is provided by a CUDA user mode driver. In at least one embodiment, the API 710 is provided by a CUDA runtime. In at least one embodiment, the driver 704 is a data value and software instruction that, if executed, performs one or more functions 712 of the API 710 during loading and executing one or more parts of the software program 702 or otherwise facilitates the operation of one or more functions 712 of the API 710. In at least one embodiment, the runtime 704 is a data value and software instruction that, if executed, performs one or more functions 712 of the API 710 during execution of the software program 702 or otherwise facilitates the operation of one or more functions 712 of the API 710. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform combined arithmetic operations by the one or more software programs 702 during execution by one or more PPUs (e.g., GPUs).

[0118] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 710 provide combined arithmetic operations through the driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and / or runtime 704 to allocate or otherwise reserve one or more memory blocks 714 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and / or runtime 704 to allocate or otherwise reserve memory blocks. In at least one embodiment, the one or more APIs 710 are used to perform combined arithmetic operations, as described below in conjunction with Figures 1 to 6 Any one of the above.

[0119] To improve the usability of software program 702 and / or optimization of one or more portions of the software program 702 for acceleration by one or more PPUs (e.g., GPUs), in one embodiment, one or more APIs 710 provide one or more API functions 712 to execute a neural network that is usable or used by one or more computing devices, as described above and hereinafter in conjunction with Figures 1 to 6 Further description. In at least one embodiment, exemplary block diagram 700 depicts a processor including one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 700 depicts a system including one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the API to cause a neural network to select a thread selection mechanism and / or otherwise perform operations described herein. In at least one embodiment, exemplary block diagram 700 shows an API for calling a neural network to cause image generation.

[0120] In at least one embodiment, a processor uses an exemplary API to call one or more neural networks, wherein the processor includes circuitry for generating one or more first images from a viewpoint outside the object based at least in part on depth information generated using one or more second neural networks and feature information generated by one or more third neural networks using one or more first neural networks and / or otherwise performing operations described herein.

[0121] Neural network logic

[0122] Fig. 8A Logic 815 is shown, as described elsewhere herein, which may be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is reasoning and / or training logic. Fig. 8A and / or Figure 8B Detailed information is provided regarding logic 815. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuits forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU).

[0123] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0124] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 801 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 801 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of a neural network, or some combination of these factors.

[0125] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 805 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software to control timing and / or order, where weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0126] In at least one embodiment, the code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 805 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0127] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0128] In at least one embodiment, logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logic and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 820, which are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, activations stored in activation storage 820 are generated from linear algebra and / or matrix-based math performed by ALU 810 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 805 and / or in code and / or data storage 801 used as operands, as well as other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0129] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 810 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0130] In at least one embodiment, activation storage 820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 820 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0131] In at least one embodiment, Fig. 8A The logic 815 shown in FIG. 8 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Fig. 8A The illustrated logic 815 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0132] Figure 8B Logic 815 is shown according to at least one embodiment. In at least one embodiment, logic 815 is reasoning and / or training logic. In at least one embodiment, logic 815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B The logic 815 shown in FIG. 8 can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8BThe logic 815 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 8B In at least one embodiment shown in , each of code and / or data storage 801 and code and / or data storage 805 is associated with a dedicated computing resource, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, each of computing hardware 802 and computing hardware 806 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 801 and code and / or data storage 805, respectively, with the results being stored in activation storage 820.

[0133] In at least one embodiment, each of the code and / or data stores 801 and 805 and the corresponding computing hardware 802 and 806 corresponds to a different layer of the neural network, such that activations obtained from one storage / compute pair 801 / 802 of the code and / or data store 801 and computing hardware 802 are provided as inputs to the next storage / compute pair 805 / 806 of the code and / or data store 805 and computing hardware 806, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 801 / 802 and 805 / 806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the logic 815 after or in parallel with the storage / compute pairs 801 / 802 and 805 / 806.

[0134] Neural network training and deployment

[0135] Fig. 9The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 906 is trained using a training data set 902. In at least one embodiment, the training data set 902 includes a reference signal database. The reference signal database includes one or more radio link monitoring reference signal (RLM-RS) resources. The RLM-RS resources may include synchronization signal blocks (SSBs), or all channel state information reference signals (CSI-RSs), or a mixture of SSBs and CSI-RSs. The training data set 902 may also include Qout and Qin threshold levels corresponding to the radio link state. The state of the radio link may be out of sync or in sync. The training data set 902 may also include one or more prediction windows corresponding to one or more reference signals and radio link states.

[0136] In at least one embodiment, the training framework 904 is a PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains an untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0137] In at least one embodiment, untrained neural network 906 is trained using supervised learning, where training data set 902 includes inputs paired with expected outputs for the inputs, or where training data set 902 includes inputs with known outputs and the outputs of neural network 906 are manually graded. In at least one embodiment, untrained neural network 906 is trained in a supervised manner, and inputs from training data set 902 are processed and the resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through untrained neural network 906. In at least one embodiment, training framework 904 adjusts the weights that control untrained neural network 906. In at least one embodiment, training framework 904 includes tools for monitoring the degree to which untrained neural network 906 converges to a model (such as trained neural network 908) suitable for generating a correct answer (such as result 914) based on input data (such as new data set 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and an adjustment algorithm such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches a desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0138] In at least one embodiment, untrained neural network 906 is trained using unsupervised learning, where untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training data set 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 906 can learn groupings within training data set 902 and can determine how individual inputs are related to untrained data set 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 908, which is capable of performing operations useful for reducing the dimensionality of new data set 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new data set 912 that deviate from the normal pattern of new data set 912.

[0139] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training data set 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to the new data set 912 without forgetting the knowledge that was infused into the trained neural network 908 during the initial training.

[0140] In at least one embodiment, the training framework 904 is a framework processed in conjunction with a software development kit such as the OpenVINO (Open Visual Reasoning and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0141] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks, recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0142] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or variations thereof.

[0143] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command line tool that facilitates conversion between training and deployment of a neural network model. In at least one embodiment, a model optimizer optimizes a neural network model to execute on various devices and / or processing units such as a GPU, a CPU, a PPU, a GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces the number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model for training. In at least one embodiment, a model optimizer performs various neural network operations, such as modifying the input of a model (e.g., adjusting the size of the input of a model), modifying the size of the input of a model (e.g., modifying the batch size of a model), modifying a model structure (e.g., modifying a layer of a model), normalization, standardization, quantization (e.g., converting the weights of a model from a first representation such as a floating point to a second representation such as an integer) and / or variations thereof.

[0144] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as reasoning engines. In at least one embodiment, the reasoning engine is a C++ library or any suitable programming language library. In at least one embodiment, the reasoning engine is used to reason about input data. In at least one embodiment, the reasoning engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the reasoning engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0145] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU), and executing a second set of layers on a second device (e.g., a CPU)).

[0146] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0147] In at least one embodiment, the untrained neural network 906 is trained on the training data set 920. The trained neural network 920 can then predict whether the radio link will fail based on the input RLM-RS input from the UE. For example, in at least one embodiment, on each RS resource used for downlink radio link quality prediction, the neural network predicts the downlink radio link quality at a future time by predicting whether the downlink radio link cannot be reliably received at a future time. For example, in at least one embodiment, when the neural network predicts that the quality is lower than a threshold value Qout, the neural network predicts that the radio link cannot be reliably received at a future time.

[0148] In at least one embodiment, the threshold Qout corresponds to an out-of-sync block error rate threshold (BLERout). An example value of BLERout is 10%. The predicted out-of-sync block error rate is derived based on assumed PDCCH transmission parameters for out-of-sync prediction.

[0149] In at least one embodiment, the PDCCH transmission parameter set is assumed to include one or more of the following: downlink control information (DCI) format; control the number of orthogonal frequency division multiplexing (OFDM) symbols; aggregation level in terms of the number of control channel elements (CCEs); an assumed ratio of PDCCH resource element (RE) energy to average secondary synchronization signal (SSS) RE energy; an assumed ratio of PDCCH RE energy to average CSI-RS RE energy; an assumed ratio of PDCCH demodulation RS (DMRS) energy to average SSS RE energy; an assumed ratio of PDCCH DMRS energy to average CSI-RS RE energy; bandwidth in terms of the number of physical resource blocks (PRBs); subcarrier spacing; DMRS precoder granularity; resource element group (REG) bundling size; cyclic prefix (CP) length; and mapping from REG to CCE.

[0150] In at least one embodiment, for SSB-based radio link prediction, the first set of values ​​of the one or more hypothesized PDCCH transmission parameters is used for out-of-sync block error rate prediction.

[0151] In at least one embodiment, for CSI-RS based radio link prediction, the second set of values ​​of the one or more hypothesized PDCCH transmission parameters is used for out-of-sync block error rate prediction.

[0152] In at least one embodiment, when the UE predicts that the radio link quality is worse than a threshold Qout of all resources in the radio link prediction resource set, the neural network 102 predicts that the downlink radio link will be "out of sync" at a future time.

[0153] In at least one embodiment, UE 101 trains reference signal resource specific neural networks to make asynchronous predictions at future times and uses them for inference. Figure 1 As shown. For each reference signal n, there is a corresponding neural network n: the input of the neural network n is based on the measurement results of the reference signal n at the time points {t[-P],…,t[0]}, and the output of the neural network n is the x-step-ahead link quality prediction of whether the link quality is lower than the threshold Qout based on the reference signal n. If the neural network n predicts that the link quality is lower than the threshold Qout, the model n produces an output bit equal to 1; otherwise, the model n produces an output bit equal to 0. The N-bit outputs from the N neural networks are then fused through an AND operation. If the result of the AND operation is 1, the UE predicts that there will be a lack of synchronization at the time point t[x]; if the result of the AND operation is 0, the UE predicts that there will be no lack of synchronization at the time point t[x].

[0154] Data Center

[0155] Fig.10 An example data center 1000 is shown in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0156] In at least one embodiment, Fig.10 As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node CRs") 1016(1)-1016(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016(1)-1016(N) may be a server having one or more of the above computing resources.

[0157] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or many racks housed in data centers (also not shown) at various geographic locations. In at least one embodiment, separate groups of node CRs within the grouped computing resources 1014 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0158] In at least one embodiment, resource coordinator 1012 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may include a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may include hardware, software, or some combination thereof.

[0159] In at least one embodiment, Fig.10 As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which can utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1022 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1014 at the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0160] In at least one embodiment, software 1032 included in software layer 1030 may include software used by at least portions of node CRs 1016(1)-1016(N), grouped computing resources 1014, and / or distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0161] In at least one embodiment, one or more applications 1042 included in application layer 1040 may include one or more types of applications used by at least portions of node CRs 1016(1)-1016(N), grouped computing resources 1014, and / or distributed file system 1028 of framework layer 1020. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0162] In at least one embodiment, any of the configuration manager 1024, the resource manager 1026, and the resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 1000 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0163] In at least one embodiment, data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, the resources described above with respect to data center 1000 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks.

[0164] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0165] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in data center 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0166] In at least one embodiment, logic 815 is integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0167] Autonomous Vehicles

[0168] Fig.11A An example of an autonomous vehicle 1100 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1100 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1100 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0169] An autonomous vehicle may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) of the U.S. Department of Transportation and the Society of Automotive Engineers (“SAE”) in the “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of the standard). In at least one embodiment, the vehicle 1100 may be capable of having one or more functions of Level 1 to Level 5 according to the autonomous driving level. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0170] In at least one embodiment, the vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1150 may be connected to a drive train of the vehicle 1100, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1100. In at least one embodiment, the propulsion system 1150 may be controlled in response to receiving a signal from a throttle / accelerator 1152.

[0171] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion), steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive signals from steering actuator 1156. In at least one embodiment, the steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, brake sensor system 1146 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1148 and / or brake sensors.

[0172] In at least one embodiment, one or more controllers 1136, which may include, but are not limited to, one or more system-on-chips (“SoCs”) ( Fig.11A1100) and / or a graphics processing unit ("GPU") to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, the one or more controllers 1136 may send signals to operate vehicle brakes via brake actuators 1148, operate steering system 1154 via one or more steering actuators 1156, and operate propulsion system 1150 via one or more throttles / accelerators 1152. In at least one embodiment, the one or more controllers 1136 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1100. In at least one embodiment, the one or more controllers 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0173] In at least one embodiment, the one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1158 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360 degree cameras), telephoto cameras (e.g., infrared cameras), and / or a plurality of other sensors. Fig.11A Not shown), mid-range camera ( Fig.11A), one or more speed sensors 1144 (e.g., for measuring the speed of the vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more brake sensors (e.g., as part of a brake sensor system 1146), and / or other sensor types.

[0174] In at least one embodiment, one or more controllers 1136 may receive input (e.g., represented by input data) from a dashboard 1132 of the vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1134, an audible annunciator, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition maps ( Fig.11A ), location data (e.g., the location of the vehicle 1100, such as on a map), directions, locations of other vehicles (e.g., occupancy grid), information about objects and states of objects sensed by one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0175] In at least one embodiment, the vehicle 1100 further includes a network interface 1124, which can use one or more wireless antennas 1126 and / or one or more modems to communicate through one or more networks. For example, in at least one embodiment, the network interface 1124 can be capable of communicating through Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1126 can also use one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, etc. protocols) to enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.).

[0176] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in vehicle 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0177] In at least one embodiment, logic 815 is integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0178] Fig. 11B According to at least one embodiment, Fig.11A 100. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different locations on the vehicle 1100.

[0179] In at least one embodiment, the camera type for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent transparent ("RCCC") filter array, a red transparent transparent blue ("RCCB") filter array, a red blue green transparent ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to improve photosensitivity.

[0180] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0181] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1100 (e.g., reflected light from the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side view cameras, one or more cameras can also be integrated within four pillars at each corner of the cabin.

[0182] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1100 can be used for surround vision to help identify the path ahead and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1136 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0183] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("complementary metal oxide semiconductor") color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects that enter the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Fig. 11BOnly one wide-angle camera 1170 is shown, but in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1100. In at least one embodiment, any number of remote cameras 1198 (e.g., a pair of telescopic stereo cameras) may be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more remote cameras 1198 may also be used for object detection and classification and basic object tracking.

[0184] In at least one embodiment, any number of stereo cameras 1168 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit including an extensible processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1100 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or in place of those described herein.

[0185] In at least one embodiment, cameras with a field of view of portions of the environment including the sides of the vehicle 1100 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids, and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1174 (e.g., Fig. 11B The four surround cameras (e.g., four surround cameras shown) can be positioned on the vehicle 1100. In at least one embodiment, the one or more surround cameras 1174 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fish-eye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fish-eye cameras can be located at the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0186] In at least one embodiment, a camera having a field of view including portions of the environment behind the vehicle 1100 (e.g., a rear view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0187] In at least one embodiment, the system or components of FIG. 11 are integrated into Figure 1-7 For example, the processor 105 may include or use the vehicle 1100 to use one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0188] Fig. 11C is a diagram showing a method according to at least one embodiment Fig.11A A block diagram of an example system architecture of an autonomous vehicle 1100. In at least one embodiment, Fig. 11C Each of the components, features, and systems of the vehicle 1100 in the vehicle 1100 is shown as being connected via a bus 1102. In at least one embodiment, the bus 1102 may include, but is not limited to, a CAN data interface (referred to herein alternatively as a "CAN bus"). In at least one embodiment, the CAN may be a network inside the vehicle 1100 that assists in controlling various features and functions of the vehicle 1100, such as actuation, acceleration, braking, steering, wipers, etc. of the brakes. In at least one embodiment, the bus 1102 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1102 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, the bus 1102 may be a CAN bus that complies with ASIL B.

[0189] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1102, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1102 may communicate with any component of vehicle 1100, and two or more buses in bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoC”) 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1100) and can be connected to a common bus, such as a CAN bus.

[0190] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Fig.11A Those described. In at least one embodiment, the controller 1136 can be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any of the various other components and systems of the vehicle 1100 and can be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment and / or other functions of the vehicle 1100.

[0191] In at least one embodiment, the vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, but is not limited to, a central processing unit ("CPU(s)") 1106, a graphics processing unit ("GPU(s")) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1104 may be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1104 may be combined in a system (e.g., a system of the vehicle 1100) along with a high-definition ("HD") map 1122, which may be downloaded from one or more servers (e.g., a system of the vehicle 1100) via a network interface 1124. Fig. 11C ) to obtain map refreshes and / or updates.

[0192] In at least one embodiment, one or more CPUs 1106 may include a CPU cluster or CPU complex (referred to herein alternatively as "CCPLEX"). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or a secondary ("L2") cache. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which enables any combination of clusters of one or more CPUs 1106 to be active at any given time.

[0193] In at least one embodiment, one or more CPUs 1106 may implement power management functions including, but not limited to, one or more of the following features: each hardware block may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0194] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (referred to herein alternatively as an "iGPU"). In at least one embodiment, one or more GPUs 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512KB). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0195] In at least one embodiment, one or more GPUs 1108 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1108 may be manufactured on fin field effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, a zero-level (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file may be allocated to each processing block. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating point data paths for providing efficient execution of workloads using a mix of computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0196] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, in some examples, to provide a peak memory bandwidth of approximately 900GB / sec. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0197] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1108 to directly access one or more CPU 1106 page tables. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to one or more CPUs 1106. In response, in at least one embodiment, 2 of the one or more CPUs 1106 may look up the virtual-physical mapping of the address in its page table and send the translation back to the one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory of both one or more CPUs 1106 and one or more GPUs 1108, thereby simplifying programming of one or more GPUs 1108 and porting applications to one or more GPUs 1108.

[0198] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that may track the frequency of accesses to other processors' memory by one or more GPUs 1108. In at least one embodiment, the one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency with which memory ranges are shared between processors.

[0199] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1106 and one or more GPUs 1108. In at least one embodiment, one or more caches 1112 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0200] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and unload some tasks of one or more GPUs 1108 (e.g., to free up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks ("Cneural networks"), recurrent neural networks ("Rneural networks"), etc.). In at least one embodiment, the Cneural network may include a CNN based on a region or region convolutional neural network ("RCneural network") and a fast RCneural network (e.g., such as for object detection) or other types of CNN.

[0201] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLA"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for Cneural networks, RCneural networks, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally greatly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single instance convolution functions and post-processor functions that support, for example, INT8, INT16, and FP16 data types for features and weights. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly Cneural networks, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: Cneural networks for object recognition and detection using data from camera sensors; Cneural networks for distance estimation using data from camera sensors; Cneural networks for emergency vehicle detection and identification and detection using data from microphones; Cneural networks for face recognition and vehicle owner recognition using data from camera sensors; and / or Cneural networks for protection and / or safety related events.

[0202] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1108, and by using an inference accelerator, for example, a designer can target one or more DLAs or one or more GPUs 1108 for any function. For example, in at least one embodiment, a designer can focus the processing of Cneural networks and floating point operations on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0203] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0204] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or a tightly coupled RAM.

[0205] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA may support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0206] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0207] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

[0208] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM for one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuits, controllers, and multiplexers. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0209] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communications for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0210] In at least one embodiment, one or more SoCs 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0211] In at least one embodiment, one or more accelerators 1114 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power consumption and low latency is well matched to the algorithm domain that requires predictable processing. In other words, the PVA excels in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in the vehicle 1100, the PVA may be designed to run classic computer vision algorithms because they can be efficient in object detection and integer math operations.

[0212] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0213] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0214] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1166 associated with vehicle 1100 orientation, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160).

[0215] In at least one embodiment, one or more SoCs 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, one or more data stores 1116 may be on-chip memory of one or more SoCs 1104 that may store neural networks to be executed on one or more GPUs 1108 and / or DLAs. In at least one embodiment, one or more data stores 1116 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1116 may include one or more L2 or L3 caches.

[0216] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist system low power state transitions, one or more SoCs 1104 thermal and temperature sensor management, and / or one or more SoCs 1104 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1104 into a lower power state and / or place the vehicle 1100 into a driver's safe parking mode (e.g., bringing the vehicle 1100 to a safe stop).

[0217] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that may be used as an audio processing engine, which may be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0218] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0219] In at least one embodiment, one or more processors 1110 may further include a safety cluster engine, which includes but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safe mode, in at least one embodiment, two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0220] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC1104, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, which are otherwise disabled.

[0221] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0222] In at least one embodiment, the video image compositor may also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor may also be used for user interface composition when the operating system desktop is being used and does not require one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1108 are powered and active for 3D rendering, the video image compositor may be used to offload one or more GPUs 1108 to improve performance and responsiveness.

[0223] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0224] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 may be used to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which may be connected via an Ethernet channel), data from the bus 1102 (e.g., speed of the vehicle 1100, steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance large-scale storage controllers, which may include their own DMA engines and may be used to free up one or more CPUs 1106 from routine data management tasks.

[0225] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that utilizes and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster, more reliable, and even more energy efficient and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data stores 1116, can provide a fast and efficient platform for level 3-5 autonomous vehicles.

[0226] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to perform various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as, for example, performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0227] The embodiments described herein allow for multiple neural networks to be executed simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a Cneural network executed on a DLA or discrete GPU (e.g., one or more GPUs 1120) may include text and word recognition, allowing traffic signs to be read and understood, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs and passing that semantic understanding to a path planning module running on the CPU complex.

[0228] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks may be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with electric lights, may be interpreted by several neural networks independently or collectively. In at least one embodiment, the warning sign itself may be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights may be recognized by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be run simultaneously, such as within a DLA and / or on one or more GPUs 1108.

[0229] In at least one embodiment, a Cneural network for face recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, the always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a safe mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0230] In at least one embodiment, a Cneural network for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoC1104 uses a Cneural network to classify environmental and urban sounds, as well as to classify visual data. In at least one embodiment, a Cneural network running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a Cneural network can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the Cneural network will seek to detect European sirens, while when operating in North America, the Cneural network will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1162 to perform emergency vehicle safety routines, slow the vehicle, drive the vehicle to the side of the road, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0231] In at least one embodiment, the vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1118 may include, for example, an X86 processor. The one or more CPUs 1118 may be used to perform any of a variety of functions, including, for example, arbitrating between ADAS sensors and one or more SoCs 1104 that may be inconsistent, and / or monitoring the status and health of one or more controllers 1136 and / or an infotainment system on a chip (“infotainment SoC”) 1130. In at least one embodiment, the one or more SoCs 1104 include one or more interconnects, and the interconnects may include a Peripheral Component Interconnect Express (PCIe).

[0232] In at least one embodiment, the vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1100 (e.g., sensor data).

[0233] In at least one embodiment, the vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, the network interface 1124 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, in order to communicate with other vehicles, a direct link may be established between the vehicle 1100 and another vehicle and / or an indirect link may be established (e.g., through a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to the vehicle 1100 about vehicles near the vehicle 1100 (e.g., vehicles in front of, to the side of, and / or behind the vehicle 1100). In at least one embodiment, the aforementioned functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 1100.

[0234] In at least one embodiment, the network interface 1124 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1136 to communicate via a wireless network. In at least one embodiment, the network interface 1124 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end function may be provided by a separate chip. In at least one embodiment, the network interface may include a wireless function for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN and / or other wireless protocols.

[0235] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1104) storage. In at least one embodiment, the one or more data stores 1128 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard disk, and / or other components and / or devices that can store at least one bit of data.

[0236] In at least one embodiment, the vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0237] In at least one embodiment, the vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, one or more RADAR sensors 1160 may be used by the vehicle 1100 for remote vehicle detection, even in darkness and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting data generated by one or more RADAR sensors 1160) to control and access object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1160 are pulse Doppler RADAR sensors.

[0238] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within 250m (meters)). In at least one embodiment, one or more RADAR sensors 1160 can help distinguish between static objects and moving objects, and can be used by the ADAS system 1138 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1160 included in the long-range RADAR system may include but are not limited to a single-base (monostatic) multi-modal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, six antennas are used, and the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1100 at a higher speed, while the traffic interference of the adjacent lanes is minimal. In at least one embodiment, the other two antennas can extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1100.

[0239] In at least one embodiment, as an example, the medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that constantly monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0240] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162 that may be positioned at the front, rear, and / or side positions of the vehicle 1100 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor 1162 may operate at a functional safety level of ASIL B.

[0241] In at least one embodiment, the vehicle 1100 may include one or more LIDAR sensors 1164. In at least one embodiment, the one or more LIDAR sensors 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1164 may operate at functional safety level ASIL B. In at least one embodiment, the vehicle 1100 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0242] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LIDAR sensors 1164 may, for example, have an advertising range of approximately 100m, have an accuracy of 2cm-3cm, and support 100Mbps Ethernet connections. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may include a small device that can be embedded in the front, rear, side, and / or corner positions of the vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low reflectivity objects, and have a range of 200m. In at least one embodiment, one or more forward-mounted LIDAR sensors 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0243] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) can also be used. In at least one embodiment, 3D flash LIDAR uses laser flash as a transmission source to illuminate up to about 200m around the vehicle 1100. In at least one embodiment, the flash LIDAR unit includes but is not limited to a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1100 to the object. In at least one embodiment, the flash LIDAR can allow each laser flash to be used to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of the vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes but is not limited to a solid-state 3D staring array LIDAR camera with no moving parts except for the fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0244] In at least one embodiment, the vehicle 1100 may also include one or more IMU sensors 1166. In at least one embodiment, the one or more IMU sensors 1166 may be located at the center of the rear axle of the vehicle 1100. In at least one embodiment, the one or more IMU sensors 1166 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 1166 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, the one or more IMU sensors 1166 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0245] In at least one embodiment, one or more IMU sensors 1166 may be implemented as a miniature high-performance GPS-aided inertial navigation system ("GPS / INS") that combines a micro-electromechanical system ("MEMS") inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1166 may enable the vehicle 1100 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1166, without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1166 and one or more GNSS sensors 1158 may be combined in a single integrated unit.

[0246] In at least one embodiment, the vehicle 1100 can include one or more microphones 1196 positioned within and / or around the vehicle 1100. In at least one embodiment, the one or more microphones 1196 can be used for emergency vehicle detection and identification.

[0247] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide-angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long-range cameras 1198, one or more mid-range cameras 1176, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1100. In at least one embodiment, the type of camera used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present invention is described herein previously with reference to the accompanying drawings. Fig.11A and Fig. 11B Each camera is described in more detail.

[0248] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the one or more vibration sensors 1142 may measure vibrations of a component (e.g., an axle) of the vehicle 1100. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0249] In at least one embodiment, the vehicle 1100 may include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, a SoC in some examples. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0250] In at least one embodiment, the ACC system may use one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 1100 change lanes when necessary. In at least one embodiment, lateral ACC is related to other ADAS applications, such as LC and CW.

[0251] In at least one embodiment, the CACC system uses information from other vehicles, which can be received indirectly from other vehicles via a network interface 1124 and / or one or more wireless antennas 1126 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link can be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link can be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 1100 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system can include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of the vehicle 1100, the CACC system can be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0252] In at least one embodiment, the FCW system is designed to warn the driver of the hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of sounds, visual warnings, vibrations and / or rapid brake pulses.

[0253] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system may automatically apply brakes to try to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include technologies such as dynamic brake support and / or collision approach braking.

[0254] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver when the vehicle 1100 crosses a lane marking. In at least one embodiment, the LDW system is not activated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1100 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1100.

[0255] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0256] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1100 detects an object outside the rear camera range while backing up. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0257] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether the safety situation actually exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1100 decides for itself whether to listen to the results of the main computer or the auxiliary computer (e.g., the first controller or the second controller in the controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant various software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to the supervisory MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to coordinate the conflict to ensure safe operation.

[0258] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU, which indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the event that the confidence score does not meet the threshold, and in the event that the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0259] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based at least in part on outputs from the main computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying metal objects that are not actually dangerous, such as drainage grates or manhole covers that will trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, when there are cyclists or pedestrians and lane departure is actually the safest operation, the neural network in the supervisory MCU can learn to override LDW. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoCs 1104.

[0260] In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error.

[0261] In at least one embodiment, the output of the ADAS system 1138 can be fed into the perception block of the main computer and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, the auxiliary computer can have its own neural network that is trained, as described herein, to reduce the risk of false positives.

[0262] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, in at least one embodiment, the infotainment system SoC 1130 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistants, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming media, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information, such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1100. For example, the infotainment SoC 1130 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connections, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 may be further used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1100, such as information from an ADAS system 1138, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0263] In at least one embodiment, the infotainment SoC 1130 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 may communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a supervisory MCU so that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more of the main controllers 1136 (e.g., the main computer and / or backup computer of the vehicle 1100). In at least one embodiment, the infotainment SoC 1130 may place the vehicle 1100 in a driver-to-safety parking mode, as described herein.

[0264] In at least one embodiment, the vehicle 1100 may further include a dashboard 1132 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the dashboard 1132 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, supplementary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the dashboard 1132. In at least one embodiment, the dashboard 1132 may be included as part of the infotainment SoC 1130, and vice versa.

[0265] In at least one embodiment, the system or components of FIG. 11 are integrated into Figure 1-7 For example, the processor 105 may include or use the vehicle 1100 to use one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0266] Fig.11D In accordance with at least one embodiment, one or more cloud-based servers and Fig.11A1. A diagram of a system for communicating between autonomous vehicles 1100. In at least one embodiment, the system may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but are not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1188 and / or PCIe connection 1186 developed by NVIDIA. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0267] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1178 may send updated neural networks 1192 and / or map information 1194 to the vehicle via one or more networks 1190, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1194 may include, but are not limited to, updates to the HD map 1122, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1192 and / or map information 1194 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0268] In at least one embodiment, one or more servers 1178 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle, and / or can be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of the training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1190, and / or the machine learning model can be used by one or more servers 1178 to remotely monitor the vehicle.

[0269] In at least one embodiment, one or more servers 1178 may receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. In at least one embodiment, one or more servers 1178 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 may include a deep learning infrastructure of a data center powered by a CPU.

[0270] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of fast, real-time inference, and may use this capability to assess and validate the health of the processors, software, and / or associated hardware in the vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1100, such as a sequence of images and / or objects that the vehicle 1100 has located in the sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1100, and, if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is malfunctioning, the one or more servers 1178 may send a signal to the vehicle 1100 instructing the fail-safe computer of the vehicle 1100 to take control, notify passengers, and complete a safe parking maneuver.

[0271] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, such as in situations where performance is not critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 815 are used to execute one or more embodiments. This article combines Fig. 8A and / or Figure 8B Provides details about the hardware structure 815.

[0272] Computer Systems

[0273] Fig.12 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, the computer system 1200 may include, but is not limited to, components, such as a processor 1202, for executing an algorithm for process data using an execution unit (including logic). In at least one embodiment, the computer system 1200 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0274] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0275] In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0276] In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, register file 1206 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

[0277] In at least one embodiment, an execution unit 1208, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic to process a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of a general purpose processor and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data on the processor's data bus to perform one or more operations on one data element at a time.

[0278] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1220 may store one or more instructions 1219 and / or data 1221 represented by data signals that processor 1202 may execute.

[0279] In at least one embodiment, the system logic chip can be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can direct data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and the system I / O interface 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an accelerated graphics port (“AGP”) interconnect 1214 .

[0280] In at least one embodiment, the computer system 1200 may use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to an I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub ("flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a traditional I / O controller 1223 including a user input and keyboard interface 1225, a serial expansion port 1227 (such as a universal serial bus ("USB") port), and a network controller 1234. In at least one embodiment, the data store 1224 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0281] In at least one embodiment, Fig.12 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Fig.12 An exemplary SoC may be shown. In at least one embodiment, Fig.12The devices shown in the can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a compute express link (CXL) interconnect.

[0282] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computer system 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0283] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0284] Fig.13 1 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0285] In at least one embodiment, electronic device 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I 2 C bus, system management bus ("SMBus"), low pin count (LPC) bus, serial peripheral interface ("SPI"), high-definition audio ("HDA") bus, serial advanced technology attachment ("SATA") bus, universal serial bus ("USB") (version 1, 2, 3, etc.), or universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig.13 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig.13 An exemplary SoC may be shown. In at least one embodiment, Fig.13The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.13 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0286] In at least one embodiment, Fig.13 It may include a display 1324, a touch screen 1325, a touch pad 1330, a near field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, a fast chipset (“EC”) 1335, a trusted platform module (“TPM”) 1338, a BIOS / firmware / flash (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0287] In at least one embodiment, other components may be communicatively coupled to the processor 1310 through the components described herein. In at least one embodiment, the accelerometer 1341, ambient light sensor (“ALS”) 1342, compass 1343, and gyroscope 1344 may be communicatively coupled to the sensor hub 1340. In at least one embodiment, the thermal sensor 1339, fan 1337, keyboard 1336, and touchpad 1330 may be communicatively coupled to the EC 1335. In at least one embodiment, the speaker 1363, earphone 1364, and microphone (“mic”) 1365 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 1362, which in turn may be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor ("NGFF").

[0288] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in electronic device 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0289] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0290] Fig.14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0291] In at least one embodiment, computer system 1400 includes, but is not limited to, at least one central processing unit ("CPU") 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1400 includes, but is not limited to, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1404, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using computer system 1400.

[0292] In at least one embodiment, computer system 1400 includes, but is not limited to, input device 1408, parallel processing system 1412, and display device 1406, which may be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1408 (such as a keyboard, mouse, touch pad, microphone, etc.). In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0293] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, logic 815 can be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0294] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0295] Fig.15 A computer system 1500 according to at least one embodiment is shown. In at least one embodiment, the computer system 1500 includes, but is not limited to, a computer 1510 and a USB disk 1520. In at least one embodiment, the computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0296] In at least one embodiment, the USB disk 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and a USB interface logic 1550. In at least one embodiment, the processing unit 1530 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1530 is a visual processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0297] In at least one embodiment, USB interface 1540 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 can include any number and type of logic that enables processing unit 1530 to interface with a device (e.g., computer 1510) via USB connector 1540.

[0298] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0299] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0300] Fig.16AAn exemplary architecture is shown in which multiple GPUs 1610(1)-1610(N) are communicatively coupled to multiple multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers whose values ​​may vary from figure to figure. In at least one embodiment, as Fig.19A and Fig.19B As disclosed, one or more of the plurality of GPUs 1610(1)-1610(N) include one or more graphics cores (also referred to simply as "cores") 1900. In at least one embodiment, the one or more graphics cores 1900 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0301] In addition, in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which may be implemented using protocols / links similar to or different from the protocols / links used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be connected via high-speed link 1628, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Fig.16A In at least one embodiment, one or more of the plurality of GPUs 1610(1)-1610(N) include a plurality of GPUs 1610(1)-1610(N) and a plurality of GPUs 1610(2)-1610(3) as shown in FIG. Fig.19A and 19BDisclosed are one or more graphics cores (which may also be referred to simply as "cores") 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as streaming multiprocessors ("SMs"), streaming processors ("SPs"), streaming processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., a 16-core, a ray tracing unit, a thread director, or a scheduler).

[0302] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1601(1)-1601(M) and GPU memory 1620 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1601 may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0303] As described herein, although each multi-core processor 1605 and GPU 1610 may be physically coupled to a specific memory 1601, 1620, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1601(1)-1601(M) may each include 64GB of system memory address space, and GPU memories 1620(1)-1620(N) may each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0304] Fig. 16BAdditional details for the interconnection between the multi-core processor 1607 and the graphics acceleration module 1646 are shown according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card that is coupled to the processor 1607 via a high-speed link 1640 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1646 may alternatively be integrated on a package or chip with the processor 1607.

[0305] In at least one embodiment, the processor 1607 includes a plurality of cores 1660A-1660D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components not shown for executing instructions and processing data. In at least one embodiment, the caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1656 may be included in the caches 1662A-1662D and shared by each group of cores 1660A-1660D. For example, one embodiment of the processor 1607 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, processor 1607 and graphics acceleration module 1646 are connected to system memory 1614, which may include Fig.16A Processor memory 1601(1)-1601(M) in.

[0306] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1662A-1662D, 1656, and system memory 1614 via inter-core communications over coherency bus 1664. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate in response to detecting a read or write to a particular cache line over coherency bus 1664. In at least one embodiment, a cache snooping protocol is implemented over coherency bus 1664 to snoop cache accesses.

[0307] In at least one embodiment, the proxy circuit 1625 communicatively couples the graphics acceleration module 1646 to the coherence bus 1664, thereby allowing the graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of the cores 1660A-1660D. In particular, in at least one embodiment, the interface 1635 provides a connection to the proxy circuit 1625 via the high-speed link 1640, and the interface 1637 connects the graphics acceleration module 1646 to the high-speed link 1640.

[0308] In at least one embodiment, the accelerator integrated circuit 1636 provides cache management, memory access, context management and interrupt management services on behalf of the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the multiple graphics processing engines 1631(1)-1631(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 include a combination of Fig.19A and Fig.19B One or more graphics cores 1900 discussed. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, line card, or chip.

[0309] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, the cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the data stored in the cache 1638 and graphics memory 1633(1)-1633(M) may be kept consistent with the core caches 1662A-1662D, 1656, and system memory 1614, possibly using a fetch unit 1644. As previously described, this can be implemented on behalf of cache 1638 and memory 1633(1)-1633(M) via proxy circuit 1625 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 to cache 1638 and receiving updates from cache 1638).

[0310] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages thread contexts. For example, context management circuitry 1648 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1648 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​may then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1647 receives and processes interrupts received from system devices.

[0311] In at least one embodiment, the MMU 1639 converts virtual / effective addresses from the graphics processing engine 1631 to real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1631 (1)-1631 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0312] In at least one embodiment, accelerator integrated circuit 1636 performs as a bridge to the system of graphics acceleration modules 1646 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of graphics processing engines 1631(1)-1631(N).

[0313] In at least one embodiment, since the hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped into the real address space seen by host processor 1607, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1636 is the physical separation of graphics processing engines 1631(1)-1631(N) so that they appear to the system as independent units.

[0314] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each graphics processing engine 1631(1)-1631(N), respectively, and N=M. In at least one embodiment, graphics memories 1633(1)-1633(M) store instructions and data being processed by each graphics processing engine 1631(1)-1631(N). In at least one embodiment, graphics memories 1633(1)-1633(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0315] In at least one embodiment, to reduce data traffic on high-speed link 1640, biasing techniques may be used to ensure that data stored in graphics memory 1633(1)-1633(M) is data that is most frequently used by graphics processing engines 1631(1)-1631(N), and preferably data that is not used (at least not frequently) by cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data that is needed by the cores (and preferably not needed by graphics processing engines 1631(1)-1631(N)) in caches 1662A-1662D, 1656, and system memory 1614.

[0316] Fig. 16C Another exemplary embodiment is shown in which an accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via interface 1637 and interface 1635 (again, which can be any form of bus or interface protocol) over a high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 can perform operations related to Fig. 16B The operations described above are similar to the operations described above, but may have higher throughput due to its close proximity to the coherent bus 1664 and caches 1662A-1662D, 1656. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0317] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0318] In at least one embodiment, graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a system hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow each operating system to access. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0319] In at least one embodiment, the graphics acceleration module 1646 or individual graphics processing engines 1631(1)-1631(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0320] Fig.16D An exemplary accelerator integrated slice 1690 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, the application is an effective address space 1682 in the system memory 1614, which stores a process element 1683. In at least one embodiment, the process element 1683 is stored in response to a GPU call 1681 from an application 1680 executing on the processor 1607. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In at least one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0321] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing engines 1631(1)-1631(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure for setting process state and sending WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment can be included.

[0322] In at least one embodiment, the process-specific programming model is implementation specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0323] In operation, in at least one embodiment, a WD fetch unit 1691 in the accelerator integrated slice 1690 fetches a next WD 1684, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in registers 1645 and used by the MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of the MMU 1639 includes a segment / page walk circuit for accessing a segment / page table 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process an interrupt event 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, effective addresses 1693 generated by the graphics processing engines 1631(1)-1631(N) are converted to real addresses by the MMU 1639.

[0324] In at least one embodiment, registers 1645 are replicated for each graphics processing engine 1631(1)-1631(N) and / or graphics acceleration module 1646 and may be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in an accelerator integrated slice 1690. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0325] Table 1 – Registers initialized by the hypervisor

[0326]

[0327] Example registers that may be initialized by the operating system are shown in Table 2.

[0328] Table 2 – Registers initialized by the operating system

[0329]

[0330] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1631(1)-1631(N) to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0331] Fig.16E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 can be accessed via a hypervisor 1696 that virtualizes a graphics acceleration module engine for an operating system 1695.

[0332] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models where the graphics acceleration module 1646 is shared by multiple processes and partitions, namely time-sliced ​​sharing and graphics-directed sharing.

[0333] In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may adhere to certain requirements, such as (1) the application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the application's job request is completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the graphics acceleration module 1646 must ensure fairness between processes.

[0334] In at least one embodiment, the application 1680 is required to make an operating system 1695 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1646.

[0335] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the user authority mask overwrite register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 can selectively apply the current authority mask overwrite register (AMOR) value before placing the AMR in the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645, which contains the effective address of the area in the effective address space 1682 of the application for the graphics acceleration module 1646 to save and restore the context state. In at least one embodiment, if it is not necessary to save the state between jobs or when the job is preempted, the pointer is optional. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0336] Upon receiving the system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 calls the hypervisor 1696 using the information shown in Table 3.

[0337] Table 3 – OS to hypervisor call parameters

[0338]

[0339] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been granted permission to use graphics acceleration module 1646. Then, in at least one embodiment, hypervisor 1696 places process element 1683 into a linked list of process elements of the corresponding graphics acceleration module 1646 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0340] Table 4 – Process element information

[0341]

[0342] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 1690 registers 1645 .

[0343] like Fig.16F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memory 1601(1)-1601(N) and GPU memory 1620(1)-1620(N). In this implementation, operations executed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memory 1601(1)-1601(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0344] In at least one embodiment, bias / coherency management circuits 1694A-1694E within one or more MMUs 1639A-1639E ensure cache coherency between caches of one or more host processors (e.g., 1605) and GPU 1610 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.16F Multiple instances of bias / consistency management circuits 1694A- 1694E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 1605 and / or within an accelerator integrated circuit 1636 .

[0345] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability of GPU memory 1620 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, the arrangement allows software of host processor 1605 to set operands and access calculation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead may be critical to the execution time of offloaded calculations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1610. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation may play a role in determining the effectiveness of GPU offloading.

[0346] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory page per GPU addition. In at least one embodiment, with or without a bias cache in GPU 1610 (e.g., for caching frequently / recently used entries of the bias table), the bias table can be implemented in a stolen memory range of one or more GPU memories 1620. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0347] In at least one embodiment, the bias table entry associated with each access to the GPU attached memory 1620 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1610 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1620. In at least one embodiment, local requests from the GPU to find its pages in the host bias are forwarded to the processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, the request from the processor 1605 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request directed to a GPU bias page can be forwarded to the GPU 1610. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism in a limited set of cases.

[0348] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in certain migrations, performing a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1605 bias to GPU bias, but not for the reverse migration.

[0349] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU biased pages that cannot be cached by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is beneficial to ensure that GPU biased pages are pages required by the GPU and not by the host processor 1605, and vice versa.

[0350] One or more hardware structures 815 are used to execute one or more embodiments. Fig. 8A and / or Figure 8B Details regarding one or more hardware structures 815 are provided.

[0351] Fig.17An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0352] Fig.17 1700 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPU), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic, which includes a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I 2 S / I 2 C controller 1740. In at least one embodiment, the integrated circuit 1700 may include a display device 1745 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industry Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0353] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in integrated circuit 1700 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0354] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks (e.g., Figure 1The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0355] Fig.18A and Fig.18B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0356] Fig.18A and Fig.18B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.18A An exemplary graphics processor 1810 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig.18B An additional exemplary graphics processor 1840 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Fig.18A The graphics processor 1810 is a low power graphics processor core. In at least one embodiment, Fig.18B The graphics processor 1840 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 can be Fig.17 A variation of the graphics processor 1710 .

[0357] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, so that the vertex processor 1805 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A-1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer displayed on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0358] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide virtual to physical address mapping for graphics processor 1810 (including for vertex processor 1805 and / or fragment processors 1815A-1815N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B may synchronize with other MMUs within the system, including with Fig.17 One or more MMUs associated with one or more application processors 1705, image processor 1715, and / or video processor 1720 enable each processor 1705-1720 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0359] In at least one embodiment, graphics processor 1840 includes: Fig.18B One or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N-1 and 1855N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0360] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processors 1810 and / or 1840 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0361] In at least one embodiment, Fig. 8A or Figure 8B systems or components integrated into Figure 1-7 For example, the processor 105 may include or use logic 815 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0362] Fig.19A and Fig.19B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Fig.19A and Fig.19B Shown in and about Figures 19A-19B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other type of processor. In at least one embodiment, Fig.19A shows that it can be included in Fig.17Graphics core 1900 within graphics processor 1710 of FIG. 1700 and, in at least one embodiment, may be such as Fig.18B Unified shader cores 1855A-1855N are shown. Fig.19B A highly parallel general purpose graphics processing unit ("GPGPU", which may be referred to as a "graphics processing unit") 1930 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, the graphics processing unit 1930 is a GPGPU including a graphics processor. In at least one embodiment, the integrated circuit 1700 includes the graphics core 1900, for example, to form an integrated circuit and / or to form a SoC, wherein such an integrated circuit and / or such a SoC performs the operations described herein.

[0363] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920 (e.g., including L1, L2, L3, last level cache, or other cache) that are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N or partitions of each core, and the graphics processor may include multiple instances of graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to graphics core 1900. In at least one embodiment, slices 1901A-1901N have sub-slices, which are parts of slices 1901A-1901N. In at least one embodiment, slices 1901A-1901N are independent of other slices or dependent on other slices. In at least one embodiment, the slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N may include a set of additional function units (AFU 1912A-1912N), floating point units (FPU 1914A-1914N), integer arithmetic logic units (ALU 1916A-1916N), address calculation units (ACU 1913A-1913N), double precision floating point units (DPFPU 1915A-1915N), and matrix processing units (MPU 1917A-1917N). In at least one embodiment, MPUs 1917A-1917N are referred to as matrix engines.

[0364] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in artificial intelligence, machine learning or large data set workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for calculating vectors (e.g., calculating mathematical operations of vectors). In at least one embodiment, the vector engine can calculate vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1901A-1901N include 16 vector engines, which are paired with 16 matrix math units to calculate matrix / tensor operations, where the vector engines and math units are exposed through matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and ray tracing units or 8 cores, thread schedulers, thread dispatchers, and additional functional units of the processor. In at least one embodiment, graphics core 1900 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0365] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0366] In at least one embodiment, one or more slices 1901A-1901N comprise a media slice that encodes, decodes, and / or transcodes data; scales data and / or converts the format of data; and / or performs video quality operations on video data.

[0367] In at least one embodiment, one or more slices 1901A-1901N are linked to L2 cache and memory structures, link connectors, high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stacks, and media engines. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., data corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it to a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by a shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 1901A-1901N include memory structures, such as an L2 cache.

[0368] In at least one embodiment, the FPU 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1915A-1915N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1917A-1917N can perform various matrix operations to accelerate the machine learning application framework, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1912A-1912N can perform additional logical operations that are not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0369] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics core 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0370] In at least one embodiment, graphics core 1900 includes an interconnect and link fabric sublayer attached to a switch and GPU-GPU bridge that enables multiple graphics processors 1900 (e.g., 8) to interconnect with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900 without glue to each other. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0371] In at least one embodiment, the graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1900 includes a computing tile, a memory tile (e.g., where the memory tile can be accessed exclusively by different tiles or different chipsets (such as Rambo tiles)), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are packaged together in the graphics core 1900 as part of a GPU. In at least one embodiment, the graphics core 1900 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a computing tile can have 8 graphics cores 1900, an L1 cache; and a base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected by fine pitch 36 micron micro bumps (e.g., copper pillars) in a face-to-face (F2F) on-chip bonding manner. In at least one embodiment, the graphics core 1900 includes a memory structure (which includes memory) and is a tile accessible to multiple tiles. In at least one embodiment, the graphics core 1900 stores, accesses, or loads its own hardware context in memory, where the hardware context is a set of data loaded from registers before the process is resumed, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0372] In at least one embodiment, graphics core 1900 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0373] In at least one embodiment, graphics core 1900 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0374] In at least one embodiment, graphics core 1900 executes an API that abstracts the hardware of graphics core 1900 and accesses libraries with instructions to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0375] In at least one embodiment, graphics core 1900 is integrated into Figure 1-7 For example, processor 105 may include or use graphics core 1900 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0376] Fig.19BA GPGPU 1930 in at least one embodiment is shown, which can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 for connecting to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a manufacturer-specific communication interface or communication structure. In at least one embodiment, GPGPU 1930 receives commands from a host processor and uses a global scheduler 1934 (which can be referred to as a thread sequencer and / or asynchronous computing engine) to assign execution threads associated with those commands to a group of computing clusters 1936A-1936H. In at least one embodiment, computing clusters 1936A-1936H share cache memory 1938. In at least one embodiment, cache memory 1938 may be used as a higher level cache for cache memory within computing clusters 1936A-1936H. In at least one embodiment, computing clusters 1936A-1936H include slices or also referred to as "slices". In at least one embodiment, GPGPU 1930 is part of a SoC, such as part of integrated circuit 1700 ( Fig.17 ).

[0377] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0378] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Fig.19AThe graphics core 1900 may include multiple types of integer and floating point logic units that can perform computational operations over a range of precisions including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0379] In at least one embodiment, multiple instances of GPGPU 1930 may be configured to operate as a computing cluster. In at least one embodiment, the communications used by computing clusters 1936A-1936H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate through host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 with a GPU link 1940 that enables direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via network devices accessible via host interface 1932. In at least one embodiment, GPU link 1940 may also be configured to enable connection to a host processor in addition to or in lieu of host interface 1932 .

[0380] In at least one embodiment, the GPGPU 1930 may be configured to train a neural network. In at least one embodiment, the GPGPU 1930 may be used within an inference platform. In at least one embodiment, when the GPGPU 1930 is used for inference, the GPGPU 1930 may include fewer computing clusters 1936A-1936H relative to when the GPGPU 1930 is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1944A-1944B may differ between the inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1930 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations of a deployed neural network.

[0381] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in GPGPU 1930 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0382] In at least one embodiment, GPGPU 1930 is integrated into Figure 1-7 For example, the processor 105 may include or use a GPGPU 1930 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0383] Fig. 20 2000 and a processor 2010A. The processor 2010A of FIG. 2000 is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, the computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset component or may be integrated within the one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 includes an I / O hub 2007 that may enable the computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I / O hub 2007 may enable a display controller that may be included in the one or more processors 2002 to provide output to the one or more display devices 2010A. In at least one embodiment, the one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal, or embedded display devices.

[0384] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to a memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use one of any number of standards based on communication link technology or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2012 form a parallel or vector processing system in a computational concentration, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2012 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the one or more parallel processors 2012 can also include a display controller and display interface (not shown) for implementing a direct connection to one or more display devices 2010B. In at least one embodiment, one or more parallel processors 2012 include one or more cores, such as graphics core 1900 discussed herein.

[0385] In at least one embodiment, system storage unit 2014 can be connected to I / O hub 2007 to provide a storage mechanism for computing system 2000. In at least one embodiment, I / O switch 2016 can be used to provide an interface mechanism for enabling connections between I / O hub 2007 and other components, such as network adapter 2018 and / or wireless network adapter 2019 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2020. In at least one embodiment, network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2019 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0386] In at least one embodiment, computing system 2000 may include other components not explicitly shown that may also be connected to I / O hub 2007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Fig. 20The communication paths between the components in the

[0387] In at least one embodiment, one or more parallel processors 2012 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU), for example, one or more parallel processors 2012 include graphics core 1900. In at least one embodiment, one or more parallel processors 2012 include circuits optimized for general processing. In at least one embodiment, the components of computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, memory hub 2005, one or more processors 2002, and I / O hub 2007 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2000 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0388] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computing system 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0389] In at least one embodiment, the computing system 2000 is integrated into Figure 1-7 For example, computing system 2000 may include processor 105 to use one or more neural networks (e.g., Figure 1 The network 102 in the embodiment of the present invention predicts the quality of one or more wireless signals based at least in part on one or more reference signals.

[0390] processor

[0391] Fig.21A2100 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2100 shown is a processor according to an exemplary embodiment. Fig. 20 Variations of one or more parallel processors 2012 are shown. In at least one embodiment, parallel processor 2100 includes one or more graphics cores 1900.

[0392] In at least one embodiment, parallel processor 2100 includes parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes I / O unit 2104, which enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link 2113. In at least one embodiment, I / O unit 2104 is connected to a host interface 2106 and a memory crossbar switch 2116, wherein host interface 2106 receives commands for performing processing operations and memory crossbar switch 2116 receives commands for performing memory operations.

[0393] In at least one embodiment, when the host interface 2106 receives command buffers via the I / O unit 2104, the host interface 2106 can direct work operations for executing those commands to the front end 2108. In at least one embodiment, the front end 2108 is coupled with a scheduler 2110 (which can be referred to as a sequencer), which is configured to assign commands or other work items to the processing cluster array 2112. In at least one embodiment, the scheduler 2110 ensures that the processing cluster array 2112 is correctly configured and in a valid state before assigning tasks to clusters in the processing cluster array 2112. In at least one embodiment, the scheduler 2110 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing cluster array 2112. In at least one embodiment, the host software can prove a workload for scheduling on the processing cluster array 2112 via one of a plurality of graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0394] In at least one embodiment, the processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B to cluster 2114N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work distribution algorithms to distribute work to the clusters 2114A-2114N in the processing cluster array 2112, which may vary depending on the workload generated for each type of program or calculation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N in the processing cluster array 2112 may be allocated to process different types of programs or to perform different types of calculations.

[0395] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2112 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0396] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from the system memory via the I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in an on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0397] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better achieve the distribution of graphics processing operations to multiple clusters 2114A-2114N in the processing cluster array 2112. In at least one embodiment, the portions of the processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, the first portion can be configured to perform vertex shading and topology generation, the second portion can be configured to perform tessellation and geometry shading, and the third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between the clusters 2114A-2114N for further processing.

[0398] In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be performed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured to be in a valid state before starting the workload specified by the incoming command buffer (e.g., batch-buffer, push buffer, etc.).

[0399] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar switch 2116, which can receive memory requests from processing cluster array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar switch 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B to partition unit 2120N), which can each be coupled to a portion of parallel processor memory 2122 (e.g., memory units). In at least one embodiment, the number of partition units 2120A-2120N is configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding second memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory cells.

[0400] In at least one embodiment, the memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across the memory units 2124A-2124N, allowing the partition units 2120A-2120N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 2122. In at least one embodiment, local instances of the parallel processor memory 2122 may be excluded in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0401] In at least one embodiment, any of the clusters 2114A-2114N in the processing cluster array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or another cluster 2114A-2114N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with the memory interface 2118 through the memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 for communicating with I / O unit 2104, and connections to local instances of parallel processor memory 2122, which enables processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0402] In at least one embodiment, multiple instances of parallel processing unit 2102 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 may include higher precision floating point units relative to other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2102 or parallel processor 2100 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0403] Fig. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is Fig.21A 2120N). In at least one embodiment, the partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 communicates with memory units (such as ROPs) in parallel processor memory. Fig.21A One of the memory units 2124A-2124N (e.g., within parallel processor memory 2122)) is coupled.

[0404] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencils, z-tests, blending, etc. In at least one embodiment, ROP 2126 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0405] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Fig.21A In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar switch 2116. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Fig. 20 2010), routed by processor 2002 for further processing, or by Fig.21A One of the processing entities within parallel processor 2100 is routed for further processing.

[0406] Fig. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig.21A In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit, which is configured to issue instructions to a set of processing engines within each processing cluster.

[0407] In at least one embodiment, the operation of the processing cluster 2114 can be controlled via a pipeline manager 2132 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 Fig.21AThe scheduler 2110 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included in the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0408] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2114 may include the same set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0409] In at least one embodiment, the instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines can be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2134.

[0410] In at least one embodiment, the graphics multiprocessor 2134 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use the cache memory (e.g., L1 cache 2148) within the processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 can also access the partition unit (e.g., Fig.21A 2120N) that are shared between all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data that can be stored in L1 cache 2148.

[0411] In at least one embodiment, each processing cluster 2114 may include a memory management unit ("MMU") 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2145 may reside in Fig.21A 2148. In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0412] In at least one embodiment, the processing clusters 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134 and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar 2116. In at least one embodiment, a preROP 2142 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., Fig.21A In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0413] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processing cluster 2114 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0414] In at least one embodiment, processing cluster 2114 is integrated into Figure 1-7 For example, the processing cluster 2114 may include a processor 105 to use one or more neural networks (e.g., Figure 1 The network 102 in the example embodiment may be configured to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0415] Fig.21DA graphics multiprocessor 2134 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to a pipeline manager 2132 of a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline including, but not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166, wherein the one or more load / store units 2166 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU core 2162 and the load / store unit 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168. In at least one embodiment, the GPGPU core 2162 is part of a SoC (such as Fig.17 part of integrated circuit 1700 in FIG. 17A ).

[0416] In at least one embodiment, the instruction cache 2152 receives the instruction stream to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In at least one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, the instruction can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2166.

[0417] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands for data paths connected to the functional units (e.g., GPGPU core 2162, load / store unit 2166) of graphics multiprocessor 2134. In at least one embodiment, register file 2158 is divided between each functional unit such that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2134.

[0418] In at least one embodiment, the GPGPU cores 2162 may each include a floating point unit (FPU) and / or an integer...

Claims

1. A processor, comprising: One or more circuits for predicting the quality of one or more wireless signals based at least in part on one or more reference signals using one or more neural networks.

2. The processor of claim 1 , wherein the reference signal is transmitted by a radio unit and comprises a predefined value used by one or more user equipment to generate an estimate of a radio link quality between a user equipment and the radio unit.

3. The processor of claim 1 , wherein the one or more reference signals are one or more inputs to the neural network and the predicted qualities of the one or more wireless signals are one or more outputs of the one or more neural networks.

4. The processor of claim 1 , wherein the one or more circuits are configured to use the predicted quality of the one or more wireless signals to immediately initiate one or more processes for adjusting one or more radio links between a user equipment and a radio unit.

5. The processor of claim 1, wherein the one or more circuits are configured to use the predicted quality of the one or more wireless signals as an input to a control circuit to adjust one or more radio links between a user equipment and a base node. 6 . The processor of claim 1 , wherein the predicted quality of the one or more wireless signals comprises whether a received signal at a user device will be out of synchronization or in synchronization. 7 . The processor of claim 1 , wherein the predicted quality of the one or more wireless signals comprises whether a received signal at the user equipment will be out of synchronization and a duration of the out of synchronization or a number of consecutive frames of the received signal.

8. A system comprising: One or more processors that predict the quality of one or more wireless signals based at least in part on one or more reference signals using one or more neural networks.

9. The system of claim 8, wherein the one or more reference signals are associated with a synchronization signal block signal.

10. The system of claim 8, wherein the one or more reference signals are associated with a channel state information reference signal.

11. The system of claim 8, wherein the one or more reference signals are associated with both a synchronization signal block signal and a channel state information reference signal.

12. The system of claim 8, wherein the one or more reference signals are used by the one or more neural networks to generate a predicted block error rate (BLER).

13. The system of claim 8, wherein the one or more reference signals are used by the one or more neural networks to generate one or more predicted physical downlink control channel (PDCCH) transmission parameters.

14. The system of claim 8, wherein the one or more processors are configured to perform preventative operations to adjust a quality of a radio link based at least in part on the predicted quality of the one or more reference signals.

15. A method comprising: The quality of one or more wireless signals is predicted based at least in part on one or more reference signals using one or more neural networks.

16. The method according to claim 15, further comprising: identifying that a radio link may fail based at least in part on the predicted quality of the one or more wireless signals; as well as Responsive to the likelihood that the radio link will fail, a control signal is generated or information is sent to a radio unit for use by the node to adjust the radio link.

17. The method according to claim 15, further comprising: Based at least in part on the predicted quality of the one or more wireless signals, it is identified that the radio link may be unstable for a next number of frames and then become stable. The method of claim 15 , wherein the one or more reference signals are transmitted periodically.

19. The method according to claim 15, further comprising: Based at least in part on the predicted quality of the one or more wireless signals, it is identified that the radio link may be unstable for a number of consecutive frames.

20. The method of claim 15, further comprising: The predicted quality of the one or more wireless signals is transmitted by the user equipment to a base station node in the fifth generation 5G network.

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